diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc
index 538488253d9b..af2930bcbba5 100644
--- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc
+++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc
@@ -29,6 +29,7 @@ [Defines]
   BUILD_NUMBER                   = 1
 
   DEFINE DO_X86EMU               = FALSE
+  DEFINE MIN_BUILD_NUMBER        = 1
 
 [BuildOptions]
   RELEASE_*_*_CC_FLAGS  = -DMDEPKG_NDEBUG -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=0
@@ -404,6 +405,8 @@ [PcdsFixedAtBuild.common]
 !endif
   gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision|$(BUILD_NUMBER)
 
+  gSynQuacerTokenSpaceGuid.PcdLowestSupportedFirmwareVersion|$(MIN_BUILD_NUMBER)
+
   #
   # 96boards mezzanine support
   #
diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf
index ddd9757201aa..b2de8a2255c9 100644
--- a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf
+++ b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf
@@ -26,13 +26,13 @@
 ################################################################################
 
 [FD.SPI_NOR_IMAGE]
-BaseAddress   = 0x08180000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
-Size          = 0x00280000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
+BaseAddress   = 0x08100000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
+Size          = 0x00300000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
 ErasePolarity = 1
 
 # This one is tricky, it must be: BlockSize * NumBlocks = Size
 BlockSize     = 0x00010000
-NumBlocks     = 0x28
+NumBlocks     = 0x30
 
 ################################################################################
 #
@@ -50,13 +50,16 @@ [FD.SPI_NOR_IMAGE]
 #
 ################################################################################
 
-0x00000000|0x00078000
+0x00000000|0x00080000
+FILE = Platform/Socionext/DeveloperBox/scp_firmware.bin
+
+0x00080000|0x00078000
 FILE = Platform/Socionext/DeveloperBox/fip_all_arm_tf.bin
 
-0x00078000|0x00008000
+0x000f8000|0x00008000
 FILE = $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/$(ARCH)/Silicon/Socionext/SynQuacer/Stage2Tables/Stage2Tables/OUTPUT/Stage2Tables.bin
 
-0x00080000|0x00200000
+0x00100000|0x00200000
 gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
 FV = FVMAIN_COMPACT
 
diff --git a/Platform/Socionext/DeveloperBox/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini b/Platform/Socionext/DeveloperBox/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
index 1f77aeab5049..32b342bd0a1b 100644
--- a/Platform/Socionext/DeveloperBox/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
+++ b/Platform/Socionext/DeveloperBox/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
@@ -19,7 +19,7 @@ Update0 = SynQuacerFvMain
 [SynQuacerFvMain]
 FirmwareType  = 0             # SystemFirmware
 AddressType   = 1             # 0 - relative address, 1 - absolute address.
-BaseAddress   = 0x08180000    # Base address offset on flash
-Length        = 0x00240000    # Length
+BaseAddress   = 0x08100000    # Base address offset on flash
+Length        = 0x00300000    # Length
 ImageOffset   = 0x00000000    # Image offset of this SystemFirmware image
 FileGuid      = e99b89f7-c120-4b25-4db1-8394edb0b4f5  # PcdEdkiiSystemFirmwareFileGuid
diff --git a/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c b/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c
index cd6ab582fdc5..816d8ba33f8c 100644
--- a/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c
+++ b/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c
@@ -23,8 +23,8 @@ STATIC NOR_FLASH_DESCRIPTION mNorFlashDevices[] = {
   {
     // UEFI code region
     SYNQUACER_SPI_NOR_BASE,                             // device base
-    0x8100000, //FixedPcdGet64 (PcdFdBaseAddress),                   // region base
-    0x300000, //FixedPcdGet32 (PcdFdSize),                          // region size
+    FixedPcdGet64 (PcdFdBaseAddress),                   // region base
+    FixedPcdGet32 (PcdFdSize),                          // region size
     SIZE_64KB,                                          // block size
     {
       0x19c118b0, 0xc423, 0x42be, { 0xb8, 0x0f, 0x70, 0x6f, 0x1f, 0xcb, 0x59, 0x9a }
diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
index 963d568e43df..1402ecafce4a 100644
--- a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
+++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
@@ -57,8 +57,8 @@ STATIC CONST EFI_RESOURCE_ATTRIBUTE_TYPE mDramResourceAttributes =
 
 STATIC CONST ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[] = {
   // Memory mapped SPI NOR flash
-  ARM_CACHED_DEVICE_REGION (0x8100000,//FixedPcdGet64 (PcdFdBaseAddress),
-                            0x300000),//FixedPcdGet32 (PcdFdSize)),
+  ARM_CACHED_DEVICE_REGION (FixedPcdGet64 (PcdFdBaseAddress),
+                            FixedPcdGet32 (PcdFdSize)),
 
   // SynQuacer OnChip peripherals
   ARM_DEVICE_REGION (SYNQUACER_PERIPHERALS_BASE,
