@@ -82,7 +82,6 @@ [FixedPcd]
gAmdStyxTokenSpaceGuid.PcdSbsaWakeUpGSIV
gAmdStyxTokenSpaceGuid.PcdSbsaWatchDogGSIV
gAmdStyxTokenSpaceGuid.PcdSocCoresPerCluster
- gAmdStyxTokenSpaceGuid.PcdParkingProtocolVersion
gAmdStyxTokenSpaceGuid.PcdSata1PortCount
[Depex]
@@ -57,12 +57,7 @@ AMD_MP_CORE_INFO_PROTOCOL *mAmdMpCoreInfoProtocol = NULL;
#define MSI_TYPER_FLAG ( 0 ) // Use TYPER register and ignore Count/Base fields
#endif
-#define PARKING_PROTOCOL_VERSION (FixedPcdGet32 (PcdParkingProtocolVersion))
-#define PARKED_OFFSET ( 4096 )
-
#define CORES_PER_CLUSTER (FixedPcdGet32 (PcdSocCoresPerCluster))
-#define PARKED_ADDRESS(Base, ClusterId, CoreId) \
- ((Base) + (CORES_PER_CLUSTER * ClusterId + CoreId) * PARKED_OFFSET)
/* Macro to populate EFI_ACPI_5_1_GIC_STRUCTURE */
@@ -73,7 +68,7 @@ AMD_MP_CORE_INFO_PROTOCOL *mAmdMpCoreInfoProtocol = NULL;
CpuNum, /* UINT32 CPUInterfaceNumber */ \
(ClusterId << 8) | CoreId, /* UINT32 AcpiProcessorUid */ \
EFI_ACPI_5_1_GIC_ENABLED, /* UINT32 Flags */ \
- PARKING_PROTOCOL_VERSION, /* UINT32 ParkingProtocolVersion */ \
+ 0, /* UINT32 ParkingProtocolVersion */ \
PerfInt, /* UINT32 PerformanceInterruptGsiv */ \
0, /* UINT64 ParkedAddress */ \
GIC_BASE, /* UINT64 PhysicalBaseAddress */ \
@@ -194,8 +189,7 @@ BuildGicC (
EFI_ACPI_5_1_GIC_STRUCTURE *GicC,
UINT32 CpuNum,
UINT32 ClusterId,
- UINT32 CoreId,
- EFI_PHYSICAL_ADDRESS MpParkingBase
+ UINT32 CoreId
)
{
UINT32 MpId, PmuSpi;
@@ -212,8 +206,6 @@ BuildGicC (
GicC->CPUInterfaceNumber = CpuNum;
GicC->AcpiProcessorUid = MpId;
GicC->Flags = EFI_ACPI_5_1_GIC_ENABLED;
- GicC->ParkingProtocolVersion = PARKING_PROTOCOL_VERSION;
- GicC->ParkedAddress = PARKED_ADDRESS(MpParkingBase, ClusterId, CoreId);
GicC->PhysicalBaseAddress = GIC_BASE;
GicC->GICV = GICV_BASE;
GicC->GICH = GICH_BASE;
@@ -281,8 +273,6 @@ MadtHeader (
ARM_CORE_INFO *ArmCoreInfoTable;
UINTN CoreCount, CpuNum;
EFI_STATUS Status;
- EFI_PHYSICAL_ADDRESS MpParkingBase;
- UINTN MpParkingSize;
Status = gBS->LocateProtocol (
&gAmdMpCoreInfoProtocolGuid,
@@ -299,13 +289,6 @@ MadtHeader (
ASSERT (CoreCount <= NUM_CORES);
ASSERT (CoreCount <= PcdGet32(PcdSocCoreCount));
- MpParkingSize = 0;
- MpParkingBase = mAmdMpCoreInfoProtocol->GetMpParkingBase(&MpParkingSize);
- if (MpParkingBase && MpParkingSize < (CoreCount * SIZE_4KB)) {
- DEBUG ((EFI_D_ERROR, "MADT: Parking Protocol not supported.\n"));
- MpParkingBase = 0;
- }
-
GicC = (EFI_ACPI_5_1_GIC_STRUCTURE *)&AcpiMadt.GicC[0];
AcpiMadt.Header.Header.Length = sizeof (EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER);
@@ -315,8 +298,7 @@ MadtHeader (
Status = BuildGicC (GicC, CpuNum,
ArmCoreInfoTable[CpuNum].ClusterId,
- ArmCoreInfoTable[CpuNum].CoreId,
- MpParkingBase
+ ArmCoreInfoTable[CpuNum].CoreId
);
ASSERT_EFI_ERROR (Status);
@@ -28,7 +28,6 @@ [Ppis]
gAmdStyxPlatInitPpiGuid = { 0xcbff429c, 0xd3e3, 0x4c50, { 0xac, 0x1a, 0x1c, 0xd2, 0xfe, 0x15, 0x1a, 0xd7 } }
[Protocols]
- gAmdMpBootProtocolGuid = { 0xe21eac84, 0x9fbf, 0x4808, { 0x83, 0x93, 0xe1, 0x93, 0x97, 0x23, 0x48, 0xab } }
gAmdMpCoreInfoProtocolGuid = { 0x0dba25f8, 0x2da1, 0x4ec5, { 0x89, 0x5d, 0x32, 0x1e, 0xd6, 0x1e, 0x3f, 0x43 } }
[Guids]
@@ -101,9 +100,6 @@ [PcdsFixedAtBuild]
# UEFI entry point
gAmdStyxTokenSpaceGuid.PcdUefiEntryAddress|0x8000E80000|UINT64|0x000a0000
- # Parking Protocol
- gAmdStyxTokenSpaceGuid.PcdParkingProtocolVersion|1|UINT32|0x000b0000
-
# The original offset in memory of the NV store firmware volume, before
# relocating it to a dynamically allocated buffer. We need this to correlate
# flash accesses to the in-memory copy with LBAs in the actual SPI flash
deleted file mode 100644
@@ -1,39 +0,0 @@
-/** @file
-
- Copyright (c) 2016, AMD Inc. All rights reserved.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef _AMD_MP_BOOT_H_
-#define _AMD_MP_BOOT_H_
-
-extern EFI_GUID gAmdMpBootProtocolGuid;
-
-typedef
-VOID
-(EFIAPI *PARK_SECONDARY_CORE) (
- IN ARM_CORE_INFO *ArmCoreInfo,
- IN EFI_PHYSICAL_ADDRESS SecondaryEntry
- );
-
-typedef struct _AMD_MP_BOOT_INFO {
- EFI_PHYSICAL_ADDRESS MpParkingBase;
- UINTN MpParkingSize;
- ARM_CORE_INFO *ArmCoreInfoTable;
- UINTN ArmCoreCount;
-} AMD_MP_BOOT_INFO;
-
-typedef struct _AMD_MP_BOOT_PROTOCOL {
- PARK_SECONDARY_CORE ParkSecondaryCore;
- AMD_MP_BOOT_INFO *MpBootInfo;
-} AMD_MP_BOOT_PROTOCOL;
-
-#endif // _AMD_MP_BOOT_H_
@@ -30,16 +30,9 @@ EFI_STATUS
OUT UINT32 *PmuSpi
);
-typedef
-EFI_PHYSICAL_ADDRESS
-(EFIAPI *GET_MP_PARKING_BASE) (
- OUT UINTN *MpParkingSize
- );
-
typedef struct _AMD_MP_CORE_INFO_PROTOCOL {
GET_ARM_CORE_INFO_TABLE GetArmCoreInfoTable;
GET_PMU_SPI_FROM_MPID GetPmuSpiFromMpId;
- GET_MP_PARKING_BASE GetMpParkingBase;
} AMD_MP_CORE_INFO_PROTOCOL;
#endif // _AMD_MP_CORE_INFO_H_
@@ -29,11 +29,9 @@
#include <Guid/ArmMpCoreInfo.h>
#include <Protocol/AmdMpCoreInfo.h>
-#include <Protocol/AmdMpBoot.h>
STATIC AMD_MP_CORE_INFO_PROTOCOL mAmdMpCoreInfoProtocol = { 0 };
-STATIC AMD_MP_BOOT_INFO mAmdMpBootInfo = { 0 };
STATIC
@@ -49,12 +47,6 @@ AmdStyxGetPmuSpiFromMpId (
OUT UINT32 *PmuSpi
);
-STATIC
-EFI_PHYSICAL_ADDRESS
-AmdStyxGetMpParkingBase (
- OUT UINTN *MpParkingSize
- );
-
#pragma pack(push, 1)
typedef struct _PMU_INFO {
@@ -101,7 +93,6 @@ PlatInitDxeEntryPoint (
// Install CoreInfo Protocol
mAmdMpCoreInfoProtocol.GetArmCoreInfoTable = AmdStyxGetArmCoreInfoTable;
mAmdMpCoreInfoProtocol.GetPmuSpiFromMpId = AmdStyxGetPmuSpiFromMpId;
- mAmdMpCoreInfoProtocol.GetMpParkingBase = AmdStyxGetMpParkingBase;
Status = gBS->InstallProtocolInterface (
&Handle,
&gAmdMpCoreInfoProtocolGuid,
@@ -153,15 +144,3 @@ AmdStyxGetPmuSpiFromMpId (
return EFI_INVALID_PARAMETER;
}
-
-STATIC
-EFI_PHYSICAL_ADDRESS
-AmdStyxGetMpParkingBase (
- OUT UINTN *MpParkingSize
- )
-{
- ASSERT (MpParkingSize != NULL);
-
- *MpParkingSize = mAmdMpBootInfo.MpParkingBase;
- return mAmdMpBootInfo.MpParkingBase;
-}
The ACPI parking protocol is a kludge to allow SOC implementations that lack EL3 support to bring up secondaries in a standardized manner. Since our UEFI implementation unconditionally relies on ARM Trusted Firmware and PSCI now, there is no point in supporting the parking protocol any longer so let's remove it. (Note also that the implementation of AmdStyxGetMpParkingBase is flawed, so it is unsure whether it has ever worked in reality) Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Silicon/AMD/Styx/AcpiTables/AcpiTables.inf | 1 - Silicon/AMD/Styx/AcpiTables/Madt.c | 24 ++---------- Silicon/AMD/Styx/AmdStyx.dec | 4 -- Silicon/AMD/Styx/Common/Protocol/AmdMpBoot.h | 39 -------------------- Silicon/AMD/Styx/Common/Protocol/AmdMpCoreInfo.h | 7 ---- Silicon/AMD/Styx/Drivers/PlatInitDxe/PlatInitDxe.c | 21 ----------- 6 files changed, 3 insertions(+), 93 deletions(-) -- 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel