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[198.145.21.10]) by mx.google.com with ESMTPS id w190si16738631pgd.338.2018.12.19.12.56.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Dec 2018 12:56:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Zp2ke9hu; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 6DB17211A2D85; Wed, 19 Dec 2018 12:56:54 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::342; helo=mail-wm1-x342.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm1-x342.google.com (mail-wm1-x342.google.com [IPv6:2a00:1450:4864:20::342]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 029A5211A209E for ; Wed, 19 Dec 2018 12:56:52 -0800 (PST) Received: by mail-wm1-x342.google.com with SMTP id d15so7428852wmb.3 for ; Wed, 19 Dec 2018 12:56:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uasr7c9HBQ//thAm32QVIgSMAJRKMhO82qqo8kNN7Yw=; b=Zp2ke9hu1PhM7pb8SHwzK+pxcyyVXTgKlAfn8+KkP7Sp8vn/sfxKVg1bVb+IuZw3r0 0zXOKrAGtbleubgnBlkHjyyOXKbTIQB1M3SBtvvFbNfkWL15kBSJY+/FBGHVU4C1U+DS Q2nrjKLv+fWYSgHQ8Chs2pEQ/BMxcqcFkG/4A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uasr7c9HBQ//thAm32QVIgSMAJRKMhO82qqo8kNN7Yw=; b=QFBY+VyDNUM0r8X3UpOpNpGZ8Lnwy+mw1W8kzAQmoKgaveLiLoV6gVLxNNLqwZolV9 UV4NRraBRsOD6sx+fZGiKf9gonv2tATNqMx5o9fE6qbumOLndVwPR6zdpw5+yuxFgRkQ tDVa27VVYFWgIWd+5+BRc1Bs31HZdRbDmxdVguo5HQGkAd+BE72JlN0Awa6LqvOLgPjZ QdhZRZeHGDJrs4yr2K29c7whb0AQPMTsQQhC8UTUx4kfXVXjwdc7hcEXI2eaGjimh9AP zybSMUgwuXk1ATavDzDzme9n+Qm3PAMxpjSy3GnLGoQDIBeowH55M1zcD9MhcAG3il72 l35g== X-Gm-Message-State: AA+aEWbMoK+eekJ03t9YKowDUrowZcgvxRlAuKs9N/OxVHzBNncFa+DB 4ZTvfuk9MSmiKY7Sts9nY14H4dLOLQl7fg== X-Received: by 2002:a1c:5545:: with SMTP id j66mr8747577wmb.15.1545253011172; Wed, 19 Dec 2018 12:56:51 -0800 (PST) Received: from harold.home ([2a01:cb1d:112:6f00:e5c9:6e00:25cb:e32e]) by smtp.gmail.com with ESMTPSA id j202sm16267294wmf.15.2018.12.19.12.56.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Dec 2018 12:56:50 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Wed, 19 Dec 2018 21:56:35 +0100 Message-Id: <20181219205640.4704-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181219205640.4704-1-ard.biesheuvel@linaro.org> References: <20181219205640.4704-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Subject: [edk2] [PATCH v2 1/6] MdePkg/Base: introduce MAX_ALLOC_ADDRESS X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jones , Hao Wu , Liming Gao , Michael D Kinney , Laszlo Ersek Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" On some architectures, the maximum representable address deviates from the virtual address range that is accessible by the firmware at boot time. For instance, on AArch64, UEFI mandates a 4 KB page size, which limits the address space to 48 bits, while more than that may be populated on a particular platform, for use by the OS. So introduce a new macro MAX_ALLOC_ADDRESS, which represent the maximum address the firmware should take into account when allocating memory ranges that need to be accessible by the CPU at boot time. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- MdePkg/Include/AArch64/ProcessorBind.h | 5 +++++ MdePkg/Include/Arm/ProcessorBind.h | 5 +++++ MdePkg/Include/Ebc/ProcessorBind.h | 5 +++++ MdePkg/Include/Ia32/ProcessorBind.h | 5 +++++ MdePkg/Include/X64/ProcessorBind.h | 5 +++++ 5 files changed, 25 insertions(+) -- 2.19.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Liming Gao diff --git a/MdePkg/Include/AArch64/ProcessorBind.h b/MdePkg/Include/AArch64/ProcessorBind.h index 968c18f915ae..f4a544b34d78 100644 --- a/MdePkg/Include/AArch64/ProcessorBind.h +++ b/MdePkg/Include/AArch64/ProcessorBind.h @@ -142,6 +142,11 @@ typedef INT64 INTN; /// #define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL +/// +/// Maximum usable address at boot time (48 bits using 4 KB pages) +/// +#define MAX_ALLOC_ADDRESS 0xFFFFFFFFFFFFULL + /// /// Maximum legal AArch64 INTN and UINTN values. /// diff --git a/MdePkg/Include/Arm/ProcessorBind.h b/MdePkg/Include/Arm/ProcessorBind.h index 8cca0f3bb050..16a61fc7a325 100644 --- a/MdePkg/Include/Arm/ProcessorBind.h +++ b/MdePkg/Include/Arm/ProcessorBind.h @@ -148,6 +148,11 @@ typedef INT32 INTN; /// #define MAX_ADDRESS 0xFFFFFFFF +/// +/// Maximum usable address at boot time +/// +#define MAX_ALLOC_ADDRESS MAX_ADDRESS + /// /// Maximum legal ARM INTN and UINTN values. /// diff --git a/MdePkg/Include/Ebc/ProcessorBind.h b/MdePkg/Include/Ebc/ProcessorBind.h index 5217cfd97eac..45beb7572817 100644 --- a/MdePkg/Include/Ebc/ProcessorBind.h +++ b/MdePkg/Include/Ebc/ProcessorBind.h @@ -103,6 +103,11 @@ typedef unsigned long UINTN; /// #define MAX_ADDRESS ((UINTN)(~0ULL >> (64 - sizeof (INTN) * 8))) +/// +/// Maximum usable address at boot time (48 bits using 4 KB pages) +/// +#define MAX_ALLOC_ADDRESS MAX_ADDRESS + /// /// Maximum legal EBC INTN and UINTN values. /// diff --git a/MdePkg/Include/Ia32/ProcessorBind.h b/MdePkg/Include/Ia32/ProcessorBind.h index 8e4de7029cfc..71d53e2543bb 100644 --- a/MdePkg/Include/Ia32/ProcessorBind.h +++ b/MdePkg/Include/Ia32/ProcessorBind.h @@ -246,6 +246,11 @@ typedef INT32 INTN; /// #define MAX_ADDRESS 0xFFFFFFFF +/// +/// Maximum usable address at boot time +/// +#define MAX_ALLOC_ADDRESS MAX_ADDRESS + /// /// Maximum legal IA-32 INTN and UINTN values. /// diff --git a/MdePkg/Include/X64/ProcessorBind.h b/MdePkg/Include/X64/ProcessorBind.h index e4254285877b..1c04090c7d03 100644 --- a/MdePkg/Include/X64/ProcessorBind.h +++ b/MdePkg/Include/X64/ProcessorBind.h @@ -260,6 +260,11 @@ typedef INT64 INTN; /// #define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL +/// +/// Maximum usable address at boot time +/// +#define MAX_ALLOC_ADDRESS MAX_ADDRESS + /// /// Maximum legal x64 INTN and UINTN values. ///