From patchwork Tue Mar 13 15:34:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 131482 Delivered-To: patches@linaro.org Received: by 10.46.84.17 with SMTP id i17csp884808ljb; Tue, 13 Mar 2018 08:35:07 -0700 (PDT) X-Google-Smtp-Source: AG47ELuOkMjoVbl45b1Yxl1iROmVzSrim0IvRZ7CGSfbDLXVL9XpWaqYLn3DCsDz3OgZ+Jav0h8C X-Received: by 2002:a17:902:b407:: with SMTP id x7-v6mr560761plr.373.1520955307477; Tue, 13 Mar 2018 08:35:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520955307; cv=none; d=google.com; s=arc-20160816; b=w9g9Ua1IdPBgy8UGOxwt4i7kElmCrbjxNgUbnhE/khjLZub7NoULrPJkfCLFXKP5FI 3jHYJOqdrHETWZgUHpLcC5th0b3vZdaZ58rlaVin4UEcH80MMTLjHHRvP6TRSqA8HMzi 5B/sg9YeAjuM/z6SNMJSztzlEfqYq07KaZQIpHwwX4nwGWAYWYn8qpDVqmA7EnduqJd7 o3YrCNSt4MbGYnhbuRj7Xwhy+p05balLIbf03NqnoR3hX59eYc1LlYSZWg4J3KYsfevU dnM1LJ7nGQ2ROYrqjEbAwqvU6j+nB+SOs4vXPUrBogazwkwbubOxfBKj5Xu/up0aFO5c XUkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=Moax0p294uKndt3CiguMn4SsRQy9dHzyxg2cfG3e5vo=; b=0RgHADlj/7BKF6F9tGdqJ+lY7Fp7HKSd2c3YPwF3cVdCMCB+aMZmShC69MvOJrG2l6 ldv84aUPtdmhZ9SZK+A3+5T8nhkx+iz3XJberVqVnb6fPvQXuaW/6AtCuAjocPEVQD55 ZsAY3JAa2onu/vHhXKNz5r75x962EfyzkbuytcCziGDz1eoTUiO0NnA+eSCHjzVTj+NC rQRsYIrh42PNf+psFjulyShEDdtRVlgnxenAJja0YAx2zqRh+KaeGSoXjyS98xDTcqiy glQmjTd/wlmsKP1jEg5NeIKrqZz3dWeB0qmfsG83wqlZKvJyGjchT+Tk/C4pIotFjDmq a3sw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id h10si281408pgc.75.2018.03.13.08.35.06 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Mar 2018 08:35:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1evlx7-0003EE-O2; Tue, 13 Mar 2018 15:35:01 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Pekka Enberg , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Andrew Baumann Subject: [PATCH 1/9] hw/arm/raspi: Don't do board-setup or secure-boot for raspi3 Date: Tue, 13 Mar 2018 15:34:50 +0000 Message-Id: <20180313153458.26822-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180313153458.26822-1-peter.maydell@linaro.org> References: <20180313153458.26822-1-peter.maydell@linaro.org> For the rpi1 and 2 we want to boot the Linux kernel via some custom setup code that makes sure that the SMC instruction acts as a no-op, because it's used for cache maintenance. The rpi3 boots AArch64 kernels, which don't need SMC for cache maintenance and always expect to be booted non-secure. Don't fill in the aarch32-specific parts of the binfo struct. Signed-off-by: Peter Maydell --- hw/arm/raspi.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) -- 2.16.2 Reviewed-by: Andrew Baumann Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index a37881433c..1ac0737149 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -82,10 +82,19 @@ static void setup_boot(MachineState *machine, int version, size_t ram_size) binfo.board_id = raspi_boardid[version]; binfo.ram_size = ram_size; binfo.nb_cpus = smp_cpus; - binfo.board_setup_addr = BOARDSETUP_ADDR; - binfo.write_board_setup = write_board_setup; - binfo.secure_board_setup = true; - binfo.secure_boot = true; + + if (version <= 2) { + /* The rpi1 and 2 require some custom setup code to run in Secure + * mode before booting a kernel (to set up the SMC vectors so + * that we get a no-op SMC; this is used by Linux to call the + * firmware for some cache maintenance operations. + * The rpi3 doesn't need this. + */ + binfo.board_setup_addr = BOARDSETUP_ADDR; + binfo.write_board_setup = write_board_setup; + binfo.secure_board_setup = true; + binfo.secure_boot = true; + } /* Pi2 and Pi3 requires SMP setup */ if (version >= 2) { From patchwork Tue Mar 13 15:34:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 131476 Delivered-To: patches@linaro.org Received: by 10.46.84.17 with SMTP id i17csp884717ljb; Tue, 13 Mar 2018 08:35:03 -0700 (PDT) X-Google-Smtp-Source: AG47ELvmR6LOKydHSmbhbeedKKRQxsy/nfTBURAa7RvDmpthtVA/0d0n4PrDkwLBf3r6Gv0Dm6J8 X-Received: by 2002:a19:4acc:: with SMTP id x195-v6mr885832lfa.46.1520955303683; Tue, 13 Mar 2018 08:35:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520955303; cv=none; d=google.com; s=arc-20160816; b=a/fomtJeY6/F8b3Rrferh/txt89eYrqbz/y6vIhtO7Hkhy3dFgcj6hdcPAlcuwQduZ QjT9OUPBHnUSsmfAyShP1chfgzOGGb+sAGaDy0OjBt/0WAUOhRK748gC+T5hRC0Gqk/J m1gsigvPgXEJ5nj79UoV265bbFJqafryuKGlaq7owpZjfHA3zuwNQkTYD+rQEZuAvMus PKjxeZWqjHgVbSOdEaA8LSpmIH7Y7RMRzrHtWkJTagrLnmZIy+6HR3tYgeBT89Zh99jr oTUDC2Gs/JqGO4PyUQ4xTgrSI94D2qWQ8HeWpgNDzi8Qg9sQJf6ZCHKX2Tj0Mlpdhl/j le2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=I+J7W86xjQa/W5GFXY1gXcMG+aKQSom9RaDZujfIguA=; b=PnEEyDCKx30nkSr7n6OPBs2iqQ8G+FKIkKWfBc7pNvENBNccbUlb1ZfpJpBRRazXIS M3f5nTccHy5/og14wTDD4ehPmpgxINsg8p6HNvPiPU3WttRUalh9NIxORYW0PmzthmZt P7uuFp46Ve8xHfAo99uUuM3K/grROUj9YCRrUkwoi5FTftB1Cf6jc23Xkat/jIM63yQM Kb8H9NWgq9Sc2H/fhJDwEWJsNOG0w4Dx1uSN14YFNjnSK9g4G0VshRCBbUUnrSNxU7UD uZ0ynIcM8GoA2Vc6/93I3OoJx9THJdVd0NJ7S88spzBQTuvMo0iP44UkblGzTky9o4Or dP4w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id c9si147868ljf.132.2018.03.13.08.35.03 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Mar 2018 08:35:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1evlx8-0003ER-ER; Tue, 13 Mar 2018 15:35:02 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Pekka Enberg , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Andrew Baumann Subject: [PATCH 2/9] hw/arm/boot: assert that secure_boot and secure_board_setup are false for AArch64 Date: Tue, 13 Mar 2018 15:34:51 +0000 Message-Id: <20180313153458.26822-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180313153458.26822-1-peter.maydell@linaro.org> References: <20180313153458.26822-1-peter.maydell@linaro.org> Add some assertions that if we're about to boot an AArch64 kernel, the board code has not mistakenly set either secure_boot or secure_board_setup. It doesn't make sense to set secure_boot, because all AArch64 kernels must be booted in non-secure mode. It might in theory make sense to set secure_board_setup, but we don't currently support that, because only the AArch32 bootloader[] code calls this hook; bootloader_aarch64[] does not. Since we don't have a current need for this functionality, just assert that we don't try to use it. If it's needed we'll add it later. Signed-off-by: Peter Maydell --- hw/arm/boot.c | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.16.2 Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 196c7fb242..e21a92f972 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -720,6 +720,13 @@ static void do_cpu_reset(void *opaque) } else { env->pstate = PSTATE_MODE_EL1h; } + /* AArch64 kernels never boot in secure mode */ + assert(!info->secure_boot); + /* This hook is only supported for AArch32 currently: + * bootloader_aarch64[] will not call the hook, and + * the code above has already dropped us into EL2 or EL1. + */ + assert(!info->secure_board_setup); } /* Set to non-secure if not a secure boot */ From patchwork Tue Mar 13 15:34:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 131475 Delivered-To: patches@linaro.org Received: by 10.46.84.17 with SMTP id i17csp884718ljb; Tue, 13 Mar 2018 08:35:03 -0700 (PDT) X-Google-Smtp-Source: AG47ELua2kDmYToYuUq0mLWPt++6uJkdD/qC7BSbIXPVxKggfvjSjJnBb3nZT17eJ+MU3OoS0/rT X-Received: by 10.223.160.42 with SMTP id k39mr1016647wrk.138.1520955303707; Tue, 13 Mar 2018 08:35:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520955303; cv=none; d=google.com; s=arc-20160816; b=mFXrIKN7Omv6cRPp8GvYWVtfTjnuiLOHaW+6J3JMdFUtBrnklrkuPw8dde/Os1ZpFx p38IHNkkZuG45nVP4pzrMqumOZmZbWiggUVQCzo6au2r1HHRcUdWP5OsK7l2z60pMXFv 31CoTrpM1X9ri4ucvGQLrOSIlYvuVpv7ODbgDA0oulpuBQHhxT+bLA9egIL9S3D68hud z6A5ptpKdtfpG/GVG2ICqZSjF0kNGfIP8d8sb2x5r2o6bQrkj776a9JEBIs+OasKjV+W 16bwssXhNV4jd4Q20IVKLorv1yBHh/HxMaucmV3UE0ZmsmKzdLMl3TcGZh7Z9JLjdjki 6l9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=YN47X/zRb0s5EGxfv46/agloo6jzVtVgYZ3CoCh/dvE=; b=NQSdWsoJ9RTGD+NMZFzaokc90wtmolF3jLybpMF7SuKHlWXyUheeuWd0ZssnwHSPPM 1CV+bbijNHjFuL+tu8ztaJe1J+QwpueDvyEhlO+dAeTtpcFzKDqwQEBDOpguZfY/2+os t/0sz+EW2Rd0wAiM8U9klAr6L0mwv8Lapnk4Y8LVXk78/XwiQPF+Q7A/ITJv+lfPIZps k71tV7Mf6MmBSbLnOCfd/sQqIrS24mOu8usTX8DOxcj8/RzIMMzvByu4jw528igh/sNY /tYnvJJBWyWXIATbkf+IecyOS8uZNtgmiJq2BCuqV3aJXdnYO0sumjqev9KVXhJyOFQp y15Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id r16si326051wrb.109.2018.03.13.08.35.03 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Mar 2018 08:35:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1evlx9-0003Em-46; Tue, 13 Mar 2018 15:35:03 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Pekka Enberg , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Andrew Baumann Subject: [PATCH 3/9] hw/arm/boot: If booting a kernel in EL2, set SCR_EL3.HCE Date: Tue, 13 Mar 2018 15:34:52 +0000 Message-Id: <20180313153458.26822-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180313153458.26822-1-peter.maydell@linaro.org> References: <20180313153458.26822-1-peter.maydell@linaro.org> If we're directly booting a Linux kernel and the CPU supports both EL3 and EL2, we start the kernel in EL2, as it expects. We must also set the SCR_EL3.HCE bit in this situation, so that the HVC instruction is enabled rather than UNDEFing. Otherwise at least some kernels will panic when trying to initialize KVM in the guest. Signed-off-by: Peter Maydell --- hw/arm/boot.c | 5 +++++ 1 file changed, 5 insertions(+) -- 2.16.2 diff --git a/hw/arm/boot.c b/hw/arm/boot.c index e21a92f972..9319b12fcd 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -729,6 +729,11 @@ static void do_cpu_reset(void *opaque) assert(!info->secure_board_setup); } + if (arm_feature(env, ARM_FEATURE_EL2)) { + /* If we have EL2 then Linux expects the HVC insn to work */ + env->cp15.scr_el3 |= SCR_HCE; + } + /* Set to non-secure if not a secure boot */ if (!info->secure_boot && (cs != first_cpu || !info->secure_board_setup)) { From patchwork Tue Mar 13 15:34:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 131477 Delivered-To: patches@linaro.org Received: by 10.46.84.17 with SMTP id i17csp884730ljb; Tue, 13 Mar 2018 08:35:04 -0700 (PDT) X-Google-Smtp-Source: AG47ELuGyPc+AV4M9Y7pFlkMnq1a9PNLqJsPu3rZV5QTibppXLwTsLqPFT7AY6kKgPoRwQ0DbGGF X-Received: by 10.223.152.141 with SMTP id w13mr995111wrb.12.1520955304340; Tue, 13 Mar 2018 08:35:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520955304; cv=none; d=google.com; s=arc-20160816; b=sWMg0AaFLU5N7PXkNzXQz9jnGv/1RuVYq0PTyw/qGVPI0vFkNGrAQV3BXPxNdBBuy6 V/wJSUsZpxN0Z77xagnHzoqjnX/PBO85XuUXfFOMu+xb0xhTF14Lqo6QEDcA/tQ3xm/6 jsqU3Z/77qg7RlFpa/ziULzxxBTDkVCjZ5J5uMDnFzhdOnoEHaOMIOI47Nt+3AnxkMZ+ 8VK7nhYMi1tmiDl4Esp2iYh4yVnvmHYju45xhVD40kvWx+M8EaPuUgBVFUqnb0wcQChj MP9Kcj1IZP5nsau7eEO9O/6jhnuzsYtscI4DOcs5uQJGJ1WhD/IR566e9+BEj0fzgOT8 oZGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=7q/S/h/s+d+0rvFHj5+iyJEKE2u2/qG5rNt6ixZ5Qrg=; b=q7TkHQEM/RuzB5KZ1H8zmt0m5DE9xTWB1dH5Z660tOjo+Ibmuv294XjoSFVOsKm1U3 S744fl28ldV8Ys5jKepI43agrTt4Yoq6ZIY31tHqVWXbcI/qco70wzSkLKGt8QowkolE 87jNvx+Oij88BwRv3vC13tjej5DjehHN/j1ackp/uoMIK1iqvlNvgjKSyyOtn8Q/3jL7 VVqx1+emzvkrB0jjwKHRotv/ROlCRzhUlIPiRXni1pkFkkYaaFyx5sRWl/GRiN6ppYGi tlevH4wsgjK+jz0XovxVCwLX7yBGTdvZNilDUDAncUW8xh+8rcJgzJv+vAGLKy1nKpXX Sj4w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 62si305321wra.342.2018.03.13.08.35.04 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Mar 2018 08:35:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1evlx9-0003F5-S1; Tue, 13 Mar 2018 15:35:03 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Pekka Enberg , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Andrew Baumann Subject: [PATCH 4/9] hw/arm/bcm2386: Fix parent type of bcm2386 Date: Tue, 13 Mar 2018 15:34:53 +0000 Message-Id: <20180313153458.26822-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180313153458.26822-1-peter.maydell@linaro.org> References: <20180313153458.26822-1-peter.maydell@linaro.org> The TypeInfo and state struct for bcm2386 disagree about what the parent class is -- the TypeInfo says it's TYPE_SYS_BUS_DEVICE, but the BCM2386State struct only defines the parent_obj field as DeviceState. This would have caused problems if anything actually tried to treat the object as a TYPE_SYS_BUS_DEVICE. Fix the TypeInfo to use TYPE_DEVICE as the parent, since we don't need any of the additional functionality TYPE_SYS_BUS_DEVICE provides. Signed-off-by: Peter Maydell --- I noticed this when I tried to make the type into one which has its own class struct, because we hit the assert that the child's class struct had better be bigger than the parent's. --- hw/arm/bcm2836.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.16.2 Reviewed-by: Andrew Baumann Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 40e8b25a46..9266f27c14 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -165,7 +165,7 @@ static void bcm2836_class_init(ObjectClass *oc, void *data) static const TypeInfo bcm2836_type_info = { .name = TYPE_BCM2836, - .parent = TYPE_SYS_BUS_DEVICE, + .parent = TYPE_DEVICE, .instance_size = sizeof(BCM2836State), .instance_init = bcm2836_init, .class_init = bcm2836_class_init, From patchwork Tue Mar 13 15:34:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 131478 Delivered-To: patches@linaro.org Received: by 10.46.84.17 with SMTP id i17csp884747ljb; Tue, 13 Mar 2018 08:35:05 -0700 (PDT) X-Google-Smtp-Source: AG47ELs5cZv5yAKiAWi/vpAEWZs1KCBhSBbwkime2PqGTdJNYiVNkRiIYtQYRStO6j1aqUaadIS3 X-Received: by 10.223.160.67 with SMTP id l3mr912153wrl.201.1520955305054; Tue, 13 Mar 2018 08:35:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520955305; cv=none; d=google.com; s=arc-20160816; b=Bg8rZwSK4oUB8c/KHvrms0qgrb/U/lszPuyvdSzut8COQJUj5y5ghYt3qNX3yGulSQ D92ULQYRkXjXM1rm3mAecKJE4mEeqfCgvjMn4uVWfa9KW934D3FmHE/XQdSnVFM10Tue sqlwOSce5hFght1GJaq90yGXk3y26SslKZdZL7sgTNhM1Lmo97Z3uPp7LmmajHumea+U aYaRlibxlOexqiPJufnHjITD7W3WljEiyjFl/54behz72ZzVJ28Ry3ocy4+iXk3ws7r9 PjYnoFIifXzqBNJC0w3dZQ4ChQi1v/C8WemwdLjrKD5FsQca0jqYgWUibQZ3VAD93UN0 CwSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=nsIGKyyFidvC+AdTqJMdTWp859RnsqAZbaUyJ4NXijo=; b=Ez0nE7tYrFj3y2xJXVYl14id6GyhAsESlNvLQMY40TRcAX57DqdJpyQX38PiPqCZY4 lEsyWfT03Md7/ShB0pDJK0V5oDXCmqzQjj8epqdNUHdQEfQsSVH6O8OGGDq07mkrj2iK pHs2N3mgOI6o02HILk04W2J3E/GQvr1NWc7k6W7LZWnMyNQthFANYUtpcLpb8VVjhQqJ dJ5dM9v15dmEcE35EEDNL6pd4kgAZGJ0Ojhzzc+cp9yuWQxYGPvrhUFoRbeHu4EXAiMv ZrYnp6HOiABIRF2tADBV06IQRF4zNPSwSGJPzJ+cL1LbvTbJB80SHjZzZ/OoLm6qFSgd M0GA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id s13si325319wrb.259.2018.03.13.08.35.04 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Mar 2018 08:35:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1evlxA-0003FQ-IQ; Tue, 13 Mar 2018 15:35:04 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Pekka Enberg , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Andrew Baumann Subject: [PATCH 5/9] hw/arm/bcm2836: Rename bcm2836 type/struct to bcm283x Date: Tue, 13 Mar 2018 15:34:54 +0000 Message-Id: <20180313153458.26822-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180313153458.26822-1-peter.maydell@linaro.org> References: <20180313153458.26822-1-peter.maydell@linaro.org> Our BCM2836 type is really a generic one that can be any of the bcm283x family. Rename it accordingly. We change only the names which are visible via the header file to the rest of the QEMU code, leaving private function names in bcm2836.c as they are. This is a preliminary to making bcm283x be an abstract parent class to specific types for the bcm2836 and bcm2837. Signed-off-by: Peter Maydell --- include/hw/arm/bcm2836.h | 12 ++++++------ hw/arm/bcm2836.c | 17 +++++++++-------- hw/arm/raspi.c | 16 ++++++++-------- 3 files changed, 23 insertions(+), 22 deletions(-) -- 2.16.2 Reviewed-by: Andrew Baumann Reviewed-by: Philippe Mathieu-Daudé diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h index 4758b4ae54..9a10a76631 100644 --- a/include/hw/arm/bcm2836.h +++ b/include/hw/arm/bcm2836.h @@ -15,12 +15,12 @@ #include "hw/arm/bcm2835_peripherals.h" #include "hw/intc/bcm2836_control.h" -#define TYPE_BCM2836 "bcm2836" -#define BCM2836(obj) OBJECT_CHECK(BCM2836State, (obj), TYPE_BCM2836) +#define TYPE_BCM283X "bcm283x" +#define BCM283X(obj) OBJECT_CHECK(BCM283XState, (obj), TYPE_BCM283X) -#define BCM2836_NCPUS 4 +#define BCM283X_NCPUS 4 -typedef struct BCM2836State { +typedef struct BCM283XState { /*< private >*/ DeviceState parent_obj; /*< public >*/ @@ -28,9 +28,9 @@ typedef struct BCM2836State { char *cpu_type; uint32_t enabled_cpus; - ARMCPU cpus[BCM2836_NCPUS]; + ARMCPU cpus[BCM283X_NCPUS]; BCM2836ControlState control; BCM2835PeripheralState peripherals; -} BCM2836State; +} BCM283XState; #endif /* BCM2836_H */ diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 9266f27c14..1d1908654b 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -25,7 +25,7 @@ static void bcm2836_init(Object *obj) { - BCM2836State *s = BCM2836(obj); + BCM283XState *s = BCM283X(obj); object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL); object_property_add_child(obj, "control", OBJECT(&s->control), NULL); @@ -44,7 +44,7 @@ static void bcm2836_init(Object *obj) static void bcm2836_realize(DeviceState *dev, Error **errp) { - BCM2836State *s = BCM2836(dev); + BCM283XState *s = BCM283X(dev); Object *obj; Error *err = NULL; int n; @@ -52,7 +52,7 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) /* common peripherals from bcm2835 */ obj = OBJECT(dev); - for (n = 0; n < BCM2836_NCPUS; n++) { + for (n = 0; n < BCM283X_NCPUS; n++) { object_initialize(&s->cpus[n], sizeof(s->cpus[n]), s->cpu_type); object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]), @@ -102,7 +102,7 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->peripherals), 1, qdev_get_gpio_in_named(DEVICE(&s->control), "gpu-fiq", 0)); - for (n = 0; n < BCM2836_NCPUS; n++) { + for (n = 0; n < BCM283X_NCPUS; n++) { /* Mirror bcm2836, which has clusterid set to 0xf * TODO: this should be converted to a property of ARM_CPU */ @@ -150,8 +150,9 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) } static Property bcm2836_props[] = { - DEFINE_PROP_STRING("cpu-type", BCM2836State, cpu_type), - DEFINE_PROP_UINT32("enabled-cpus", BCM2836State, enabled_cpus, BCM2836_NCPUS), + DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type), + DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, + BCM283X_NCPUS), DEFINE_PROP_END_OF_LIST() }; @@ -164,9 +165,9 @@ static void bcm2836_class_init(ObjectClass *oc, void *data) } static const TypeInfo bcm2836_type_info = { - .name = TYPE_BCM2836, + .name = TYPE_BCM283X, .parent = TYPE_DEVICE, - .instance_size = sizeof(BCM2836State), + .instance_size = sizeof(BCM283XState), .instance_init = bcm2836_init, .class_init = bcm2836_class_init, }; diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 1ac0737149..58c6e80a17 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -32,7 +32,7 @@ static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44}; typedef struct RasPiState { - BCM2836State soc; + BCM283XState soc; MemoryRegion ram; } RasPiState; @@ -136,7 +136,7 @@ static void raspi_init(MachineState *machine, int version) BusState *bus; DeviceState *carddev; - object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM2836); + object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X); object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), &error_abort); @@ -189,9 +189,9 @@ static void raspi2_machine_init(MachineClass *mc) mc->no_floppy = 1; mc->no_cdrom = 1; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); - mc->max_cpus = BCM2836_NCPUS; - mc->min_cpus = BCM2836_NCPUS; - mc->default_cpus = BCM2836_NCPUS; + mc->max_cpus = BCM283X_NCPUS; + mc->min_cpus = BCM283X_NCPUS; + mc->default_cpus = BCM283X_NCPUS; mc->default_ram_size = 1024 * 1024 * 1024; mc->ignore_memory_transaction_failures = true; }; @@ -212,9 +212,9 @@ static void raspi3_machine_init(MachineClass *mc) mc->no_floppy = 1; mc->no_cdrom = 1; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"); - mc->max_cpus = BCM2836_NCPUS; - mc->min_cpus = BCM2836_NCPUS; - mc->default_cpus = BCM2836_NCPUS; + mc->max_cpus = BCM283X_NCPUS; + mc->min_cpus = BCM283X_NCPUS; + mc->default_cpus = BCM283X_NCPUS; mc->default_ram_size = 1024 * 1024 * 1024; } DEFINE_MACHINE("raspi3", raspi3_machine_init) From patchwork Tue Mar 13 15:34:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 131479 Delivered-To: patches@linaro.org Received: by 10.46.84.17 with SMTP id i17csp884766ljb; Tue, 13 Mar 2018 08:35:05 -0700 (PDT) X-Google-Smtp-Source: AG47ELshb+zwPmMX48n65mavtyNS0Sc6h38GtRwJvT88zeL4apcpHCCz7wbYQwcwPCS1xZEuDcfy X-Received: by 10.223.196.204 with SMTP id o12mr997411wrf.121.1520955305790; Tue, 13 Mar 2018 08:35:05 -0700 (PDT) ARC-Seal: i=1; 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[2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 136si291524wms.222.2018.03.13.08.35.05 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Mar 2018 08:35:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1evlxB-0003Fi-98; Tue, 13 Mar 2018 15:35:05 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Pekka Enberg , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Andrew Baumann Subject: [PATCH 6/9] hw/arm/bcm2836: Create proper bcm2837 device Date: Tue, 13 Mar 2018 15:34:55 +0000 Message-Id: <20180313153458.26822-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180313153458.26822-1-peter.maydell@linaro.org> References: <20180313153458.26822-1-peter.maydell@linaro.org> The bcm2837 is pretty similar to the bcm2836, but it does have some differences. Notably, the MPIDR affinity aff1 values it sets for the CPUs are 0x0, rather than the 0xf that the bcm2836 uses, and if this is wrong Linux will not boot. Rather than trying to have one device with properties that configure it differently for the two cases, create two separate QOM devices for the two SoCs. We use the same approach as hw/arm/aspeed_soc.c and share code and have a data table that might differ per-SoC. For the moment the two types don't actually have different behaviour. Signed-off-by: Peter Maydell --- include/hw/arm/bcm2836.h | 19 +++++++++++++++++++ hw/arm/bcm2836.c | 37 ++++++++++++++++++++++++++++++++----- hw/arm/raspi.c | 3 ++- 3 files changed, 53 insertions(+), 6 deletions(-) -- 2.16.2 Reviewed-by: Philippe Mathieu-Daudé diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h index 9a10a76631..93248399ba 100644 --- a/include/hw/arm/bcm2836.h +++ b/include/hw/arm/bcm2836.h @@ -20,6 +20,13 @@ #define BCM283X_NCPUS 4 +/* These type names are for specific SoCs; other than instantiating + * them, code using these devices should always handle them via the + * BCM283x base class, so they have no BCM2836(obj) etc macros. + */ +#define TYPE_BCM2836 "bcm2836" +#define TYPE_BCM2837 "bcm2837" + typedef struct BCM283XState { /*< private >*/ DeviceState parent_obj; @@ -33,4 +40,16 @@ typedef struct BCM283XState { BCM2835PeripheralState peripherals; } BCM283XState; +typedef struct BCM283XInfo BCM283XInfo; + +typedef struct BCM283XClass { + DeviceClass parent_class; + const BCM283XInfo *info; +} BCM283XClass; + +#define BCM283X_CLASS(klass) \ + OBJECT_CLASS_CHECK(BCM283XClass, (klass), TYPE_BCM283X) +#define BCM283X_GET_CLASS(obj) \ + OBJECT_GET_CLASS(BCM283XClass, (obj), TYPE_BCM283X) + #endif /* BCM2836_H */ diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 1d1908654b..07d2705f96 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -23,6 +23,19 @@ /* "QA7" (Pi2) interrupt controller and mailboxes etc. */ #define BCM2836_CONTROL_BASE 0x40000000 +struct BCM283XInfo { + const char *name; +}; + +static const BCM283XInfo bcm283x_socs[] = { + { + .name = TYPE_BCM2836, + }, + { + .name = TYPE_BCM2837, + }, +}; + static void bcm2836_init(Object *obj) { BCM283XState *s = BCM283X(obj); @@ -156,25 +169,39 @@ static Property bcm2836_props[] = { DEFINE_PROP_END_OF_LIST() }; -static void bcm2836_class_init(ObjectClass *oc, void *data) +static void bcm283x_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); + BCM283XClass *bc = BCM283X_CLASS(oc); - dc->props = bcm2836_props; + bc->info = data; dc->realize = bcm2836_realize; + dc->props = bcm2836_props; } -static const TypeInfo bcm2836_type_info = { +static const TypeInfo bcm283x_type_info = { .name = TYPE_BCM283X, .parent = TYPE_DEVICE, .instance_size = sizeof(BCM283XState), .instance_init = bcm2836_init, - .class_init = bcm2836_class_init, + .class_size = sizeof(BCM283XClass), + .abstract = true, }; static void bcm2836_register_types(void) { - type_register_static(&bcm2836_type_info); + int i; + + type_register_static(&bcm283x_type_info); + for (i = 0; i < ARRAY_SIZE(bcm283x_socs); i++) { + TypeInfo ti = { + .name = bcm283x_socs[i].name, + .parent = TYPE_BCM283X, + .class_init = bcm283x_class_init, + .class_data = (void *) &bcm283x_socs[i], + }; + type_register(&ti); + } } type_init(bcm2836_register_types) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 58c6e80a17..f588720138 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -136,7 +136,8 @@ static void raspi_init(MachineState *machine, int version) BusState *bus; DeviceState *carddev; - object_initialize(&s->soc, sizeof(s->soc), TYPE_BCM283X); + object_initialize(&s->soc, sizeof(s->soc), + version == 3 ? TYPE_BCM2837 : TYPE_BCM2836); object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), &error_abort); From patchwork Tue Mar 13 15:34:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 131480 Delivered-To: patches@linaro.org Received: by 10.46.84.17 with SMTP id i17csp884782ljb; Tue, 13 Mar 2018 08:35:06 -0700 (PDT) X-Google-Smtp-Source: AG47ELs4FGrUIKI+z4nI4cTr6qgEsOOAFrdZTtR6ck8WH6IapPWiBc3d1fxI68odiFbChmbBQ80/ X-Received: by 10.28.54.89 with SMTP id d86mr1221668wma.16.1520955306462; Tue, 13 Mar 2018 08:35:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520955306; cv=none; d=google.com; s=arc-20160816; b=shUQYHwHY/Q6VmJ5Nyd9Y8y1RuTF7lt6nOzsGPz3MOZeg7NTvbnf0p4zgtdUckViZR 007WYlB4poon/z7C5saNuzD9e0eKgqAOMfqLUv7sIFnNHwsJY9IhwMAFacM7bbELmzix 1GZKC36yzZ91IHc9PG3I/GBKryAAHqV0dJNrKUUd5S/qaOBmZnJnDJkX28QKWLWI9ljz DqpaMo5d5nZ1iENVPb3IIz2kBmC0eQpRHGX8bxAgIaG9QM65lhwEjd6OHHgkLyTT8oMb Qjyk7b30w849m9tlEM5Y7yQFTyYBrfhg+7Md6Fl4xYkSolF4hDkCrcGRAIatBTjdubw5 jeqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=9BteupbPsug9iUj+zZyvMYumndQ+T8rwze+rfs5/KPY=; b=gN5SUVjJARGX4osW8ScuwRnHUD7yXBAMHVHr3D9BAUHFXfMm8v/m3u0rrYA/KUgG32 Q7/s56ORm1jlVGsAdyPrLNAsqp4FF129S1GwnjcBCiMhJL5ZZE7NCs1eMO08pqUqvlc6 B/zXmy1NBSlX63d6Mk35/lPgHAIaTFtVGMGyAfk8b0HL85A0Z3JB7sdM2W/FPaq0aHpH aBUKFeBnWLDGv2D2TCe+zWnHXya+kJ2OUST05pDZfjkqLQmbxURi1gc89/q4VZljRUft 2zQK609OgJNz4zDX63I2GUhpPhuZj/r1gKsW172pE3JGFcb7jQ0e9+JPw+Kt4mLUPs+m QYzA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id k2si119108wmf.153.2018.03.13.08.35.06 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Mar 2018 08:35:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1evlxC-0003G0-0N; Tue, 13 Mar 2018 15:35:06 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Pekka Enberg , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Andrew Baumann Subject: [PATCH 7/9] hw/arm/bcm2836: Use correct affinity values for BCM2837 Date: Tue, 13 Mar 2018 15:34:56 +0000 Message-Id: <20180313153458.26822-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180313153458.26822-1-peter.maydell@linaro.org> References: <20180313153458.26822-1-peter.maydell@linaro.org> The BCM2837 sets the Aff1 field of the MPIDR affinity values for the CPUs to 0, whereas the BCM2836 uses 0xf. Set this correctly, as it is required for Linux to boot. Signed-off-by: Peter Maydell --- hw/arm/bcm2836.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.16.2 Reviewed-by: Andrew Baumann Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 07d2705f96..7140257c98 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -25,14 +25,17 @@ struct BCM283XInfo { const char *name; + int clusterid; }; static const BCM283XInfo bcm283x_socs[] = { { .name = TYPE_BCM2836, + .clusterid = 0xf, }, { .name = TYPE_BCM2837, + .clusterid = 0x0, }, }; @@ -58,6 +61,8 @@ static void bcm2836_init(Object *obj) static void bcm2836_realize(DeviceState *dev, Error **errp) { BCM283XState *s = BCM283X(dev); + BCM283XClass *bc = BCM283X_GET_CLASS(dev); + const BCM283XInfo *info = bc->info; Object *obj; Error *err = NULL; int n; @@ -119,7 +124,7 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) /* Mirror bcm2836, which has clusterid set to 0xf * TODO: this should be converted to a property of ARM_CPU */ - s->cpus[n].mp_affinity = 0xF00 | n; + s->cpus[n].mp_affinity = (info->clusterid << 8) | n; /* set periphbase/CBAR value for CPU-local registers */ object_property_set_int(OBJECT(&s->cpus[n]), From patchwork Tue Mar 13 15:34:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 131481 Delivered-To: patches@linaro.org Received: by 10.46.84.17 with SMTP id i17csp884796ljb; Tue, 13 Mar 2018 08:35:07 -0700 (PDT) X-Google-Smtp-Source: AG47ELvxH2raNeu5JbMT4l0MDEB4EKf0VSFdqH4l9ubJXdxUuVUkIyHGRgOlKtndk9Xju1UaQKgF X-Received: by 10.223.158.196 with SMTP id b4mr1006392wrf.112.1520955307195; Tue, 13 Mar 2018 08:35:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520955307; cv=none; d=google.com; s=arc-20160816; b=Ze6BVnSd3BDwlpZTylXGIM/UFJQ5/ZLHtIuJJpojsNmGzJ1Z1c5TA/uQaSyZEkpdL+ ewDI4y8Y1oxIE/HKctVANii1TVUczt3sq/4p0HdOvDYl05nomq5YC4dDEK0NIiNUkmzp MGz9n11T0neY4hlLQGZXT3AB35e3TiY/4oSxWKfFaEAIN9+Ic7FSe3YhPC+N5e8UQhvc kDhfyxvVajWKbYtfFOfXthkBhkMGFM7mtMxhBBYklKNHO5eVUlYOnTiBFS3UBkuXtqm/ hNZfRQYWmi8pS2LVrLvGf5uAaCXduTA5xlI9+AAjIVK56ho2mc7XdNz8bztDc2kUjZYN Ow4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=2e9tgmjPvIR2v7LocAzMQtkqqdh+4SwQiNDQfF5WJJc=; b=lku3eWcuxi6bnFoBFUdvtmTIA27KOlQTsmYGs2jTDgquYQVg8Bmgkc3rSQvEw6oLxt we+ruERlFNba0ules7rMSUvKp902YobDOPLAezpjU/tcA3HFVSiebOhwvHNb7dYSibg7 GpXPK+q8ARwT+vbByvb607k05/ZEtt8RoXkjJC9itLaWb8HRY+tjggiRE2La1eRClywR Y77E3i/MuW481mJpmyOgh5sr+M2pfTbQr6J3YMgjW13elKrLpfu9j6W2Ffwg8dZpDPpD Jo341dyKu96np8lmDOHdKP0aT7eAHB4oX5GYkd8Hazt6MQwYbBb+bpo/CWiTZb158yqD eKvw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id p26si313338wrp.224.2018.03.13.08.35.07 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Mar 2018 08:35:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1evlxC-0003GI-Ne; Tue, 13 Mar 2018 15:35:06 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Pekka Enberg , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Andrew Baumann Subject: [PATCH 8/9] hw/arm/bcm2836: Hardcode correct CPU type Date: Tue, 13 Mar 2018 15:34:57 +0000 Message-Id: <20180313153458.26822-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180313153458.26822-1-peter.maydell@linaro.org> References: <20180313153458.26822-1-peter.maydell@linaro.org> Now we have separate types for BCM2386 and BCM2387, we might as well just hard-code the CPU type they use rather than having it passed through as an object property. This then lets us put the initialization of the CPU object in init rather than realize. Signed-off-by: Peter Maydell --- hw/arm/bcm2836.c | 22 +++++++++++++--------- hw/arm/raspi.c | 2 -- 2 files changed, 13 insertions(+), 11 deletions(-) -- 2.16.2 Reviewed-by: Andrew Baumann Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 7140257c98..12f75b55a7 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -25,16 +25,19 @@ struct BCM283XInfo { const char *name; + const char *cpu_type; int clusterid; }; static const BCM283XInfo bcm283x_socs[] = { { .name = TYPE_BCM2836, + .cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"), .clusterid = 0xf, }, { .name = TYPE_BCM2837, + .cpu_type = ARM_CPU_TYPE_NAME("cortex-a53"), .clusterid = 0x0, }, }; @@ -42,6 +45,16 @@ static const BCM283XInfo bcm283x_socs[] = { static void bcm2836_init(Object *obj) { BCM283XState *s = BCM283X(obj); + BCM283XClass *bc = BCM283X_GET_CLASS(obj); + const BCM283XInfo *info = bc->info; + int n; + + for (n = 0; n < BCM283X_NCPUS; n++) { + object_initialize(&s->cpus[n], sizeof(s->cpus[n]), + info->cpu_type); + object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]), + &error_abort); + } object_initialize(&s->control, sizeof(s->control), TYPE_BCM2836_CONTROL); object_property_add_child(obj, "control", OBJECT(&s->control), NULL); @@ -69,14 +82,6 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) /* common peripherals from bcm2835 */ - obj = OBJECT(dev); - for (n = 0; n < BCM283X_NCPUS; n++) { - object_initialize(&s->cpus[n], sizeof(s->cpus[n]), - s->cpu_type); - object_property_add_child(obj, "cpu[*]", OBJECT(&s->cpus[n]), - &error_abort); - } - obj = object_property_get_link(OBJECT(dev), "ram", &err); if (obj == NULL) { error_setg(errp, "%s: required ram link not found: %s", @@ -168,7 +173,6 @@ static void bcm2836_realize(DeviceState *dev, Error **errp) } static Property bcm2836_props[] = { - DEFINE_PROP_STRING("cpu-type", BCM283XState, cpu_type), DEFINE_PROP_UINT32("enabled-cpus", BCM283XState, enabled_cpus, BCM283X_NCPUS), DEFINE_PROP_END_OF_LIST() diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index f588720138..ae15997669 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -150,8 +150,6 @@ static void raspi_init(MachineState *machine, int version) /* Setup the SOC */ object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram), &error_abort); - object_property_set_str(OBJECT(&s->soc), machine->cpu_type, "cpu-type", - &error_abort); object_property_set_int(OBJECT(&s->soc), smp_cpus, "enabled-cpus", &error_abort); int board_rev = version == 3 ? 0xa02082 : 0xa21041; From patchwork Tue Mar 13 15:34:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 131483 Delivered-To: patches@linaro.org Received: by 10.46.84.17 with SMTP id i17csp884822ljb; Tue, 13 Mar 2018 08:35:08 -0700 (PDT) X-Google-Smtp-Source: AG47ELvghZYahfM3gtiQHT1D9iEXhLTF2WxcxHebPAkvL72hZ1p8d5jbDp+AJub3Wm7EjzzIVSQT X-Received: by 10.223.153.45 with SMTP id x42mr1022437wrb.124.1520955307977; Tue, 13 Mar 2018 08:35:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1520955307; cv=none; d=google.com; s=arc-20160816; b=Rdn39d4DeXdvW03rTmH0ZLucRKd9uV5VsqpYEKPYouyUw0h0pDl8qanRz526tlMkU5 xeTFJ6Q6jujlcv0y2t2bUjwzihaiF3HrbmXkfUn3k7jeP6mjkRqED/G3AoPoKnrF5sFv EAUAeHEIPStw8qdweWC5GUaip1cRyxdvr3eTE+wx/a9Kq45xyoFDkkZUa1Q7FYYaq7pH wShJd16m9+G7hA7uVYjqO7BdARyEz1z03UZixmVvJPm16yJnXujvhlJR9TgG6KMR4GpB PzZ8uvu+hvGMjsEqQV/n0FlbS/7nJ+81xWStQt7yH7RDCGbm6Z2scv6nmRNuZgrDlcZ5 kRpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=CvnRNeh6ibfMrYNuS93D15H2Eb2EK4mAY4BMUSe1ppY=; b=pgPw9c5hLVd3K6++8rlcybBGbxAkHczCmXaOZ0ZzA4Zyo+HZsEbR/Ul0+Gn3zPStvS W10hk2ulgqG01xKhIr6wEMBm+YkwHUVqwXCkU2YStO0twQe8B+qYtbjK6V1PKRk+Xj9r nQiXtM1IzFWo9zAVnYVs9sUpgL3fLRm7Yq8k7A60bmlcDrRrmYBjgwYBAgHLUfGmBp28 l7x4Tf6I5b7pIc8TF/jlA6Csbvp27J+BpPunCLj6oM9ts/0xaaUAXoEo0HMpsf7O76lk LbeNnYgalI9p/EUw66a49sFm+J3lfQDVoDOSOeGeV3eJW1BkFCF22s0Z4StwamRdvFNA WaMA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 198si299650wmo.87.2018.03.13.08.35.07 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Mar 2018 08:35:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1evlxD-0003Gh-Gd; Tue, 13 Mar 2018 15:35:07 +0000 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, Pekka Enberg , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Andrew Baumann Subject: [PATCH 9/9] hw/arm/raspi: Provide spin-loop code for AArch64 CPUs Date: Tue, 13 Mar 2018 15:34:58 +0000 Message-Id: <20180313153458.26822-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180313153458.26822-1-peter.maydell@linaro.org> References: <20180313153458.26822-1-peter.maydell@linaro.org> The raspi3 has AArch64 CPUs, which means that our smpboot code for keeping the secondary CPUs in a pen needs to have a version for A64 as well as A32. Without this, the secondary CPUs go into an infinite loop of taking undefined instruction exceptions. Signed-off-by: Peter Maydell --- hw/arm/raspi.c | 41 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) -- 2.16.2 Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index ae15997669..06f1e08ca9 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -27,6 +27,7 @@ #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */ #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */ #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */ +#define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */ /* Table of Linux board IDs for different Pi versions */ static const int raspi_boardid[] = {[1] = 0xc42, [2] = 0xc43, [3] = 0xc44}; @@ -63,6 +64,40 @@ static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info) info->smp_loader_start); } +static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info) +{ + /* Unlike the AArch32 version we don't need to call the board setup hook. + * The mechanism for doing the spin-table is also entirely different. + * We must have four 64-bit fields at absolute addresses + * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for + * our CPUs, and which we must ensure are zero initialized before + * the primary CPU goes into the kernel. We put these variables inside + * a rom blob, so that the reset for ROM contents zeroes them for us. + */ + static const uint32_t smpboot[] = { + 0xd2801b05, /* mov x5, 0xd8 */ + 0xd53800a6, /* mrs x6, mpidr_el1 */ + 0x924004c6, /* and x6, x6, #0x3 */ + 0xd503205f, /* spin: wfe */ + 0xf86678a4, /* ldr x4, [x5,x6,lsl #3] */ + 0xb4ffffc4, /* cbz x4, spin */ + 0xd2800000, /* mov x0, #0x0 */ + 0xd2800001, /* mov x1, #0x0 */ + 0xd2800002, /* mov x2, #0x0 */ + 0xd2800003, /* mov x3, #0x0 */ + 0xd61f0080, /* br x4 */ + }; + + static const uint64_t spintables[] = { + 0, 0, 0, 0 + }; + + rom_add_blob_fixed("raspi_smpboot", smpboot, sizeof(smpboot), + info->smp_loader_start); + rom_add_blob_fixed("raspi_spintables", spintables, sizeof(spintables), + SPINTABLE_ADDR); +} + static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info) { arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR); @@ -99,7 +134,11 @@ static void setup_boot(MachineState *machine, int version, size_t ram_size) /* Pi2 and Pi3 requires SMP setup */ if (version >= 2) { binfo.smp_loader_start = SMPBOOT_ADDR; - binfo.write_secondary_boot = write_smpboot; + if (version == 2) { + binfo.write_secondary_boot = write_smpboot; + } else { + binfo.write_secondary_boot = write_smpboot64; + } binfo.secondary_cpu_reset_hook = reset_secondary; }