From patchwork Tue Apr 4 06:12:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Amit Pundir X-Patchwork-Id: 96663 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp46767qgd; Mon, 3 Apr 2017 23:12:54 -0700 (PDT) X-Received: by 10.84.197.131 with SMTP id n3mr26352775pld.43.1491286374789; Mon, 03 Apr 2017 23:12:54 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f1si16391190pln.331.2017.04.03.23.12.54; Mon, 03 Apr 2017 23:12:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751031AbdDDGMy (ORCPT + 6 others); Tue, 4 Apr 2017 02:12:54 -0400 Received: from mail-pg0-f46.google.com ([74.125.83.46]:34843 "EHLO mail-pg0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750926AbdDDGMx (ORCPT ); Tue, 4 Apr 2017 02:12:53 -0400 Received: by mail-pg0-f46.google.com with SMTP id 81so142591032pgh.2 for ; Mon, 03 Apr 2017 23:12:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Cg3yR7bGqv3Lnjpf7dVccuebwulzk+7RQuTL0CiOhJA=; b=G+M/cTOGuwd4/YVjbGAmRIiE9ueILBFl7cH+fartAxaeLMb/9eSzTfo/uVXYmOUd3A eYK22bkX2y/Z5pXUhIoqP9v3YN6u6wDY0RbWafnnEwB0TkjdBSD6IYrkdVpSguxZxMra EQIrAsGXPkOvQrLtpX+046Sx4qcgg8on02VAk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Cg3yR7bGqv3Lnjpf7dVccuebwulzk+7RQuTL0CiOhJA=; b=Wvd0ihoIBTzgdPX6OtV3+/0xWdThbQHkLe6CBEbMf0smdJc23Qo4/QRMEHb68fCx89 vnn8DTVY2nxNuDsSpmvq87cMrol62UN+sQJd/FXykW66VxQDjZLrdRLVUGHBk41bvzGn te95kFTehHE8vzJpqA7rGBkDDNsyeFWnnoG0deikAMDsG/AM2IHI7aE7ULl4K9KKlUGd HjHA1G+OxywawOjy7lGJbS99+oniGvpt0t0N30pM6YVVuhtHYTb5Vn3q5Hr5zpzhwCyi n9fWUMTX9jRuYfRtYI/fH9mVdbPFf5YWqmgHng8Kpd73pH9sMRk5i34PhFC3hBBcydKG 990A== X-Gm-Message-State: AFeK/H1toh0+fohSvbHDcI8pDKd2/FqJWKcdTHWGTav4HzFVrK3oAa/DUcsxWiJInS7kqpAY X-Received: by 10.84.208.227 with SMTP id c32mr26768337plj.71.1491286372742; Mon, 03 Apr 2017 23:12:52 -0700 (PDT) Received: from localhost.localdomain ([106.51.240.246]) by smtp.gmail.com with ESMTPSA id p9sm29164025pfe.22.2017.04.03.23.12.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 03 Apr 2017 23:12:52 -0700 (PDT) From: Amit Pundir To: gregkh@linuxfoundation.org Cc: stable@vger.kernel.org, =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Florian Fainelli Subject: [PATCH 01/33] ARM: BCM5301X: Add back handler ignoring external imprecise aborts Date: Tue, 4 Apr 2017 11:42:14 +0530 Message-Id: <1491286366-30720-2-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491286366-30720-1-git-send-email-amit.pundir@linaro.org> References: <1491286366-30720-1-git-send-email-amit.pundir@linaro.org> MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Rafał Miłecki Since early BCM5301X days we got abort handler that was removed by commit 937b12306ea79 ("ARM: BCM5301X: remove workaround imprecise abort fault handler"). It assumed we need to deal only with pending aborts left by the bootloader. Unfortunately this isn't true for BCM5301X. When probing PCI config space (device enumeration) it is expected to have master aborts on the PCI bus. Most bridges don't forward (or they allow disabling it) these errors onto the AXI/AMBA bus but not the Northstar (BCM5301X) one. iProc PCIe controller on Northstar seems to be some older one, without a control register for errors forwarding. It means we need to workaround this at platform level. All newer platforms are not affected by this issue. Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli (cherry picked from commit 09f3510fb70a46c8921f2cf4a90dbcae460a6820) Signed-off-by: Amit Pundir --- arch/arm/mach-bcm/bcm_5301x.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) -- 2.7.4 diff --git a/arch/arm/mach-bcm/bcm_5301x.c b/arch/arm/mach-bcm/bcm_5301x.c index c8830a2..fe067f6 100644 --- a/arch/arm/mach-bcm/bcm_5301x.c +++ b/arch/arm/mach-bcm/bcm_5301x.c @@ -9,14 +9,42 @@ #include #include +#include +#include + +#define FSR_EXTERNAL (1 << 12) +#define FSR_READ (0 << 10) +#define FSR_IMPRECISE 0x0406 static const char *const bcm5301x_dt_compat[] __initconst = { "brcm,bcm4708", NULL, }; +static int bcm5301x_abort_handler(unsigned long addr, unsigned int fsr, + struct pt_regs *regs) +{ + /* + * We want to ignore aborts forwarded from the PCIe bus that are + * expected and shouldn't really be passed by the PCIe controller. + * The biggest disadvantage is the same FSR code may be reported when + * reading non-existing APB register and we shouldn't ignore that. + */ + if (fsr == (FSR_EXTERNAL | FSR_READ | FSR_IMPRECISE)) + return 0; + + return 1; +} + +static void __init bcm5301x_init_early(void) +{ + hook_fault_code(16 + 6, bcm5301x_abort_handler, SIGBUS, BUS_OBJERR, + "imprecise external abort"); +} + DT_MACHINE_START(BCM5301X, "BCM5301X") .l2c_aux_val = 0, .l2c_aux_mask = ~0, .dt_compat = bcm5301x_dt_compat, + .init_early = bcm5301x_init_early, MACHINE_END From patchwork Tue Apr 4 06:12:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Amit Pundir X-Patchwork-Id: 96664 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp46769qgd; Mon, 3 Apr 2017 23:12:57 -0700 (PDT) X-Received: by 10.84.232.77 with SMTP id f13mr26650404pln.95.1491286376999; Mon, 03 Apr 2017 23:12:56 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f1si16391190pln.331.2017.04.03.23.12.56; Mon, 03 Apr 2017 23:12:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751052AbdDDGM4 (ORCPT + 6 others); Tue, 4 Apr 2017 02:12:56 -0400 Received: from mail-pg0-f42.google.com ([74.125.83.42]:33048 "EHLO mail-pg0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751018AbdDDGMz (ORCPT ); Tue, 4 Apr 2017 02:12:55 -0400 Received: by mail-pg0-f42.google.com with SMTP id x125so142440207pgb.0 for ; Mon, 03 Apr 2017 23:12:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kXGTMSAGFQOdutcYGxVXPwmAcbfA+XwQuU4y0wUDkRI=; b=G9t0dIS3Wb/+GEH87XIaWr5Zlqwd9kKwFXndjJ3KENI+CfBDiOUMTHbO8b2GeodKzn 5QsmR7QJymCru/IV/b6sDvjSxWZW98TDHh+EQ4d5+9dx5RDSwf3V0HRhYZ0NCK5fOKGt ghRbBhI6VViOor5RbHqr6hy+6/TNFRjFPtVkU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kXGTMSAGFQOdutcYGxVXPwmAcbfA+XwQuU4y0wUDkRI=; b=FFiWWxCgPqOBIL0eS3RpxBL2oVa7nwL/mLWKJBV6J48iuX2PPR5yo+nti6ThEr59sg VMIvbzmddhJFbJ3/E6tpp9nWMMOsLmb41DJGCuJJ3lMINSxIrmf7Ypa4PezJozc0d23/ Pa4bYGhnEt8YWZ8WYiUZOwHBL+diE7CdkR//RYWCnPIhueRWLpCQVnL3KEN7wUfFleWw FwUgj7BzYqY1ZlaUmRqTuQBCsOdCk0V/Bjj4VbayhmxOxgOYvnIyfde7WSUuQwg3QYiU zQEKoVJW7L4ognhaxCALzI8dV9CYs+GsoLkcGxdUFvH7N90eOP8FPobgvgGSeYSqMRm2 pF/Q== X-Gm-Message-State: AFeK/H0D3l14RzqW/gnuofa/psvM7SKeZGtT7FywZIEEyXckg4HsMmjW6IHttEW9klzHzQAG X-Received: by 10.99.218.69 with SMTP id l5mr21940222pgj.219.1491286374921; Mon, 03 Apr 2017 23:12:54 -0700 (PDT) Received: from localhost.localdomain ([106.51.240.246]) by smtp.gmail.com with ESMTPSA id p9sm29164025pfe.22.2017.04.03.23.12.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 03 Apr 2017 23:12:54 -0700 (PDT) From: Amit Pundir To: gregkh@linuxfoundation.org Cc: stable@vger.kernel.org, =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Florian Fainelli Subject: [PATCH 02/33] ARM: dts: BCM5301X: Set 5 GHz wireless frequency limits on Netgear R8000 Date: Tue, 4 Apr 2017 11:42:15 +0530 Message-Id: <1491286366-30720-3-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491286366-30720-1-git-send-email-amit.pundir@linaro.org> References: <1491286366-30720-1-git-send-email-amit.pundir@linaro.org> MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Rafał Miłecki Netgear R8000 is a tri-band home router. It has three BCM43602 chipsets two of them for 5 GHz band. Both seem the same and their firmwares report the same set of channels. The problem is due to hardware / board design there are extra limitations that should be respected. First PHY should be used for U-NII-2 and U-NII-3. Third PHY should be used for U-NII-1. Using them in a different way may result in wireless not working or in noticeably reduced performance. Basic version of this info was provided by Broadcom employee, then it has been verified by me using original vendor firmware (which has limitations hardcoded in UI). This patch uses recently introduced ieee80211-freq-limit property to describe these limitations at DT level. Referencing PCIe devices in DT required specifying all related bridges. Below you can see (a bit complex) PCI tree from R8000 that explains all entries that I needed to put in DT. 0000:00:00.0 14e4:8012 Bridge Device └─ 0000:01:00.0 14e4:aa52 Network Controller 0001:00:00.0 14e4:8012 Bridge Device └─ 0001:01:00.0 10b5:8603 Bridge Device ├─ 0001:02:01.0 10b5:8603 Bridge Device │ └─ 0001:03:00.0 14e4:aa52 Network Controller ├─ 0001:02:02.0 10b5:8603 Bridge Device │ └─ 0001:04:00.0 14e4:aa52 Network Controller ├─ 0001:02:03.0 000d:0000 0x000000 ├─ 0001:02:04.0 000d:0000 0x000000 ├─ 0001:02:05.0 000d:0000 0x000000 ├─ 0001:02:06.0 000d:0000 0x000000 ├─ (...) ├─ 0001:02:1d.0 000d:0000 0x000000 ├─ 0001:02:1e.0 000d:0000 0x000000 └─ 0001:02:1f.0 000d:0000 0x000000 Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli (cherry picked from commit 5d1f2d2c253037a5d89b48347d90868fa9407102) Signed-off-by: Amit Pundir --- arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 48 +++++++++++++++++++++++++++++ arch/arm/boot/dts/bcm5301x.dtsi | 8 +++++ 2 files changed, 56 insertions(+) -- 2.7.4 diff --git a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts index ca18151..3551718 100644 --- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts @@ -107,6 +107,54 @@ }; }; +&pcie0 { + #address-cells = <3>; + #size-cells = <2>; + + bridge@0,0,0 { + reg = <0x0000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + + wifi@0,1,0 { + reg = <0x0000 0 0 0 0>; + ieee80211-freq-limit = <5735000 5835000>; + }; + }; +}; + +&pcie1 { + #address-cells = <3>; + #size-cells = <2>; + + bridge@1,0,0 { + reg = <0x0000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + + bridge@1,1,0 { + reg = <0x0000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + + bridge@1,2,2 { + reg = <0x1000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + + wifi@1,4,0 { + reg = <0x0000 0 0 0 0>; + ieee80211-freq-limit = <5170000 5730000>; + }; + }; + }; + }; +}; + &usb2 { vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index ae4b388..c52711b 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -236,6 +236,14 @@ #gpio-cells = <2>; }; + pcie0: pcie@12000 { + reg = <0x00012000 0x1000>; + }; + + pcie1: pcie@13000 { + reg = <0x00013000 0x1000>; + }; + usb2: usb2@21000 { reg = <0x00021000 0x1000>; From patchwork Tue Apr 4 06:12:16 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Amit Pundir X-Patchwork-Id: 96665 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp46778qgd; Mon, 3 Apr 2017 23:12:59 -0700 (PDT) X-Received: by 10.84.233.143 with SMTP id l15mr26573591plk.93.1491286378924; Mon, 03 Apr 2017 23:12:58 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f1si16391190pln.331.2017.04.03.23.12.58; Mon, 03 Apr 2017 23:12:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751043AbdDDGM6 (ORCPT + 6 others); Tue, 4 Apr 2017 02:12:58 -0400 Received: from mail-pg0-f54.google.com ([74.125.83.54]:34869 "EHLO mail-pg0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750962AbdDDGM5 (ORCPT ); Tue, 4 Apr 2017 02:12:57 -0400 Received: by mail-pg0-f54.google.com with SMTP id 81so142592490pgh.2 for ; Mon, 03 Apr 2017 23:12:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7tdNtg9jqtV/z6ixbd10BA62wXv0/lVScWREvmLhjFI=; b=GL+vWonZ64gGd+4XZSUz5HOPstB1lvRs+avDB5sjCupcDy1xGWPmZXEJ5u/Kz5WcEp 0A1BbkFqZ+cGAx+ZoJOshZl1tIrEfMdPerP56cbM7M3KIawJfiGz6uu+4YtO001x28KG wBqBNUv8oIHN+PmVXzaZkzkU8iVtURoqpzWYQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7tdNtg9jqtV/z6ixbd10BA62wXv0/lVScWREvmLhjFI=; b=EzOZZiCkqrlrFlwMeMjkhLXx4kXkazOy+eA/+Du85+7WIBq4K0aTisKbNFiwwIrN/i AuYkAM+t3YQZKuX6KMifB2jeqiZqtZvCrZ/qSv+wp7Ukjc33cNEY+ot0yeximdjV44TG ylmHC7Olx5noCS4whzwk+QHrLjyO4F5AgBVVTf0he56/Xvx9frqKtYDo/T4DDRVs6Vck 3R/4J9hDdE84dHB6QFetw845WT+aeLN07iN/O2JrPasvXAFdfms9Y0EMsE1/mqJy5yHT F9IjmHrLiLgPy1pK5pfB7Fv3saB4ans5EqA2V4f+g9FaYwQG+M8NcfxTUYOs2iRsGzuP 1D3w== X-Gm-Message-State: AFeK/H1qGN0ViygJ1i+wTzBgXjZqmkyDv7fmtAH1ENnrWpyBM/BQYDf7c0oNYphjjc/lj5F8 X-Received: by 10.98.10.23 with SMTP id s23mr20730907pfi.78.1491286376942; Mon, 03 Apr 2017 23:12:56 -0700 (PDT) Received: from localhost.localdomain ([106.51.240.246]) by smtp.gmail.com with ESMTPSA id p9sm29164025pfe.22.2017.04.03.23.12.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 03 Apr 2017 23:12:56 -0700 (PDT) From: Amit Pundir To: gregkh@linuxfoundation.org Cc: stable@vger.kernel.org, Jon Mason , Florian Fainelli Subject: [PATCH 03/33] ARM: dts: BCM5301X: Correct GIC_PPI interrupt flags Date: Tue, 4 Apr 2017 11:42:16 +0530 Message-Id: <1491286366-30720-4-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491286366-30720-1-git-send-email-amit.pundir@linaro.org> References: <1491286366-30720-1-git-send-email-amit.pundir@linaro.org> MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Jon Mason GIC_PPI flags were misconfigured for the timers, resulting in errors like: [ 0.000000] GIC: PPI11 is secure or misconfigured Changing them to being edge triggered corrects the issue Suggested-by: Rafał Miłecki Signed-off-by: Jon Mason Fixes: d27509f1 ("ARM: BCM5301X: add dts files for BCM4708 SoC") Signed-off-by: Florian Fainelli (cherry picked from commit 0c2bf9f95983fe30aa2f6463cb761cd42c2d521a) Signed-off-by: Amit Pundir --- arch/arm/boot/dts/bcm5301x.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index c52711b..0e929d4 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -66,14 +66,14 @@ timer@20200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x20200 0x100>; - interrupts = ; + interrupts = ; clocks = <&periph_clk>; }; local-timer@20600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x20600 0x100>; - interrupts = ; + interrupts = ; clocks = <&periph_clk>; };