From patchwork Fri Feb 5 16:59:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 376953 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp2480190jah; Fri, 5 Feb 2021 09:55:56 -0800 (PST) X-Google-Smtp-Source: ABdhPJxlh3PwDr4AmaZDlitDQY/iTuHRRSTgcr3HufEqUHSF619gOjfu9t3BgQ8wUKIDiHk07FfN X-Received: by 2002:a25:6ad6:: with SMTP id f205mr7485627ybc.41.1612547756731; Fri, 05 Feb 2021 09:55:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612547756; cv=none; d=google.com; s=arc-20160816; b=r0NCqx1qFlm8WsRaZ7wk+PJBApQ75sxIecqFIvcGrmfoyAFGbamRguBhMlxHNwi9CJ YLZLGjk36EaPsuWGqhOZv5WMyYPozYiP1A6YpEO16+B5Cr3E/QrwyL/A0N6ntyNpB1at hBP/lE5ZO/Qpr3lI6V4nMHpM0WHE0zdPQb+eWWI3afJVS9DMV7MK9PlDvhXR6+wymT4W 55ngTsrKO99fZtXJXeDxL9dXJsdIYV7oAc8pE5bLEKi0DVPfQt2dF5Ul3a9P6Og6v8cc XaqW8PC276ElU2u+AqKAE4861TD0TBCapJW64D+gOXhiZTqqK9i+0OjM76iyp+6mq/lW nufw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=g+EZctwruwxJ+bIOTViWFK3zdYVscML+NxpdSxKPVAo=; b=OxJ3hYapr7/NgDk2l93F+qgc06StkuPKEdogNOLf42IP+bUHj9DLQnAxsU/9rYj5R8 wjI6KFkn2061ObR7KeP20G75AuHFqSkG/mWDCa9JSuYtEvYgK412G6ArAc0kLuMtL5Yw +6GuSZW5MKMTB1T0qNElNuRtr2kVKK+0OopaLMA+JfubyqkU7GsM1Ngc3FnKbV8URdIc Of2ahQyOzfyVqtRM70TTffuvaIM8vOBN6vj1wLLpHdSJC/2ZPisS6rPrH+2/vFbuFahC qIMycOtYbqXRfJtKaH7a4kuLBaHMmR9O06dMwE+E1vCp46fKx2Af5J8AYXNmboloUb8D ZInA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Qvp1pu4u; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e132si8574237ybe.451.2021.02.05.09.55.56 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 05 Feb 2021 09:55:56 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Qvp1pu4u; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40574 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l85Km-00025M-4j for patch@linaro.org; Fri, 05 Feb 2021 12:55:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:45924) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l84TG-0006bq-KU for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:00:40 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:54108) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l84T3-0003zK-Cn for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:00:36 -0500 Received: by mail-wm1-x336.google.com with SMTP id j11so6564364wmi.3 for ; Fri, 05 Feb 2021 09:00:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=g+EZctwruwxJ+bIOTViWFK3zdYVscML+NxpdSxKPVAo=; b=Qvp1pu4u+vQKimrApKXyxwfCm/A3lbHEMeMumikqS/kes2ckAZiLYMYis9DgDtPnuV sAUxp9ba40f0HUl5kqgedpLD8Rcr6YJrrYrjaEJ9OM+ftu/DC1K5s60/PRBUcDqhSSdp LbYmxV6TN06Z8J1GW8cbf0PbcXxeAyEcVIEorL6BoJuP4/kNUptADtLhN50z1q2b6wgx vw1SkZgeLe7aDBipIDUU4YMPqvno26U+mlzSVFZLt/TN+Xla4yu8N/+amQdqeUQl209c LvrUrfN7S2rSUH7/JjLFyn/kHDGguVo+gKT7Rl2ze2VEa/270LAWSuJYESCaf9Qn9oxD vp8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g+EZctwruwxJ+bIOTViWFK3zdYVscML+NxpdSxKPVAo=; b=LmozJUo3qHDnHA+cXP/CjVneo8xyPVsI1b6R1eh9qsHqH1JmGmDigxqatu+dPlDFYw q6Pz3QL29RcHje43bpdkFIbOo9eKAMkF2fWwrDjnlC1wkmo2TqvY2Dk4otwbQM86I3qy niQMK7NZfCj/gyhlaUG2gWcDzza5fqwtbFVFVDXzTKi3XW362Xwu1np2vx0f3uEUDzG9 M/brke7EFzUIqfNTMLwKhFo63jAoAcuEXDCc4HjgYttoe5mN32Tm2vVK/jCRzNgI4oyc QmUtRsTay9I79gRKXRQB0T8hr/zuYNxERigRVeANgHMFPXfnGOdXug+3LLwbMnCKGlD2 fCcw== X-Gm-Message-State: AOAM531gnDl+NzOoM9zQ6xqb9pnbNE15/wnOpdirqKhI/NWcHdg80qFk FoYMHo7aFqjUVjjRjKd45TbzjA== X-Received: by 2002:a1c:2905:: with SMTP id p5mr4288589wmp.156.1612544422513; Fri, 05 Feb 2021 09:00:22 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:22 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 01/24] hw/arm/mps2-tz: Make SYSCLK frequency board-specific Date: Fri, 5 Feb 2021 16:59:56 +0000 Message-Id: <20210205170019.25319-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The AN524 has a different SYSCLK frequency from the AN505 and AN521; make the SYSCLK frequency a field in the MPS2TZMachineClass rather than a compile-time constant so we can support the AN524. Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 90caa914934..82ce6262817 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -76,6 +76,7 @@ struct MPS2TZMachineClass { MachineClass parent; MPS2TZFPGAType fpga_type; uint32_t scc_id; + uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */ const char *armsse_type; }; @@ -111,8 +112,6 @@ struct MPS2TZMachineState { OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) -/* Main SYSCLK frequency in Hz */ -#define SYSCLK_FRQ 20000000 /* Slow 32Khz S32KCLK frequency in Hz */ #define S32KCLK_FRQ (32 * 1000) @@ -186,6 +185,7 @@ static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size) { + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); CMSDKAPBUART *uart = opaque; int i = uart - &mms->uart[0]; int rxirqno = i * 2; @@ -196,7 +196,7 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, object_initialize_child(OBJECT(mms), name, uart, TYPE_CMSDK_APB_UART); qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); - qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ); + qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->sysclk_frq); sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); s = SYS_BUS_DEVICE(uart); sysbus_connect_irq(s, 0, get_sse_irq_in(mms, txirqno)); @@ -403,7 +403,7 @@ static void mps2tz_common_init(MachineState *machine) /* These clocks don't need migration because they are fixed-frequency */ mms->sysclk = clock_new(OBJECT(machine), "SYSCLK"); - clock_set_hz(mms->sysclk, SYSCLK_FRQ); + clock_set_hz(mms->sysclk, mmc->sysclk_frq); mms->s32kclk = clock_new(OBJECT(machine), "S32KCLK"); clock_set_hz(mms->s32kclk, S32KCLK_FRQ); @@ -670,6 +670,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data) mmc->fpga_type = FPGA_AN505; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); mmc->scc_id = 0x41045050; + mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ mmc->armsse_type = TYPE_IOTKIT; } @@ -685,6 +686,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data) mmc->fpga_type = FPGA_AN521; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); mmc->scc_id = 0x41045210; + mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ mmc->armsse_type = TYPE_SSE200; } From patchwork Fri Feb 5 16:59:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 376956 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp2482311jah; Fri, 5 Feb 2021 09:58:59 -0800 (PST) X-Google-Smtp-Source: ABdhPJx/3GaywJlS5ekLwSxV0ZNFPBvRfTofRw10PvhgvAkoMviwwGfH0Eouj69myRWq3HrjIO+4 X-Received: by 2002:a25:2645:: with SMTP id m66mr8007323ybm.356.1612547939593; Fri, 05 Feb 2021 09:58:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612547939; cv=none; d=google.com; s=arc-20160816; b=o5xZZ/7jc4aBdtoWq6dFnUvigr9YOmQnHDjszLL8dW6Bkb6watHZDf4EVqvWxV7UBp m1pEKLQBQDfZEtF5hjo0CrME3dirE5v0ePWYw5/X1kDaOwcbc9Fa4GlfySWXViZFEPD8 o2ddy5ZZwbiKfIybXIbjEKQ/bFfDivj7nyX9NOoQh0a0a617eawU9I/km6lJLflAvech Nf6XcO5RQruv42zYDeehj7Gj6xtJj8BEhfcnKLSA+n+0lUks7is2wPM7htq+DjQ+2McP BLxZSdxSCwqty4hp6gmpXA57gMVi58XO7yBYX2p0njfnCc+Bl7uvtAAkee+91HZPSWYH lgNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6e/ocFlNpbvzWzShp69RWnr5b+cScjq0s1B9GZ0rX5w=; b=a/liDL17MFEkmiv7JxVqgw9S1IEU7E4WryLCwkdm0ukT/ELspWfVQMi+JM3u2o57lT g/GGuNsfu2a2+6gnI2QZVxK5YDaHFJCb460HMHRwryYznkJNjWJOqlopCbkGGj15nnrO wHyehyApgyUkRQNpT0ucVWS+LXzyRBvuyfHX488FURE8CuCdjVZLMilMh1CQzQ+Dq4Uq NS98mGGdyGaOZFzv6XFlKUWrdZlB3vpgxmFFn6VbJSFiX4ugltKRkHlbiftfxh+49W5n srht5knjwb+epCCXJQ4SuXBNpugIWdasrOIKDoXPFZqiZe3OP0jH0onefUA7vy2vfEiV Tjrg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VU1fOfjB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:22 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 02/24] hw/misc/mps2-scc: Support configurable number of OSCCLK values Date: Fri, 5 Feb 2021 16:59:57 +0000 Message-Id: <20210205170019.25319-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Currently the MPS2 SCC device implements a fixed number of OSCCLK values (3). The variant of this device in the MPS3 AN524 board has 6 OSCCLK values. Switch to using a PROP_ARRAY, which allows board code to specify how large the OSCCLK array should be as well as its values. With a variable-length property array, the SCC no longer specifies default values for the OSCCLKs, so we must set them explicitly in the board code. This defaults are actually incorrect for the an521 and an505; we will correct this bug in a following patch. This is a migration compatibility break for all the mps boards. Signed-off-by: Peter Maydell --- It would be possible to avoid the compat break, but we've already broken compat for the mps boards this release cycle (eg in commit eeae0b2bf4e69de2) when we added Clock support to the armsse code, so there's no point in trying to keep compat for this change. --- include/hw/misc/mps2-scc.h | 7 +++---- hw/arm/mps2-tz.c | 5 +++++ hw/arm/mps2.c | 5 +++++ hw/misc/mps2-scc.c | 24 +++++++++++++----------- 4 files changed, 26 insertions(+), 15 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h index f65d8732031..514da49f69e 100644 --- a/include/hw/misc/mps2-scc.h +++ b/include/hw/misc/mps2-scc.h @@ -19,8 +19,6 @@ #define TYPE_MPS2_SCC "mps2-scc" OBJECT_DECLARE_SIMPLE_TYPE(MPS2SCC, MPS2_SCC) -#define NUM_OSCCLK 3 - struct MPS2SCC { /*< private >*/ SysBusDevice parent_obj; @@ -39,8 +37,9 @@ struct MPS2SCC { uint32_t dll; uint32_t aid; uint32_t id; - uint32_t oscclk[NUM_OSCCLK]; - uint32_t oscclk_reset[NUM_OSCCLK]; + uint32_t num_oscclk; + uint32_t *oscclk; + uint32_t *oscclk_reset; }; #endif diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 82ce6262817..7c066c11ed4 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -219,6 +219,11 @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); + /* This will need to be per-FPGA image eventually */ + qdev_prop_set_uint32(sccdev, "len-oscclk", 3); + qdev_prop_set_uint32(sccdev, "oscclk[0]", 50000000); + qdev_prop_set_uint32(sccdev, "oscclk[1]", 24576000); + qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000); sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal); return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); } diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 39add416db5..81413b7133e 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -373,6 +373,11 @@ static void mps2_common_init(MachineState *machine) qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); + /* All these FPGA images have the same OSCCLK configuration */ + qdev_prop_set_uint32(sccdev, "len-oscclk", 3); + qdev_prop_set_uint32(sccdev, "oscclk[0]", 50000000); + qdev_prop_set_uint32(sccdev, "oscclk[1]", 24576000); + qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000); sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000); object_initialize_child(OBJECT(mms), "fpgaio", diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c index ce1dfe93562..52a4e183b71 100644 --- a/hw/misc/mps2-scc.c +++ b/hw/misc/mps2-scc.c @@ -57,7 +57,7 @@ static bool scc_cfg_write(MPS2SCC *s, unsigned function, { trace_mps2_scc_cfg_write(function, device, value); - if (function != 1 || device >= NUM_OSCCLK) { + if (function != 1 || device >= s->num_oscclk) { qemu_log_mask(LOG_GUEST_ERROR, "MPS2 SCC config write: bad function %d device %d\n", function, device); @@ -75,7 +75,7 @@ static bool scc_cfg_write(MPS2SCC *s, unsigned function, static bool scc_cfg_read(MPS2SCC *s, unsigned function, unsigned device, uint32_t *value) { - if (function != 1 || device >= NUM_OSCCLK) { + if (function != 1 || device >= s->num_oscclk) { qemu_log_mask(LOG_GUEST_ERROR, "MPS2 SCC config read: bad function %d device %d\n", function, device); @@ -227,7 +227,7 @@ static void mps2_scc_reset(DeviceState *dev) s->cfgctrl = 0x100000; s->cfgstat = 0; s->dll = 0xffff0001; - for (i = 0; i < NUM_OSCCLK; i++) { + for (i = 0; i < s->num_oscclk; i++) { s->oscclk[i] = s->oscclk_reset[i]; } for (i = 0; i < ARRAY_SIZE(s->led); i++) { @@ -254,12 +254,14 @@ static void mps2_scc_realize(DeviceState *dev, Error **errp) LED_COLOR_GREEN, name); g_free(name); } + + s->oscclk = g_new0(uint32_t, s->num_oscclk); } static const VMStateDescription mps2_scc_vmstate = { .name = "mps2-scc", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { VMSTATE_UINT32(cfg0, MPS2SCC), VMSTATE_UINT32(cfg1, MPS2SCC), @@ -268,7 +270,8 @@ static const VMStateDescription mps2_scc_vmstate = { VMSTATE_UINT32(cfgctrl, MPS2SCC), VMSTATE_UINT32(cfgstat, MPS2SCC), VMSTATE_UINT32(dll, MPS2SCC), - VMSTATE_UINT32_ARRAY(oscclk, MPS2SCC, NUM_OSCCLK), + VMSTATE_VARRAY_UINT32(oscclk, MPS2SCC, num_oscclk, + 0, vmstate_info_uint32, uint32_t), VMSTATE_END_OF_LIST() } }; @@ -280,14 +283,13 @@ static Property mps2_scc_properties[] = { DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, cfg4, 0), DEFINE_PROP_UINT32("scc-aid", MPS2SCC, aid, 0), DEFINE_PROP_UINT32("scc-id", MPS2SCC, id, 0), - /* These are the initial settings for the source clocks on the board. + /* + * These are the initial settings for the source clocks on the board. * In hardware they can be configured via a config file read by the * motherboard configuration controller to suit the FPGA image. - * These default values are used by most of the standard FPGA images. */ - DEFINE_PROP_UINT32("oscclk0", MPS2SCC, oscclk_reset[0], 50000000), - DEFINE_PROP_UINT32("oscclk1", MPS2SCC, oscclk_reset[1], 24576000), - DEFINE_PROP_UINT32("oscclk2", MPS2SCC, oscclk_reset[2], 25000000), + DEFINE_PROP_ARRAY("oscclk", MPS2SCC, num_oscclk, oscclk_reset, + qdev_prop_uint32, uint32_t), DEFINE_PROP_END_OF_LIST(), }; From patchwork Fri Feb 5 16:59:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 376940 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp2448496jah; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:23 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 03/24] hw/arm/mps2-tz: Correct the OSCCLK settings for mps2-an505 and mps2-an511 Date: Fri, 5 Feb 2021 16:59:58 +0000 Message-Id: <20210205170019.25319-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We were previously using the default OSCCLK settings, which are correct for the older MPS2 boards (mps2-an385, mps2-an386, mps2-an500, mps2-an511), but wrong for the mps2-an505 and mps2-511 implemented in mps2-tz.c. Now we're setting the values explicitly we can fix them to be correct. Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 7c066c11ed4..976f5f5c682 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -221,8 +221,8 @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); /* This will need to be per-FPGA image eventually */ qdev_prop_set_uint32(sccdev, "len-oscclk", 3); - qdev_prop_set_uint32(sccdev, "oscclk[0]", 50000000); - qdev_prop_set_uint32(sccdev, "oscclk[1]", 24576000); + qdev_prop_set_uint32(sccdev, "oscclk[0]", 40000000); + qdev_prop_set_uint32(sccdev, "oscclk[1]", 24580000); qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000); sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal); return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); From patchwork Fri Feb 5 16:59:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 376958 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp2483599jah; Fri, 5 Feb 2021 10:00:39 -0800 (PST) X-Google-Smtp-Source: ABdhPJyRzSwB75vw50aIGEu78gRZt9vye+QsKM0YlO4PAsge71Q6wnLKUVWqZRsZpSnRvvEC12Zt X-Received: by 2002:a25:a267:: with SMTP id b94mr7975816ybi.277.1612548039283; Fri, 05 Feb 2021 10:00:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612548039; cv=none; d=google.com; s=arc-20160816; b=ELpjlmaWFEbMi/8HSv9Onsl3RNwvDTfkGOefVfR17p1SeFFV/tTQ0iR4HiGigfGGXu NrfVJrZKSZMer4964mTH4QU6Zh/Jh2WdOrb4aId/HicXsuZbgp/ZAcwHuPjlKwMchT2Q S/SNiN15WW4BJn83owoajX2+bFrtxFDfwc5gOPUes3zb+wiPkKuT3UpAsu6AcV/PAn2Q 69nqbcj5/jDxn5M3dqHUCyDoeVgnjX9jDRW3O47yJibkMxihBaH+DRkgnanlfhtcgANG PmtkAben3ammgy+sWcykVxtrLOfVHInN3EEnYDdRIrDyxnm3YAEzXbT1CFizoLEmoob6 Kl0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=FHr6FuqE0B2b9d2HJA4DI+zb7En8n9XfTjpsu+vmnps=; b=zs8etwJ+/xTUphEaFQe4T+oumMTd2vq8xK9cXx92xOmUHAl3KUmGKwmpm9XFH6FTf3 UanVLvO6E6Czwh+cFO5AEs9QSu89zpmFg8HxhqT+J6kDlwzR1Ma/8MrZGzxw6Sn6u9Fq BGSys2SP2tYqmF71QvTvc9CLjAAt/rDVQfUoEXHuaCM08+KNmdn/+LFHm4XZAu/vms61 SOg2ggEhrfI1M8k53lj3HONjRhoY49ycxv4fmP10FR6K0PjNujDxj6JWQIh/b/chdldn FvY+1IBNaTEVzsvyJz+NAYXDz8uCELMsZWrL0aySQprd8LEsW9AH4RLJqCt5YBUVyx6K B3Qw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VwtlGJvq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t2si9193977ybo.344.2021.02.05.10.00.39 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 05 Feb 2021 10:00:39 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VwtlGJvq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52476 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l85PK-00073r-C5 for patch@linaro.org; Fri, 05 Feb 2021 13:00:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46152) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l84TZ-0006kM-Uz for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:00:58 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:34278) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l84T8-00041a-Nh for qemu-devel@nongnu.org; Fri, 05 Feb 2021 12:00:57 -0500 Received: by mail-wm1-x32b.google.com with SMTP id o10so8223197wmc.1 for ; Fri, 05 Feb 2021 09:00:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=FHr6FuqE0B2b9d2HJA4DI+zb7En8n9XfTjpsu+vmnps=; b=VwtlGJvqc9vzrrtxKLU+wWrLnXTjlDfg0aroLhg4kM1G3UF0A8Z4NgDMZ9mYx/1fBg RCj8pWT1J6SogJaBttzVilfetr05xULGMdAfbCenKz8G92aSaQmaPViZhO2ZxtpT+tUp l9YcYGvE7uKWs27P4csHIGkWs3vCdfXY52/ZNd17YGHY69p/gb4ASNOHtmanPAMACbb+ ytBqkBAbse4qGtcxToac1I0l4SbIqjw9gomjNWbwVWkObH34A6L1piRGLYeoZGr43P/w TScjOuZ75Xnetq9YJxCBX/n3OX9qXHfTNH8jswv7EsBN1zte7D0bVWcGz3uXFe67ahbs kkrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FHr6FuqE0B2b9d2HJA4DI+zb7En8n9XfTjpsu+vmnps=; b=o0pyHJXj90k53I1OxCd3X28gSzKD/z+BRnfWbjMqhhzcM9Z/Td5s55S1sGhZk7ziJy H+QAd8WfZkZxq1o/wTA+/bEHjsJ2BYezQhrlAEKN6Md8DxesIqA0gXoO8D/vI61kdtCT Oj82hK0lz00LQUpg9PZNu3TSw6/MzA/qUUe6ZymXXtpu2CYGkbdHH6pefGuPtCyTCWk7 nBS3RDmVK2Q0F65wtg88CUDCR9oq9DAW2njTiWLRkV/RLtm2eC4cvcT2JPPSTcrs3qnp erYusCGNPFu5aJS5Rr5lMTMwRYVJTXsm9fyqyoUyA0wAQDrv8oFFz7qRA2/tQmF70VzF 7eag== X-Gm-Message-State: AOAM532cO9cprDRSmVMXQCVTUMpSUfRkXjsqQQtoydo6Rr/jdfPoEodT hBZHHiKdkzsb7L9TFCMVqM1oyIAmJkAocw== X-Received: by 2002:a05:600c:3504:: with SMTP id h4mr4444267wmq.168.1612544425124; Fri, 05 Feb 2021 09:00:25 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:24 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 04/24] hw/arm/mps2-tz: Make the OSCCLK settings be configurable per-board Date: Fri, 5 Feb 2021 16:59:59 +0000 Message-Id: <20210205170019.25319-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The AN505 and AN511 happen to share the same OSCCLK values, but the AN524 will have a different set (and more of them), so split the settings out to be per-board. Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 976f5f5c682..9add1453cc2 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -77,6 +77,8 @@ struct MPS2TZMachineClass { MPS2TZFPGAType fpga_type; uint32_t scc_id; uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */ + uint32_t len_oscclk; + const uint32_t *oscclk; const char *armsse_type; }; @@ -115,6 +117,12 @@ OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) /* Slow 32Khz S32KCLK frequency in Hz */ #define S32KCLK_FRQ (32 * 1000) +static const uint32_t an505_oscclk[] = { + 40000000, + 24580000, + 25000000, +}; + /* Create an alias of an entire original MemoryRegion @orig * located at @base in the memory map. */ @@ -213,17 +221,18 @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, MPS2SCC *scc = opaque; DeviceState *sccdev; MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); + int i; object_initialize_child(OBJECT(mms), "scc", scc, TYPE_MPS2_SCC); sccdev = DEVICE(scc); qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2); qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008); qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id); - /* This will need to be per-FPGA image eventually */ - qdev_prop_set_uint32(sccdev, "len-oscclk", 3); - qdev_prop_set_uint32(sccdev, "oscclk[0]", 40000000); - qdev_prop_set_uint32(sccdev, "oscclk[1]", 24580000); - qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000); + qdev_prop_set_uint32(sccdev, "len-oscclk", mmc->len_oscclk); + for (i = 0; i < mmc->len_oscclk; i++) { + g_autofree char *propname = g_strdup_printf("oscclk[%d]", i); + qdev_prop_set_uint32(sccdev, propname, mmc->oscclk[i]); + } sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal); return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0); } @@ -676,6 +685,8 @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data) mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); mmc->scc_id = 0x41045050; mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ + mmc->oscclk = an505_oscclk; + mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); mmc->armsse_type = TYPE_IOTKIT; } @@ -692,6 +703,8 @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data) mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); mmc->scc_id = 0x41045210; mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ + mmc->oscclk = an505_oscclk; /* AN521 is the same as AN505 here */ + mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); mmc->armsse_type = TYPE_SSE200; } From patchwork Fri Feb 5 17:00:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 376954 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp2480574jah; Fri, 5 Feb 2021 09:56:32 -0800 (PST) X-Google-Smtp-Source: ABdhPJy3zgmzGUSSBi26eYebkr1Cj1M6ap1lCIx2KY9nsW7ET9egrvu4endb6OqLbf0xgUBGSvB0 X-Received: by 2002:a25:cc89:: with SMTP id l131mr7720535ybf.346.1612547792864; Fri, 05 Feb 2021 09:56:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612547792; cv=none; d=google.com; s=arc-20160816; b=N3kYTX4c+5yGL+FSPU+8hTAONAa6PdhK+lrUuwuMrYDFAsec1UHk0ybM9hsNmBh8x4 mkh64/Bz+Q+Nv7GiP6fv01WzeI3exu4jKablZ2tWdGpPmAcvR+CSsYIa59BZHe6WQkdq 5NVahbpoZIRh8Wbfm+g9yPRg1n2e4RmQ4Xra2hrFg6pku+jnp6Tz/aGJcIsasGWfjybz xBNO4+igtTFclQekWqLHtUfk9avvdqDml3NuX1A0+Bgk9gRsG2dAVB8aSou65w73jJww PN78MX0HfdvEq4DDlJx12hcFBZsxZQ7bk588F8FUIrzuzJcrNSJh70IazgXoHeonluiX gK6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vPha70CdlIz8Ft1BgdKuRx55ClhohOzaXUUXYhoxm5M=; b=eduD5bcklB4nYUOxYtRER4GfML0c7+eDpgBRAcBY1+iYc7E2goITJLlvQlBO3N0/zv ARowOgLHl6E5zZFk5k31QWETk4AO8HxJasxQjEPCTr3S2DZw9wPo/ZldM4uil2iQs9iC sBqPa3L2zY2t/fI3tWeOYqbWaur7DfS671DXXnFr0w07ZWCbFSFq9n407evK0F4brhSx Lq36GskF3DaZ3dxWujJaKg0uiH7h7rVIMXwS//DIP7YRVsO7MQMsFcx4zyf4MYt7i7j+ 2WuH3wnZSPcdsrcm7FJcYPtvcf8drLdKCq5P0uXJKW6/4BYeJL/LQf9ITsblVLCuDcom UUMA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="g/8Lv/PC"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:25 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 05/24] hw/misc/mps2-fpgaio: Make number of LEDs configurable by board Date: Fri, 5 Feb 2021 17:00:00 +0000 Message-Id: <20210205170019.25319-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The MPS2 board has 2 LEDs, but the MPS3 board has 10 LEDs. The FPGAIO device is similar on both sets of boards, but the LED0 register has correspondingly more bits that have an effect. Add a device property for number of LEDs. Signed-off-by: Peter Maydell --- include/hw/misc/mps2-fpgaio.h | 5 ++++- hw/misc/mps2-fpgaio.c | 31 +++++++++++++++++++++++-------- 2 files changed, 27 insertions(+), 9 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/include/hw/misc/mps2-fpgaio.h b/include/hw/misc/mps2-fpgaio.h index a010fdb2b6d..bfe73134e78 100644 --- a/include/hw/misc/mps2-fpgaio.h +++ b/include/hw/misc/mps2-fpgaio.h @@ -28,13 +28,16 @@ #define TYPE_MPS2_FPGAIO "mps2-fpgaio" OBJECT_DECLARE_SIMPLE_TYPE(MPS2FPGAIO, MPS2_FPGAIO) +#define MPS2FPGAIO_MAX_LEDS 32 + struct MPS2FPGAIO { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ MemoryRegion iomem; - LEDState *led[2]; + LEDState *led[MPS2FPGAIO_MAX_LEDS]; + uint32_t num_leds; uint32_t led0; uint32_t prescale; diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c index 6af0e8f837a..b28a1be22cc 100644 --- a/hw/misc/mps2-fpgaio.c +++ b/hw/misc/mps2-fpgaio.c @@ -177,9 +177,14 @@ static void mps2_fpgaio_write(void *opaque, hwaddr offset, uint64_t value, switch (offset) { case A_LED0: - s->led0 = value & 0x3; - led_set_state(s->led[0], value & 0x01); - led_set_state(s->led[1], value & 0x02); + if (s->num_leds != 0) { + int i; + + s->led0 = value & MAKE_64BIT_MASK(0, s->num_leds); + for (i = 0; i < s->num_leds; i++) { + led_set_state(s->led[i], value & (1 << i)); + } + } break; case A_PRESCALE: resync_counter(s); @@ -238,7 +243,7 @@ static void mps2_fpgaio_reset(DeviceState *dev) s->pscntr = 0; s->pscntr_sync_ticks = now; - for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) { + for (size_t i = 0; i < s->num_leds; i++) { device_cold_reset(DEVICE(s->led[i])); } } @@ -256,11 +261,19 @@ static void mps2_fpgaio_init(Object *obj) static void mps2_fpgaio_realize(DeviceState *dev, Error **errp) { MPS2FPGAIO *s = MPS2_FPGAIO(dev); + int i; - s->led[0] = led_create_simple(OBJECT(dev), GPIO_POLARITY_ACTIVE_HIGH, - LED_COLOR_GREEN, "USERLED0"); - s->led[1] = led_create_simple(OBJECT(dev), GPIO_POLARITY_ACTIVE_HIGH, - LED_COLOR_GREEN, "USERLED1"); + if (s->num_leds > MPS2FPGAIO_MAX_LEDS) { + error_setg(errp, "num-leds cannot be greater than %d", + MPS2FPGAIO_MAX_LEDS); + return; + } + + for (i = 0; i < s->num_leds; i++) { + g_autofree char *ledname = g_strdup_printf("USERLED%d", i); + s->led[i] = led_create_simple(OBJECT(dev), GPIO_POLARITY_ACTIVE_HIGH, + LED_COLOR_GREEN, ledname); + } } static bool mps2_fpgaio_counters_needed(void *opaque) @@ -303,6 +316,8 @@ static const VMStateDescription mps2_fpgaio_vmstate = { static Property mps2_fpgaio_properties[] = { /* Frequency of the prescale counter */ DEFINE_PROP_UINT32("prescale-clk", MPS2FPGAIO, prescale_clk, 20000000), + /* Number of LEDs controlled by LED0 register */ + DEFINE_PROP_UINT32("num-leds", MPS2FPGAIO, num_leds, 2), DEFINE_PROP_END_OF_LIST(), }; From patchwork Fri Feb 5 17:00:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 376946 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp2471331jah; Fri, 5 Feb 2021 09:43:42 -0800 (PST) X-Google-Smtp-Source: ABdhPJyqBCaHh4859gA5oEhVhU75Ueo6t8OHTvYcv8fcNGjJD2cJBo9lvfs8ktjaQbUGXcV1kLmm X-Received: by 2002:a25:cf56:: with SMTP id f83mr7930911ybg.216.1612547022401; Fri, 05 Feb 2021 09:43:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612547022; cv=none; d=google.com; s=arc-20160816; b=0P5QeowAF6F0rKM3P0JKzDb7RZw+BFnrmLh5S5LZTsvIsNURCTO5wEvCz91l8foVJc HbCcGdIjjaZxdv15NqGRpdBIL/WtO8Nw4lLl2vHElHcIBUjrPAFrU8SiQbAQuni8CmPL EkVY47SztJmMu7uGEJAZyme40/NElnEegLyCNvI7IEG+GWx+0jiZMowT3BuJ2buYDBl+ D6WMJZ8pCMaB1UGNRYlqWnIhPcQzDIypQ7LzGNM6oeUA/OeGB8ukG7FMviNbr0PSoKL0 ttql1FrHwIiP6+0+tGxghWIjE3aGImfjFkdl4XxtcZU4CX2A9/IZYtWPtyxFxAduBHDf O69A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/oJeRnXgSDJEHEJaO9pMCaTGB+0Qu174IkpqLDjGWdU=; b=iqf/5rXD0hbrJJyjnQX28q2YQfyi5f2MjNviCsZqsEnySd5x92GvGpkfizuuM1G2UM deNeorplLWTjioulN3F94yRdKHKlw6GDs9U2Eism5+AtLVbsQLNb6+U2r9CJexnQeR8B rK5mHquD1hglm221ozuLosD2PwRf7AGSCUYmHsnX9gmFWL8oxXSNvgEOMSPH+mNkcuPt sKFIY4r8QFMdI+OxhvwdSaQb0Ls0XbUoLNnDL8zBWk88MFjbchP5KYYxMWzOvtG+DA+n u/PUkqR54H7bI+h/Rh0R4i+xjL6YAISP+PNq5yTGSsA3XtmRyKbE0yNENQlgR0kDRZX0 5rbw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xiGUezDf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:26 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 06/24] hw/misc/mps2-fpgaio: Support SWITCH register Date: Fri, 5 Feb 2021 17:00:01 +0000 Message-Id: <20210205170019.25319-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" MPS3 boards have an extra SWITCH register in the FPGAIO block which reports the value of some switches. Implement this, governed by a property the board code can use to specify whether whether it exists. Signed-off-by: Peter Maydell --- include/hw/misc/mps2-fpgaio.h | 1 + hw/misc/mps2-fpgaio.c | 10 ++++++++++ 2 files changed, 11 insertions(+) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/include/hw/misc/mps2-fpgaio.h b/include/hw/misc/mps2-fpgaio.h index bfe73134e78..83c6e18a4ee 100644 --- a/include/hw/misc/mps2-fpgaio.h +++ b/include/hw/misc/mps2-fpgaio.h @@ -38,6 +38,7 @@ struct MPS2FPGAIO { MemoryRegion iomem; LEDState *led[MPS2FPGAIO_MAX_LEDS]; uint32_t num_leds; + bool have_switches; uint32_t led0; uint32_t prescale; diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c index b28a1be22cc..b54657a4f07 100644 --- a/hw/misc/mps2-fpgaio.c +++ b/hw/misc/mps2-fpgaio.c @@ -35,6 +35,7 @@ REG32(CLK100HZ, 0x14) REG32(COUNTER, 0x18) REG32(PRESCALE, 0x1c) REG32(PSCNTR, 0x20) +REG32(SWITCH, 0x28) REG32(MISC, 0x4c) static uint32_t counter_from_tickoff(int64_t now, int64_t tick_offset, int frq) @@ -156,7 +157,15 @@ static uint64_t mps2_fpgaio_read(void *opaque, hwaddr offset, unsigned size) resync_counter(s); r = s->pscntr; break; + case A_SWITCH: + if (!s->have_switches) { + goto bad_offset; + } + /* User-togglable board switches. We don't model that, so report 0. */ + r = 0; + break; default: + bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "MPS2 FPGAIO read: bad offset %x\n", (int) offset); r = 0; @@ -318,6 +327,7 @@ static Property mps2_fpgaio_properties[] = { DEFINE_PROP_UINT32("prescale-clk", MPS2FPGAIO, prescale_clk, 20000000), /* Number of LEDs controlled by LED0 register */ DEFINE_PROP_UINT32("num-leds", MPS2FPGAIO, num_leds, 2), + DEFINE_PROP_BOOL("have-switches", MPS2FPGAIO, have_switches, false), DEFINE_PROP_END_OF_LIST(), }; From patchwork Fri Feb 5 17:00:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 376945 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp2467842jah; Fri, 5 Feb 2021 09:39:28 -0800 (PST) X-Google-Smtp-Source: ABdhPJypP3J1vIXZYf+APV68mk64fFPxvgnqlK5MR0Dhymj0Vi+rZNy8OtmedJa1Qh3ZcDf7/fXe X-Received: by 2002:a25:ad54:: with SMTP id l20mr8222147ybe.491.1612546768153; Fri, 05 Feb 2021 09:39:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612546768; cv=none; d=google.com; s=arc-20160816; b=OyIcLfavDjlUlquudYM0rhEgFmJjXVsIFs3nPxiMcsT8K12Qg/w3cphe/XfnyRvDj7 17uSNva02DBnoB3DlXy9oDHLCD/KkHef45Ww0MaWRfDvwyF3IlGtUnu6s2L7es09fLn/ qmTP/84gB08VkJE9c6vEFzWhzaITrALB6MuX4l96QojzVSyszqyUNBp+O6pkt+LEXJW+ 3qAREsSjV1S456kLVXYaccIpWpFZBm9nLqFLK0CeGgRYTywLCMK7mjxjtLVVK8IIqZT+ b/93LiDx/T1ICxpTCOfRKgX8E30qkKIT6Rh1UgSH2Uviz9YjWhkvCA73lSfB10VNExA/ gfAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=RMlSEt6PiH0qMk4plcisXlg9m+5b90Bk6CfkYCOT5n0=; b=0kj8TW7tFSQ0tDv0OQQ+b1iWLpm/VMkWOQeiOTZ0uNMqkdtOIeGY4M7xF6Bp96RgbF z2woiYiNhh2oIVjoGGY3X9P44kcds1nMBB/b0gCAGLAoooApMzBWGIl3z44/wrSGTNpn O3j+3Yvh8Df6xRN43pCWKrowa9NZVHReumxUQR/RVegYlpZDoue4+85D5QIBnQndex2i 5fReYm4aJRC2jZa0AIWvseRPdWDHbZ5Ix3HB45xLffp10rvT6k4UKjz+LKF9Pit7Oh/6 2OWMSrO1nwzsqFaL+arPUpYBk6WcM/yY/e6qduGkyLOozMuaUaf5mLqjwd/YpxdHkJh2 3scA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vbfFqhNM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:27 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 07/24] hw/arm/mps2-tz: Make FPGAIO switch and LED config per-board Date: Fri, 5 Feb 2021 17:00:02 +0000 Message-Id: <20210205170019.25319-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Set the FPGAIO num-leds and have-switches properties explicitly per-board, rather than relying on the defaults. The AN505 and AN521 both have the same settings as the default values, but the AN524 will be different. Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 9add1453cc2..94618ae54d2 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -79,6 +79,8 @@ struct MPS2TZMachineClass { uint32_t sysclk_frq; /* Main SYSCLK frequency in Hz */ uint32_t len_oscclk; const uint32_t *oscclk; + uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ + bool fpgaio_switches; /* Does FPGAIO have SWITCH register? */ const char *armsse_type; }; @@ -241,8 +243,11 @@ static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size) { MPS2FPGAIO *fpgaio = opaque; + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); object_initialize_child(OBJECT(mms), "fpgaio", fpgaio, TYPE_MPS2_FPGAIO); + qdev_prop_set_uint32(DEVICE(fpgaio), "num-leds", mmc->fpgaio_num_leds); + qdev_prop_set_bit(DEVICE(fpgaio), "have-switches", mmc->fpgaio_switches); sysbus_realize(SYS_BUS_DEVICE(fpgaio), &error_fatal); return sysbus_mmio_get_region(SYS_BUS_DEVICE(fpgaio), 0); } @@ -687,6 +692,8 @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data) mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ mmc->oscclk = an505_oscclk; mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); + mmc->fpgaio_num_leds = 2; + mmc->fpgaio_switches = false; mmc->armsse_type = TYPE_IOTKIT; } @@ -705,6 +712,8 @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data) mmc->sysclk_frq = 20 * 1000 * 1000; /* 20MHz */ mmc->oscclk = an505_oscclk; /* AN521 is the same as AN505 here */ mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); + mmc->fpgaio_num_leds = 2; + mmc->fpgaio_switches = false; mmc->armsse_type = TYPE_SSE200; } From patchwork Fri Feb 5 17:00:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 376943 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp2462934jah; Fri, 5 Feb 2021 09:34:48 -0800 (PST) X-Google-Smtp-Source: ABdhPJy03GcAGSZF3+ELDRob4O9A1FGNoZ2oIOKXyAmiuNU3LzzEmMAP29hFojH9TKiwCnB5nCIJ X-Received: by 2002:a25:d750:: with SMTP id o77mr8009208ybg.194.1612546488085; Fri, 05 Feb 2021 09:34:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612546488; cv=none; d=google.com; s=arc-20160816; b=F297yv2Pf4Pao+H8+slrTXF63kXo1JiTt/u/L7U+9KgwHzuSvSgyFH3DLbGhE/KCZM kKsM4tbNaOkKsdES0WN93aL6sa8dQSBqFPb2DVu33PqRS8wPoYHdh3+BJGhA4+NBGqKk VjsR1vGpbE7jon+AZDoLyR5COJs5JOD6KCaKleUN/N75Lt7C5pena21O57RIEtekrfG0 WRZM3whJNXZPfcpH184vQx/6WWa4r4PzyvMM2qSQZj5DEszzyx4CZ3QIiriHCgQ9VpzX v9FwihtA59YwS/C2hni19fl/8vnaLYk+qFgY+Jv9Uyk24eByO9HEnanKHD3b3Czv3OIy V4UA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=va0A81ClB5F8EaAWROYYvDbctjGQ9fM8K2ZTOurTkG4=; b=KUId+Y7546v6Z+YQ7plLKGW73RGt0u1i9CPsnwvHF4JknfDW/qUrkRU9F6OjSSgWhI Xujn1cqoy7ElwnYFzwsb+cHSp7PeZ0aDO/FBx4WBv5VRWV2TsVWoSIu3zHDRjxrjWsv7 AoKPHaTFnNBnnJdl5Y6gf3AOj8FgX6z2nosJ/1YP+mpYIGVfrnc90mLgYO3RIgh5Ptyb wCpUqtYUowhpyV7T3D2VOhXr7JgDSLPhlvFD+FV4CHy1ZvDgEnuIAmrXnH1stZr+AY2B FlXA2lwz9O1/mI24RHDpwoh1tf9qPHO+v7vIZg5CQXBAFCdE27ID84A7UBYzK+6aEK2d Bovg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TTcdLbMw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:27 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 08/24] hw/arm/mps2-tz: Condition IRQ splitting on number of CPUs, not board type Date: Fri, 5 Feb 2021 17:00:03 +0000 Message-Id: <20210205170019.25319-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In the mps2-tz board code, we handle devices whose interrupt lines must be wired to all CPUs by creating IRQ splitter devices for the AN521, because it has 2 CPUs, but wiring the device IRQ directly to the SSE/IoTKit input for the AN505, which has only 1 CPU. We can avoid making an explicit check on the board type constant by instead creating and using the IRQ splitters for any board with more than 1 CPU. This avoids having to add extra cases to the conditionals every time we add new boards. Signed-off-by: Peter Maydell --- This removes the only current user of mmc->fpga_type, but we're going to want it again later in the series. --- hw/arm/mps2-tz.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 94618ae54d2..4d8e42fa6b6 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -139,17 +139,14 @@ static void make_ram_alias(MemoryRegion *mr, const char *name, static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) { /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */ - MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); + MachineClass *mc = MACHINE_GET_CLASS(mms); assert(irqno < MPS2TZ_NUMIRQ); - switch (mmc->fpga_type) { - case FPGA_AN505: - return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irqno); - case FPGA_AN521: + if (mc->max_cpus > 1) { return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); - default: - g_assert_not_reached(); + } else { + return qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "EXP_IRQ", irqno); } } @@ -437,10 +434,12 @@ static void mps2tz_common_init(MachineState *machine) sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); /* - * The AN521 needs us to create splitters to feed the IRQ inputs - * for each CPU in the SSE-200 from each device in the board. + * If this board has more than one CPU, then we need to create splitters + * to feed the IRQ inputs for each CPU in the SSE from each device in the + * board. If there is only one CPU, we can just wire the device IRQ + * directly to the SSE's IRQ input. */ - if (mmc->fpga_type == FPGA_AN521) { + if (mc->max_cpus > 1) { for (i = 0; i < MPS2TZ_NUMIRQ; i++) { char *name = g_strdup_printf("mps2-irq-splitter%d", i); SplitIRQ *splitter = &mms->cpu_irq_splitter[i]; From patchwork Fri Feb 5 17:00:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 376962 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp2489885jah; Fri, 5 Feb 2021 10:08:03 -0800 (PST) X-Google-Smtp-Source: ABdhPJzRXep2IbjG0VYMVcuzdp8+NL7OWRAbXD2ChV7L4C8CFGcEwtY2rjSyg6EFvv2hS1Yt6FEN X-Received: by 2002:a25:5f49:: with SMTP id h9mr8108307ybm.213.1612548483861; Fri, 05 Feb 2021 10:08:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612548483; cv=none; d=google.com; s=arc-20160816; b=B0NzU0pna5T6kmTZxWihUnDa7Pp1xxvfIRNjOfTqBzMYDZaLYj4dkOBdZTIk5c+5UY I4y38dP/IFuBloVCixyxROo8a/OikItrl+jDa+PqV0QQibioiXUV3htNW5AG1o5egeAR thC761ktYx/ZQWSI4BhFPQekSkTIAJ7C5KH5axphpuAgoh6HIwDvUKD1+HgL9c4MRShp ewBJtApfHx6sw76j7GJLyu69rwnc00rBflHJI+/xjjqIB+077g/C0xpMeDGHd9+44NHP vyE0IgJ6sgU9MuSxhVsVerg1NMTO9D7HHNWTuOCu17+tp5HjKHF+9/kZDqSbU0OCy91J GOUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WtrfuXabVXGeTIyTEVS5d0lsWCXmLnI61ZuEmNjOGlM=; b=pDkBQTvmChfz4Vc6H/mNjwp33E5a+8cVtOAI2URjXwazLgpzDLZQdqLA44Hb8e3SNA UEmLvKoafXgUCtIDwtRCp9oPWyV2JJzW0qertvLIfYV2n8Jh0MrTxWeXdr4Mi3lKxeuJ 7KnTQhJ32NzfeBcLbLQm3ZFOcsNTZAFBgnZKHoQIIEbK4WW6MzEbLlBJIzEroyTtFa3x ZP2drISxU6ArkCcsYrb7AdsEKK5Zq8xHrvhWVCtE4lRejIBXN8VYPoKWfVLuDj4wqs9L v3rOvVNRrpw+4vEcKMV1mYX0UBJPq7S9hySX68qm2PwyNVJlucNmIpUuErHfmBZfomBH +zfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DDtqw24M; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:28 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 09/24] hw/arm/mps2-tz: Make number of IRQs board-specific Date: Fri, 5 Feb 2021 17:00:04 +0000 Message-Id: <20210205170019.25319-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The AN524 has more interrupt lines than the AN505 and AN521; make numirq board-specific rather than a compile-time constant. Since the difference is small (92 on the current boards and 95 on the new one) we don't dynamically allocate the cpu_irq_splitter[] array but leave it as a fixed length array whose size is the maximum needed for any of the boards. Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 4d8e42fa6b6..0f021676854 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -65,7 +65,7 @@ #include "hw/qdev-clock.h" #include "qom/object.h" -#define MPS2TZ_NUMIRQ 92 +#define MPS2TZ_NUMIRQ_MAX 92 typedef enum MPS2TZFPGAType { FPGA_AN505, @@ -81,6 +81,7 @@ struct MPS2TZMachineClass { const uint32_t *oscclk; uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ bool fpgaio_switches; /* Does FPGAIO have SWITCH register? */ + int numirq; /* Number of external interrupts */ const char *armsse_type; }; @@ -105,7 +106,7 @@ struct MPS2TZMachineState { SplitIRQ sec_resp_splitter; qemu_or_irq uart_irq_orgate; DeviceState *lan9118; - SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ]; + SplitIRQ cpu_irq_splitter[MPS2TZ_NUMIRQ_MAX]; Clock *sysclk; Clock *s32kclk; }; @@ -140,8 +141,9 @@ static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) { /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */ MachineClass *mc = MACHINE_GET_CLASS(mms); + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); - assert(irqno < MPS2TZ_NUMIRQ); + assert(irqno < mmc->numirq); if (mc->max_cpus > 1) { return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); @@ -428,7 +430,7 @@ static void mps2tz_common_init(MachineState *machine) iotkitdev = DEVICE(&mms->iotkit); object_property_set_link(OBJECT(&mms->iotkit), "memory", OBJECT(system_memory), &error_abort); - qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", MPS2TZ_NUMIRQ); + qdev_prop_set_uint32(iotkitdev, "EXP_NUMIRQ", mmc->numirq); qdev_connect_clock_in(iotkitdev, "MAINCLK", mms->sysclk); qdev_connect_clock_in(iotkitdev, "S32KCLK", mms->s32kclk); sysbus_realize(SYS_BUS_DEVICE(&mms->iotkit), &error_fatal); @@ -439,8 +441,9 @@ static void mps2tz_common_init(MachineState *machine) * board. If there is only one CPU, we can just wire the device IRQ * directly to the SSE's IRQ input. */ + assert(mmc->numirq <= MPS2TZ_NUMIRQ_MAX); if (mc->max_cpus > 1) { - for (i = 0; i < MPS2TZ_NUMIRQ; i++) { + for (i = 0; i < mmc->numirq; i++) { char *name = g_strdup_printf("mps2-irq-splitter%d", i); SplitIRQ *splitter = &mms->cpu_irq_splitter[i]; @@ -693,6 +696,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data) mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); mmc->fpgaio_num_leds = 2; mmc->fpgaio_switches = false; + mmc->numirq = 92; mmc->armsse_type = TYPE_IOTKIT; } @@ -713,6 +717,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data) mmc->len_oscclk = ARRAY_SIZE(an505_oscclk); mmc->fpgaio_num_leds = 2; mmc->fpgaio_switches = false; + mmc->numirq = 92; mmc->armsse_type = TYPE_SSE200; } From patchwork Fri Feb 5 17:00:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 376941 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp2453548jah; Fri, 5 Feb 2021 09:29:08 -0800 (PST) X-Google-Smtp-Source: ABdhPJy8cRrZo1wHLrc6JzDtaWQFhwCXA7tXgOwqozY2MfW3J2LssOAigBri7/74aJUcUOF42/3a X-Received: by 2002:a25:3247:: with SMTP id y68mr7316486yby.153.1612546148109; Fri, 05 Feb 2021 09:29:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612546148; cv=none; d=google.com; s=arc-20160816; b=bL0rMQsnv2NBDJ1bAYUl7H5xoGzKHJUJiI13Jj354eItQuKPemi0YX4vxafgsCV65Y a569je3/41sxDNTB1eINKEppo4yssCiJ5AfCnomBHZmno5krX+2gVVkEulwd9Zm7TD/m inSuQxT01hmZG3MJYnasXjbhxfOYmJibAwEr2dczr/zQeLKAQXUZH3uDZ1q6wwVl445C NaVRk2G/KaOkg0+3XTqZa+6A7OOVomaPuySFUc1uGgafDxq8QxTJmbyRgQ15zo12dwrj NfY3+8aZLYTOUe28Em4D1N+dDA9hmPw/KtmlJfhH2rnM1YyDdW8csi35gZ//c08KEzJQ bdKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DWcDLedvIdrpO/Dyf18yelSJMFxD3oqKzuBHwfEwOy0=; b=rzUPXvqTfuKI+vgNqTdHhfnkeb3fvjXh7XAFzWE3Czqd92pLZJ9ss1TtAHWTuBYFrw aQzo303Q8mEHOnkPhsC1D8EQw5TtwKXWKOfltHalCrjCCxwMQkfIsR3IBx8I0ujkQO9n pM/9kjGn2y/Zl7cZMMiJ/KNY3GY37jo+3XaGmC5+7Lxe9ZD7KNMGb6Ftd4Xiyr5i1Dip 67Pd7M4j6Rk63R8LzBtKR8ZkJ0BUJNpu5D95olCxGcg7blRKJAPweD0zTapkn2EuxrHP A0hD01eIhF0i+zzXrgFs8QqalxXEk7xYsarEeBGqmhVdrpQz862A0wJJ2Q5HnbDoasBL JPqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MwNWdA25; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:29 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 10/24] hw/misc/mps2-scc: Implement CFG_REG5 and CFG_REG6 for MPS3 AN524 Date: Fri, 5 Feb 2021 17:00:05 +0000 Message-Id: <20210205170019.25319-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The AN524 version of the SCC interface has different behaviour for some of the CFG registers; implement it. Each board in this family can have minor differences in the meaning of the CFG registers, so rather than trying to specify all the possible semantics via individual device properties, we make the behaviour conditional on the part-number field of the SCC_ID register which the board code already passes us. For the AN524, the differences are: * CFG3 is reserved rather than being board switches * CFG5 is a new register ("ACLK Frequency in Hz") * CFG6 is a new register ("Clock divider for BRAM") We implement both of the new registers as reads-as-written. Signed-off-by: Peter Maydell --- include/hw/misc/mps2-scc.h | 3 ++ hw/misc/mps2-scc.c | 71 ++++++++++++++++++++++++++++++++++++-- 2 files changed, 72 insertions(+), 2 deletions(-) -- 2.20.1 diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h index 514da49f69e..49d070616aa 100644 --- a/include/hw/misc/mps2-scc.h +++ b/include/hw/misc/mps2-scc.h @@ -29,7 +29,10 @@ struct MPS2SCC { uint32_t cfg0; uint32_t cfg1; + uint32_t cfg2; uint32_t cfg4; + uint32_t cfg5; + uint32_t cfg6; uint32_t cfgdata_rtn; uint32_t cfgdata_out; uint32_t cfgctrl; diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c index 52a4e183b71..562ace06a58 100644 --- a/hw/misc/mps2-scc.c +++ b/hw/misc/mps2-scc.c @@ -31,8 +31,11 @@ REG32(CFG0, 0) REG32(CFG1, 4) +REG32(CFG2, 8) REG32(CFG3, 0xc) REG32(CFG4, 0x10) +REG32(CFG5, 0x14) +REG32(CFG6, 0x18) REG32(CFGDATA_RTN, 0xa0) REG32(CFGDATA_OUT, 0xa4) REG32(CFGCTRL, 0xa8) @@ -49,6 +52,12 @@ REG32(DLL, 0x100) REG32(AID, 0xFF8) REG32(ID, 0xFFC) +static int scc_partno(MPS2SCC *s) +{ + /* Return the partno field of the SCC_ID (0x524, 0x511, etc) */ + return extract32(s->id, 4, 8); +} + /* Handle a write via the SYS_CFG channel to the specified function/device. * Return false on error (reported to guest via SYS_CFGCTRL ERROR bit). */ @@ -100,7 +109,18 @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size) case A_CFG1: r = s->cfg1; break; + case A_CFG2: + if (scc_partno(s) != 0x524) { + /* CFG2 reserved on other boards */ + goto bad_offset; + } + r = s->cfg2; + break; case A_CFG3: + if (scc_partno(s) == 0x524) { + /* CFG3 reserved on AN524 */ + goto bad_offset; + } /* These are user-settable DIP switches on the board. We don't * model that, so just return zeroes. */ @@ -109,6 +129,20 @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size) case A_CFG4: r = s->cfg4; break; + case A_CFG5: + if (scc_partno(s) != 0x524) { + /* CFG5 reserved on other boards */ + goto bad_offset; + } + r = s->cfg5; + break; + case A_CFG6: + if (scc_partno(s) != 0x524) { + /* CFG6 reserved on other boards */ + goto bad_offset; + } + r = s->cfg6; + break; case A_CFGDATA_RTN: r = s->cfgdata_rtn; break; @@ -131,6 +165,7 @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size) r = s->id; break; default: + bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "MPS2 SCC read: bad offset %x\n", (int) offset); r = 0; @@ -159,6 +194,30 @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value, led_set_state(s->led[i], extract32(value, i, 1)); } break; + case A_CFG2: + if (scc_partno(s) != 0x524) { + /* CFG2 reserved on other boards */ + goto bad_offset; + } + /* AN524: QSPI Select signal */ + s->cfg2 = value; + break; + case A_CFG5: + if (scc_partno(s) != 0x524) { + /* CFG5 reserved on other boards */ + goto bad_offset; + } + /* AN524: ACLK frequency in Hz */ + s->cfg5 = value; + break; + case A_CFG6: + if (scc_partno(s) != 0x524) { + /* CFG6 reserved on other boards */ + goto bad_offset; + } + /* AN524: Clock divider for BRAM */ + s->cfg6 = value; + break; case A_CFGDATA_OUT: s->cfgdata_out = value; break; @@ -202,6 +261,7 @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value, s->dll = deposit32(s->dll, 24, 8, extract32(value, 24, 8)); break; default: + bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "MPS2 SCC write: bad offset 0x%x\n", (int) offset); break; @@ -222,6 +282,9 @@ static void mps2_scc_reset(DeviceState *dev) trace_mps2_scc_reset(); s->cfg0 = 0; s->cfg1 = 0; + s->cfg2 = 0; + s->cfg5 = 0; + s->cfg6 = 0; s->cfgdata_rtn = 0; s->cfgdata_out = 0; s->cfgctrl = 0x100000; @@ -260,11 +323,15 @@ static void mps2_scc_realize(DeviceState *dev, Error **errp) static const VMStateDescription mps2_scc_vmstate = { .name = "mps2-scc", - .version_id = 2, - .minimum_version_id = 2, + .version_id = 3, + .minimum_version_id = 3, .fields = (VMStateField[]) { VMSTATE_UINT32(cfg0, MPS2SCC), VMSTATE_UINT32(cfg1, MPS2SCC), + VMSTATE_UINT32(cfg2, MPS2SCC), + /* cfg3, cfg4 are read-only so need not be migrated */ + VMSTATE_UINT32(cfg5, MPS2SCC), + VMSTATE_UINT32(cfg6, MPS2SCC), VMSTATE_UINT32(cfgdata_rtn, MPS2SCC), VMSTATE_UINT32(cfgdata_out, MPS2SCC), VMSTATE_UINT32(cfgctrl, MPS2SCC), From patchwork Fri Feb 5 17:00:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 376963 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp2492748jah; Fri, 5 Feb 2021 10:11:37 -0800 (PST) X-Google-Smtp-Source: ABdhPJwk/3ZrKmC2bxIEb0atbRvaC0Qv1uUYDFSnXc3sZEhDNgN1lV9ywOrc8GKbb9rgg2p8eUjV X-Received: by 2002:a25:443:: with SMTP id 64mr7611994ybe.363.1612548697190; Fri, 05 Feb 2021 10:11:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612548697; cv=none; d=google.com; s=arc-20160816; b=W56lVmhznCgF5NMVza4bMKDSrUEGbEVeuezL/eLaY0h/7NlEhK7rijxNYBOaGC9IRV fW/xedX2HJoFVLp0KQ4vH/sOHcYPh6ATbk+ddZxDKr/YFLPKqpZ2VTP35gJK+3EIiuzC GTC23estGCQiU0KtUkoV0vV9RSTQRRAXc12HADs4U/QaPzfbxoT+doDHoWQfXXGChz1O 8mjWSUHI3ZmIjP50+O0WK98ExADFpjPB874rCoYZAkKgxrcIwjw7rj2qF9hIj7uyqk7O fXLWaZlhj1eIFjvFyC3GHnaG8ABKdODXO5WKNWPU5Dtc0g/4xAPkzxa/WZ6XFPeOvgcy T92w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=z2Vyh+lBTQMBhsM4yGTc2A7bMPBGx/fyuKp+EIKhHX0=; b=mlUjZNqKG0V8d9fsaYzbW/el8WgWi/+p3pdwRAWUC4EonblaJEsE/95xkAAjLRiweW cSBm6at4TWd9HgAzBlYxt8CmXHdaMAr1v2qRTFyCwMpOTkjVOO++p/C9yOwFkW416b18 icSfqtuXhyK/8S0P187Va2e2nxtvwx5uQKGaxPQoVUJ7m3NCRRPO38OUBLHRMdizDNSx DbbSC2qoihP5IFOxRHu2Aq24+Nyypr11LzXhrkR1niN8Yr0SuafLnMtr3ieFYhfqs8nW Yj6VPqBvMx7KbnHqQqcxP11nYOPI0dWUFMN8qd48udpkgRUVjanjV+BCre2dnw00Obkp u13Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eJHfa3q+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:30 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 11/24] hw/arm/mps2-tz: Correct wrong interrupt numbers for DMA and SPI Date: Fri, 5 Feb 2021 17:00:06 +0000 Message-Id: <20210205170019.25319-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" On the MPS2 boards, the first 32 interrupt lines are entirely internal to the SSE; interrupt lines for devices outside the SSE start at 32. In the application notes that document each FPGA image, the interrupt wiring is documented from the point of view of the CPU, so '0' is the first of the SSE's interrupts and the devices in the FPGA image itself are '32' and up: so the UART 0 Receive interrupt is 32, the SPI #0 interrupt is 51, and so on. Within our implementation, because the external interrupts must be connected to the EXP_IRQ[0...n] lines of the SSE object, we made the get_sse_irq_in() function take an irqno whose values start at 0 for the first FPGA device interrupt. In this numbering scheme the UART 0 Receive interrupt is 0, the SPI #0 interrupt is 19, and so on. The result of these two different numbering schemes has been that half of the devices were wired up to the wrong IRQs: the UART IRQs are wired up correctly, but the DMA and SPI devices were passing start-at-32 values to get_sse_irq_in() and so being mis-connected. Fix the bug by making get_sse_irq_in() take values specified with the same scheme that the hardware manuals use, to avoid confusion. Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) -- 2.20.1 diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 0f021676854..844092f4fd5 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -139,11 +139,21 @@ static void make_ram_alias(MemoryRegion *mr, const char *name, static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) { - /* Return a qemu_irq which will signal IRQ n to all CPUs in the SSE. */ + /* + * Return a qemu_irq which will signal IRQ n to all CPUs in the + * SSE. The irqno should be as the CPU sees it, so the first + * external-to-the-SSE interrupt is 32. + */ MachineClass *mc = MACHINE_GET_CLASS(mms); MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); - assert(irqno < mmc->numirq); + assert(irqno >= 32 && irqno < (mmc->numirq + 32)); + + /* + * Convert from "CPU irq number" (as listed in the FPGA image + * documentation) to the SSE external-interrupt number. + */ + irqno -= 32; if (mc->max_cpus > 1) { return qdev_get_gpio_in(DEVICE(&mms->cpu_irq_splitter[irqno]), 0); @@ -197,9 +207,9 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); CMSDKAPBUART *uart = opaque; int i = uart - &mms->uart[0]; - int rxirqno = i * 2; - int txirqno = i * 2 + 1; - int combirqno = i + 10; + int rxirqno = i * 2 + 32; + int txirqno = i * 2 + 33; + int combirqno = i + 42; SysBusDevice *s; DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); @@ -266,7 +276,7 @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, s = SYS_BUS_DEVICE(mms->lan9118); sysbus_realize_and_unref(s, &error_fatal); - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 16)); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 48)); return sysbus_mmio_get_region(s, 0); } @@ -507,7 +517,7 @@ static void mps2tz_common_init(MachineState *machine) &error_fatal); qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal); qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, - get_sse_irq_in(mms, 15)); + get_sse_irq_in(mms, 47)); /* Most of the devices in the FPGA are behind Peripheral Protection * Controllers. The required order for initializing things is: From patchwork Fri Feb 5 17:00:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 376942 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp2461195jah; Fri, 5 Feb 2021 09:33:49 -0800 (PST) X-Google-Smtp-Source: ABdhPJyPJWG3/aZBQByng/7yNpU09807t+JxIljCzbGs3c9XT8I1swOq3jAL3LEAUXfm6yaaSe+5 X-Received: by 2002:a25:ef0e:: with SMTP id g14mr7742947ybd.372.1612546429730; Fri, 05 Feb 2021 09:33:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612546429; cv=none; d=google.com; s=arc-20160816; b=ZTU1FxgOU6x1OpBuE6XARmPqfFOy4jtB5gsPcdC3v0kGuBqotxH029+dkTkY6J6c7h VUn7z90ywVKRig8M6AkvSGxZiicbXeDeOl8ugyu+6Hst+BG6C0aEUBYsPrg9DEEJm5gK 4hNQsJIV6/rtKWrV14th+cyPNLRShALX6mmaEAzbFXBzw5kpn1KLsi1RuykUQU/LlDFQ 6TdiXPPln/z5kFh9Vp35mvl0e5a611eU+WLOyzVFjivp/AvFXkrmtA+AA7t3GgnCd30N PFCYVdYiBO59ags9t2zWITJmyHvFboNxbjSluwU9XGdDHLHTQr/9k6IaV9ejZLErIlop w/lA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/pIYyrQAv+HRu+fw0UlomO31PGq1UabPbDOzFOgakDc=; b=NqzDQ04sHtIumiXBNHr1tj9AHFIqCkS0YrHRc7n5t5pQqhNHbPsIQXHdUObFuZ8qgz hD5szA7zxBSAmtwY+fIK1xN7kBCqth8NoKsT0WGRpf9vyUwctVSThf9dM/30DOsep5P6 81RADjUZttDZcjHMXv+iYl5CeYDGY71SCsKXlnFpUuq5LifStavW/nhy7xztcbZX5Uur JbZeWqv2ANTKytsgSTkeSQ8jgd3rhFTEihEORDSrRrdl5AOhjtJyREtwXG6cKgx8yMmV 7ye3Kq8nOGTVU9uKIbKBp4tKtpHZlZAMz0Nvp5F9KTPo+Eu46qCUulX/hAmTQfrfqnUt wEVg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MK10JLpR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:31 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 12/24] hw/arm/mps2-tz: Allow PPCPortInfo structures to specify device interrupts Date: Fri, 5 Feb 2021 17:00:07 +0000 Message-Id: <20210205170019.25319-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The mps2-tz code uses PPCPortInfo data structures to define what devices are present and how they are wired up. Currently we use these to specify device types and addresses, but hard-code the interrupt line wiring in each make_* helper function. This works for the two boards we have at the moment, but the AN524 has some devices with different interrupt assignments. This commit adds the framework to allow PPCPortInfo structures to specify interrupt numbers. We add an array of interrupt numbers to the PPCPortInfo struct, and pass it through to the make_* helpers. The following commit will change the make_* helpers over to using the framework. Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 36 ++++++++++++++++++++++++------------ 1 file changed, 24 insertions(+), 12 deletions(-) -- 2.20.1 diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 844092f4fd5..0c75b2230ed 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -170,7 +170,8 @@ static qemu_irq get_sse_irq_in(MPS2TZMachineState *mms, int irqno) * needs to be plugged into the downstream end of the PPC port. */ typedef MemoryRegion *MakeDevFn(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size); + const char *name, hwaddr size, + const int *irqs); typedef struct PPCPortInfo { const char *name; @@ -178,6 +179,7 @@ typedef struct PPCPortInfo { void *opaque; hwaddr addr; hwaddr size; + int irqs[3]; /* currently no device needs more IRQ lines than this */ } PPCPortInfo; typedef struct PPCInfo { @@ -186,8 +188,9 @@ typedef struct PPCInfo { } PPCInfo; static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, - void *opaque, - const char *name, hwaddr size) + void *opaque, + const char *name, hwaddr size, + const int *irqs) { /* Initialize, configure and realize a TYPE_UNIMPLEMENTED_DEVICE, * and return a pointer to its MemoryRegion. @@ -202,7 +205,8 @@ static MemoryRegion *make_unimp_dev(MPS2TZMachineState *mms, } static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); CMSDKAPBUART *uart = opaque; @@ -227,7 +231,8 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, } static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { MPS2SCC *scc = opaque; DeviceState *sccdev; @@ -249,7 +254,8 @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms, void *opaque, } static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { MPS2FPGAIO *fpgaio = opaque; MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); @@ -262,7 +268,8 @@ static MemoryRegion *make_fpgaio(MPS2TZMachineState *mms, void *opaque, } static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { SysBusDevice *s; NICInfo *nd = &nd_table[0]; @@ -281,7 +288,8 @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, } static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { TZMPC *mpc = opaque; int i = mpc - &mms->ssram_mpc[0]; @@ -318,7 +326,8 @@ static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, } static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { PL080State *dma = opaque; int i = dma - &mms->dma[0]; @@ -373,7 +382,8 @@ static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, } static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { /* * The AN505 has five PL022 SPI controllers. @@ -395,7 +405,8 @@ static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque, } static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque, - const char *name, hwaddr size) + const char *name, hwaddr size, + const int *irqs) { ArmSbconI2CState *i2c = opaque; SysBusDevice *s; @@ -604,7 +615,8 @@ static void mps2tz_common_init(MachineState *machine) continue; } - mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size); + mr = pinfo->devfn(mms, pinfo->opaque, pinfo->name, pinfo->size, + pinfo->irqs); portname = g_strdup_printf("port[%d]", port); object_property_set_link(OBJECT(ppc), portname, OBJECT(mr), &error_fatal); From patchwork Fri Feb 5 17:00:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 376944 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp2467486jah; Fri, 5 Feb 2021 09:39:05 -0800 (PST) X-Google-Smtp-Source: ABdhPJw4/J5LPknHJREYs6IN5DELM2GnvuqULZNa3sy1kquQ5LIB5QDyYmUASiF0xKxFwC8XpZrb X-Received: by 2002:a25:40e:: with SMTP id 14mr7605090ybe.66.1612546745788; Fri, 05 Feb 2021 09:39:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612546745; cv=none; d=google.com; s=arc-20160816; b=IDCAXEwKt4/MoG12JrTtdVrbRkqgNz96llM/4EYFj8u+HQ5YaO+ev1hs75XxFbSWuL jv/T81S56AZvZ0ZHl27z9vuAghPnKYCk7vARpF5jSJgiFJTEB1L9Ng0ReyHOp5oUrpqt R59df6XN9qpeayLI0gMkwOzrrLcOBnc2dPFEH31JdQDASWUOnFEwvSSMRK236h6VRPOR Pi6zF0QY0VvJgwtdmN00AMb3lTtO3Bol5ZhZ2NoVWc1/WUVNtWMShvESa2MbWb4yX8lT epYONL1+GF0LH7CA4573HauKhfXYuvR27kpFSV5uLa+qBb/D/rVYev9Rby0aOfYzgOe0 YLHQ== ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:32 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 13/24] hw/arm/mps2-tz: Move device IRQ info to data structures Date: Fri, 5 Feb 2021 17:00:08 +0000 Message-Id: <20210205170019.25319-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the specification of the IRQ information for the uart, ethernet, dma and spi devices to the data structures. (The other devices handled by the PPCPortInfo structures don't have any interrupt lines we need to wire up.) Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 52 +++++++++++++++++++++++------------------------- 1 file changed, 25 insertions(+), 27 deletions(-) -- 2.20.1 diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 0c75b2230ed..07694413005 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -208,12 +208,10 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, const int *irqs) { + /* The irq[] array is tx, rx, combined, in that order */ MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); CMSDKAPBUART *uart = opaque; int i = uart - &mms->uart[0]; - int rxirqno = i * 2 + 32; - int txirqno = i * 2 + 33; - int combirqno = i + 42; SysBusDevice *s; DeviceState *orgate_dev = DEVICE(&mms->uart_irq_orgate); @@ -222,11 +220,11 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", mmc->sysclk_frq); sysbus_realize(SYS_BUS_DEVICE(uart), &error_fatal); s = SYS_BUS_DEVICE(uart); - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, txirqno)); - sysbus_connect_irq(s, 1, get_sse_irq_in(mms, rxirqno)); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); + sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1])); sysbus_connect_irq(s, 2, qdev_get_gpio_in(orgate_dev, i * 2)); sysbus_connect_irq(s, 3, qdev_get_gpio_in(orgate_dev, i * 2 + 1)); - sysbus_connect_irq(s, 4, get_sse_irq_in(mms, combirqno)); + sysbus_connect_irq(s, 4, get_sse_irq_in(mms, irqs[2])); return sysbus_mmio_get_region(SYS_BUS_DEVICE(uart), 0); } @@ -283,7 +281,7 @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, s = SYS_BUS_DEVICE(mms->lan9118); sysbus_realize_and_unref(s, &error_fatal); - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 48)); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); return sysbus_mmio_get_region(s, 0); } @@ -329,6 +327,7 @@ static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, const int *irqs) { + /* The irq[] array is DMACINTR, DMACINTERR, DMACINTTC, in that order */ PL080State *dma = opaque; int i = dma - &mms->dma[0]; SysBusDevice *s; @@ -373,9 +372,9 @@ static MemoryRegion *make_dma(MPS2TZMachineState *mms, void *opaque, s = SYS_BUS_DEVICE(dma); /* Wire up DMACINTR, DMACINTERR, DMACINTTC */ - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 58 + i * 3)); - sysbus_connect_irq(s, 1, get_sse_irq_in(mms, 56 + i * 3)); - sysbus_connect_irq(s, 2, get_sse_irq_in(mms, 57 + i * 3)); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); + sysbus_connect_irq(s, 1, get_sse_irq_in(mms, irqs[1])); + sysbus_connect_irq(s, 2, get_sse_irq_in(mms, irqs[2])); g_free(mscname); return sysbus_mmio_get_region(s, 0); @@ -394,13 +393,12 @@ static MemoryRegion *make_spi(MPS2TZMachineState *mms, void *opaque, * lines are set via the "MISC" register in the MPS2 FPGAIO device. */ PL022State *spi = opaque; - int i = spi - &mms->spi[0]; SysBusDevice *s; object_initialize_child(OBJECT(mms), name, spi, TYPE_PL022); sysbus_realize(SYS_BUS_DEVICE(spi), &error_fatal); s = SYS_BUS_DEVICE(spi); - sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 51 + i)); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); return sysbus_mmio_get_region(s, 0); } @@ -551,16 +549,16 @@ static void mps2tz_common_init(MachineState *machine) }, { .name = "apb_ppcexp1", .ports = { - { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000 }, - { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000 }, - { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000 }, - { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000 }, - { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000 }, - { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000 }, - { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000 }, - { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000 }, - { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000 }, - { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000 }, + { "spi0", make_spi, &mms->spi[0], 0x40205000, 0x1000, { 51 } }, + { "spi1", make_spi, &mms->spi[1], 0x40206000, 0x1000, { 52 } }, + { "spi2", make_spi, &mms->spi[2], 0x40209000, 0x1000, { 53 } }, + { "spi3", make_spi, &mms->spi[3], 0x4020a000, 0x1000, { 54 } }, + { "spi4", make_spi, &mms->spi[4], 0x4020b000, 0x1000, { 55 } }, + { "uart0", make_uart, &mms->uart[0], 0x40200000, 0x1000, { 32, 33, 42 } }, + { "uart1", make_uart, &mms->uart[1], 0x40201000, 0x1000, { 34, 35, 43 } }, + { "uart2", make_uart, &mms->uart[2], 0x40202000, 0x1000, { 36, 37, 44 } }, + { "uart3", make_uart, &mms->uart[3], 0x40203000, 0x1000, { 38, 39, 45 } }, + { "uart4", make_uart, &mms->uart[4], 0x40204000, 0x1000, { 40, 41, 46 } }, { "i2c0", make_i2c, &mms->i2c[0], 0x40207000, 0x1000 }, { "i2c1", make_i2c, &mms->i2c[1], 0x40208000, 0x1000 }, { "i2c2", make_i2c, &mms->i2c[2], 0x4020c000, 0x1000 }, @@ -582,15 +580,15 @@ static void mps2tz_common_init(MachineState *machine) { "gpio1", make_unimp_dev, &mms->gpio[1], 0x40101000, 0x1000 }, { "gpio2", make_unimp_dev, &mms->gpio[2], 0x40102000, 0x1000 }, { "gpio3", make_unimp_dev, &mms->gpio[3], 0x40103000, 0x1000 }, - { "eth", make_eth_dev, NULL, 0x42000000, 0x100000 }, + { "eth", make_eth_dev, NULL, 0x42000000, 0x100000, { 48 } }, }, }, { .name = "ahb_ppcexp1", .ports = { - { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000 }, - { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000 }, - { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000 }, - { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000 }, + { "dma0", make_dma, &mms->dma[0], 0x40110000, 0x1000, { 58, 56, 57 } }, + { "dma1", make_dma, &mms->dma[1], 0x40111000, 0x1000, { 61, 59, 60 } }, + { "dma2", make_dma, &mms->dma[2], 0x40112000, 0x1000, { 64, 62, 63 } }, + { "dma3", make_dma, &mms->dma[3], 0x40113000, 0x1000, { 67, 65, 66 } }, }, }, }; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:32 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 14/24] hw/arm/mps2-tz: Size the uart-irq-orgate based on the number of UARTs Date: Fri, 5 Feb 2021 17:00:09 +0000 Message-Id: <20210205170019.25319-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We create an OR gate to wire together the overflow IRQs for all the UARTs on the board; this has to have twice the number of inputs as there are UARTs, since each UART feeds it a TX overflow and an RX overflow interrupt line. Replace the hardcoded '10' with a calculation based on the size of the uart[] array in the MPS2TZMachineState. (We rely on OR gate inputs that are never wired up or asserted being treated as always-zero.) Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) -- 2.20.1 diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 07694413005..87993516816 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -516,13 +516,18 @@ static void mps2tz_common_init(MachineState *machine) */ memory_region_add_subregion(system_memory, 0x80000000, machine->ram); - /* The overflow IRQs for all UARTs are ORed together. + /* + * The overflow IRQs for all UARTs are ORed together. * Tx, Rx and "combined" IRQs are sent to the NVIC separately. - * Create the OR gate for this. + * Create the OR gate for this: it has one input for the TX overflow + * and one for the RX overflow for each UART we might have. + * (If the board has fewer than the maximum possible number of UARTs + * those inputs are never wired up and are treated as always-zero.) */ object_initialize_child(OBJECT(mms), "uart-irq-orgate", &mms->uart_irq_orgate, TYPE_OR_IRQ); - object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines", 10, + object_property_set_int(OBJECT(&mms->uart_irq_orgate), "num-lines", + 2 * ARRAY_SIZE(mms->uart), &error_fatal); qdev_realize(DEVICE(&mms->uart_irq_orgate), NULL, &error_fatal); qdev_connect_gpio_out(DEVICE(&mms->uart_irq_orgate), 0, From patchwork Fri Feb 5 17:00:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 376950 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp2477242jah; Fri, 5 Feb 2021 09:51:13 -0800 (PST) X-Google-Smtp-Source: ABdhPJwVwKzmJfCOBQRmw5n3acquiI4b046INvgcAgCy7nscx3r+Na7G6JNBlOYEY8dGsm1zimga X-Received: by 2002:a25:cb05:: with SMTP id b5mr7878491ybg.233.1612547473237; Fri, 05 Feb 2021 09:51:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612547473; cv=none; d=google.com; s=arc-20160816; b=ra/LGlfTf8y7ysi6woD3ydu36AsYDJfxbLukhRZAVlIo/9wcSos+JxT6tsZoEsyjQK rqaICRrWNwMTgtGSviD8uSB18IZQ3ElFezvVfhh/7EHp2umYj7jW3Ld/b26aZsw8XOI4 OfRIBKUgOueTIVqMRM2YX3kOEOTFL1fwniHLiCXTYqWL1mEycPT3w0lL8mwd7dxiLxKE 2Tr4yxpblcuXddpeYN3+5s7Z1rbUjVBNurbGafOzbEVMzTY+sGKVnBk47wET6FFxSR7y X+VXc5crQnvrSjc0Stm2b3eQdvG4BW601QYahZ8CYFl6Sm9Vy33FHL1Si1StFMpD+Pn0 FXhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=VpEyWn0wqUXodQwTIXDgKgRTk0zKQyW4b0d+sVm3VCI=; b=kGmYZ17MHI0cgaoAlZz7fz1A87HP7NnvIXFHxgusym3M0O2EeY6MkgZ+HqmHCv5Ozt m3EP4nL77+/i0a9/4S0cTkExL/RQLjykVRO6a6q/2nZ8BAyVz2HGK+So2rNKSoe3J8Ea dHPuO/w/cLYNjOg3eDOuJafWIXEbhRjTQdMZOqDkEcJxHTkS6lbWGLiy4lZRApk9Jx7A 74+zlRgpY8W3f9uKjH0svVrXJaYEIXiZK86aRM+dzshZd1Cw1dBTZNT2p95nJO2U1a30 gAiwaQWekTEKC7OUI/0CMz+JMWCLlp3wXPc4veOCuSI+z0rKwTzYMtgtAXdDz1WNxtDJ yIfg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BIWjCI6j; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:33 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 15/24] hw/arm/mps2-tz: Allow boards to have different PPCInfo data Date: Fri, 5 Feb 2021 17:00:10 +0000 Message-Id: <20210205170019.25319-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The AN505 and AN521 have the same device layout, but the AN524 is somewhat different. Allow for more than one PPCInfo array, which can be selected based on the board type. Signed-off-by: Peter Maydell --- We can't just put the arrays at file-scope and set up pointers to them in the MPS2TZMachineClass struct, because the array members include entries like "&mms->uart[0]" which is only valid inside the mps2tz_common_init() function. --- hw/arm/mps2-tz.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) -- 2.20.1 diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 87993516816..721ac444920 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -423,6 +423,8 @@ static void mps2tz_common_init(MachineState *machine) MemoryRegion *system_memory = get_system_memory(); DeviceState *iotkitdev; DeviceState *dev_splitter; + const PPCInfo *ppcs; + int num_ppcs; int i; if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) { @@ -544,7 +546,7 @@ static void mps2tz_common_init(MachineState *machine) * + wire up the PPC's control lines to the IoTKit object */ - const PPCInfo ppcs[] = { { + const PPCInfo an505_ppcs[] = { { .name = "apb_ppcexp0", .ports = { { "ssram-0", make_mpc, &mms->ssram_mpc[0], 0x58007000, 0x1000 }, @@ -598,7 +600,17 @@ static void mps2tz_common_init(MachineState *machine) }, }; - for (i = 0; i < ARRAY_SIZE(ppcs); i++) { + switch (mmc->fpga_type) { + case FPGA_AN505: + case FPGA_AN521: + ppcs = an505_ppcs; + num_ppcs = ARRAY_SIZE(an505_ppcs); + break; + default: + g_assert_not_reached(); + } + + for (i = 0; i < num_ppcs; i++) { const PPCInfo *ppcinfo = &ppcs[i]; TZPPC *ppc = &mms->ppc[i]; DeviceState *ppcdev; From patchwork Fri Feb 5 17:00:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 376961 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp2489838jah; Fri, 5 Feb 2021 10:08:00 -0800 (PST) X-Google-Smtp-Source: ABdhPJyn1htFFVWO9Hd1vhTyW/RgtseTJxgrGwYkHvaz7e9dfRLDqw8B0OYtXkAFexOlH73Hats7 X-Received: by 2002:a25:8590:: with SMTP id x16mr7644133ybk.435.1612548480046; Fri, 05 Feb 2021 10:08:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612548480; cv=none; d=google.com; s=arc-20160816; b=WPxJ77P5JFYQ8BA1vo+A3F/dVQV73Uz1SQ/lW7PuKyhLZ5ptxrHULx6fTkL+ezL3WG ifIXFKSCqnk0cJwksZbFHxnhF/RsvN2DJ7Tsl+inBv3oXsY5WxMXnwUE4+KFwE0wCsht lhtppiNZFY1++ZOwgWlrWLxjazojksHuKje1aJ4Mu6inJ5F1tcRujoE7mUfFLbZhCCoZ 9s9kr+WQAGANxg0pRnp+OWVLGm2J9ZcLyMR4q7W9eQUra9Ft5wlFUrtLX02hMASGedRm iv89tm7sp/DsjcbQ59sNe8mrDXSaokLNO3lad/9GW7/VHFr5M/E+ggUxZjfRHFDXJLt1 GnaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xP6Xb4op7arwmIlS9Ob8QiEZZSJzfIan0T/eBfhQnhQ=; b=m8+pp+hQHJhBhHWRJEA+raAQoliifTxSGY7ZNOV4ZKG0Z7XkLDJiwTnsRscGIQOaPN obz5EZ3yqYQu/4dxh4/yTc4CQmIWpPABU55wFBUodXpqBZyIRh5DZerA2t7N8HvMERIr 4YBvgjBh5sjiOvpwO1yT6IHI5hEjpogJ2d9bDzCWoU1CB92vOSXxN4cjQQdFZb2QMjir bMW8Hny2AvZnIJA9Hx/PAVEGKcrgjdZeB4BGWvNUreCLeWri7moXNOlDRdvVcVbxomJv nroCHQN35I/9erUcSekBrKSP60eHxjZioBgNSzwef84/l+2B7wTEbNE6M0shLuYc5xea rg5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LhrF5ece; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:34 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 16/24] hw/arm/mps2-tz: Make RAM arrangement board-specific Date: Fri, 5 Feb 2021 17:00:11 +0000 Message-Id: <20210205170019.25319-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The AN505 and AN521 have the same layout of RAM; the AN524 does not. Replace the current hard-coding of where the RAM is and which parts of it are behind which MPCs with a data-driven approach. Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 175 +++++++++++++++++++++++++++++++++++++---------- 1 file changed, 138 insertions(+), 37 deletions(-) -- 2.20.1 diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 721ac444920..1e8dde768c2 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -66,12 +66,35 @@ #include "qom/object.h" #define MPS2TZ_NUMIRQ_MAX 92 +#define MPS2TZ_RAM_MAX 4 typedef enum MPS2TZFPGAType { FPGA_AN505, FPGA_AN521, } MPS2TZFPGAType; +/* + * Define the layout of RAM in a board, including which parts are + * behind which MPCs. + * mrindex specifies the index into mms->ram[] to use for the backing RAM; + * -1 means "use the system RAM". + */ +typedef struct RAMInfo { + const char *name; + uint32_t base; + uint32_t size; + int mpc; /* MPC number, -1 for "not behind an MPC" */ + int mrindex; + int flags; +} RAMInfo; + +/* + * Flag values: + * IS_ALIAS: this RAM area is an alias to the upstream end of the + * MPC specified by its .mpc value + */ +#define IS_ALIAS 1 + struct MPS2TZMachineClass { MachineClass parent; MPS2TZFPGAType fpga_type; @@ -82,6 +105,7 @@ struct MPS2TZMachineClass { uint32_t fpgaio_num_leds; /* Number of LEDs in FPGAIO LED0 register */ bool fpgaio_switches; /* Does FPGAIO have SWITCH register? */ int numirq; /* Number of external interrupts */ + const RAMInfo *raminfo; const char *armsse_type; }; @@ -89,12 +113,11 @@ struct MPS2TZMachineState { MachineState parent; ARMSSE iotkit; - MemoryRegion ssram[3]; - MemoryRegion ssram1_m; + MemoryRegion ram[MPS2TZ_RAM_MAX]; MPS2SCC scc; MPS2FPGAIO fpgaio; TZPPC ppc[5]; - TZMPC ssram_mpc[3]; + TZMPC mpc[3]; PL022State spi[5]; ArmSbconI2CState i2c[4]; UnimplementedDeviceState i2s_audio; @@ -126,6 +149,77 @@ static const uint32_t an505_oscclk[] = { 25000000, }; +static const RAMInfo an505_raminfo[] = { { + .name = "ssram-0", + .base = 0x00000000, + .size = 0x00400000, + .mpc = 0, + .mrindex = 0, + }, { + .name = "ssram-1", + .base = 0x28000000, + .size = 0x00200000, + .mpc = 1, + .mrindex = 1, + }, { + .name = "ssram-2", + .base = 0x28200000, + .size = 0x00200000, + .mpc = 2, + .mrindex = 2, + }, { + .name = "ssram-0-alias", + .base = 0x00400000, + .size = 0x00400000, + .mpc = 0, + .mrindex = 3, + .flags = IS_ALIAS, + }, { + /* Use the largest bit of contiguous RAM as our "system memory" */ + .name = "mps.ram", + .base = 0x80000000, + .size = 16 * MiB, + .mpc = -1, + .mrindex = -1, + }, { + .name = NULL, + }, +}; + +static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mpc) +{ + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); + const RAMInfo *p; + + for (p = mmc->raminfo; p->name; p++) { + if (p->mpc == mpc && !(p->flags & IS_ALIAS)) { + return p; + } + } + /* if raminfo array doesn't have an entry for each MPC this is a bug */ + g_assert_not_reached(); +} + +static MemoryRegion *mr_for_raminfo(MPS2TZMachineState *mms, + const RAMInfo *raminfo) +{ + /* Return an initialized MemoryRegion for the RAMInfo. */ + MemoryRegion *ram; + + if (raminfo->mrindex < 0) { + /* Means this RAMInfo is for QEMU's "system memory" */ + MachineState *machine = MACHINE(mms); + return machine->ram; + } + + assert(raminfo->mrindex < MPS2TZ_RAM_MAX); + ram = &mms->ram[raminfo->mrindex]; + + memory_region_init_ram(ram, NULL, raminfo->name, + raminfo->size, &error_fatal); + return ram; +} + /* Create an alias of an entire original MemoryRegion @orig * located at @base in the memory map. */ @@ -290,35 +384,23 @@ static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, const int *irqs) { TZMPC *mpc = opaque; - int i = mpc - &mms->ssram_mpc[0]; - MemoryRegion *ssram = &mms->ssram[i]; + int i = mpc - &mms->mpc[0]; MemoryRegion *upstream; - char *mpcname = g_strdup_printf("%s-mpc", name); - static uint32_t ramsize[] = { 0x00400000, 0x00200000, 0x00200000 }; - static uint32_t rambase[] = { 0x00000000, 0x28000000, 0x28200000 }; + const RAMInfo *raminfo = find_raminfo_for_mpc(mms, i); + MemoryRegion *ram = mr_for_raminfo(mms, raminfo); - memory_region_init_ram(ssram, NULL, name, ramsize[i], &error_fatal); - - object_initialize_child(OBJECT(mms), mpcname, mpc, TYPE_TZ_MPC); - object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ssram), + object_initialize_child(OBJECT(mms), name, mpc, TYPE_TZ_MPC); + object_property_set_link(OBJECT(mpc), "downstream", OBJECT(ram), &error_fatal); sysbus_realize(SYS_BUS_DEVICE(mpc), &error_fatal); /* Map the upstream end of the MPC into system memory */ upstream = sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 1); - memory_region_add_subregion(get_system_memory(), rambase[i], upstream); + memory_region_add_subregion(get_system_memory(), raminfo->base, upstream); /* and connect its interrupt to the IoTKit */ qdev_connect_gpio_out_named(DEVICE(mpc), "irq", 0, qdev_get_gpio_in_named(DEVICE(&mms->iotkit), "mpcexp_status", i)); - /* The first SSRAM is a special case as it has an alias; accesses to - * the alias region at 0x00400000 must also go to the MPC upstream. - */ - if (i == 0) { - make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", upstream, 0x00400000); - } - - g_free(mpcname); /* Return the register interface MR for our caller to map behind the PPC */ return sysbus_mmio_get_region(SYS_BUS_DEVICE(mpc), 0); } @@ -415,6 +497,28 @@ static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque, return sysbus_mmio_get_region(s, 0); } +static void create_non_mpc_ram(MPS2TZMachineState *mms) +{ + /* + * Handle the RAMs which are either not behind MPCs or which are + * aliases to another MPC. + */ + const RAMInfo *p; + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); + + for (p = mmc->raminfo; p->name; p++) { + if (p->flags & IS_ALIAS) { + SysBusDevice *mpc_sbd = SYS_BUS_DEVICE(&mms->mpc[p->mpc]); + MemoryRegion *upstream = sysbus_mmio_get_region(mpc_sbd, 1); + make_ram_alias(&mms->ram[p->mrindex], p->name, upstream, p->base); + } else if (p->mpc == -1) { + /* RAM not behind an MPC */ + MemoryRegion *mr = mr_for_raminfo(mms, p); + memory_region_add_subregion(get_system_memory(), p->base, mr); + } + } +} + static void mps2tz_common_init(MachineState *machine) { MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); @@ -499,24 +603,17 @@ static void mps2tz_common_init(MachineState *machine) qdev_connect_gpio_out_named(iotkitdev, "sec_resp_cfg", 0, qdev_get_gpio_in(dev_splitter, 0)); - /* The IoTKit sets up much of the memory layout, including + /* + * The IoTKit sets up much of the memory layout, including * the aliases between secure and non-secure regions in the - * address space. The FPGA itself contains: - * - * 0x00000000..0x003fffff SSRAM1 - * 0x00400000..0x007fffff alias of SSRAM1 - * 0x28000000..0x283fffff 4MB SSRAM2 + SSRAM3 - * 0x40100000..0x4fffffff AHB Master Expansion 1 interface devices - * 0x80000000..0x80ffffff 16MB PSRAM - */ - - /* The FPGA images have an odd combination of different RAMs, + * address space, and also most of the devices in the system. + * The FPGA itself contains various RAMs and some additional devices. + * The FPGA images have an odd combination of different RAMs, * because in hardware they are different implementations and * connected to different buses, giving varying performance/size * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily - * call the 16MB our "system memory", as it's the largest lump. + * call the largest lump our "system memory". */ - memory_region_add_subregion(system_memory, 0x80000000, machine->ram); /* * The overflow IRQs for all UARTs are ORed together. @@ -549,9 +646,9 @@ static void mps2tz_common_init(MachineState *machine) const PPCInfo an505_ppcs[] = { { .name = "apb_ppcexp0", .ports = { - { "ssram-0", make_mpc, &mms->ssram_mpc[0], 0x58007000, 0x1000 }, - { "ssram-1", make_mpc, &mms->ssram_mpc[1], 0x58008000, 0x1000 }, - { "ssram-2", make_mpc, &mms->ssram_mpc[2], 0x58009000, 0x1000 }, + { "ssram-0-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 }, + { "ssram-1-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 }, + { "ssram-2-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 }, }, }, { .name = "apb_ppcexp1", @@ -684,6 +781,8 @@ static void mps2tz_common_init(MachineState *machine) create_unimplemented_device("FPGA NS PC", 0x48007000, 0x1000); + create_non_mpc_ram(mms); + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000); } @@ -734,6 +833,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data) mmc->fpgaio_num_leds = 2; mmc->fpgaio_switches = false; mmc->numirq = 92; + mmc->raminfo = an505_raminfo; mmc->armsse_type = TYPE_IOTKIT; } @@ -755,6 +855,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data) mmc->fpgaio_num_leds = 2; mmc->fpgaio_switches = false; mmc->numirq = 92; + mmc->raminfo = an505_raminfo; /* AN521 is the same as AN505 here */ mmc->armsse_type = TYPE_SSE200; } From patchwork Fri Feb 5 17:00:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 376949 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp2476873jah; Fri, 5 Feb 2021 09:50:46 -0800 (PST) X-Google-Smtp-Source: ABdhPJzeFY0UtmvGncrJw8GgvOKehq9YglX7+c291lXp7wg/ztpV2Op9VmEB/FisPUuD3a0lyUVL X-Received: by 2002:a25:c553:: with SMTP id v80mr7957518ybe.422.1612547446476; Fri, 05 Feb 2021 09:50:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612547446; cv=none; d=google.com; s=arc-20160816; b=IDL+vYYhbpYaLOh/i1bm8Qn7FKF4igFwVptb9PdpBnnSYXkYKvLxUlNKyM3YwQVR5V dnvRs7/x6JQop8y+96Cz1TeJOX+Y0N7s43zpvW38C/elYqHUClJR32q/E1ktC/JTP2xu 1iW64O7ey6EGMuvYPVRv3sm4iz2IFWh609Lv7obeD3HBiZa+wAwvfvvVD7OyNseloTo2 CUMzSpEzSqtnK9myA14boHcvg5I63iQh9MYW6MCD5NZjozsOGX9Iv6c/JSd/2EZ7wwLX UAKTTDIPALPQUrFs0B0mvlx2EOjL1nHTDyw1Xu8GmcOxHgFEelF49v1ByTPadWocCONa OxCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jMMA1bcWT9Cf0LVPoBI3bN3FRfuppErnoBYF5x3xFs8=; b=aaxqzc/C3e8Fdo0rXzw5YZ6z2/cN16f0srE4OgYG51OPncEg7673Oxm6pMNWyX7s3T Vcwa7A13XraggdalPUQa6mI5ptUO2jbfP2dJ8fiy460HzM4A9J8KVsgxgU1lFblK57Ck TbD9KrpWKI37l6G27AAafgB4x/O0ejFPlXOdqJeMvsWBS1Tex0CIdvrsGvk0iQ68vLM9 DGFED31Q+cZ/6pcjKf+WjdHIzY6/2uLaB5lgtxvETdI2BKfI4cxcsdLAw8Aj4Jzh19Y5 eAxe0/WdN/+/H39EAzdGV7rRFvG3XBIPknwwdHCCTCSS5YJQlhWVDCF9wXFZiscUJTRg 2ZEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BSJcvNyl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:35 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 17/24] hw/arm/mps2-tz: Set MachineClass default_ram info from RAMInfo data Date: Fri, 5 Feb 2021 17:00:12 +0000 Message-Id: <20210205170019.25319-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Instead of hardcoding the MachineClass default_ram_size and default_ram_id fields, set them on class creation by finding the entry in the RAMInfo array which is marked as being the QEMU system RAM. Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) -- 2.20.1 diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 1e8dde768c2..b46b32746e0 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -811,8 +811,26 @@ static void mps2tz_class_init(ObjectClass *oc, void *data) mc->init = mps2tz_common_init; iic->check = mps2_tz_idau_check; - mc->default_ram_size = 16 * MiB; - mc->default_ram_id = "mps.ram"; +} + +static void mps2tz_set_default_ram_info(MPS2TZMachineClass *mmc) +{ + /* + * Set mc->default_ram_size and default_ram_id from the + * information in mmc->raminfo. + */ + MachineClass *mc = MACHINE_CLASS(mmc); + const RAMInfo *p; + + for (p = mmc->raminfo; p->name; p++) { + if (p->mrindex < 0) { + /* Found the entry for "system memory" */ + mc->default_ram_size = p->size; + mc->default_ram_id = p->name; + return; + } + } + g_assert_not_reached(); } static void mps2tz_an505_class_init(ObjectClass *oc, void *data) @@ -835,6 +853,7 @@ static void mps2tz_an505_class_init(ObjectClass *oc, void *data) mmc->numirq = 92; mmc->raminfo = an505_raminfo; mmc->armsse_type = TYPE_IOTKIT; + mps2tz_set_default_ram_info(mmc); } static void mps2tz_an521_class_init(ObjectClass *oc, void *data) @@ -857,6 +876,7 @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data) mmc->numirq = 92; mmc->raminfo = an505_raminfo; /* AN521 is the same as AN505 here */ mmc->armsse_type = TYPE_SSE200; + mps2tz_set_default_ram_info(mmc); } static const TypeInfo mps2tz_info = { From patchwork Fri Feb 5 17:00:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 376960 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp2488141jah; Fri, 5 Feb 2021 10:05:43 -0800 (PST) X-Google-Smtp-Source: ABdhPJxRX3yIAWH8fLrYn1jSDDmBlegyNTvbDQqObpf97/gGeXNF4RFYApMhs932llsvyzhCUaCu X-Received: by 2002:ab0:1d8e:: with SMTP id l14mr4109940uak.65.1612548343333; Fri, 05 Feb 2021 10:05:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612548343; cv=none; d=google.com; s=arc-20160816; b=RmLS98rQx1cA9iFFiI7fMaX7Z3pZm6NO/tzHen2ZEU8jRbpjHXTdofYyDi8WmhmOBQ s+mVsK6hTlNIXhiX8SN90aclcbt1YnfhzHefDDlQTzyAPrgVrBX/dxd6/8upDIRM/bab mcIUBtbGYppov7wFehWfCXYYGVwkXdfyPg66jlsxI3pnbZH5DJss7fhDquIUpz+e2G1l ZqXA2TC/c3zndraMKLbYOCT5F3YoIqUXMCYU1Lzg5uUmJyFW154PWXFr6g7oovszH2TR Nst4n3Af98lIQZqaCviumQUQOX7N09k0R6yr9Np5hQuxz10uotLwWR8a4isioA91cao4 zfqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=M0p8lPGYTACYbzRLtR7fBRTYLnsV3hqqOQcj+ku4dlo=; b=wQKoLMtKR7O+k/nq0VHwurQ9zAZxvTAu4g3ecoeLpTQCpVZpDeQ38S45wHe2kLHxMi cebDGnDpGhwyamJMlYoSZe7EsSzvrRVv2yoZagTVskG84w0GLxoHPmZ7flD2Oz0gCC0W tPU7oD0FCN4+1Koh425a47SnvrDIcfthTI0Q6TwUXyp4G1ht3CaCIi1wcNNDzMwwB67m t5qPG8624u8MrJK0KMKKNj6p98RwH15nK3IqVpd3DdsONa9wA6qsPcGgLJSaIgXXWudT 2VYpBZ/kvpVWrYlx5pf2vbJTQPqLV5ydFnkDyxBfG/J5ORqpbB+gH48CZU4Seh1lKXcs oTfA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pY+t6REU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:35 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 18/24] hw/arm/mps2-tz: Support ROMs as well as RAMs Date: Fri, 5 Feb 2021 17:00:13 +0000 Message-Id: <20210205170019.25319-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The AN505 and AN521 don't have any read-only memory, but the AN524 does; add a flag to ROMInfo to mark a region as ROM. Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.20.1 diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index b46b32746e0..ce5e804c734 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -92,8 +92,10 @@ typedef struct RAMInfo { * Flag values: * IS_ALIAS: this RAM area is an alias to the upstream end of the * MPC specified by its .mpc value + * IS_ROM: this RAM area is read-only */ #define IS_ALIAS 1 +#define IS_ROM 2 struct MPS2TZMachineClass { MachineClass parent; @@ -209,6 +211,7 @@ static MemoryRegion *mr_for_raminfo(MPS2TZMachineState *mms, if (raminfo->mrindex < 0) { /* Means this RAMInfo is for QEMU's "system memory" */ MachineState *machine = MACHINE(mms); + assert(!(raminfo->flags & IS_ROM)); return machine->ram; } @@ -217,6 +220,9 @@ static MemoryRegion *mr_for_raminfo(MPS2TZMachineState *mms, memory_region_init_ram(ram, NULL, raminfo->name, raminfo->size, &error_fatal); + if (raminfo->flags & IS_ROM) { + memory_region_set_readonly(ram, true); + } return ram; } From patchwork Fri Feb 5 17:00:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 376948 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp2476357jah; Fri, 5 Feb 2021 09:50:02 -0800 (PST) X-Google-Smtp-Source: ABdhPJwIkWnIZtsGpiM10XpRF96HSpGwouh9YVXsgWr/yidQpDACosZAXFDXFz6Eozn/bN1fcu3t X-Received: by 2002:a25:9012:: with SMTP id s18mr7639675ybl.443.1612547402663; Fri, 05 Feb 2021 09:50:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612547402; cv=none; d=google.com; s=arc-20160816; b=0+IE4+pNrOR9kBrp8f/e4SVAq7R8R//4+fgwj0kearYdrijWJ3kCuHTFBWUf46pgJG uNwmEMkOmCj9yPhiw5bTWCYDV240n32X48UzSUHowSNWq7rpxNuPSCtBVfT3c1EKmWAS sn1+y9n5gcRyBoXONnnkxVpbYJhOPDsBlvq4dt3xeFrrk/ArpFoxuRdKewTvE2nRJ+cu 7bwfLrFw36hZNWp3M7zZ/6enjGO0MFXGtMY23Hi0IrTtNNHHQGLZphcuQgkSh6HVLN92 MFKdPZ9Y7on8B7fpHA4RkFfOM7/rWypcFvLxYWopwk/FdU65KAb5P4wVF9QNrZ9P/2Fm 59Zg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=jBPg420nC8pQh3qALQMd4OOROzhv7e66E6mvu1AgKfg=; b=j38DYMxx3D8M/0n/ua8H5Dctgjrrb3Z7MSsbeqt/8GOdlrSFXT0Ljmk75atSxmG8Wg zVugaJRxWXuP6mLe0VGdsoadFkB/bA1YcadADn0SIsMsdVIosKpwECchGRFi9BpR1Itp Z0g2NpHolvSb4GJW0/r8Wv6WRzlqJSYlq6LRt3MA84E3m5ax/whNSr0O8i+yEh/J/Y9j AgZUxcTY6orclj7CyfAJRwQG/56rOYj0dpSerriYF7Qrikx89yorFwtiKI+3mTv3WGAa kbJEscBtFNZCkVcz1X1QdIilyID9Xc8FPVjWGll3uyUHkgAxtQ1BrHO3ijRtAfYf7ewa ibsA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aMO9rVa9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:36 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 19/24] hw/arm/mps2-tz: Get armv7m_load_kernel() size argument from RAMInfo Date: Fri, 5 Feb 2021 17:00:14 +0000 Message-Id: <20210205170019.25319-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The armv7m_load_kernel() function takes a mem_size argument which it expects to be the size of the memory region at guest address 0. (It uses this argument only as a limit on how large a raw image file it can load at address zero). Instead of hardcoding this value, find the RAMInfo corresponding to the 0 address and extract its size. Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index ce5e804c734..17173057af2 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -525,6 +525,20 @@ static void create_non_mpc_ram(MPS2TZMachineState *mms) } } +static uint32_t boot_ram_size(MPS2TZMachineState *mms) +{ + /* Return the size of the RAM block at guest address zero */ + const RAMInfo *p; + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); + + for (p = mmc->raminfo; p->name; p++) { + if (p->base == 0) { + return p->size; + } + } + g_assert_not_reached(); +} + static void mps2tz_common_init(MachineState *machine) { MPS2TZMachineState *mms = MPS2TZ_MACHINE(machine); @@ -789,7 +803,8 @@ static void mps2tz_common_init(MachineState *machine) create_non_mpc_ram(mms); - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x400000); + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, + boot_ram_size(mms)); } static void mps2_tz_idau_check(IDAUInterface *ii, uint32_t address, From patchwork Fri Feb 5 17:00:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 376957 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp2482572jah; Fri, 5 Feb 2021 09:59:23 -0800 (PST) X-Google-Smtp-Source: ABdhPJy/FG/aSiI8eDPflW55o3sm6hNl8YxP5eGoSYHhRaaE3dkyGgORZ1NfaNUsG8nCXchb40Y0 X-Received: by 2002:a25:d6c2:: with SMTP id n185mr8192740ybg.71.1612547963358; Fri, 05 Feb 2021 09:59:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612547963; cv=none; d=google.com; s=arc-20160816; b=FU298KcjLLGqUGD00ZBh7/YetJOBlDza0A/VBSS5xO1mAIuigrEgGmossFm6/UttF9 EE23TZFPqr+NGtuUzk5FZaLbXl+qGNO9mAb6OrK9XsiUNoQV5Ob92BPYMog4bTu8uzuL g5MGPttaF6kYKvti7gwtZBBpPoHwfmJ+3mBGcLavV9hrlcJmlOVwe5eCdP/ige4rU0Ov u9su2zBH6/bCmII5WFS5uJTQ3iRhnBheX2+lXZGAayOb/653xvqlt1zeYSGCkKE/LMYg PM4I4ufyklc35Q+5wbEahLyLsibh3M0KlMQUlV1CInoLix+VCXVYhjyP5avO24xRnOVi HFFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DE4kV9oRwWVFbHVvXhpOiSYu9RVGMP8mh3PWmkMh9ek=; b=1HXhV2rimfQjOt0oNKVFCb0o77813oZCpAMYI4sxsclvW0P0g/LGPZXbNoPI7NsuNF 0aVjkpDBX7Q5Vh2I0An1NzwbWcRwwLWgXPpEoa5f/Qb9A2fuK2xnOne+9JzxaYjycfn2 /sAVCHSbKHbiF3WUX8t5Oeo/UW/je11VGhT3In38sH3BdzOtyhUmKXvKRNddjuhBBhhg xui4j1d601hvLJam7Kk/XYnCWjsjAK8+mPUznAYtheIalJOKFcQVBw38IET7sWNqnso3 M8AhJV5rscvIXZOfti7jhSxNNMxLqmsRGWEbj6Aop+mKpHUQYlJ6e2hsujPZe+DrEvjx aKVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JpPNUj0T; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:37 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 20/24] hw/arm/mps2-tz: Add new mps3-an524 board Date: Fri, 5 Feb 2021 17:00:15 +0000 Message-Id: <20210205170019.25319-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add support for the mps3-an524 board; this is an SSE-200 based FPGA image, like the existing mps2-an521. It has a usefully larger amount of RAM, and a PL031 RTC, as well as some more minor differences. In real hardware this image runs on a newer generation of the FPGA board, the MPS3 rather than the older MPS2. Architecturally the two boards are similar, so we implement the MPS3 boards in the mps2-tz.c file as variations of the existing MPS2 boards. Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 136 +++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 132 insertions(+), 4 deletions(-) -- 2.20.1 diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 17173057af2..aa57c4b2596 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -27,11 +27,13 @@ * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html * Application Note AN521: * http://infocenter.arm.com/help/topic/com.arm.doc.dai0521c/index.html + * Application Note AN524: + * https://developer.arm.com/documentation/dai0524/latest/ * * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide * (ARM ECM0601256) for the details of some of the device layout: * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html - * Similarly, the AN521 uses the SSE-200, and the SSE-200 TRM defines + * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM defines * most of the device layout: * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf * @@ -65,12 +67,13 @@ #include "hw/qdev-clock.h" #include "qom/object.h" -#define MPS2TZ_NUMIRQ_MAX 92 +#define MPS2TZ_NUMIRQ_MAX 95 #define MPS2TZ_RAM_MAX 4 typedef enum MPS2TZFPGAType { FPGA_AN505, FPGA_AN521, + FPGA_AN524, } MPS2TZFPGAType; /* @@ -121,13 +124,15 @@ struct MPS2TZMachineState { TZPPC ppc[5]; TZMPC mpc[3]; PL022State spi[5]; - ArmSbconI2CState i2c[4]; + ArmSbconI2CState i2c[5]; UnimplementedDeviceState i2s_audio; UnimplementedDeviceState gpio[4]; UnimplementedDeviceState gfx; + UnimplementedDeviceState cldc; + UnimplementedDeviceState rtc; PL080State dma[4]; TZMSC msc[4]; - CMSDKAPBUART uart[5]; + CMSDKAPBUART uart[6]; SplitIRQ sec_resp_splitter; qemu_or_irq uart_irq_orgate; DeviceState *lan9118; @@ -139,6 +144,7 @@ struct MPS2TZMachineState { #define TYPE_MPS2TZ_MACHINE "mps2tz" #define TYPE_MPS2TZ_AN505_MACHINE MACHINE_TYPE_NAME("mps2-an505") #define TYPE_MPS2TZ_AN521_MACHINE MACHINE_TYPE_NAME("mps2-an521") +#define TYPE_MPS3TZ_AN524_MACHINE MACHINE_TYPE_NAME("mps3-an524") OBJECT_DECLARE_TYPE(MPS2TZMachineState, MPS2TZMachineClass, MPS2TZ_MACHINE) @@ -151,6 +157,15 @@ static const uint32_t an505_oscclk[] = { 25000000, }; +static const uint32_t an524_oscclk[] = { + 24000000, + 32000000, + 50000000, + 50000000, + 24576000, + 23750000, +}; + static const RAMInfo an505_raminfo[] = { { .name = "ssram-0", .base = 0x00000000, @@ -188,6 +203,37 @@ static const RAMInfo an505_raminfo[] = { { }, }; +static const RAMInfo an524_raminfo[] = { { + .name = "bram", + .base = 0x00000000, + .size = 512 * KiB, + .mpc = 0, + .mrindex = 0, + }, { + .name = "sram", + .base = 0x20000000, + .size = 32 * 4 * KiB, + .mpc = 1, + .mrindex = 1, + }, { + /* We don't model QSPI flash yet; for now expose it as simple ROM */ + .name = "QSPI", + .base = 0x28000000, + .size = 8 * MiB, + .mpc = 1, + .mrindex = 2, + .flags = IS_ROM, + }, { + .name = "DDR", + .base = 0x60000000, + .size = 2 * GiB, + .mpc = 2, + .mrindex = -1, + }, { + .name = NULL, + }, +}; + static const RAMInfo *find_raminfo_for_mpc(MPS2TZMachineState *mms, int mpc) { MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_GET_CLASS(mms); @@ -717,12 +763,66 @@ static void mps2tz_common_init(MachineState *machine) }, }; + const PPCInfo an524_ppcs[] = { { + .name = "apb_ppcexp0", + .ports = { + { "bram-mpc", make_mpc, &mms->mpc[0], 0x58007000, 0x1000 }, + { "qspi-mpc", make_mpc, &mms->mpc[1], 0x58008000, 0x1000 }, + { "ddr-mpc", make_mpc, &mms->mpc[2], 0x58009000, 0x1000 }, + }, + }, { + .name = "apb_ppcexp1", + .ports = { + { "i2c0", make_i2c, &mms->i2c[0], 0x41200000, 0x1000 }, + { "i2c1", make_i2c, &mms->i2c[1], 0x41201000, 0x1000 }, + { "spi0", make_spi, &mms->spi[0], 0x41202000, 0x1000, { 52 } }, + { "spi1", make_spi, &mms->spi[1], 0x41203000, 0x1000, { 53 } }, + { "spi2", make_spi, &mms->spi[2], 0x41204000, 0x1000, { 54 } }, + { "i2c2", make_i2c, &mms->i2c[2], 0x41205000, 0x1000 }, + { "i2c3", make_i2c, &mms->i2c[3], 0x41206000, 0x1000 }, + { /* port 7 reserved */ }, + { "i2c4", make_i2c, &mms->i2c[4], 0x41208000, 0x1000 }, + }, + }, { + .name = "apb_ppcexp2", + .ports = { + { "scc", make_scc, &mms->scc, 0x41300000, 0x1000 }, + { "i2s-audio", make_unimp_dev, &mms->i2s_audio, + 0x41301000, 0x1000 }, + { "fpgaio", make_fpgaio, &mms->fpgaio, 0x41302000, 0x1000 }, + { "uart0", make_uart, &mms->uart[0], 0x41303000, 0x1000, { 32, 33, 42 } }, + { "uart1", make_uart, &mms->uart[1], 0x41304000, 0x1000, { 34, 35, 43 } }, + { "uart2", make_uart, &mms->uart[2], 0x41305000, 0x1000, { 36, 37, 44 } }, + { "uart3", make_uart, &mms->uart[3], 0x41306000, 0x1000, { 38, 39, 45 } }, + { "uart4", make_uart, &mms->uart[4], 0x41307000, 0x1000, { 40, 41, 46 } }, + { "uart5", make_uart, &mms->uart[5], 0x41308000, 0x1000, { 124, 125, 126 } }, + + { /* port 9 reserved */ }, + { "clcd", make_unimp_dev, &mms->cldc, 0x4130a000, 0x1000 }, + { "rtc", make_unimp_dev, &mms->rtc, 0x4130b000, 0x1000 }, + }, + }, { + .name = "ahb_ppcexp0", + .ports = { + { "gpio0", make_unimp_dev, &mms->gpio[0], 0x41100000, 0x1000 }, + { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 }, + { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 }, + { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 }, + { "eth", make_eth_dev, NULL, 0x41400000, 0x100000, { 48 } }, + }, + }, + }; + switch (mmc->fpga_type) { case FPGA_AN505: case FPGA_AN521: ppcs = an505_ppcs; num_ppcs = ARRAY_SIZE(an505_ppcs); break; + case FPGA_AN524: + ppcs = an524_ppcs; + num_ppcs = ARRAY_SIZE(an524_ppcs); + break; default: g_assert_not_reached(); } @@ -900,6 +1000,27 @@ static void mps2tz_an521_class_init(ObjectClass *oc, void *data) mps2tz_set_default_ram_info(mmc); } +static void mps3tz_an524_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + MPS2TZMachineClass *mmc = MPS2TZ_MACHINE_CLASS(oc); + + mc->desc = "ARM MPS3 with AN524 FPGA image for dual Cortex-M33"; + mc->default_cpus = 2; + mc->min_cpus = mc->default_cpus; + mc->max_cpus = mc->default_cpus; + mmc->fpga_type = FPGA_AN524; + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); + mmc->scc_id = 0x41045240; + mmc->sysclk_frq = 32 * 1000 * 1000; /* 32MHz */ + mmc->oscclk = an524_oscclk; + mmc->len_oscclk = ARRAY_SIZE(an524_oscclk); + mmc->numirq = 95; + mmc->raminfo = an524_raminfo; + mmc->armsse_type = TYPE_SSE200; + mps2tz_set_default_ram_info(mmc); +} + static const TypeInfo mps2tz_info = { .name = TYPE_MPS2TZ_MACHINE, .parent = TYPE_MACHINE, @@ -925,11 +1046,18 @@ static const TypeInfo mps2tz_an521_info = { .class_init = mps2tz_an521_class_init, }; +static const TypeInfo mps3tz_an524_info = { + .name = TYPE_MPS3TZ_AN524_MACHINE, + .parent = TYPE_MPS2TZ_MACHINE, + .class_init = mps3tz_an524_class_init, +}; + static void mps2tz_machine_init(void) { type_register_static(&mps2tz_info); type_register_static(&mps2tz_an505_info); type_register_static(&mps2tz_an521_info); + type_register_static(&mps3tz_an524_info); } type_init(mps2tz_machine_init); From patchwork Fri Feb 5 17:00:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 376952 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp2479830jah; Fri, 5 Feb 2021 09:55:22 -0800 (PST) X-Google-Smtp-Source: ABdhPJwzUcfTVMlb3Ns0hOvFft4UflvppbGvA1YSMfrw2kb3/3vJbeGiBZPcGDTbFjAwa91m2V1e X-Received: by 2002:a25:db4b:: with SMTP id g72mr7731851ybf.90.1612547722615; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:38 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 21/24] hw/arm/mps2-tz: Stub out USB controller for mps3-an524 Date: Fri, 5 Feb 2021 17:00:16 +0000 Message-Id: <20210205170019.25319-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The AN524 has a USB controller (an ISP1763); we don't have a model of it but we should provide a stub "unimplemented-device" for it. This is slightly complicated because the USB controller shares a PPC port with the ethernet controller. Implement a make_* function which provides creates a container MemoryRegion with both the ethernet controller and an unimplemented-device stub for the USB controller. Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index aa57c4b2596..db1afa4bd22 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -119,6 +119,8 @@ struct MPS2TZMachineState { ARMSSE iotkit; MemoryRegion ram[MPS2TZ_RAM_MAX]; + MemoryRegion eth_usb_container; + MPS2SCC scc; MPS2FPGAIO fpgaio; TZPPC ppc[5]; @@ -130,6 +132,7 @@ struct MPS2TZMachineState { UnimplementedDeviceState gfx; UnimplementedDeviceState cldc; UnimplementedDeviceState rtc; + UnimplementedDeviceState usb; PL080State dma[4]; TZMSC msc[4]; CMSDKAPBUART uart[6]; @@ -431,6 +434,49 @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, return sysbus_mmio_get_region(s, 0); } +static MemoryRegion *make_eth_usb(MPS2TZMachineState *mms, void *opaque, + const char *name, hwaddr size, + const int *irqs) +{ + /* + * The AN524 makes the ethernet and USB share a PPC port. + * irqs[] is the ethernet IRQ. + */ + SysBusDevice *s; + NICInfo *nd = &nd_table[0]; + + memory_region_init(&mms->eth_usb_container, OBJECT(mms), + "mps2-tz-eth-usb-container", 0x200000); + + /* + * In hardware this is a LAN9220; the LAN9118 is software compatible + * except that it doesn't support the checksum-offload feature. + */ + qemu_check_nic_model(nd, "lan9118"); + mms->lan9118 = qdev_new(TYPE_LAN9118); + qdev_set_nic_properties(mms->lan9118, nd); + + s = SYS_BUS_DEVICE(mms->lan9118); + sysbus_realize_and_unref(s, &error_fatal); + sysbus_connect_irq(s, 0, get_sse_irq_in(mms, irqs[0])); + + memory_region_add_subregion(&mms->eth_usb_container, + 0, sysbus_mmio_get_region(s, 0)); + + /* The USB OTG controller is an ISP1763; we don't have a model of it. */ + object_initialize_child(OBJECT(mms), "usb-otg", + &mms->usb, TYPE_UNIMPLEMENTED_DEVICE); + qdev_prop_set_string(DEVICE(&mms->usb), "name", "usb-otg"); + qdev_prop_set_uint64(DEVICE(&mms->usb), "size", 0x100000); + s = SYS_BUS_DEVICE(&mms->usb); + sysbus_realize(s, &error_fatal); + + memory_region_add_subregion(&mms->eth_usb_container, + 0x100000, sysbus_mmio_get_region(s, 0)); + + return &mms->eth_usb_container; +} + static MemoryRegion *make_mpc(MPS2TZMachineState *mms, void *opaque, const char *name, hwaddr size, const int *irqs) @@ -808,7 +854,7 @@ static void mps2tz_common_init(MachineState *machine) { "gpio1", make_unimp_dev, &mms->gpio[1], 0x41101000, 0x1000 }, { "gpio2", make_unimp_dev, &mms->gpio[2], 0x41102000, 0x1000 }, { "gpio3", make_unimp_dev, &mms->gpio[3], 0x41103000, 0x1000 }, - { "eth", make_eth_dev, NULL, 0x41400000, 0x100000, { 48 } }, + { "eth-usb", make_eth_usb, NULL, 0x41400000, 0x200000, { 48 } }, }, }, }; From patchwork Fri Feb 5 17:00:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 376964 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp2497143jah; Fri, 5 Feb 2021 10:17:28 -0800 (PST) X-Google-Smtp-Source: ABdhPJwo3Ot/hk2ZQn6kq7H2kMbhVz2NpzNIozHkvufBIJuKXVf8DWM/mk9ZeUtfg+vhuXXdcGrp X-Received: by 2002:a5b:98a:: with SMTP id c10mr8258882ybq.406.1612549047965; Fri, 05 Feb 2021 10:17:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612549047; cv=none; d=google.com; s=arc-20160816; b=DhGE54kMPW9ms8Bs6yQ3GEeei1IEUa2Nev7NYVcLOsdJ8Nn42DkZ2gWSd8m/9kPpdS MrhBNME/mZam2doc8iFUYRXhRVrquOVf7RlEUuRfi4jB/w1HXAlaFz3PK6enja2JKVb/ AsYaQOBaYxwOUWP2neKiGmIjaHCE1eohoWKhzzcC/CoSKa8D41c4pR9eWZO9Cdwcxlp3 8j++pTcgxGEAfmVq3wKf45ROui6w7rrsQZVAqBAzQh8963+cyYMnKysZuhViZ/w/Dr/Q ETLpmF0JH8+zZ4vVwoXhqipveBpJq0vmELCOjeMHvCnIDbA8seCAoOVzft0KJrJDZWBQ lxRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=fbSQXUXJEDGMaGC9KOnv4xEcH7gCV3geuE6p5sgHfh8=; b=J57Z7Q2B1rfSJOJcisKKdyDOSEehAW2niCFE2ez7p71xhVRKlxc4WVOCqEXUinqdz2 EPvusZCWetwHNHw4Ih0/GyoS4ZUHwkVJT0ShJ3RFthClykRTdWXvEXPuCYrnavJt05An 6aBCjTKsDydk+1rkFD/ylPd2vOCCyu5IeYp6Q+5mcQPH6nETY7h3R0IKvrjf2AaammP4 hm5fIMswOrm8alOSSufGR2cq2vt9eWo4r2nJNwF81+Wfi9YFqFW9R+c8lkeSmktaW4qa tjJLyIogZQ5QVEnTlpTbpYRPhnZxc1XMZ1gfRuCEkQZHFYTBlYYvuLg8EuA6bpkG1JGQ K4PQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Hte+Patv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:39 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 22/24] hw/arm/mps2-tz: Provide PL031 RTC on mps3-an524 Date: Fri, 5 Feb 2021 17:00:17 +0000 Message-Id: <20210205170019.25319-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The AN524 has a PL031 RTC, which we have a model of; provide it rather than an unimplemented-device stub. Signed-off-by: Peter Maydell --- hw/arm/mps2-tz.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index db1afa4bd22..27feb36616e 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -59,6 +59,7 @@ #include "hw/misc/tz-msc.h" #include "hw/arm/armsse.h" #include "hw/dma/pl080.h" +#include "hw/rtc/pl031.h" #include "hw/ssi/pl022.h" #include "hw/i2c/arm_sbcon_i2c.h" #include "hw/net/lan9118.h" @@ -131,8 +132,8 @@ struct MPS2TZMachineState { UnimplementedDeviceState gpio[4]; UnimplementedDeviceState gfx; UnimplementedDeviceState cldc; - UnimplementedDeviceState rtc; UnimplementedDeviceState usb; + PL031State rtc; PL080State dma[4]; TZMSC msc[4]; CMSDKAPBUART uart[6]; @@ -595,6 +596,23 @@ static MemoryRegion *make_i2c(MPS2TZMachineState *mms, void *opaque, return sysbus_mmio_get_region(s, 0); } +static MemoryRegion *make_rtc(MPS2TZMachineState *mms, void *opaque, + const char *name, hwaddr size, + const int *irqs) +{ + PL031State *pl031 = opaque; + SysBusDevice *s; + + object_initialize_child(OBJECT(mms), name, pl031, TYPE_PL031); + s = SYS_BUS_DEVICE(pl031); + sysbus_realize(s, &error_fatal); + /* + * The board docs don't give an IRQ number for the PL031, so + * presumably it is not connected. + */ + return sysbus_mmio_get_region(s, 0); +} + static void create_non_mpc_ram(MPS2TZMachineState *mms) { /* @@ -845,7 +863,7 @@ static void mps2tz_common_init(MachineState *machine) { /* port 9 reserved */ }, { "clcd", make_unimp_dev, &mms->cldc, 0x4130a000, 0x1000 }, - { "rtc", make_unimp_dev, &mms->rtc, 0x4130b000, 0x1000 }, + { "rtc", make_rtc, &mms->rtc, 0x4130b000, 0x1000 }, }, }, { .name = "ahb_ppcexp0", From patchwork Fri Feb 5 17:00:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 376965 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp2499993jah; Fri, 5 Feb 2021 10:21:01 -0800 (PST) X-Google-Smtp-Source: ABdhPJw301U5oFVxdF6Yl7kI+xWMUffFwKOiuleKP9EE6L5LrCb7vhMmmbFYDFEYg58aeBXVTVJ3 X-Received: by 2002:a25:a288:: with SMTP id c8mr8040792ybi.516.1612549261204; Fri, 05 Feb 2021 10:21:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612549261; cv=none; d=google.com; s=arc-20160816; b=b4TzTtVqmKm2G8m248KSNoR1sX0hprBMrdZWxPGskNKIGMBaDHGI9Gh84tSrMefP9H 2yQdXaA+49xXqW47nEZx8ptmKJnWdlBxaf87UlH10H8oQjLrUamo9oC+7e/EkdAO5D47 mEpN8S7+XJgwYrG84RNMOJR/ph/VfkRpnDDI8N7732o0698S1HWKYJKKizKOh1zvg01k 91HOiWvfBmHSMuan/u87NvnYoH0cALtb5/JxajdgQe6TvPUbggyq3kutnCjjz9SFiRUK FfZoQKdg8d1TZeTSsTXq3IhKu3WeYSGIIRmN9M4icZb6HFfqGIGAmIFFSOC9X30EosiH iBmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=saCU3fNa93sGe02vfYgHjxSHpcdvDyRLS+pyj+1uZRs=; b=IccR/SwIQT92oALrqv1vDGHIG6BOC+kdRf/dy578o/hqmwSgyv3XAqUd764jfVzgrP /YMTl1ubhx1Qos+TD5jJYTAz3/AnjctcmPP5sS2YGxmpARPMHewrD4PzblEydZQAK1fa 8C8CwEUFSEnIA8V0MrHCFeGmReRYQAgX2uZ9EhoBlwAt/9CGNOIr8xVrxMbqVBzlDjxC yZ80E6AjhkPQ2BgAZ5/uXWf/A5R8n0/70oPDjbruTPR81/jkoWiX03mTBvixS2SiXhoL qRkp3h9DNJrkGK2dlWeGxUoCz0eK/JQk1WerZ2bnPn6Q1HD68pGhHh0pQ9KIVwE3nwyd 35UQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Vqi0kulH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:39 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 23/24] docs/system/arm/mps2.rst: Document the new mps3-an524 board Date: Fri, 5 Feb 2021 17:00:18 +0000 Message-Id: <20210205170019.25319-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add brief documentation of the new mps3-an524 board. Signed-off-by: Peter Maydell --- docs/system/arm/mps2.rst | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst index 8c5b5f1fe07..601ccea15cb 100644 --- a/docs/system/arm/mps2.rst +++ b/docs/system/arm/mps2.rst @@ -1,12 +1,15 @@ -Arm MPS2 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``) -================================================================================================================ +Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``) +========================================================================================================================================= These board models all use Arm M-profile CPUs. -The Arm MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger -FPGA but is otherwise the same as the 2). Since the CPU itself -and most of the devices are in the FPGA, the details of the board -as seen by the guest depend significantly on the FPGA image. +The Arm MPS2, MPS2+ and MPS3 dev boards are FPGA based (the 2+ has a +bigger FPGA but is otherwise the same as the 2; the 3 has a bigger +FPGA again, can handle 4GB of RAM and has a USB controller and QSPI flash). + +Since the CPU itself and most of the devices are in the FPGA, the +details of the board as seen by the guest depend significantly on the +FPGA image. QEMU models the following FPGA images: @@ -22,12 +25,21 @@ QEMU models the following FPGA images: Cortex-M3 'DesignStart' as documented in Arm Application Note AN511 ``mps2-an521`` Dual Cortex-M33 as documented in Arm Application Note AN521 +``mps3-an524`` + Dual Cortex-M33 on an MPS3, as documented in Arm Application Note AN524 Differences between QEMU and real hardware: - AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to block RAM is unimplemented (QEMU always maps this to ZBT SSRAM1, as if zbt_boot_ctrl is always zero) +- AN524 remapping of low memory to either BRAM or to QSPI flash is + unimplemented (QEMU always maps this to BRAM, ignoring the + SCC CFG_REG0 memory-remap bit) - QEMU provides a LAN9118 ethernet rather than LAN9220; the only guest visible difference is that the LAN9118 doesn't support checksum offloading +- QEMU does not model the QSPI flash in MPS3 boards as real QSPI + flash, but only as simple ROM, so attempting to rewrite the flash + from the guest will fail +- QEMU does not model the USB controller in MPS3 boards From patchwork Fri Feb 5 17:00:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 376947 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp2471612jah; Fri, 5 Feb 2021 09:44:05 -0800 (PST) X-Google-Smtp-Source: ABdhPJx4GzHxzZfaZANstP07ctTrgdWRE/tMwDq3EtFAbGhW85Ci16EPhsV/Xnoa2prgcgWAmvlf X-Received: by 2002:a25:390:: with SMTP id 138mr8249811ybd.148.1612547045265; Fri, 05 Feb 2021 09:44:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612547045; cv=none; d=google.com; s=arc-20160816; b=k5iwqcaiggK4JGeFFGJY56DcmFcRgev5YcoTsq0a4SapyZzHc5Kmi9fZzRWjDXP2lZ uCShJqMhEapiJJKSWyA/sM6U+ZfimWLUYSlZsY20yd1IwygxPWehm7BAOhpozgtQxavJ sBW63KeJwUpbjcnX+Ou6W6LE4wl5KEp9DloaU6HwWzfPMJLkIf1LS3b8UYyZgofl/IV2 MaIx4bF9derT8oCTSOvHMWn6G2CoeZeTtRFS6LFI6dPxMxnsxIFiLq6NlS08biVNcRCu vpbHqTWjFGFVT8pcEI9iRGWnHFRpQ3/Mwf8baok+fDR42kw8t0yoBRNN8DmkwF5FZCU/ wa7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Lp/PXJ/Lg+jhfej9/mPuXMN8i+zU7pqYIRVDjsjSQS8=; b=pb8ZQXdrxnAX2CLat4DV9pGItcXf1ftl5THoEh0Kla+/ybohMggWc3Hbt0/drYJbJJ okVgf9+/AH37ICZ/zq2tujUd7WBV0w76ljPfH7QJWvb0nyuoYpNKUeW5py7LwM9pSG0E nSk8Hf0Z/6ufAdt8V3rzpYCb6Io5Nzs8rWTQls/qRRDwApOorFk8Q2tTCAIu8MmgGhJm e7aBj/+oAOSH4QfXdU0vkELPmEeo+Z/QFrQH8YgX6TreuY/MZJ9kL2tqwvaZdg/lIc+E JIZvHCJTPEJhz13n/TSmTq/X7fLvTDBVo17bSiFViFH9cs+vTs3Oz6GeD2k2YG7NTCBL kWAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yW1fULBK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l11sm12200010wrt.23.2021.02.05.09.00.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 Feb 2021 09:00:40 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 24/24] hw/arm/mps2: Update old infocenter.arm.com URLs Date: Fri, 5 Feb 2021 17:00:19 +0000 Message-Id: <20210205170019.25319-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210205170019.25319-1-peter.maydell@linaro.org> References: <20210205170019.25319-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Update old infocenter.arm.com URLs to the equivalent developer.arm.com ones (the old URLs should redirect, but we might as well avoid the redirection notice, and the new URLs are pleasantly shorter). This commit covers the links to the MPS2 board TRM, the various Application Notes, the IoTKit and SSE-200 documents. Signed-off-by: Peter Maydell --- There are some other infocenter URLs in the codebase; we should probably update those too, but they don't really fit in with this patchset, so I'll do them separately later. --- include/hw/arm/armsse.h | 4 ++-- include/hw/misc/armsse-cpuid.h | 2 +- include/hw/misc/armsse-mhu.h | 2 +- include/hw/misc/iotkit-secctl.h | 2 +- include/hw/misc/iotkit-sysctl.h | 2 +- include/hw/misc/iotkit-sysinfo.h | 2 +- include/hw/misc/mps2-fpgaio.h | 2 +- hw/arm/mps2-tz.c | 11 +++++------ hw/misc/armsse-cpuid.c | 2 +- hw/misc/armsse-mhu.c | 2 +- hw/misc/iotkit-sysctl.c | 2 +- hw/misc/iotkit-sysinfo.c | 2 +- hw/misc/mps2-fpgaio.c | 2 +- hw/misc/mps2-scc.c | 2 +- 14 files changed, 19 insertions(+), 20 deletions(-) -- 2.20.1 Reviewed-by: Philippe Mathieu-Daudé diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h index 676cd4f36b0..09284ca75cf 100644 --- a/include/hw/arm/armsse.h +++ b/include/hw/arm/armsse.h @@ -14,9 +14,9 @@ * hardware, which include the IoT Kit and the SSE-050, SSE-100 and * SSE-200. Currently we model: * - the Arm IoT Kit which is documented in - * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html + * https://developer.arm.com/documentation/ecm0601256/latest * - the SSE-200 which is documented in - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf + * https://developer.arm.com/documentation/101104/latest/ * * The IoTKit contains: * a Cortex-M33 diff --git a/include/hw/misc/armsse-cpuid.h b/include/hw/misc/armsse-cpuid.h index a61355e5161..9c0926322cb 100644 --- a/include/hw/misc/armsse-cpuid.h +++ b/include/hw/misc/armsse-cpuid.h @@ -12,7 +12,7 @@ /* * This is a model of the "CPU_IDENTITY" register block which is part of the * Arm SSE-200 and documented in - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf + * https://developer.arm.com/documentation/101104/latest/ * * QEMU interface: * + QOM property "CPUID": the value to use for the CPUID register diff --git a/include/hw/misc/armsse-mhu.h b/include/hw/misc/armsse-mhu.h index 2671b5b978b..41925ded89b 100644 --- a/include/hw/misc/armsse-mhu.h +++ b/include/hw/misc/armsse-mhu.h @@ -12,7 +12,7 @@ /* * This is a model of the Message Handling Unit (MHU) which is part of the * Arm SSE-200 and documented in - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf + * https://developer.arm.com/documentation/101104/latest/ * * QEMU interface: * + sysbus MMIO region 0: the system information register bank diff --git a/include/hw/misc/iotkit-secctl.h b/include/hw/misc/iotkit-secctl.h index 54c212b515c..227d44abe49 100644 --- a/include/hw/misc/iotkit-secctl.h +++ b/include/hw/misc/iotkit-secctl.h @@ -11,7 +11,7 @@ /* This is a model of the security controller which is part of the * Arm IoT Kit and documented in - * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html + * https://developer.arm.com/documentation/ecm0601256/latest * * QEMU interface: * + sysbus MMIO region 0 is the "secure privilege control block" registers diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h index 2b5636b218c..2bc391138db 100644 --- a/include/hw/misc/iotkit-sysctl.h +++ b/include/hw/misc/iotkit-sysctl.h @@ -12,7 +12,7 @@ /* * This is a model of the "system control element" which is part of the * Arm IoTKit and documented in - * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html + * https://developer.arm.com/documentation/ecm0601256/latest * Specifically, it implements the "system information block" and * "system control register" blocks. * diff --git a/include/hw/misc/iotkit-sysinfo.h b/include/hw/misc/iotkit-sysinfo.h index 7e620e2eafe..055771d2098 100644 --- a/include/hw/misc/iotkit-sysinfo.h +++ b/include/hw/misc/iotkit-sysinfo.h @@ -12,7 +12,7 @@ /* * This is a model of the "system information block" which is part of the * Arm IoTKit and documented in - * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html + * https://developer.arm.com/documentation/ecm0601256/latest * QEMU interface: * + QOM property "SYS_VERSION": value to use for SYS_VERSION register * + QOM property "SYS_CONFIG": value to use for SYS_CONFIG register diff --git a/include/hw/misc/mps2-fpgaio.h b/include/hw/misc/mps2-fpgaio.h index 83c6e18a4ee..7f622bae536 100644 --- a/include/hw/misc/mps2-fpgaio.h +++ b/include/hw/misc/mps2-fpgaio.h @@ -12,7 +12,7 @@ /* This is a model of the FPGAIO register block in the AN505 * FPGA image for the MPS2 dev board; it is documented in the * application note: - * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html + * https://developer.arm.com/documentation/dai0505/latest/ * * QEMU interface: * + sysbus MMIO region 0: the register bank diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 27feb36616e..944f44f4a31 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -22,21 +22,20 @@ * https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2 * * Board TRM: - * http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf + * https://developer.arm.com/documentation/100112/latest/ * Application Note AN505: - * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html + * https://developer.arm.com/documentation/dai0505/latest/ * Application Note AN521: - * http://infocenter.arm.com/help/topic/com.arm.doc.dai0521c/index.html + * https://developer.arm.com/documentation/dai0521/latest/ * Application Note AN524: * https://developer.arm.com/documentation/dai0524/latest/ * * The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide * (ARM ECM0601256) for the details of some of the device layout: - * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html + * https://developer.arm.com/documentation/ecm0601256/latest * Similarly, the AN521 and AN524 use the SSE-200, and the SSE-200 TRM defines * most of the device layout: - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf - * + * https://developer.arm.com/documentation/101104/latest/ */ #include "qemu/osdep.h" diff --git a/hw/misc/armsse-cpuid.c b/hw/misc/armsse-cpuid.c index d58138dc28c..e785a090519 100644 --- a/hw/misc/armsse-cpuid.c +++ b/hw/misc/armsse-cpuid.c @@ -12,7 +12,7 @@ /* * This is a model of the "CPU_IDENTITY" register block which is part of the * Arm SSE-200 and documented in - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf + * https://developer.arm.com/documentation/101104/latest/ * * It consists of one read-only CPUID register (set by QOM property), plus the * usual ID registers. diff --git a/hw/misc/armsse-mhu.c b/hw/misc/armsse-mhu.c index a45d97fada8..0be7f0fc874 100644 --- a/hw/misc/armsse-mhu.c +++ b/hw/misc/armsse-mhu.c @@ -12,7 +12,7 @@ /* * This is a model of the Message Handling Unit (MHU) which is part of the * Arm SSE-200 and documented in - * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf + * https://developer.arm.com/documentation/101104/latest/ */ #include "qemu/osdep.h" diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c index 964b48c74d9..222511c4b04 100644 --- a/hw/misc/iotkit-sysctl.c +++ b/hw/misc/iotkit-sysctl.c @@ -12,7 +12,7 @@ /* * This is a model of the "system control element" which is part of the * Arm IoTKit and documented in - * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html + * https://developer.arm.com/documentation/ecm0601256/latest * Specifically, it implements the "system control register" blocks. */ diff --git a/hw/misc/iotkit-sysinfo.c b/hw/misc/iotkit-sysinfo.c index b2dcfc4376c..52e70053df7 100644 --- a/hw/misc/iotkit-sysinfo.c +++ b/hw/misc/iotkit-sysinfo.c @@ -12,7 +12,7 @@ /* * This is a model of the "system information block" which is part of the * Arm IoTKit and documented in - * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html + * https://developer.arm.com/documentation/ecm0601256/latest * It consists of 2 read-only version/config registers, plus the * usual ID registers. */ diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c index b54657a4f07..64a383e063b 100644 --- a/hw/misc/mps2-fpgaio.c +++ b/hw/misc/mps2-fpgaio.c @@ -12,7 +12,7 @@ /* This is a model of the "FPGA system control and I/O" block found * in the AN505 FPGA image for the MPS2 devboard. * It is documented in AN505: - * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html + * https://developer.arm.com/documentation/dai0505/latest/ */ #include "qemu/osdep.h" diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c index 562ace06a58..140a4b9ceba 100644 --- a/hw/misc/mps2-scc.c +++ b/hw/misc/mps2-scc.c @@ -13,7 +13,7 @@ * found in the FPGA images of MPS2 development boards. * * Documentation of it can be found in the MPS2 TRM: - * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100112_0100_03_en/index.html + * https://developer.arm.com/documentation/100112/latest/ * and also in the Application Notes documenting individual FPGA images. */