From patchwork Tue Apr 4 06:17:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Pundir X-Patchwork-Id: 96672 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp48098qgd; Mon, 3 Apr 2017 23:17:39 -0700 (PDT) X-Received: by 10.84.230.131 with SMTP id e3mr27229053plk.100.1491286659696; Mon, 03 Apr 2017 23:17:39 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a9si746909pgf.57.2017.04.03.23.17.39; Mon, 03 Apr 2017 23:17:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752461AbdDDGRj (ORCPT + 6 others); Tue, 4 Apr 2017 02:17:39 -0400 Received: from mail-pg0-f51.google.com ([74.125.83.51]:34532 "EHLO mail-pg0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751082AbdDDGRi (ORCPT ); Tue, 4 Apr 2017 02:17:38 -0400 Received: by mail-pg0-f51.google.com with SMTP id 21so142749590pgg.1 for ; Mon, 03 Apr 2017 23:17:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=vNWIVuOVGtJ5eowm9iarUdPiM95ki0Bbc3wJlQ3Bh1s=; b=O41uKx4ykzqk1juMpe/p6Dry4AHeRbkToRwh6fGTRo0OKucx5p4v5nxg6ilalaQ5Pm jS6fZvWgT0gkkZpHJpow9ZT6L+CcH57S7qBMKQnKfFk2yCuBtQ2ZzwXgjwEe1bmKzqVD 2+OYM/ORq8uooE2k1gnfOsSOvgLp/+YDtEZwc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=vNWIVuOVGtJ5eowm9iarUdPiM95ki0Bbc3wJlQ3Bh1s=; b=c2i2gg778oVvjVt7NW2mwbkKxWBjZRnrSRK9pcSnCYKDPM5nqGY6sKIdXrBSx7+Cot k4GdzqCzA2ztHnQSMG34IINt6xCU59q7uQjJriSl4qed9pMbox98sB42iwpVQVI7D0RA uhtkPgFcA9NrtoYv2EmzKVtFnpnNO67jNSWN/h4dha2xRlG4pcyToYt2fTXdTVhHHdRG 6PjZGHyW3t8iefjcJHHC3Sj8LnxG6b72iYA3jSF2B+soMq+eR7E6F/2h6mArDiD2c+B8 SYVh0DbKxbvm2JiifVeXlJ71VYLbgj86dBTQIDuwjx6uBtVXLutNBaixSJu4ltK8X8uD n9sA== X-Gm-Message-State: AFeK/H2T5YdDUpkVMEUORyD4V22rBq4FU2hk8MUILkzm2FV2NrT14574g/Ux6yhkuC/LDNJN X-Received: by 10.99.170.70 with SMTP id x6mr22239320pgo.111.1491286657639; Mon, 03 Apr 2017 23:17:37 -0700 (PDT) Received: from localhost.localdomain ([106.51.240.246]) by smtp.gmail.com with ESMTPSA id l126sm29224804pfl.56.2017.04.03.23.17.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 03 Apr 2017 23:17:37 -0700 (PDT) From: Amit Pundir To: gregkh@linuxfoundation.org Cc: stable@vger.kernel.org, Boris Brezillon , Stephen Boyd Subject: [PATCH 10/33] clk: bcm: Support rate change propagation on bcm2835 clocks Date: Tue, 4 Apr 2017 11:47:24 +0530 Message-Id: <1491286653-31193-1-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Boris Brezillon Some peripheral clocks, like the VEC (Video EnCoder) clock need to be set to a precise rate (in our case 108MHz). With the current implementation, where peripheral clocks are not allowed to forward rate change requests to their parents, it is impossible to match this requirement unless the bootloader has configured things correctly, or a specific rate has been assigned through the DT (with the assigned-clk-rates property). Add a new field to struct bcm2835_clock_data to specify which parent clocks accept rate change propagation, and support set rate propagation in bcm2835_clock_determine_rate(). Signed-off-by: Boris Brezillon Reviewed-by: Eric Anholt Signed-off-by: Stephen Boyd (cherry picked from commit 155e8b3b0ee320ae866b97dd31eba8a1f080a772) Signed-off-by: Amit Pundir --- drivers/clk/bcm/clk-bcm2835.c | 67 ++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 63 insertions(+), 4 deletions(-) -- 2.7.4 diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index 2acaa77..df96fe6 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -436,6 +436,9 @@ struct bcm2835_clock_data { const char *const *parents; int num_mux_parents; + /* Bitmap encoding which parents accept rate change propagation. */ + unsigned int set_rate_parent; + u32 ctl_reg; u32 div_reg; @@ -1017,10 +1020,60 @@ bcm2835_clk_is_pllc(struct clk_hw *hw) return strncmp(clk_hw_get_name(hw), "pllc", 4) == 0; } +static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw, + int parent_idx, + unsigned long rate, + u32 *div, + unsigned long *prate) +{ + struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); + struct bcm2835_cprman *cprman = clock->cprman; + const struct bcm2835_clock_data *data = clock->data; + unsigned long best_rate; + u32 curdiv, mindiv, maxdiv; + struct clk_hw *parent; + + parent = clk_hw_get_parent_by_index(hw, parent_idx); + + if (!(BIT(parent_idx) & data->set_rate_parent)) { + *prate = clk_hw_get_rate(parent); + *div = bcm2835_clock_choose_div(hw, rate, *prate, true); + + return bcm2835_clock_rate_from_divisor(clock, *prate, + *div); + } + + if (data->frac_bits) + dev_warn(cprman->dev, + "frac bits are not used when propagating rate change"); + + /* clamp to min divider of 2 if we're dealing with a mash clock */ + mindiv = data->is_mash_clock ? 2 : 1; + maxdiv = BIT(data->int_bits) - 1; + + /* TODO: Be smart, and only test a subset of the available divisors. */ + for (curdiv = mindiv; curdiv <= maxdiv; curdiv++) { + unsigned long tmp_rate; + + tmp_rate = clk_hw_round_rate(parent, rate * curdiv); + tmp_rate /= curdiv; + if (curdiv == mindiv || + (tmp_rate > best_rate && tmp_rate <= rate)) + best_rate = tmp_rate; + + if (best_rate == rate) + break; + } + + *div = curdiv << CM_DIV_FRAC_BITS; + *prate = curdiv * best_rate; + + return best_rate; +} + static int bcm2835_clock_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { - struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); struct clk_hw *parent, *best_parent = NULL; bool current_parent_is_pllc; unsigned long rate, best_rate = 0; @@ -1048,9 +1101,8 @@ static int bcm2835_clock_determine_rate(struct clk_hw *hw, if (bcm2835_clk_is_pllc(parent) && !current_parent_is_pllc) continue; - prate = clk_hw_get_rate(parent); - div = bcm2835_clock_choose_div(hw, req->rate, prate, true); - rate = bcm2835_clock_rate_from_divisor(clock, prate, div); + rate = bcm2835_clock_choose_div_and_prate(hw, i, req->rate, + &div, &prate); if (rate > best_rate && rate <= req->rate) { best_parent = parent; best_prate = prate; @@ -1262,6 +1314,13 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, init.name = data->name; init.flags = data->flags | CLK_IGNORE_UNUSED; + /* + * Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate + * rate changes on at least of the parents. + */ + if (data->set_rate_parent) + init.flags |= CLK_SET_RATE_PARENT; + if (data->is_vpu_clock) { init.ops = &bcm2835_vpu_clock_clk_ops; } else { From patchwork Tue Apr 4 06:17:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Pundir X-Patchwork-Id: 96673 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp48108qgd; Mon, 3 Apr 2017 23:17:41 -0700 (PDT) X-Received: by 10.84.224.131 with SMTP id s3mr26740204plj.162.1491286661835; Mon, 03 Apr 2017 23:17:41 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a9si746909pgf.57.2017.04.03.23.17.41; Mon, 03 Apr 2017 23:17:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750961AbdDDGRl (ORCPT + 6 others); Tue, 4 Apr 2017 02:17:41 -0400 Received: from mail-pg0-f44.google.com ([74.125.83.44]:34549 "EHLO mail-pg0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751066AbdDDGRk (ORCPT ); Tue, 4 Apr 2017 02:17:40 -0400 Received: by mail-pg0-f44.google.com with SMTP id 21so142750424pgg.1 for ; Mon, 03 Apr 2017 23:17:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Y8zOukan2JejQjnNm7LJz+LbfC8C/DLn0s86i/CVMzM=; b=ZBaPkuwkhM5CPqUIovzf5SP7w3Z30JdPFP00pGmyWlWraPQ+jbXu55PU5r6Baxg5dB 6Vh2uRy9JLhln70mCbzmUhL5tNgJMqekXQhenMO/mDU89ll5duCDnFscJlUGyc7pxRuV j7tVKFVkaXuWIztfHUjSutSvFap0xXu4e3e7s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Y8zOukan2JejQjnNm7LJz+LbfC8C/DLn0s86i/CVMzM=; b=e/rFWGLFK2nStei8Gd0wA4A4/j+d09IZH47AjMAaWyAUdUG167nFQiP8hXiiFQdpmk sWSji0JgWy/d0BwWcVekv7S2ADRNvNHsWU8mR+p1Z7rTsUYmg4dyZZ6yrVDTw/zPy1I2 SwqieTiVA7OuSdn/+efQyvvK13FOPNg3VAdYbabB2tGW9k5VND3VrCW4x5rLYJ/2c+xR q48HWsdH20ZhwzyNYaHPJMyuHhzcpVYjrcX6h5IB9lpXBQ/kchsUIPnV0d0VRJwV2fji tL4CfbznH4Q6AqdFp0KEbIYoZH98CtPyizqUE/ZYm7XBQ2GaIWUAoh4llOxeTT4T43C1 FHvg== X-Gm-Message-State: AFeK/H1JDIh+Bbr5P6aFcTYqt97PAaFb1abiil514NwcVYhZeY81zfQfdVXtNXS4SH3HKB2w X-Received: by 10.98.36.81 with SMTP id r78mr21350673pfj.178.1491286659952; Mon, 03 Apr 2017 23:17:39 -0700 (PDT) Received: from localhost.localdomain ([106.51.240.246]) by smtp.gmail.com with ESMTPSA id l126sm29224804pfl.56.2017.04.03.23.17.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 03 Apr 2017 23:17:39 -0700 (PDT) From: Amit Pundir To: gregkh@linuxfoundation.org Cc: stable@vger.kernel.org, Boris Brezillon , Stephen Boyd Subject: [PATCH 11/33] clk: bcm: Allow rate change propagation to PLLH_AUX on VEC clock Date: Tue, 4 Apr 2017 11:47:25 +0530 Message-Id: <1491286653-31193-2-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491286653-31193-1-git-send-email-amit.pundir@linaro.org> References: <1491286653-31193-1-git-send-email-amit.pundir@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Boris Brezillon The VEC clock requires needs to be set at exactly 108MHz. Allow rate change propagation on PLLH_AUX to match this requirement wihtout impacting other IPs (PLLH is currently only used by the HDMI encoder, which cannot be enabled when the VEC encoder is enabled). Signed-off-by: Boris Brezillon Reviewed-by: Eric Anholt Signed-off-by: Stephen Boyd (cherry picked from commit d86d46af84855403c00018be1c3e7bc190f2a6cd) Signed-off-by: Amit Pundir --- drivers/clk/bcm/clk-bcm2835.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index df96fe6..eaf82f4 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -1861,7 +1861,12 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .ctl_reg = CM_VECCTL, .div_reg = CM_VECDIV, .int_bits = 4, - .frac_bits = 0), + .frac_bits = 0, + /* + * Allow rate change propagation only on PLLH_AUX which is + * assigned index 7 in the parent array. + */ + .set_rate_parent = BIT(7)), /* dsi clocks */ [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK( From patchwork Tue Apr 4 06:17:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Pundir X-Patchwork-Id: 96674 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp48117qgd; Mon, 3 Apr 2017 23:17:44 -0700 (PDT) X-Received: by 10.84.229.10 with SMTP id b10mr26704583plk.148.1491286664244; Mon, 03 Apr 2017 23:17:44 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a9si746909pgf.57.2017.04.03.23.17.44; Mon, 03 Apr 2017 23:17:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751005AbdDDGRn (ORCPT + 6 others); Tue, 4 Apr 2017 02:17:43 -0400 Received: from mail-pg0-f43.google.com ([74.125.83.43]:34573 "EHLO mail-pg0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751020AbdDDGRn (ORCPT ); Tue, 4 Apr 2017 02:17:43 -0400 Received: by mail-pg0-f43.google.com with SMTP id 21so142751357pgg.1 for ; Mon, 03 Apr 2017 23:17:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=748spIC5zfHXulxOiBih0Tgm/jI0ve+M+oXVdPAI3to=; b=ch4Ndl0LqV4NAwREPI3xWnAGKQgPZvbBLK+iBFWvlKe3dAvS7u7UqeOKVYPuhPddVA sbwJljAyysAZfATGw/MLuSqeqjxT8V+jx9NDHWFg4hYVl+re5KAHkrLozMSG+mWoM7ud UsAXsqTWFdWtFPo47Poy4kb7yls1feuVtVUAY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=748spIC5zfHXulxOiBih0Tgm/jI0ve+M+oXVdPAI3to=; b=OrUBhZIz+sUf5HRhuJu8Z9pxd/vzw53HF3qC6UCQyWvgc2S2cnuXSIjx2TA6Lf/rVJ QlaYbaeOHF7UAeFH+jlHtqejWQ2lp49MplXNx2CxaHYxPd/dgIvYP+pp+D/XBFuppcQ7 N9qDII44QEMSLA5SWjRFaykLCYy4WEcwB4pfEg0aSnGC2xK5J9VVGB0R4fTBZzo2b8LL EVPmjFkk8MeC0ljnAD6r7nNhJWsMfc0Q4CNjnA4w6GqRWOZAx5BY6tcQ2wa/h7hecF2i lAuO7u7UM3haJoPDhPM+8gSZAYgi16GOBV0DcN2od3Giqt7hXF9Igo+crEkToMcFwGst o0pA== X-Gm-Message-State: AFeK/H1dlIiEa236IeehlgvbPp5Jwbk4niqy9MlQ8YpEGmjfbwzvu8G0/A6GLlv3rWpCA5kF X-Received: by 10.99.52.202 with SMTP id b193mr21427789pga.131.1491286662235; Mon, 03 Apr 2017 23:17:42 -0700 (PDT) Received: from localhost.localdomain ([106.51.240.246]) by smtp.gmail.com with ESMTPSA id l126sm29224804pfl.56.2017.04.03.23.17.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 03 Apr 2017 23:17:41 -0700 (PDT) From: Amit Pundir To: gregkh@linuxfoundation.org Cc: stable@vger.kernel.org, Boris Brezillon , Stephen Boyd Subject: [PATCH 12/33] clk: bcm: Fix 'maybe-uninitialized' warning in bcm2835_clock_choose_div_and_prate() Date: Tue, 4 Apr 2017 11:47:26 +0530 Message-Id: <1491286653-31193-3-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491286653-31193-1-git-send-email-amit.pundir@linaro.org> References: <1491286653-31193-1-git-send-email-amit.pundir@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Boris Brezillon best_rate is reported as potentially uninitialized by gcc. Signed-off-by: Boris Brezillon Fixes: 155e8b3b0ee3 ("clk: bcm: Support rate change propagation on bcm2835 clocks") Reported-by: Stephen Rothwell Reviewed-by: Eric Anholt Signed-off-by: Stephen Boyd (cherry picked from commit 2aab7a2055a1705c9e30920d95a596226999eb21) Signed-off-by: Amit Pundir --- drivers/clk/bcm/clk-bcm2835.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index eaf82f4..0d14409 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -1029,7 +1029,7 @@ static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw, struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); struct bcm2835_cprman *cprman = clock->cprman; const struct bcm2835_clock_data *data = clock->data; - unsigned long best_rate; + unsigned long best_rate = 0; u32 curdiv, mindiv, maxdiv; struct clk_hw *parent; From patchwork Tue Apr 4 06:17:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Pundir X-Patchwork-Id: 96675 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp48127qgd; Mon, 3 Apr 2017 23:17:46 -0700 (PDT) X-Received: by 10.98.1.213 with SMTP id 204mr21546483pfb.51.1491286666462; Mon, 03 Apr 2017 23:17:46 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a9si746909pgf.57.2017.04.03.23.17.46; Mon, 03 Apr 2017 23:17:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751169AbdDDGRp (ORCPT + 6 others); Tue, 4 Apr 2017 02:17:45 -0400 Received: from mail-pg0-f42.google.com ([74.125.83.42]:34966 "EHLO mail-pg0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751031AbdDDGRp (ORCPT ); Tue, 4 Apr 2017 02:17:45 -0400 Received: by mail-pg0-f42.google.com with SMTP id 81so142700820pgh.2 for ; Mon, 03 Apr 2017 23:17:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2RNM8+/EuIrB0J33Li0qTrRkKmm+73o0TkJ+B7RfUeM=; b=Enft2dsLF+c9kh0XXDts2DtXhpnRsSjhielLqwI5PZg4rZvtvlOBSqOuc1iHQbr5w6 Hk+mWEkT4h9tTCuxBkNF0F1jhf4vzeVLpU8yBExrX+BR77ggfhoDxupDvfztqFtqpvge /hogLK1lj5lEKr/JQEvTwbNggM7bhgOU6r0p0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2RNM8+/EuIrB0J33Li0qTrRkKmm+73o0TkJ+B7RfUeM=; b=m0kpV5Q9alQ2KPY9Bsr6qc4kPWyrcv36OmQ+aDhM6IAFnBMAk4aBFUg+lKgOA1Kl4s lV6zgfMkf4S8leZcqM+zzoTQ+zidhEeAULw69fCqmdVYTtwBSXE63wK0B0ciROIEpke9 HoWgJcg//1A6mK0kNlaACDcOJvWj+rZQcrc73Lako2rd5RgWyfINbpo2NqWNgCENMZro xFcEqDFExCbRTwU1l5t4AbU2zyyX4qNCckSeHOB+jsHXss7ulMYKHdbTgHaZhGqnumxW O7mEDQ+d1PGbdXIcLqCdJUEPPoyaSEvXiftyEj3B5NFny9uJHSDGnXYn1aTJZ0yt9gsh Kqpw== X-Gm-Message-State: AFeK/H0oaO41DSqQwqxVKWQSHfepwtMGn7kpfLUbvxfW5L6tYqelKz1QtOqJdRw+6AiQgP0C X-Received: by 10.99.109.137 with SMTP id i131mr21727832pgc.103.1491286664474; Mon, 03 Apr 2017 23:17:44 -0700 (PDT) Received: from localhost.localdomain ([106.51.240.246]) by smtp.gmail.com with ESMTPSA id l126sm29224804pfl.56.2017.04.03.23.17.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 03 Apr 2017 23:17:43 -0700 (PDT) From: Amit Pundir To: gregkh@linuxfoundation.org Cc: stable@vger.kernel.org, Eric Anholt , Stephen Boyd Subject: [PATCH 13/33] clk: bcm2835: Don't rate change PLLs on behalf of DSI PLL dividers. Date: Tue, 4 Apr 2017 11:47:27 +0530 Message-Id: <1491286653-31193-4-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491286653-31193-1-git-send-email-amit.pundir@linaro.org> References: <1491286653-31193-1-git-send-email-amit.pundir@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Eric Anholt Our core PLLs are intended to be configured once and left alone. With the SET_RATE_PARENT, asking to set the PLLD_DSI1 clock rate would change PLLD just to get closer to the requested DSI clock, thus changing PLLD_PER, the UART and ethernet PHY clock rates downstream of it, and breaking ethernet. We *do* want PLLH to change so that PLLH_AUX can be exactly the value we want, though. Thus, we need to have a per-divider policy of whether to pass rate changes up. Signed-off-by: Eric Anholt Signed-off-by: Stephen Boyd (cherry picked from commit 55486091bd1e1c5ed28c43c0d6b3392468a9adb5) Signed-off-by: Amit Pundir --- drivers/clk/bcm/clk-bcm2835.c | 42 ++++++++++++++++++++++++++++-------------- 1 file changed, 28 insertions(+), 14 deletions(-) -- 2.7.4 diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index 0d14409..3d0848d 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -428,6 +428,7 @@ struct bcm2835_pll_divider_data { u32 load_mask; u32 hold_mask; u32 fixed_divider; + u32 flags; }; struct bcm2835_clock_data { @@ -1252,7 +1253,7 @@ bcm2835_register_pll_divider(struct bcm2835_cprman *cprman, init.num_parents = 1; init.name = divider_name; init.ops = &bcm2835_pll_divider_clk_ops; - init.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED; + init.flags = data->flags | CLK_IGNORE_UNUSED; divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL); if (!divider) @@ -1466,7 +1467,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .a2w_reg = A2W_PLLA_CORE, .load_mask = CM_PLLA_LOADCORE, .hold_mask = CM_PLLA_HOLDCORE, - .fixed_divider = 1), + .fixed_divider = 1, + .flags = CLK_SET_RATE_PARENT), [BCM2835_PLLA_PER] = REGISTER_PLL_DIV( .name = "plla_per", .source_pll = "plla", @@ -1474,7 +1476,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .a2w_reg = A2W_PLLA_PER, .load_mask = CM_PLLA_LOADPER, .hold_mask = CM_PLLA_HOLDPER, - .fixed_divider = 1), + .fixed_divider = 1, + .flags = CLK_SET_RATE_PARENT), [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV( .name = "plla_dsi0", .source_pll = "plla", @@ -1490,7 +1493,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .a2w_reg = A2W_PLLA_CCP2, .load_mask = CM_PLLA_LOADCCP2, .hold_mask = CM_PLLA_HOLDCCP2, - .fixed_divider = 1), + .fixed_divider = 1, + .flags = CLK_SET_RATE_PARENT), /* PLLB is used for the ARM's clock. */ [BCM2835_PLLB] = REGISTER_PLL( @@ -1514,7 +1518,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .a2w_reg = A2W_PLLB_ARM, .load_mask = CM_PLLB_LOADARM, .hold_mask = CM_PLLB_HOLDARM, - .fixed_divider = 1), + .fixed_divider = 1, + .flags = CLK_SET_RATE_PARENT), /* * PLLC is the core PLL, used to drive the core VPU clock. @@ -1543,7 +1548,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .a2w_reg = A2W_PLLC_CORE0, .load_mask = CM_PLLC_LOADCORE0, .hold_mask = CM_PLLC_HOLDCORE0, - .fixed_divider = 1), + .fixed_divider = 1, + .flags = CLK_SET_RATE_PARENT), [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV( .name = "pllc_core1", .source_pll = "pllc", @@ -1551,7 +1557,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .a2w_reg = A2W_PLLC_CORE1, .load_mask = CM_PLLC_LOADCORE1, .hold_mask = CM_PLLC_HOLDCORE1, - .fixed_divider = 1), + .fixed_divider = 1, + .flags = CLK_SET_RATE_PARENT), [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV( .name = "pllc_core2", .source_pll = "pllc", @@ -1559,7 +1566,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .a2w_reg = A2W_PLLC_CORE2, .load_mask = CM_PLLC_LOADCORE2, .hold_mask = CM_PLLC_HOLDCORE2, - .fixed_divider = 1), + .fixed_divider = 1, + .flags = CLK_SET_RATE_PARENT), [BCM2835_PLLC_PER] = REGISTER_PLL_DIV( .name = "pllc_per", .source_pll = "pllc", @@ -1567,7 +1575,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .a2w_reg = A2W_PLLC_PER, .load_mask = CM_PLLC_LOADPER, .hold_mask = CM_PLLC_HOLDPER, - .fixed_divider = 1), + .fixed_divider = 1, + .flags = CLK_SET_RATE_PARENT), /* * PLLD is the display PLL, used to drive DSI display panels. @@ -1596,7 +1605,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .a2w_reg = A2W_PLLD_CORE, .load_mask = CM_PLLD_LOADCORE, .hold_mask = CM_PLLD_HOLDCORE, - .fixed_divider = 1), + .fixed_divider = 1, + .flags = CLK_SET_RATE_PARENT), [BCM2835_PLLD_PER] = REGISTER_PLL_DIV( .name = "plld_per", .source_pll = "plld", @@ -1604,7 +1614,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .a2w_reg = A2W_PLLD_PER, .load_mask = CM_PLLD_LOADPER, .hold_mask = CM_PLLD_HOLDPER, - .fixed_divider = 1), + .fixed_divider = 1, + .flags = CLK_SET_RATE_PARENT), [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV( .name = "plld_dsi0", .source_pll = "plld", @@ -1649,7 +1660,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .a2w_reg = A2W_PLLH_RCAL, .load_mask = CM_PLLH_LOADRCAL, .hold_mask = 0, - .fixed_divider = 10), + .fixed_divider = 10, + .flags = CLK_SET_RATE_PARENT), [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV( .name = "pllh_aux", .source_pll = "pllh", @@ -1657,7 +1669,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .a2w_reg = A2W_PLLH_AUX, .load_mask = CM_PLLH_LOADAUX, .hold_mask = 0, - .fixed_divider = 1), + .fixed_divider = 1, + .flags = CLK_SET_RATE_PARENT), [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV( .name = "pllh_pix", .source_pll = "pllh", @@ -1665,7 +1678,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .a2w_reg = A2W_PLLH_PIX, .load_mask = CM_PLLH_LOADPIX, .hold_mask = 0, - .fixed_divider = 10), + .fixed_divider = 10, + .flags = CLK_SET_RATE_PARENT), /* the clocks */ From patchwork Tue Apr 4 06:17:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Pundir X-Patchwork-Id: 96676 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp48139qgd; Mon, 3 Apr 2017 23:17:48 -0700 (PDT) X-Received: by 10.84.231.199 with SMTP id g7mr26750370pln.163.1491286668742; Mon, 03 Apr 2017 23:17:48 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a9si746909pgf.57.2017.04.03.23.17.48; Mon, 03 Apr 2017 23:17:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751043AbdDDGRs (ORCPT + 6 others); Tue, 4 Apr 2017 02:17:48 -0400 Received: from mail-pg0-f50.google.com ([74.125.83.50]:36828 "EHLO mail-pg0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750962AbdDDGRr (ORCPT ); Tue, 4 Apr 2017 02:17:47 -0400 Received: by mail-pg0-f50.google.com with SMTP id g2so140800482pge.3 for ; Mon, 03 Apr 2017 23:17:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WoH7+NHaqc3j7vfAKZeTXTmdchZnv5OU73TP3NmPGE8=; b=CHUYL7yMVzr0X8lKns9PdveiKedKCElrNIt8X8nstDz4TW+BUvuELNkNGISxJSaky3 FYESjsIhPlQjNEkQWpIm1Qw3tLvAuRb1467KiO6ZS7nWuMul7SUyoO6gNAblNuIbFKgu vQAPVsXgdY+IL5hawirTMWgcvMEPtHybJGnsA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WoH7+NHaqc3j7vfAKZeTXTmdchZnv5OU73TP3NmPGE8=; b=YGi25h/eihHguB3Df+nn2ngB+I9umcSpr7/yYlAleJPiHoX950unXQPksaZKdlvVle 1PE5GsRCr6ezmEoNyji5qtcLIpcxtCEzuk6JTy7yPpf7TyxhHwfd3JKfaY+7DxSJ8hDQ U6CrsyhtRy4w6F00USFHyysOQDriyobKm1q7Mv37/FYwukib7bNQ/s6x8u94EpfryHlt Tdni1gikJqp1yGzus7VPE9lqOf0nSA6PR71T1MM0zw5QAGD813DvuGYykInjIeJVthWF 9eWkPGgGR78CdKXZEW0lUz9iflrMcgjHESoiO7MgW5eParfNueY34spewV6nKsXEuSLb Nu6g== X-Gm-Message-State: AFeK/H1Aff+MnVFU6UpzcwMo5jEIyrzcbjHMIXQm8vg/zd2S2O8FrrbNJrItoA0Cgigs7K5R X-Received: by 10.99.217.17 with SMTP id r17mr22245197pgg.140.1491286666628; Mon, 03 Apr 2017 23:17:46 -0700 (PDT) Received: from localhost.localdomain ([106.51.240.246]) by smtp.gmail.com with ESMTPSA id l126sm29224804pfl.56.2017.04.03.23.17.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 03 Apr 2017 23:17:46 -0700 (PDT) From: Amit Pundir To: gregkh@linuxfoundation.org Cc: stable@vger.kernel.org, Eric Anholt , Stephen Boyd Subject: [PATCH 14/33] clk: bcm2835: Register the DSI0/DSI1 pixel clocks. Date: Tue, 4 Apr 2017 11:47:28 +0530 Message-Id: <1491286653-31193-5-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491286653-31193-1-git-send-email-amit.pundir@linaro.org> References: <1491286653-31193-1-git-send-email-amit.pundir@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Eric Anholt The DSI pixel clocks are muxed from clocks generated in the analog phy by the DSI driver. In order to set them as parents, we need to do the same name lookup dance on them as we do for our root oscillator. Signed-off-by: Eric Anholt Signed-off-by: Stephen Boyd (cherry picked from commit 8a39e9fa578229fd4604266c6ebb1a3a77d7994c) Signed-off-by: Amit Pundir --- .../bindings/clock/brcm,bcm2835-cprman.txt | 15 ++- drivers/clk/bcm/clk-bcm2835.c | 121 +++++++++++++++++++-- include/dt-bindings/clock/bcm2835.h | 2 + 3 files changed, 125 insertions(+), 13 deletions(-) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt b/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt index e56a1df..dd906db 100644 --- a/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt +++ b/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt @@ -16,7 +16,20 @@ Required properties: - #clock-cells: Should be <1>. The permitted clock-specifier values can be found in include/dt-bindings/clock/bcm2835.h - reg: Specifies base physical address and size of the registers -- clocks: The external oscillator clock phandle +- clocks: phandles to the parent clocks used as input to the module, in + the following order: + + - External oscillator + - DSI0 byte clock + - DSI0 DDR2 clock + - DSI0 DDR clock + - DSI1 byte clock + - DSI1 DDR2 clock + - DSI1 DDR clock + + Only external oscillator is required. The DSI clocks may + not be present, in which case their children will be + unusable. Example: diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index 3d0848d..2e7423d 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -297,11 +297,32 @@ #define LOCK_TIMEOUT_NS 100000000 #define BCM2835_MAX_FB_RATE 1750000000u +/* + * Names of clocks used within the driver that need to be replaced + * with an external parent's name. This array is in the order that + * the clocks node in the DT references external clocks. + */ +static const char *const cprman_parent_names[] = { + "xosc", + "dsi0_byte", + "dsi0_ddr2", + "dsi0_ddr", + "dsi1_byte", + "dsi1_ddr2", + "dsi1_ddr", +}; + struct bcm2835_cprman { struct device *dev; void __iomem *regs; spinlock_t regs_lock; /* spinlock for all clocks */ - const char *osc_name; + + /* + * Real names of cprman clock parents looked up through + * of_clk_get_parent_name(), which will be used in the + * parent_names[] arrays for clock registration. + */ + const char *real_parent_names[ARRAY_SIZE(cprman_parent_names)]; /* Must be last */ struct clk_hw_onecell_data onecell; @@ -907,6 +928,9 @@ static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock, const struct bcm2835_clock_data *data = clock->data; u64 temp; + if (data->int_bits == 0 && data->frac_bits == 0) + return parent_rate; + /* * The divisor is a 12.12 fixed point field, but only some of * the bits are populated in any given clock. @@ -930,7 +954,12 @@ static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw, struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); struct bcm2835_cprman *cprman = clock->cprman; const struct bcm2835_clock_data *data = clock->data; - u32 div = cprman_read(cprman, data->div_reg); + u32 div; + + if (data->int_bits == 0 && data->frac_bits == 0) + return parent_rate; + + div = cprman_read(cprman, data->div_reg); return bcm2835_clock_rate_from_divisor(clock, parent_rate, div); } @@ -1209,7 +1238,7 @@ static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman, memset(&init, 0, sizeof(init)); /* All of the PLLs derive from the external oscillator. */ - init.parent_names = &cprman->osc_name; + init.parent_names = &cprman->real_parent_names[0]; init.num_parents = 1; init.name = data->name; init.ops = &bcm2835_pll_clk_ops; @@ -1295,18 +1324,22 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, struct bcm2835_clock *clock; struct clk_init_data init; const char *parents[1 << CM_SRC_BITS]; - size_t i; + size_t i, j; int ret; /* - * Replace our "xosc" references with the oscillator's - * actual name. + * Replace our strings referencing parent clocks with the + * actual clock-output-name of the parent. */ for (i = 0; i < data->num_mux_parents; i++) { - if (strcmp(data->parents[i], "xosc") == 0) - parents[i] = cprman->osc_name; - else - parents[i] = data->parents[i]; + parents[i] = data->parents[i]; + + for (j = 0; j < ARRAY_SIZE(cprman_parent_names); j++) { + if (strcmp(parents[i], cprman_parent_names[j]) == 0) { + parents[i] = cprman->real_parent_names[j]; + break; + } + } } memset(&init, 0, sizeof(init)); @@ -1433,6 +1466,47 @@ static const char *const bcm2835_clock_vpu_parents[] = { __VA_ARGS__) /* + * DSI parent clocks. The DSI byte/DDR/DDR2 clocks come from the DSI + * analog PHY. The _inv variants are generated internally to cprman, + * but we don't use them so they aren't hooked up. + */ +static const char *const bcm2835_clock_dsi0_parents[] = { + "gnd", + "xosc", + "testdebug0", + "testdebug1", + "dsi0_ddr", + "dsi0_ddr_inv", + "dsi0_ddr2", + "dsi0_ddr2_inv", + "dsi0_byte", + "dsi0_byte_inv", +}; + +static const char *const bcm2835_clock_dsi1_parents[] = { + "gnd", + "xosc", + "testdebug0", + "testdebug1", + "dsi1_ddr", + "dsi1_ddr_inv", + "dsi1_ddr2", + "dsi1_ddr2_inv", + "dsi1_byte", + "dsi1_byte_inv", +}; + +#define REGISTER_DSI0_CLK(...) REGISTER_CLK( \ + .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi0_parents), \ + .parents = bcm2835_clock_dsi0_parents, \ + __VA_ARGS__) + +#define REGISTER_DSI1_CLK(...) REGISTER_CLK( \ + .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents), \ + .parents = bcm2835_clock_dsi1_parents, \ + __VA_ARGS__) + +/* * the real definition of all the pll, pll_dividers and clocks * these make use of the above REGISTER_* macros */ @@ -1895,6 +1969,18 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .div_reg = CM_DSI1EDIV, .int_bits = 4, .frac_bits = 8), + [BCM2835_CLOCK_DSI0P] = REGISTER_DSI0_CLK( + .name = "dsi0p", + .ctl_reg = CM_DSI0PCTL, + .div_reg = CM_DSI0PDIV, + .int_bits = 0, + .frac_bits = 0), + [BCM2835_CLOCK_DSI1P] = REGISTER_DSI1_CLK( + .name = "dsi1p", + .ctl_reg = CM_DSI1PCTL, + .div_reg = CM_DSI1PDIV, + .int_bits = 0, + .frac_bits = 0), /* the gates */ @@ -1953,8 +2039,19 @@ static int bcm2835_clk_probe(struct platform_device *pdev) if (IS_ERR(cprman->regs)) return PTR_ERR(cprman->regs); - cprman->osc_name = of_clk_get_parent_name(dev->of_node, 0); - if (!cprman->osc_name) + memcpy(cprman->real_parent_names, cprman_parent_names, + sizeof(cprman_parent_names)); + of_clk_parent_fill(dev->of_node, cprman->real_parent_names, + ARRAY_SIZE(cprman_parent_names)); + + /* + * Make sure the external oscillator has been registered. + * + * The other (DSI) clocks are not present on older device + * trees, which we still need to support for backwards + * compatibility. + */ + if (!cprman->real_parent_names[0]) return -ENODEV; platform_set_drvdata(pdev, cprman); diff --git a/include/dt-bindings/clock/bcm2835.h b/include/dt-bindings/clock/bcm2835.h index 360e00c..a0c812b 100644 --- a/include/dt-bindings/clock/bcm2835.h +++ b/include/dt-bindings/clock/bcm2835.h @@ -64,3 +64,5 @@ #define BCM2835_CLOCK_CAM1 46 #define BCM2835_CLOCK_DSI0E 47 #define BCM2835_CLOCK_DSI1E 48 +#define BCM2835_CLOCK_DSI0P 49 +#define BCM2835_CLOCK_DSI1P 50 From patchwork Tue Apr 4 06:17:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Pundir X-Patchwork-Id: 96677 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp48147qgd; Mon, 3 Apr 2017 23:17:51 -0700 (PDT) X-Received: by 10.99.176.5 with SMTP id h5mr21937866pgf.179.1491286671061; Mon, 03 Apr 2017 23:17:51 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a9si746909pgf.57.2017.04.03.23.17.50; Mon, 03 Apr 2017 23:17:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751082AbdDDGRu (ORCPT + 6 others); Tue, 4 Apr 2017 02:17:50 -0400 Received: from mail-pg0-f41.google.com ([74.125.83.41]:33159 "EHLO mail-pg0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750962AbdDDGRt (ORCPT ); Tue, 4 Apr 2017 02:17:49 -0400 Received: by mail-pg0-f41.google.com with SMTP id x125so142549224pgb.0 for ; Mon, 03 Apr 2017 23:17:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=j64GvdH77f2NtPDChqPhOWc8qq74IAHuBiWxe0RnM8o=; b=Bohttqs0krLh6U8R/dd7UUIDmybHU/reJD6qkW49a7zp/IeVxYZ2dc85K2/DHSVzEI QAbINbwWmQ3dWPQPhfbIXqeVyCS2fKh/mygdI0/E0NVnYmM4eVyibKy/oLWWchj9EfoE whHQRCE92iZ3+DSlxGjVY0lhTtnTv7x9ogqNk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=j64GvdH77f2NtPDChqPhOWc8qq74IAHuBiWxe0RnM8o=; b=Uunzhjr7HgZ39aBRYkRKi5pXRK9mk1N1dQIuQslb+Mtl6jRA4DhuYZcyxfzs2OyICM FSSg5nkcRgnsNCoqVklGxAQW95gO9NQmRmDKPixSOsj9vpmXUEXFtCsHepmK1Vr/j0FK 1PPoinSxr1JOPSwltkripyJX01UuppXBzBIgJaUrEGVB7Apvo9+XWgKCiVqP7S+2TZ4h RuRcps/Ce8diZwo4UpspSyzOioGzDm55Nikb6wFARdK0xZ6BEHind3fYnkKwdNXWi1or ebXTGjTnwiDD3tFR2w4SFXMz9VS0aDKknHQdnSNO0o4XtSDWohHWcXyoGciv2zSn/LSb x+aw== X-Gm-Message-State: AFeK/H04ZSt3CE2XHUnROabmWovltXSmlbgoFCzij4NedZ8/6eOs8M83M/kw46cFrhgt6sQ9 X-Received: by 10.99.163.91 with SMTP id v27mr21877600pgn.171.1491286668833; Mon, 03 Apr 2017 23:17:48 -0700 (PDT) Received: from localhost.localdomain ([106.51.240.246]) by smtp.gmail.com with ESMTPSA id l126sm29224804pfl.56.2017.04.03.23.17.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 03 Apr 2017 23:17:48 -0700 (PDT) From: Amit Pundir To: gregkh@linuxfoundation.org Cc: stable@vger.kernel.org, Eric Anholt , Stephen Boyd Subject: [PATCH 15/33] clk: bcm2835: Add leaf clock measurement support, disabled by default Date: Tue, 4 Apr 2017 11:47:29 +0530 Message-Id: <1491286653-31193-6-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491286653-31193-1-git-send-email-amit.pundir@linaro.org> References: <1491286653-31193-1-git-send-email-amit.pundir@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Eric Anholt This proved incredibly useful during debugging of the DSI driver, to see if our clocks were running at rate we requested. Let's leave it here for the next person interacting with clocks on the platform (and so that hopefully we can just hook it up to debugfs some day). Signed-off-by: Eric Anholt Signed-off-by: Stephen Boyd (cherry picked from commit 3f9195811d8d829556c4cd88d3f9e56a80d5ba60) Signed-off-by: Amit Pundir --- drivers/clk/bcm/clk-bcm2835.c | 144 ++++++++++++++++++++++++++++++++++-------- 1 file changed, 119 insertions(+), 25 deletions(-) -- 2.7.4 diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index 2e7423d..0258538 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -39,6 +39,7 @@ #include #include #include +#include #include #include #include @@ -98,7 +99,8 @@ #define CM_SMIDIV 0x0b4 /* no definition for 0x0b8 and 0x0bc */ #define CM_TCNTCTL 0x0c0 -#define CM_TCNTDIV 0x0c4 +# define CM_TCNT_SRC1_SHIFT 12 +#define CM_TCNTCNT 0x0c4 #define CM_TECCTL 0x0c8 #define CM_TECDIV 0x0cc #define CM_TD0CTL 0x0d0 @@ -338,6 +340,61 @@ static inline u32 cprman_read(struct bcm2835_cprman *cprman, u32 reg) return readl(cprman->regs + reg); } +/* Does a cycle of measuring a clock through the TCNT clock, which may + * source from many other clocks in the system. + */ +static unsigned long bcm2835_measure_tcnt_mux(struct bcm2835_cprman *cprman, + u32 tcnt_mux) +{ + u32 osccount = 19200; /* 1ms */ + u32 count; + ktime_t timeout; + + spin_lock(&cprman->regs_lock); + + cprman_write(cprman, CM_TCNTCTL, CM_KILL); + + cprman_write(cprman, CM_TCNTCTL, + (tcnt_mux & CM_SRC_MASK) | + (tcnt_mux >> CM_SRC_BITS) << CM_TCNT_SRC1_SHIFT); + + cprman_write(cprman, CM_OSCCOUNT, osccount); + + /* do a kind delay at the start */ + mdelay(1); + + /* Finish off whatever is left of OSCCOUNT */ + timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); + while (cprman_read(cprman, CM_OSCCOUNT)) { + if (ktime_after(ktime_get(), timeout)) { + dev_err(cprman->dev, "timeout waiting for OSCCOUNT\n"); + count = 0; + goto out; + } + cpu_relax(); + } + + /* Wait for BUSY to clear. */ + timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); + while (cprman_read(cprman, CM_TCNTCTL) & CM_BUSY) { + if (ktime_after(ktime_get(), timeout)) { + dev_err(cprman->dev, "timeout waiting for !BUSY\n"); + count = 0; + goto out; + } + cpu_relax(); + } + + count = cprman_read(cprman, CM_TCNTCNT); + + cprman_write(cprman, CM_TCNTCTL, 0); + +out: + spin_unlock(&cprman->regs_lock); + + return count * 1000; +} + static int bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base, struct debugfs_reg32 *regs, size_t nregs, struct dentry *dentry) @@ -473,6 +530,8 @@ struct bcm2835_clock_data { bool is_vpu_clock; bool is_mash_clock; + + u32 tcnt_mux; }; struct bcm2835_gate_data { @@ -1008,6 +1067,17 @@ static int bcm2835_clock_on(struct clk_hw *hw) CM_GATE); spin_unlock(&cprman->regs_lock); + /* Debug code to measure the clock once it's turned on to see + * if it's ticking at the rate we expect. + */ + if (data->tcnt_mux && false) { + dev_info(cprman->dev, + "clk %s: rate %ld, measure %ld\n", + data->name, + clk_hw_get_rate(hw), + bcm2835_measure_tcnt_mux(cprman, data->tcnt_mux)); + } + return 0; } @@ -1765,7 +1835,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .ctl_reg = CM_OTPCTL, .div_reg = CM_OTPDIV, .int_bits = 4, - .frac_bits = 0), + .frac_bits = 0, + .tcnt_mux = 6), /* * Used for a 1Mhz clock for the system clocksource, and also used * bythe watchdog timer and the camera pulse generator. @@ -1799,13 +1870,15 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .ctl_reg = CM_H264CTL, .div_reg = CM_H264DIV, .int_bits = 4, - .frac_bits = 8), + .frac_bits = 8, + .tcnt_mux = 1), [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK( .name = "isp", .ctl_reg = CM_ISPCTL, .div_reg = CM_ISPDIV, .int_bits = 4, - .frac_bits = 8), + .frac_bits = 8, + .tcnt_mux = 2), /* * Secondary SDRAM clock. Used for low-voltage modes when the PLL @@ -1816,13 +1889,15 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .ctl_reg = CM_SDCCTL, .div_reg = CM_SDCDIV, .int_bits = 6, - .frac_bits = 0), + .frac_bits = 0, + .tcnt_mux = 3), [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK( .name = "v3d", .ctl_reg = CM_V3DCTL, .div_reg = CM_V3DDIV, .int_bits = 4, - .frac_bits = 8), + .frac_bits = 8, + .tcnt_mux = 4), /* * VPU clock. This doesn't have an enable bit, since it drives * the bus for everything else, and is special so it doesn't need @@ -1836,7 +1911,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .int_bits = 12, .frac_bits = 8, .flags = CLK_IS_CRITICAL, - .is_vpu_clock = true), + .is_vpu_clock = true, + .tcnt_mux = 5), /* clocks with per parent mux */ [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK( @@ -1844,19 +1920,22 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .ctl_reg = CM_AVEOCTL, .div_reg = CM_AVEODIV, .int_bits = 4, - .frac_bits = 0), + .frac_bits = 0, + .tcnt_mux = 38), [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK( .name = "cam0", .ctl_reg = CM_CAM0CTL, .div_reg = CM_CAM0DIV, .int_bits = 4, - .frac_bits = 8), + .frac_bits = 8, + .tcnt_mux = 14), [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK( .name = "cam1", .ctl_reg = CM_CAM1CTL, .div_reg = CM_CAM1DIV, .int_bits = 4, - .frac_bits = 8), + .frac_bits = 8, + .tcnt_mux = 15), [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK( .name = "dft", .ctl_reg = CM_DFTCTL, @@ -1868,7 +1947,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .ctl_reg = CM_DPICTL, .div_reg = CM_DPIDIV, .int_bits = 4, - .frac_bits = 8), + .frac_bits = 8, + .tcnt_mux = 17), /* Arasan EMMC clock */ [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK( @@ -1876,7 +1956,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .ctl_reg = CM_EMMCCTL, .div_reg = CM_EMMCDIV, .int_bits = 4, - .frac_bits = 8), + .frac_bits = 8, + .tcnt_mux = 39), /* General purpose (GPIO) clocks */ [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK( @@ -1885,7 +1966,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .div_reg = CM_GP0DIV, .int_bits = 12, .frac_bits = 12, - .is_mash_clock = true), + .is_mash_clock = true, + .tcnt_mux = 20), [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK( .name = "gp1", .ctl_reg = CM_GP1CTL, @@ -1893,7 +1975,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .int_bits = 12, .frac_bits = 12, .flags = CLK_IS_CRITICAL, - .is_mash_clock = true), + .is_mash_clock = true, + .tcnt_mux = 21), [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK( .name = "gp2", .ctl_reg = CM_GP2CTL, @@ -1908,40 +1991,46 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .ctl_reg = CM_HSMCTL, .div_reg = CM_HSMDIV, .int_bits = 4, - .frac_bits = 8), + .frac_bits = 8, + .tcnt_mux = 22), [BCM2835_CLOCK_PCM] = REGISTER_PER_CLK( .name = "pcm", .ctl_reg = CM_PCMCTL, .div_reg = CM_PCMDIV, .int_bits = 12, .frac_bits = 12, - .is_mash_clock = true), + .is_mash_clock = true, + .tcnt_mux = 23), [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK( .name = "pwm", .ctl_reg = CM_PWMCTL, .div_reg = CM_PWMDIV, .int_bits = 12, .frac_bits = 12, - .is_mash_clock = true), + .is_mash_clock = true, + .tcnt_mux = 24), [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK( .name = "slim", .ctl_reg = CM_SLIMCTL, .div_reg = CM_SLIMDIV, .int_bits = 12, .frac_bits = 12, - .is_mash_clock = true), + .is_mash_clock = true, + .tcnt_mux = 25), [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK( .name = "smi", .ctl_reg = CM_SMICTL, .div_reg = CM_SMIDIV, .int_bits = 4, - .frac_bits = 8), + .frac_bits = 8, + .tcnt_mux = 27), [BCM2835_CLOCK_UART] = REGISTER_PER_CLK( .name = "uart", .ctl_reg = CM_UARTCTL, .div_reg = CM_UARTDIV, .int_bits = 10, - .frac_bits = 12), + .frac_bits = 12, + .tcnt_mux = 28), /* TV encoder clock. Only operating frequency is 108Mhz. */ [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK( @@ -1954,7 +2043,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { * Allow rate change propagation only on PLLH_AUX which is * assigned index 7 in the parent array. */ - .set_rate_parent = BIT(7)), + .set_rate_parent = BIT(7), + .tcnt_mux = 29), /* dsi clocks */ [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK( @@ -1962,25 +2052,29 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .ctl_reg = CM_DSI0ECTL, .div_reg = CM_DSI0EDIV, .int_bits = 4, - .frac_bits = 8), + .frac_bits = 8, + .tcnt_mux = 18), [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK( .name = "dsi1e", .ctl_reg = CM_DSI1ECTL, .div_reg = CM_DSI1EDIV, .int_bits = 4, - .frac_bits = 8), + .frac_bits = 8, + .tcnt_mux = 19), [BCM2835_CLOCK_DSI0P] = REGISTER_DSI0_CLK( .name = "dsi0p", .ctl_reg = CM_DSI0PCTL, .div_reg = CM_DSI0PDIV, .int_bits = 0, - .frac_bits = 0), + .frac_bits = 0, + .tcnt_mux = 12), [BCM2835_CLOCK_DSI1P] = REGISTER_DSI1_CLK( .name = "dsi1p", .ctl_reg = CM_DSI1PCTL, .div_reg = CM_DSI1PDIV, .int_bits = 0, - .frac_bits = 0), + .frac_bits = 0, + .tcnt_mux = 13), /* the gates */ From patchwork Tue Apr 4 06:17:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Pundir X-Patchwork-Id: 96678 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp48152qgd; Mon, 3 Apr 2017 23:17:53 -0700 (PDT) X-Received: by 10.98.47.4 with SMTP id v4mr20972585pfv.86.1491286673195; Mon, 03 Apr 2017 23:17:53 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a9si746909pgf.57.2017.04.03.23.17.53; Mon, 03 Apr 2017 23:17:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751130AbdDDGRw (ORCPT + 6 others); Tue, 4 Apr 2017 02:17:52 -0400 Received: from mail-pg0-f54.google.com ([74.125.83.54]:34638 "EHLO mail-pg0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750962AbdDDGRw (ORCPT ); Tue, 4 Apr 2017 02:17:52 -0400 Received: by mail-pg0-f54.google.com with SMTP id 21so142754680pgg.1 for ; Mon, 03 Apr 2017 23:17:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=npA6z32Ekq1KR9faVmOm9RjjDwIR5Sp0t0EtlJQILWc=; b=Wpp49jILiNLvrEDGvICUp+X/SLn9OlO5K4IKZlG2IdmcbYlnyojIC0dTGsJ+ldhmYv U79MCfd40PSwN2xuKnn7ek+/eisRfDz+wA+HeWEfgCT68vk2LIkKIPTjxuBLTS4LHW3g oVl+hlgDvoyvrjU5qvgT69WQxKu0tUx2Kalso= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=npA6z32Ekq1KR9faVmOm9RjjDwIR5Sp0t0EtlJQILWc=; b=VUFS3iJRK2Kij+errvMgnRfzU98tVAsOb0whrKAIe3lTK5Vrs8nWU9xTVxzOa8G1xS /5NJNjvJHzCoWmQX94Hq9OGrt2nbJ0RiXj3Wwa3txVunCpvOspo6peJs6JRvfxnJTl9z UmQDkn9MyVL+LE452qeXJeIlD5O8+Q4QPfg/MovrC/RY3qF8Iv6hEHuL+4tgYcjidTdi zQSB6qn9XZdRnNag3PPcP86hT0VZFVO4OpyrjCHWwZoDhOsJyETkirXeeV0s8EPypNah vdPlnJ3A4reLi7jhREsnmtzpPOSOIuDVSbjJG1RIUnW3Aa/pQA/+pbqLgodrkAUgNUzZ /zWQ== X-Gm-Message-State: AFeK/H2Wv0nmhrjP8zKWgG7/CuOrlag16Ejrw6ymACSJU9M98C5N9GCGpLL5KK5e7u0rrsbv X-Received: by 10.99.127.12 with SMTP id a12mr21950916pgd.5.1491286671191; Mon, 03 Apr 2017 23:17:51 -0700 (PDT) Received: from localhost.localdomain ([106.51.240.246]) by smtp.gmail.com with ESMTPSA id l126sm29224804pfl.56.2017.04.03.23.17.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 03 Apr 2017 23:17:50 -0700 (PDT) From: Amit Pundir To: gregkh@linuxfoundation.org Cc: stable@vger.kernel.org, Matthias Reichl , Martin Sperl , Vinod Koul Subject: [PATCH 16/33] dmaengine: bcm2835: Fix cyclic DMA period splitting Date: Tue, 4 Apr 2017 11:47:30 +0530 Message-Id: <1491286653-31193-7-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491286653-31193-1-git-send-email-amit.pundir@linaro.org> References: <1491286653-31193-1-git-send-email-amit.pundir@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Matthias Reichl The code responsible for splitting periods into chunks that can be handled by the DMA controller missed to update total_len, the number of bytes processed in the current period, when there are more chunks to follow. Therefore total_len was stuck at 0 and the code didn't work at all. This resulted in a wrong control block layout and audio issues because the cyclic DMA callback wasn't executing on period boundaries. Fix this by adding the missing total_len update. Signed-off-by: Matthias Reichl Signed-off-by: Martin Sperl Tested-by: Clive Messer Reviewed-by: Eric Anholt Signed-off-by: Vinod Koul (cherry picked from commit 2201ac6129fa162ac24da089a034bb0971648ebb) Signed-off-by: Amit Pundir --- drivers/dma/bcm2835-dma.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c index e18dc59..6204cc3 100644 --- a/drivers/dma/bcm2835-dma.c +++ b/drivers/dma/bcm2835-dma.c @@ -251,8 +251,11 @@ static void bcm2835_dma_create_cb_set_length( */ /* have we filled in period_length yet? */ - if (*total_len + control_block->length < period_len) + if (*total_len + control_block->length < period_len) { + /* update number of bytes in this period so far */ + *total_len += control_block->length; return; + } /* calculate the length that remains to reach period_length */ control_block->length = period_len - *total_len; From patchwork Tue Apr 4 06:17:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Pundir X-Patchwork-Id: 96679 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp48158qgd; Mon, 3 Apr 2017 23:17:55 -0700 (PDT) X-Received: by 10.84.204.136 with SMTP id b8mr25932408ple.176.1491286675216; Mon, 03 Apr 2017 23:17:55 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a9si746909pgf.57.2017.04.03.23.17.55; Mon, 03 Apr 2017 23:17:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751801AbdDDGRy (ORCPT + 6 others); Tue, 4 Apr 2017 02:17:54 -0400 Received: from mail-pg0-f54.google.com ([74.125.83.54]:34650 "EHLO mail-pg0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751074AbdDDGRy (ORCPT ); Tue, 4 Apr 2017 02:17:54 -0400 Received: by mail-pg0-f54.google.com with SMTP id 21so142755385pgg.1 for ; Mon, 03 Apr 2017 23:17:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LbXlpECKUS8/0IvUj99Xd1nUAoEFknsi8jtAdkiYLeg=; b=derxYS0WT31PBOZSFGnEIcnvShSBoehvNLp5w921zb+hAjzD9HJHbeVztQgvoH+Rqc tBbsip+Zp5qqcOmc3dviyLDchOa14MwjjLwx5+2RJ5iWStBkvrTClNlVuZQ8Ux2uC0Oj uq0dQyBvY2+lEFKN/z+epR7GW2iPWbQNqxAn4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LbXlpECKUS8/0IvUj99Xd1nUAoEFknsi8jtAdkiYLeg=; b=pPpf04Zex52fsc9Xk7ItBw79lwLB+cJE3MKbksUR8zWpZqisOir/UzRdW2KD1vNhu8 zWz/2M2an9MVicJuAARYC6+CC63DrWKW1iHp24yJ/psYrNDsab8kc8rT/Ui4xN1p7Bn3 EM8W3jgJbdYN+gUxmOWMGaU/ZpZ73N4O3yuCyw5hgUnRbNaZto7Y2+cCs5Dj9/ufKyhU e7IvlaG0wcsQTmaVKjPZvSqkxH3HNd63fsi1t+fDsvnfTyTX5ygHscINEspCtt1ZUcv6 HvXZF0SMfPcqpGT6hdWkwulKAaPG4h9NWYwIT/hlHqJUk3Q0q8g6D4c4/tfZ/xUb8tqs dfJQ== X-Gm-Message-State: AFeK/H2vy3X1/YRGY2GYuxLC4NO7+73XRdA4MR74xvAr9IlGB4J7lX3lVVMtwNYZPzXN2AMb X-Received: by 10.99.115.6 with SMTP id o6mr21383045pgc.216.1491286673279; Mon, 03 Apr 2017 23:17:53 -0700 (PDT) Received: from localhost.localdomain ([106.51.240.246]) by smtp.gmail.com with ESMTPSA id l126sm29224804pfl.56.2017.04.03.23.17.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 03 Apr 2017 23:17:52 -0700 (PDT) From: Amit Pundir To: gregkh@linuxfoundation.org Cc: stable@vger.kernel.org, John Youn , Felipe Balbi Subject: [PATCH 17/33] usb: dwc2: Remove unnecessary kfree Date: Tue, 4 Apr 2017 11:47:31 +0530 Message-Id: <1491286653-31193-8-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491286653-31193-1-git-send-email-amit.pundir@linaro.org> References: <1491286653-31193-1-git-send-email-amit.pundir@linaro.org> Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: John Youn This shouldn't be freed by the HCD as it is owned by the core and allocated with devm_kzalloc. Signed-off-by: John Youn Signed-off-by: Felipe Balbi (cherry picked from commit cd4b1e34655d46950c065d9284b596cd8d7b28cd) Signed-off-by: Amit Pundir --- drivers/usb/dwc2/hcd.c | 1 - 1 file changed, 1 deletion(-) -- 2.7.4 diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c index df5a065..1b6f5e1 100644 --- a/drivers/usb/dwc2/hcd.c +++ b/drivers/usb/dwc2/hcd.c @@ -5184,7 +5184,6 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq) error2: usb_put_hcd(hcd); error1: - kfree(hsotg->core_params); #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS kfree(hsotg->last_frame_num_array); From patchwork Tue Apr 4 06:17:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Amit Pundir X-Patchwork-Id: 96680 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp48176qgd; Mon, 3 Apr 2017 23:17:57 -0700 (PDT) X-Received: by 10.98.87.216 with SMTP id i85mr21704243pfj.151.1491286677271; Mon, 03 Apr 2017 23:17:57 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a9si746909pgf.57.2017.04.03.23.17.57; Mon, 03 Apr 2017 23:17:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751237AbdDDGR4 (ORCPT + 6 others); Tue, 4 Apr 2017 02:17:56 -0400 Received: from mail-pg0-f47.google.com ([74.125.83.47]:34667 "EHLO mail-pg0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750962AbdDDGR4 (ORCPT ); Tue, 4 Apr 2017 02:17:56 -0400 Received: by mail-pg0-f47.google.com with SMTP id 21so142756191pgg.1 for ; Mon, 03 Apr 2017 23:17:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ReFQDEBKfMl7fxZkhWSQqvrSiHRA2Q5zEjurGWC4ahQ=; b=L3u0sNuhJopsjODb6KLFhYnQETksNQnyxerC83ovqUY5rbPuyaIez43w3hgjz4Lrq5 V+zeT0xfLntVSS3yXYSgXxxSZz5+fRctaNnM/tssLnhJZQ+4M3x+4+lfoftQQ8GDHlgJ sKP6Ui0BZ2toR/N690aD7MXS/jBTRRFt0nrdk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ReFQDEBKfMl7fxZkhWSQqvrSiHRA2Q5zEjurGWC4ahQ=; b=Ko4R1O98Do4KLL5Zp+7Bd/E2WvFSXhI4Kn/EvrxqiKFDJ0CTEsPH1hn7WHLq3QCMnY 2k9+6cAyzUF/Uf9vbr8gtmwmWC19OGuRONqwMhMScI+UGchk2yny0IkxQXi5hS+XfXfR 6qKpKNtdDH6N2olgBdDYo2+7ul7QLXOLxrxxvFqawwBaS7M6ZoBQh5qTcZPFcVurEUDt iLvPNsAerrmHdFDp4p8YmgaqjToFQZjEEJzdntD8ocaAZgu1ERRHUzlSiUIHrSKG7AXC lsdtDyGcOhamuCVUmkj/UF3XyHHgLvUnlM1+27C/M62JDG47+/Kmqys3yNGM1QcXhywF iNvg== X-Gm-Message-State: AFeK/H2lRP6XXYLhjgcN+JeB8+fWDJCgKiIkCAFSHAWm97EhYLvCS0Vb16I3KPGNcoLphDPC X-Received: by 10.99.216.85 with SMTP id k21mr21815455pgj.10.1491286675387; Mon, 03 Apr 2017 23:17:55 -0700 (PDT) Received: from localhost.localdomain ([106.51.240.246]) by smtp.gmail.com with ESMTPSA id l126sm29224804pfl.56.2017.04.03.23.17.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 03 Apr 2017 23:17:54 -0700 (PDT) From: Amit Pundir To: gregkh@linuxfoundation.org Cc: stable@vger.kernel.org, =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Brian Norris Subject: [PATCH 18/33] mtd: bcm47xxpart: fix parsing first block after aligned TRX Date: Tue, 4 Apr 2017 11:47:32 +0530 Message-Id: <1491286653-31193-9-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491286653-31193-1-git-send-email-amit.pundir@linaro.org> References: <1491286653-31193-1-git-send-email-amit.pundir@linaro.org> MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Rafał Miłecki After parsing TRX we should skip to the first block placed behind it. Our code was working only with TRX with length not aligned to the blocksize. In other cases (length aligned) it was missing the block places right after TRX. This fixes calculation and simplifies the comment. Signed-off-by: Rafał Miłecki Signed-off-by: Brian Norris (cherry picked from commit bd5d21310133921021d78995ad6346f908483124) Signed-off-by: Amit Pundir --- drivers/mtd/bcm47xxpart.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) -- 2.7.4 diff --git a/drivers/mtd/bcm47xxpart.c b/drivers/mtd/bcm47xxpart.c index 3779475..283ff7e 100644 --- a/drivers/mtd/bcm47xxpart.c +++ b/drivers/mtd/bcm47xxpart.c @@ -229,12 +229,10 @@ static int bcm47xxpart_parse(struct mtd_info *master, last_trx_part = curr_part - 1; - /* - * We have whole TRX scanned, skip to the next part. Use - * roundown (not roundup), as the loop will increase - * offset in next step. - */ - offset = rounddown(offset + trx->length, blocksize); + /* Jump to the end of TRX */ + offset = roundup(offset + trx->length, blocksize); + /* Next loop iteration will increase the offset */ + offset -= blocksize; continue; } From patchwork Tue Apr 4 06:17:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Amit Pundir X-Patchwork-Id: 96681 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp48184qgd; Mon, 3 Apr 2017 23:17:59 -0700 (PDT) X-Received: by 10.84.239.8 with SMTP id w8mr26478948plk.73.1491286679526; Mon, 03 Apr 2017 23:17:59 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a9si746909pgf.57.2017.04.03.23.17.59; Mon, 03 Apr 2017 23:17:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751846AbdDDGR6 (ORCPT + 6 others); Tue, 4 Apr 2017 02:17:58 -0400 Received: from mail-pg0-f41.google.com ([74.125.83.41]:35885 "EHLO mail-pg0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750962AbdDDGR6 (ORCPT ); Tue, 4 Apr 2017 02:17:58 -0400 Received: by mail-pg0-f41.google.com with SMTP id g2so140804544pge.3 for ; Mon, 03 Apr 2017 23:17:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=svPl+qa3WWfj1THCd0+ysyLD3KrIs6wEKjnI4EF1Qok=; b=Tr2iYfubOn1rfdvrgnoQd7JhDXlbSdJMEcedeWSdbSazMiVCGR0r8a0OB0r7rJckKB gmSkQODDhVaB7n/FtZ4wHEpSPUwusx+iyJuJtZo07HfeK12DlPkWM4xLCh9dNqv4ByRg eWbnH8TLiC4jeBrNWOQOzK3juDpVci1KA32hg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=svPl+qa3WWfj1THCd0+ysyLD3KrIs6wEKjnI4EF1Qok=; b=iePjh+qNj3TZcVS2qQo7h5m0QeKuX2WzDcxzX5S9yaN3sgNLpPGVFzk6SEF/mxHlL9 qchIVCnXZz/uXIJ6oCvtWIKAF94eIqES8yVkIBU2iO9M2MLC2twpp6ZYGtae6relQPi9 rcCg0XIu4MjDCCPZo+8sGT2UnO0N/Nsmyhy2FCz/qIBADHTq8RSuzuh8cXR3GbPe0MTP iLb7fHJ9vUaBBpr69dIsBCtD0ph40UPqfOdUpwb4Tcnt41g6IbtHaXEg7k9RIgHOCRGs Lh7NqXua5hnJtY6wjeQaViEP+Jf7jQOgTJs7XMOv9gy7lfGHttTY1SkDh5RdO6MH64yM Cz9g== X-Gm-Message-State: AFeK/H2ya6JOpkDYl6UOyBJspHtMuJUJC9J9C0Eq4AHaVOdVk7TMD+nz/+IVCVwtM0A6UF85 X-Received: by 10.99.217.17 with SMTP id r17mr22245818pgg.140.1491286677611; Mon, 03 Apr 2017 23:17:57 -0700 (PDT) Received: from localhost.localdomain ([106.51.240.246]) by smtp.gmail.com with ESMTPSA id l126sm29224804pfl.56.2017.04.03.23.17.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 03 Apr 2017 23:17:56 -0700 (PDT) From: Amit Pundir To: gregkh@linuxfoundation.org Cc: stable@vger.kernel.org, =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , "David S . Miller" Subject: [PATCH 19/33] net: add devm version of alloc_etherdev_mqs function Date: Tue, 4 Apr 2017 11:47:33 +0530 Message-Id: <1491286653-31193-10-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491286653-31193-1-git-send-email-amit.pundir@linaro.org> References: <1491286653-31193-1-git-send-email-amit.pundir@linaro.org> MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Rafał Miłecki This patch adds devm_alloc_etherdev_mqs function and devm_alloc_etherdev macro. These can be used for simpler netdev allocation without having to care about calling free_netdev. Thanks to this change drivers, their error paths and removal paths may get simpler by a bit. Signed-off-by: Rafał Miłecki Signed-off-by: David S. Miller (cherry picked from commit 40be0dda0725886b623d67868db3219a2e74683b) Signed-off-by: Amit Pundir --- include/linux/etherdevice.h | 5 +++++ net/ethernet/eth.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+) -- 2.7.4 diff --git a/include/linux/etherdevice.h b/include/linux/etherdevice.h index 6fec9e8..83ae88c 100644 --- a/include/linux/etherdevice.h +++ b/include/linux/etherdevice.h @@ -54,6 +54,11 @@ struct net_device *alloc_etherdev_mqs(int sizeof_priv, unsigned int txqs, #define alloc_etherdev(sizeof_priv) alloc_etherdev_mq(sizeof_priv, 1) #define alloc_etherdev_mq(sizeof_priv, count) alloc_etherdev_mqs(sizeof_priv, count, count) +struct net_device *devm_alloc_etherdev_mqs(struct device *dev, int sizeof_priv, + unsigned int txqs, + unsigned int rxqs); +#define devm_alloc_etherdev(dev, sizeof_priv) devm_alloc_etherdev_mqs(dev, sizeof_priv, 1, 1) + struct sk_buff **eth_gro_receive(struct sk_buff **head, struct sk_buff *skb); int eth_gro_complete(struct sk_buff *skb, int nhoff); diff --git a/net/ethernet/eth.c b/net/ethernet/eth.c index 24d7aff..fbf1de9 100644 --- a/net/ethernet/eth.c +++ b/net/ethernet/eth.c @@ -391,6 +391,34 @@ struct net_device *alloc_etherdev_mqs(int sizeof_priv, unsigned int txqs, } EXPORT_SYMBOL(alloc_etherdev_mqs); +static void devm_free_netdev(struct device *dev, void *res) +{ + free_netdev(*(struct net_device **)res); +} + +struct net_device *devm_alloc_etherdev_mqs(struct device *dev, int sizeof_priv, + unsigned int txqs, unsigned int rxqs) +{ + struct net_device **dr; + struct net_device *netdev; + + dr = devres_alloc(devm_free_netdev, sizeof(*dr), GFP_KERNEL); + if (!dr) + return NULL; + + netdev = alloc_etherdev_mqs(sizeof_priv, txqs, rxqs); + if (!netdev) { + devres_free(dr); + return NULL; + } + + *dr = netdev; + devres_add(dev, dr); + + return netdev; +} +EXPORT_SYMBOL(devm_alloc_etherdev_mqs); + ssize_t sysfs_format_mac(char *buf, const unsigned char *addr, int len) { return scnprintf(buf, PAGE_SIZE, "%*phC\n", len, addr);