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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 01/16] tcg/s390x: Rename from tcg/s390 Date: Sun, 7 Feb 2021 18:50:46 -0800 Message-Id: <20210208025101.271726-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208025101.271726-1-richard.henderson@linaro.org> References: <20210208025101.271726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This emphasizes that we don't support s390, only 64-bit s390x hosts. Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- meson.build | 2 -- tcg/{s390 => s390x}/tcg-target-con-set.h | 0 tcg/{s390 => s390x}/tcg-target-con-str.h | 0 tcg/{s390 => s390x}/tcg-target.h | 0 tcg/{s390 => s390x}/tcg-target.c.inc | 0 5 files changed, 2 deletions(-) rename tcg/{s390 => s390x}/tcg-target-con-set.h (100%) rename tcg/{s390 => s390x}/tcg-target-con-str.h (100%) rename tcg/{s390 => s390x}/tcg-target.h (100%) rename tcg/{s390 => s390x}/tcg-target.c.inc (100%) -- 2.25.1 diff --git a/meson.build b/meson.build index 2d8b433ff0..d6ddf88b00 100644 --- a/meson.build +++ b/meson.build @@ -233,8 +233,6 @@ if not get_option('tcg').disabled() tcg_arch = 'tci' elif config_host['ARCH'] == 'sparc64' tcg_arch = 'sparc' - elif config_host['ARCH'] == 's390x' - tcg_arch = 's390' elif config_host['ARCH'] in ['x86_64', 'x32'] tcg_arch = 'i386' elif config_host['ARCH'] == 'ppc64' diff --git a/tcg/s390/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h similarity index 100% rename from tcg/s390/tcg-target-con-set.h rename to tcg/s390x/tcg-target-con-set.h diff --git a/tcg/s390/tcg-target-con-str.h b/tcg/s390x/tcg-target-con-str.h similarity index 100% rename from tcg/s390/tcg-target-con-str.h rename to tcg/s390x/tcg-target-con-str.h diff --git a/tcg/s390/tcg-target.h b/tcg/s390x/tcg-target.h similarity index 100% rename from tcg/s390/tcg-target.h rename to tcg/s390x/tcg-target.h diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc similarity index 100% rename from tcg/s390/tcg-target.c.inc rename to tcg/s390x/tcg-target.c.inc From patchwork Mon Feb 8 02:50:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 378526 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp4350973jah; Sun, 7 Feb 2021 20:07:08 -0800 (PST) X-Google-Smtp-Source: ABdhPJwsbdy3tZqt+XFs4p4X6eEpYuf/3s0FNs82XqgQ3B0ewRjlFWhDe1Hs6HdvHgkQd9bunGgu X-Received: by 2002:a25:83d0:: with SMTP id v16mr24806856ybm.40.1612757228798; Sun, 07 Feb 2021 20:07:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612757228; cv=none; d=google.com; s=arc-20160816; b=t0MBP5Eost1OGvSusr0BLhb409aUz/DUL+J+I8QFx0ZUdl+biB+K+ac7f1BwVWFyUx NbO042ZSzZr1FdP0FoO5niLOmokULadLmaTGMbo5q9G3nA3yCxf7wsgGPVK0oV1rdtez 1weg6mmqtw/FQxtGWDQK8vtzAnh+/zWITQ1Vk5h/b3HUl7Af76fy+a+qaIYpGQ1Cyinh fyJTPX5S03/F8fgmXkCOrsAL/l8eR/0JOTuqIdoDsXSLxbu1s85QXqltA8njl4+yZB6o VyWhlJJGDmckFMxuejq5JUdVUalG6mt/5PsRtRU1RXsN6Jlw7wB92EwY1k6c0jdGTD9L u/DA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mFFYC/bBe+aX80StY3T1pSBCo00lrevoIYEo9VDtg20=; b=I5aUWBg6pa3czORJtZ7vu2EjKPoQP3dueNXI2av2UrqMVJRqNZszL7RsviuiOpGYIX sQDpusDrepqY5kt64za0pNjyk5kOnMOBont3wKho4C0R9XCUWrdj82AFnuyypVKovUi2 SErtDr37+CRny7xHbcGg2C9wiVLe6YoN4FHj45/HRVl5cgHVosRBy7m6nytO45tVs0El SsqkHYASoPh7zgr9nOOsa6GvkVLN+8sN/H5qhvBhX2XbY+mrc+EmEbTOFRqJv1BH89TC boaCC7xJZsyo+7RmFI4CviMCIFARAuf8SYUlxMjncmXLnIt+t3JLRjgmq9XACJDNysX5 NxpA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=z66+h93t; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 02/16] tcg/s390x: Change FACILITY representation Date: Sun, 7 Feb 2021 18:50:47 -0800 Message-Id: <20210208025101.271726-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208025101.271726-1-richard.henderson@linaro.org> References: <20210208025101.271726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , David Hildenbrand Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will shortly need to be able to check facilities beyond the first 64. Instead of explicitly masking against s390_facilities, create a HAVE_FACILITY macro that indexes an array. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- v2: Change name to HAVE_FACILITY (david) --- tcg/s390x/tcg-target.h | 29 ++++++++------- tcg/s390x/tcg-target.c.inc | 74 +++++++++++++++++++------------------- 2 files changed, 52 insertions(+), 51 deletions(-) -- 2.25.1 diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 641464eea4..c612d24803 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -52,16 +52,19 @@ typedef enum TCGReg { /* A list of relevant facilities used by this translator. Some of these are required for proper operation, and these are checked at startup. */ -#define FACILITY_ZARCH_ACTIVE (1ULL << (63 - 2)) -#define FACILITY_LONG_DISP (1ULL << (63 - 18)) -#define FACILITY_EXT_IMM (1ULL << (63 - 21)) -#define FACILITY_GEN_INST_EXT (1ULL << (63 - 34)) -#define FACILITY_LOAD_ON_COND (1ULL << (63 - 45)) +#define FACILITY_ZARCH_ACTIVE 2 +#define FACILITY_LONG_DISP 18 +#define FACILITY_EXT_IMM 21 +#define FACILITY_GEN_INST_EXT 34 +#define FACILITY_LOAD_ON_COND 45 #define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND #define FACILITY_DISTINCT_OPS FACILITY_LOAD_ON_COND -#define FACILITY_LOAD_ON_COND2 (1ULL << (63 - 53)) +#define FACILITY_LOAD_ON_COND2 53 -extern uint64_t s390_facilities; +extern uint64_t s390_facilities[1]; + +#define HAVE_FACILITY(X) \ + ((s390_facilities[FACILITY_##X / 64] >> (63 - FACILITY_##X % 64)) & 1) /* optional instructions */ #define TCG_TARGET_HAS_div2_i32 1 @@ -82,8 +85,8 @@ extern uint64_t s390_facilities; #define TCG_TARGET_HAS_clz_i32 0 #define TCG_TARGET_HAS_ctz_i32 0 #define TCG_TARGET_HAS_ctpop_i32 0 -#define TCG_TARGET_HAS_deposit_i32 (s390_facilities & FACILITY_GEN_INST_EXT) -#define TCG_TARGET_HAS_extract_i32 (s390_facilities & FACILITY_GEN_INST_EXT) +#define TCG_TARGET_HAS_deposit_i32 HAVE_FACILITY(GEN_INST_EXT) +#define TCG_TARGET_HAS_extract_i32 HAVE_FACILITY(GEN_INST_EXT) #define TCG_TARGET_HAS_sextract_i32 0 #define TCG_TARGET_HAS_extract2_i32 0 #define TCG_TARGET_HAS_movcond_i32 1 @@ -96,7 +99,7 @@ extern uint64_t s390_facilities; #define TCG_TARGET_HAS_extrl_i64_i32 0 #define TCG_TARGET_HAS_extrh_i64_i32 0 #define TCG_TARGET_HAS_goto_ptr 1 -#define TCG_TARGET_HAS_direct_jump (s390_facilities & FACILITY_GEN_INST_EXT) +#define TCG_TARGET_HAS_direct_jump HAVE_FACILITY(GEN_INST_EXT) #define TCG_TARGET_HAS_qemu_st8_i32 0 #define TCG_TARGET_HAS_div2_i64 1 @@ -117,11 +120,11 @@ extern uint64_t s390_facilities; #define TCG_TARGET_HAS_eqv_i64 0 #define TCG_TARGET_HAS_nand_i64 0 #define TCG_TARGET_HAS_nor_i64 0 -#define TCG_TARGET_HAS_clz_i64 (s390_facilities & FACILITY_EXT_IMM) +#define TCG_TARGET_HAS_clz_i64 HAVE_FACILITY(EXT_IMM) #define TCG_TARGET_HAS_ctz_i64 0 #define TCG_TARGET_HAS_ctpop_i64 0 -#define TCG_TARGET_HAS_deposit_i64 (s390_facilities & FACILITY_GEN_INST_EXT) -#define TCG_TARGET_HAS_extract_i64 (s390_facilities & FACILITY_GEN_INST_EXT) +#define TCG_TARGET_HAS_deposit_i64 HAVE_FACILITY(GEN_INST_EXT) +#define TCG_TARGET_HAS_extract_i64 HAVE_FACILITY(GEN_INST_EXT) #define TCG_TARGET_HAS_sextract_i64 0 #define TCG_TARGET_HAS_extract2_i64 0 #define TCG_TARGET_HAS_movcond_i64 1 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 695d7ee652..3b632d8b24 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -66,7 +66,7 @@ We don't need this when we have pc-relative loads with the general instructions extension facility. */ #define TCG_REG_TB TCG_REG_R12 -#define USE_REG_TB (!(s390_facilities & FACILITY_GEN_INST_EXT)) +#define USE_REG_TB (!HAVE_FACILITY(GEN_INST_EXT)) #ifndef CONFIG_SOFTMMU #define TCG_GUEST_BASE_REG TCG_REG_R13 @@ -377,7 +377,7 @@ static void * const qemu_st_helpers[16] = { #endif static const tcg_insn_unit *tb_ret_addr; -uint64_t s390_facilities; +uint64_t s390_facilities[1]; static bool patch_reloc(tcg_insn_unit *src_rw, int type, intptr_t value, intptr_t addend) @@ -580,7 +580,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, } /* Try all 48-bit insns that can load it in one go. */ - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { if (sval == (int32_t)sval) { tcg_out_insn(s, RIL, LGFI, ret, sval); return; @@ -623,7 +623,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, } /* Otherwise, stuff it in the constant pool. */ - if (s390_facilities & FACILITY_GEN_INST_EXT) { + if (HAVE_FACILITY(GEN_INST_EXT)) { tcg_out_insn(s, RIL, LGRL, ret, 0); new_pool_label(s, sval, R_390_PC32DBL, s->code_ptr - 2, 2); } else if (USE_REG_TB && !in_prologue) { @@ -709,7 +709,7 @@ static void tcg_out_ld_abs(TCGContext *s, TCGType type, { intptr_t addr = (intptr_t)abs; - if ((s390_facilities & FACILITY_GEN_INST_EXT) && !(addr & 1)) { + if (HAVE_FACILITY(GEN_INST_EXT) && !(addr & 1)) { ptrdiff_t disp = tcg_pcrel_diff(s, abs) >> 1; if (disp == (int32_t)disp) { if (type == TCG_TYPE_I32) { @@ -743,7 +743,7 @@ static inline void tcg_out_risbg(TCGContext *s, TCGReg dest, TCGReg src, static void tgen_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) { - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { tcg_out_insn(s, RRE, LGBR, dest, src); return; } @@ -763,7 +763,7 @@ static void tgen_ext8s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) static void tgen_ext8u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) { - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { tcg_out_insn(s, RRE, LLGCR, dest, src); return; } @@ -783,7 +783,7 @@ static void tgen_ext8u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) static void tgen_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) { - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { tcg_out_insn(s, RRE, LGHR, dest, src); return; } @@ -803,7 +803,7 @@ static void tgen_ext16s(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) static void tgen_ext16u(TCGContext *s, TCGType type, TCGReg dest, TCGReg src) { - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { tcg_out_insn(s, RRE, LLGHR, dest, src); return; } @@ -891,7 +891,7 @@ static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) tgen_ext32u(s, dest, dest); return; } - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { if ((val & valid) == 0xff) { tgen_ext8u(s, TCG_TYPE_I64, dest, dest); return; @@ -912,7 +912,7 @@ static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) } /* Try all 48-bit insns that can perform it in one go. */ - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { for (i = 0; i < 2; i++) { tcg_target_ulong mask = ~(0xffffffffull << i*32); if (((val | ~valid) & mask) == mask) { @@ -921,7 +921,7 @@ static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) } } } - if ((s390_facilities & FACILITY_GEN_INST_EXT) && risbg_mask(val)) { + if (HAVE_FACILITY(GEN_INST_EXT) && risbg_mask(val)) { tgen_andi_risbg(s, dest, dest, val); return; } @@ -970,7 +970,7 @@ static void tgen_ori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) } /* Try all 48-bit insns that can perform it in one go. */ - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { for (i = 0; i < 2; i++) { tcg_target_ulong mask = (0xffffffffull << i*32); if ((val & mask) != 0 && (val & ~mask) == 0) { @@ -995,7 +995,7 @@ static void tgen_ori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) /* Perform the OR via sequential modifications to the high and low parts. Do this via recursion to handle 16-bit vs 32-bit masks in each half. */ - tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM); + tcg_debug_assert(HAVE_FACILITY(EXT_IMM)); tgen_ori(s, type, dest, val & 0x00000000ffffffffull); tgen_ori(s, type, dest, val & 0xffffffff00000000ull); } @@ -1004,7 +1004,7 @@ static void tgen_ori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) static void tgen_xori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) { /* Try all 48-bit insns that can perform it in one go. */ - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { if ((val & 0xffffffff00000000ull) == 0) { tcg_out_insn(s, RIL, XILF, dest, val); return; @@ -1028,7 +1028,7 @@ static void tgen_xori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) tcg_tbrel_diff(s, NULL)); } else { /* Perform the xor by parts. */ - tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM); + tcg_debug_assert(HAVE_FACILITY(EXT_IMM)); if (val & 0xffffffff) { tcg_out_insn(s, RIL, XILF, dest, val); } @@ -1062,7 +1062,7 @@ static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, goto exit; } - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { if (type == TCG_TYPE_I32) { op = (is_unsigned ? RIL_CLFI : RIL_CFI); tcg_out_insn_RIL(s, op, r1, c2); @@ -1125,7 +1125,7 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, bool have_loc; /* With LOC2, we can always emit the minimum 3 insns. */ - if (s390_facilities & FACILITY_LOAD_ON_COND2) { + if (HAVE_FACILITY(LOAD_ON_COND2)) { /* Emit: d = 0, d = (cc ? 1 : d). */ cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); tcg_out_movi(s, TCG_TYPE_I64, dest, 0); @@ -1133,7 +1133,7 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, return; } - have_loc = (s390_facilities & FACILITY_LOAD_ON_COND) != 0; + have_loc = HAVE_FACILITY(LOAD_ON_COND); /* For HAVE_LOC, only the paths through GTU/GT/LEU/LE are smaller. */ restart: @@ -1219,7 +1219,7 @@ static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest, TCGArg v3, int v3const) { int cc; - if (s390_facilities & FACILITY_LOAD_ON_COND) { + if (HAVE_FACILITY(LOAD_ON_COND)) { cc = tgen_cmp(s, type, c, c1, c2, c2const, false); if (v3const) { tcg_out_insn(s, RIE, LOCGHI, dest, v3, cc); @@ -1252,7 +1252,7 @@ static void tgen_clz(TCGContext *s, TCGReg dest, TCGReg a1, } else { tcg_out_mov(s, TCG_TYPE_I64, dest, a2); } - if (s390_facilities & FACILITY_LOAD_ON_COND) { + if (HAVE_FACILITY(LOAD_ON_COND)) { /* Emit: if (one bit found) dest = r0. */ tcg_out_insn(s, RRF, LOCGR, dest, TCG_REG_R0, 2); } else { @@ -1328,7 +1328,7 @@ static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c, { int cc; - if (s390_facilities & FACILITY_GEN_INST_EXT) { + if (HAVE_FACILITY(GEN_INST_EXT)) { bool is_unsigned = is_unsigned_cond(c); bool in_range; S390Opcode opc; @@ -1522,7 +1522,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc, cross pages using the address of the last byte of the access. */ a_off = (a_bits >= s_bits ? 0 : s_mask - a_mask); tlb_mask = (uint64_t)TARGET_PAGE_MASK | a_mask; - if ((s390_facilities & FACILITY_GEN_INST_EXT) && a_off == 0) { + if (HAVE_FACILITY(GEN_INST_EXT) && a_off == 0) { tgen_andi_risbg(s, TCG_REG_R3, addr_reg, tlb_mask); } else { tcg_out_insn(s, RX, LA, TCG_REG_R3, addr_reg, TCG_REG_NONE, a_off); @@ -1812,7 +1812,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_insn(s, RI, AHI, a0, a2); break; } - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { tcg_out_insn(s, RIL, AFI, a0, a2); break; } @@ -2036,7 +2036,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_insn(s, RI, AGHI, a0, a2); break; } - if (s390_facilities & FACILITY_EXT_IMM) { + if (HAVE_FACILITY(EXT_IMM)) { if (a2 == (int32_t)a2) { tcg_out_insn(s, RIL, AGFI, a0, a2); break; @@ -2261,8 +2261,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, /* The host memory model is quite strong, we simply need to serialize the instruction stream. */ if (args[0] & TCG_MO_ST_LD) { - tcg_out_insn(s, RR, BCR, - s390_facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0); + tcg_out_insn(s, RR, BCR, HAVE_FACILITY(FAST_BCR_SER) ? 14 : 15, 0); } break; @@ -2325,7 +2324,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_or_i64: case INDEX_op_xor_i32: case INDEX_op_xor_i64: - return (s390_facilities & FACILITY_DISTINCT_OPS + return (HAVE_FACILITY(DISTINCT_OPS) ? C_O1_I2(r, r, ri) : C_O1_I2(r, 0, ri)); @@ -2333,19 +2332,19 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) /* If we have the general-instruction-extensions, then we have MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */ - return (s390_facilities & FACILITY_GEN_INST_EXT + return (HAVE_FACILITY(GEN_INST_EXT) ? C_O1_I2(r, 0, ri) : C_O1_I2(r, 0, rI)); case INDEX_op_mul_i64: - return (s390_facilities & FACILITY_GEN_INST_EXT + return (HAVE_FACILITY(GEN_INST_EXT) ? C_O1_I2(r, 0, rJ) : C_O1_I2(r, 0, rI)); case INDEX_op_shl_i32: case INDEX_op_shr_i32: case INDEX_op_sar_i32: - return (s390_facilities & FACILITY_DISTINCT_OPS + return (HAVE_FACILITY(DISTINCT_OPS) ? C_O1_I2(r, r, ri) : C_O1_I2(r, 0, ri)); @@ -2389,7 +2388,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: - return (s390_facilities & FACILITY_LOAD_ON_COND2 + return (HAVE_FACILITY(LOAD_ON_COND2) ? C_O1_I4(r, r, ri, rI, 0) : C_O1_I4(r, r, ri, r, 0)); @@ -2404,13 +2403,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_add2_i32: case INDEX_op_sub2_i32: - return (s390_facilities & FACILITY_EXT_IMM + return (HAVE_FACILITY(EXT_IMM) ? C_O2_I4(r, r, 0, 1, ri, r) : C_O2_I4(r, r, 0, 1, r, r)); case INDEX_op_add2_i64: case INDEX_op_sub2_i64: - return (s390_facilities & FACILITY_EXT_IMM + return (HAVE_FACILITY(EXT_IMM) ? C_O2_I4(r, r, 0, 1, rA, r) : C_O2_I4(r, r, 0, 1, r, r)); @@ -2426,13 +2425,12 @@ static void query_s390_facilities(void) /* Is STORE FACILITY LIST EXTENDED available? Honestly, I believe this is present on all 64-bit systems, but let's check for it anyway. */ if (hwcap & HWCAP_S390_STFLE) { - register int r0 __asm__("0"); - register void *r1 __asm__("1"); + register int r0 __asm__("0") = ARRAY_SIZE(s390_facilities) - 1; + register void *r1 __asm__("1") = s390_facilities; /* stfle 0(%r1) */ - r1 = &s390_facilities; asm volatile(".word 0xb2b0,0x1000" - : "=r"(r0) : "0"(0), "r"(r1) : "memory", "cc"); + : "=r"(r0) : "r"(r0), "r"(r1) : "memory", "cc"); } } From patchwork Mon Feb 8 02:50:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 378501 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp4336877jah; Sun, 7 Feb 2021 19:38:54 -0800 (PST) X-Google-Smtp-Source: ABdhPJyMMtiay1MYHc+Ebm2g0hWCMGENVfBx03mbe9+CVnh/D0xzs/vwl8LF4jtcD2cY0LGuSy4G X-Received: by 2002:a25:bec6:: with SMTP id k6mr22881948ybm.420.1612755534049; Sun, 07 Feb 2021 19:38:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612755534; cv=none; d=google.com; s=arc-20160816; b=jycN8gwWPEEJQ28fTchSbzlh1jAuZwMIhauiNdbPk1/pG/w//j2oXNYdBi8LtRTtlr /B6HonCdMlXkRV7PQw6/R0wGCn+LsAcl7HFpLxnefuLyVAj1fceiqRh7xJ0F/5VD81q+ cuV5+lXo9IYzJPti0mFRGcBoxkQEd/+GuAWD8cFgsCg4abavAEbWp1PBhtJGCuNNB8W5 yCr+LpjLyDNoA6iKqANucPHH9JdGc0++eygYk0vM7Q699fS9ASSE3PB3SYur9LC2CpWv XTa8EhJFWAv2H9e2P/NgkFOEYI6B1MJOAI/k0a69kUZHdcfND5k02+Te5DHwpjN9tgsq Z42Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=SRq7hg6Vj1nHDtcJzgW8chIU3xuJIIPY1S3vOosE/88=; b=ptWopEVKE/ERCiLEjFtU+Ne7bDnjVtaSQtAVenAF3snUJ8OsjWSPYBcMtqDA7gchQX w4dtVsWPz4OVepn/6pYVQotpEhEHzQWL1RvUuV8vKAOR0olS1TnNnZAUNiohEuVUSwrd dyGjF0+A5bjTQIHwub9jUT7oIaJubFGxYeV4VNS/LoCUFT3JqvikUy78sftF4PqFqRyx VJhS9sy0QrCMU+ayg3e4/whrme9ZsjO++2VcftuhDMPj2jJ/Ek+hxtD5CzZz3ZZJzYek WB29lSOiJC7GeX46htK14dsv6GVDNrtB/IS8smL76StqCvTaxm9KRSuMX+j/SAV59qaq OKOw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eaHP7OIB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 03/16] tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGReg Date: Sun, 7 Feb 2021 18:50:48 -0800 Message-Id: <20210208025101.271726-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208025101.271726-1-richard.henderson@linaro.org> References: <20210208025101.271726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , David Hildenbrand Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" They are rightly values in the same enumeration. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 28 +++++++--------------------- 1 file changed, 7 insertions(+), 21 deletions(-) -- 2.25.1 diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index c612d24803..3a701d9256 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -29,22 +29,13 @@ #define TCG_TARGET_TLB_DISPLACEMENT_BITS 19 typedef enum TCGReg { - TCG_REG_R0 = 0, - TCG_REG_R1, - TCG_REG_R2, - TCG_REG_R3, - TCG_REG_R4, - TCG_REG_R5, - TCG_REG_R6, - TCG_REG_R7, - TCG_REG_R8, - TCG_REG_R9, - TCG_REG_R10, - TCG_REG_R11, - TCG_REG_R12, - TCG_REG_R13, - TCG_REG_R14, - TCG_REG_R15 + TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3, + TCG_REG_R4, TCG_REG_R5, TCG_REG_R6, TCG_REG_R7, + TCG_REG_R8, TCG_REG_R9, TCG_REG_R10, TCG_REG_R11, + TCG_REG_R12, TCG_REG_R13, TCG_REG_R14, TCG_REG_R15, + + TCG_AREG0 = TCG_REG_R10, + TCG_REG_CALL_STACK = TCG_REG_R15 } TCGReg; #define TCG_TARGET_NB_REGS 16 @@ -136,7 +127,6 @@ extern uint64_t s390_facilities[1]; #define TCG_TARGET_HAS_mulsh_i64 0 /* used for function call generation */ -#define TCG_REG_CALL_STACK TCG_REG_R15 #define TCG_TARGET_STACK_ALIGN 8 #define TCG_TARGET_CALL_STACK_OFFSET 160 @@ -145,10 +135,6 @@ extern uint64_t s390_facilities[1]; #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) -enum { - TCG_AREG0 = TCG_REG_R10, -}; - static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, uintptr_t jmp_rw, uintptr_t addr) { From patchwork Mon Feb 8 02:50:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 378527 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp4351712jah; Sun, 7 Feb 2021 20:08:31 -0800 (PST) X-Google-Smtp-Source: ABdhPJy5VMxGdEM2YVKDbP0O5OKFQQKigcDQwZOfQmwHShQKwDym18euJhGbHSXXgOWmOlakfWlO X-Received: by 2002:a25:b992:: with SMTP id r18mr22942491ybg.86.1612757311718; Sun, 07 Feb 2021 20:08:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612757311; cv=none; d=google.com; s=arc-20160816; b=YEUiSJNjFBNyEttWh8oOjMJ74e1tvfyuT7VMbqn+lHElWhwfp8duIL217+SxpziwL6 Hom1f6ng0Xy7RfDeI8/KU6Duu2Xfl/2JZn1DTEwyxRlw0J5Mzmq1R69F3ZlEDlOTDQVY JoiTBDs++sZa3M0sYs/9mInI4NBCtZCIOwHsNB9/06A9BZkOr86ipmLqoPfG0wljyBKr oJz/MYxzIIBowcIuA/I76z7o12pDMN3vdPGu2qHAQm6Oh/SAko0zNu4hn3ROJt83KwYS L+GJ9KJ+L8os8WY9A6C+3+4F5B+/TOxHYK78jNp0vspExuN3u5XXPIEX3QeJwxtUC5hJ geZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1ZP9rcz+bqyMzUuxz4tto926+fSJHcTzu1HPZk7aj5Q=; b=Og6Ex5mqCkYouBAypwx+faO+rS1bCB72+iAPvvBd8s/0hzak1x0TSQI54h44Pe018N 8OU7iqJ4RTfS9/cIFbtIFHLwCKdXgxxB7y6fErTLl4FwjGmVbZATofqFG4Ne8naa79Vm 0YOjpR5ME3waxRww4T0Tb4CcJerOhfC8DL2BLbbsmUsiSmII6ybTVnzbB1Q4EnV+BMUT Yd1Bykr4Jkt1gAzWzgpYVnDlD67hpuoH+Ip4SYSa1bop+FhywBiNXhRbhgfto2PcasEj FGuOYyOnBtFz//ThsFDHclrZ6Gxk3RmDuZsTnMjEVFUyZJ3G15Wy7vVVHYMxxusaUgwF 6CgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qFQIsHnX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 04/16] tcg/s390x: Add host vector framework Date: Sun, 7 Feb 2021 18:50:49 -0800 Message-Id: <20210208025101.271726-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208025101.271726-1-richard.henderson@linaro.org> References: <20210208025101.271726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add registers and function stubs. The functionality is disabled via squashing s390_facilities[2] to 0. We must still include results for the mandatory opcodes in tcg_target_op_def, as all opcodes are checked during tcg init. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 4 + tcg/s390x/tcg-target-con-str.h | 1 + tcg/s390x/tcg-target.h | 35 ++++++++- tcg/s390x/tcg-target.opc.h | 12 +++ tcg/s390x/tcg-target.c.inc | 137 ++++++++++++++++++++++++++++++++- 5 files changed, 184 insertions(+), 5 deletions(-) create mode 100644 tcg/s390x/tcg-target.opc.h -- 2.25.1 diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index 31985e4903..ce9432cfe3 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -13,13 +13,17 @@ C_O0_I1(r) C_O0_I2(L, L) C_O0_I2(r, r) C_O0_I2(r, ri) +C_O0_I2(v, r) C_O1_I1(r, L) C_O1_I1(r, r) +C_O1_I1(v, r) +C_O1_I1(v, vr) C_O1_I2(r, 0, ri) C_O1_I2(r, 0, rI) C_O1_I2(r, 0, rJ) C_O1_I2(r, r, ri) C_O1_I2(r, rZ, r) +C_O1_I2(v, v, v) C_O1_I4(r, r, ri, r, 0) C_O1_I4(r, r, ri, rI, 0) C_O2_I2(b, a, 0, r) diff --git a/tcg/s390x/tcg-target-con-str.h b/tcg/s390x/tcg-target-con-str.h index 892d8f8c06..8bb0358ae5 100644 --- a/tcg/s390x/tcg-target-con-str.h +++ b/tcg/s390x/tcg-target-con-str.h @@ -10,6 +10,7 @@ */ REGS('r', ALL_GENERAL_REGS) REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) +REGS('v', ALL_VECTOR_REGS) /* * A (single) even/odd pair for division. * TODO: Add something to the register allocator to allow diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 3a701d9256..e8659bf576 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -34,11 +34,20 @@ typedef enum TCGReg { TCG_REG_R8, TCG_REG_R9, TCG_REG_R10, TCG_REG_R11, TCG_REG_R12, TCG_REG_R13, TCG_REG_R14, TCG_REG_R15, + TCG_REG_V0 = 32, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3, + TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7, + TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11, + TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15, + TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19, + TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23, + TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27, + TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31, + TCG_AREG0 = TCG_REG_R10, TCG_REG_CALL_STACK = TCG_REG_R15 } TCGReg; -#define TCG_TARGET_NB_REGS 16 +#define TCG_TARGET_NB_REGS 64 /* A list of relevant facilities used by this translator. Some of these are required for proper operation, and these are checked at startup. */ @@ -51,8 +60,9 @@ typedef enum TCGReg { #define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND #define FACILITY_DISTINCT_OPS FACILITY_LOAD_ON_COND #define FACILITY_LOAD_ON_COND2 53 +#define FACILITY_VECTOR 129 -extern uint64_t s390_facilities[1]; +extern uint64_t s390_facilities[3]; #define HAVE_FACILITY(X) \ ((s390_facilities[FACILITY_##X / 64] >> (63 - FACILITY_##X % 64)) & 1) @@ -126,6 +136,27 @@ extern uint64_t s390_facilities[1]; #define TCG_TARGET_HAS_muluh_i64 0 #define TCG_TARGET_HAS_mulsh_i64 0 +#define TCG_TARGET_HAS_v64 HAVE_FACILITY(VECTOR) +#define TCG_TARGET_HAS_v128 HAVE_FACILITY(VECTOR) +#define TCG_TARGET_HAS_v256 0 + +#define TCG_TARGET_HAS_andc_vec 0 +#define TCG_TARGET_HAS_orc_vec 0 +#define TCG_TARGET_HAS_not_vec 0 +#define TCG_TARGET_HAS_neg_vec 0 +#define TCG_TARGET_HAS_abs_vec 0 +#define TCG_TARGET_HAS_roti_vec 0 +#define TCG_TARGET_HAS_rots_vec 0 +#define TCG_TARGET_HAS_rotv_vec 0 +#define TCG_TARGET_HAS_shi_vec 0 +#define TCG_TARGET_HAS_shs_vec 0 +#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_mul_vec 0 +#define TCG_TARGET_HAS_sat_vec 0 +#define TCG_TARGET_HAS_minmax_vec 0 +#define TCG_TARGET_HAS_bitsel_vec 0 +#define TCG_TARGET_HAS_cmpsel_vec 0 + /* used for function call generation */ #define TCG_TARGET_STACK_ALIGN 8 #define TCG_TARGET_CALL_STACK_OFFSET 160 diff --git a/tcg/s390x/tcg-target.opc.h b/tcg/s390x/tcg-target.opc.h new file mode 100644 index 0000000000..67afc82a93 --- /dev/null +++ b/tcg/s390x/tcg-target.opc.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2021 Linaro + * + * This work is licensed under the terms of the GNU GPL, version 2 or + * (at your option) any later version. + * + * See the COPYING file in the top-level directory for details. + * + * Target-specific opcodes for host vector expansion. These will be + * emitted by tcg_expand_vec_op. For those familiar with GCC internals, + * consider these to be UNSPEC with names. + */ diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 3b632d8b24..4656efea83 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -43,6 +43,8 @@ #define TCG_CT_CONST_ZERO 0x800 #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 16) +#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) + /* * For softmmu, we need to avoid conflicts with the first 3 * argument registers to perform the tlb lookup, and to call @@ -268,8 +270,13 @@ typedef enum S390Opcode { #ifdef CONFIG_DEBUG_TCG static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { - "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", - "%r8", "%r9", "%r10" "%r11" "%r12" "%r13" "%r14" "%r15" + "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", + "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", + "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", + "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", + "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", }; #endif @@ -295,6 +302,32 @@ static const int tcg_target_reg_alloc_order[] = { TCG_REG_R4, TCG_REG_R3, TCG_REG_R2, + + /* V8-V15 are call saved, and omitted. */ + TCG_REG_V0, + TCG_REG_V1, + TCG_REG_V2, + TCG_REG_V3, + TCG_REG_V4, + TCG_REG_V5, + TCG_REG_V6, + TCG_REG_V7, + TCG_REG_V16, + TCG_REG_V17, + TCG_REG_V18, + TCG_REG_V19, + TCG_REG_V20, + TCG_REG_V21, + TCG_REG_V22, + TCG_REG_V23, + TCG_REG_V24, + TCG_REG_V25, + TCG_REG_V26, + TCG_REG_V27, + TCG_REG_V28, + TCG_REG_V29, + TCG_REG_V30, + TCG_REG_V31, }; static const int tcg_target_call_iarg_regs[] = { @@ -377,7 +410,7 @@ static void * const qemu_st_helpers[16] = { #endif static const tcg_insn_unit *tb_ret_addr; -uint64_t s390_facilities[1]; +uint64_t s390_facilities[3]; static bool patch_reloc(tcg_insn_unit *src_rw, int type, intptr_t value, intptr_t addend) @@ -2273,6 +2306,42 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } } +static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg dst, TCGReg src) +{ + g_assert_not_reached(); +} + +static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg dst, TCGReg base, intptr_t offset) +{ + g_assert_not_reached(); +} + +static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg dst, int64_t val) +{ + g_assert_not_reached(); +} + +static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, + unsigned vecl, unsigned vece, + const TCGArg *args, const int *const_args) +{ + g_assert_not_reached(); +} + +int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) +{ + return 0; +} + +void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, + TCGArg a0, ...) +{ + g_assert_not_reached(); +} + static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) { switch (op) { @@ -2413,11 +2482,34 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) ? C_O2_I4(r, r, 0, 1, rA, r) : C_O2_I4(r, r, 0, 1, r, r)); + case INDEX_op_st_vec: + return C_O0_I2(v, r); + case INDEX_op_ld_vec: + case INDEX_op_dupm_vec: + return C_O1_I1(v, r); + case INDEX_op_dup_vec: + return C_O1_I1(v, vr); + case INDEX_op_add_vec: + case INDEX_op_sub_vec: + case INDEX_op_and_vec: + case INDEX_op_or_vec: + case INDEX_op_xor_vec: + case INDEX_op_cmp_vec: + return C_O1_I2(v, v, v); + default: g_assert_not_reached(); } } +/* + * Mainline glibc added HWCAP_S390_VX before it was kernel abi. + * Some distros have fixed this up locally, others have not. + */ +#ifndef HWCAP_S390_VXRS +#define HWCAP_S390_VXRS 2048 +#endif + static void query_s390_facilities(void) { unsigned long hwcap = qemu_getauxval(AT_HWCAP); @@ -2432,6 +2524,16 @@ static void query_s390_facilities(void) asm volatile(".word 0xb2b0,0x1000" : "=r"(r0) : "r"(r0), "r"(r1) : "memory", "cc"); } + + /* + * Use of vector registers requires os support beyond the facility bit. + * If the kernel does not advertise support, disable the facility bits. + * There is nothing else we currently care about in the 3rd word, so + * disable VECTOR with one store. + */ + if (1 || !(hwcap & HWCAP_S390_VXRS)) { + s390_facilities[2] = 0; + } } static void tcg_target_init(TCGContext *s) @@ -2440,6 +2542,10 @@ static void tcg_target_init(TCGContext *s) tcg_target_available_regs[TCG_TYPE_I32] = 0xffff; tcg_target_available_regs[TCG_TYPE_I64] = 0xffff; + if (HAVE_FACILITY(VECTOR)) { + tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull; + tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull; + } tcg_target_call_clobber_regs = 0; tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); @@ -2454,6 +2560,31 @@ static void tcg_target_init(TCGContext *s) /* The return register can be considered call-clobbered. */ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V20); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V21); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V22); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V23); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V24); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V25); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V26); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V27); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V28); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V29); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V30); + tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V31); + s->reserved_regs = 0; tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* XXX many insns can't be used with R0, so we better avoid it for now */ From patchwork Mon Feb 8 02:50:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 378505 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp4338410jah; Sun, 7 Feb 2021 19:41:59 -0800 (PST) X-Google-Smtp-Source: ABdhPJzSwK2aP71mypZR0bB8vPXmxkQBgcq3alZQWa985kpIRdiGQnz3VkCqxcD9LSqjmsKN9T9N X-Received: by 2002:a25:b048:: with SMTP id e8mr23835440ybj.0.1612755719434; Sun, 07 Feb 2021 19:41:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612755719; cv=none; d=google.com; s=arc-20160816; b=b89ReVvhLzPCQ+MpyA33DAOfzLt6GmMIJwXymDMo565OtpvsXm2yKRP4QgYO5r8UkW JzClojaAV6oItquVV1WNr4sjqoTG22oqDJJ7Y1Bw0PJk/AyByjU1pMK9BDYaa/EcpjjL WcvKgfZdIxydjG1DDi82kiD5ztmzbyoREgsnUH4oObbYsEM9NO0+nWWteojtbOPpUCKF SK7Wd2+XcjmdkL3HKcu+GZsC5l6G/f2LywLtyriyb8e9QTlvpAAqTyD2PIWBEbk2oW3C IZu+FnE4ipBR77XcMceilgT34SnOqpJEDbJP3BrgDfnwHNyqddnbqRxeLhLBo0TbxwnM qPqQ== ARC-Message-Signature: i=1; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 05/16] tcg/s390x: Implement tcg_out_ld/st for vector types Date: Sun, 7 Feb 2021 18:50:50 -0800 Message-Id: <20210208025101.271726-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208025101.271726-1-richard.henderson@linaro.org> References: <20210208025101.271726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 117 +++++++++++++++++++++++++++++++++---- 1 file changed, 105 insertions(+), 12 deletions(-) -- 2.25.1 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 4656efea83..df10ee0feb 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -265,6 +265,12 @@ typedef enum S390Opcode { RX_STC = 0x42, RX_STH = 0x40, + VRX_VL = 0xe706, + VRX_VLLEZ = 0xe704, + VRX_VST = 0xe70e, + VRX_VSTEF = 0xe70b, + VRX_VSTEG = 0xe70a, + NOP = 0x0707, } S390Opcode; @@ -532,6 +538,26 @@ static void tcg_out_insn_RSY(TCGContext *s, S390Opcode op, TCGReg r1, #define tcg_out_insn_RX tcg_out_insn_RS #define tcg_out_insn_RXY tcg_out_insn_RSY +static int RXB(TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4) +{ + return ((v1 & 16) << (7 - 3)) + | ((v2 & 16) << (6 - 3)) + | ((v3 & 16) << (5 - 3)) + | ((v4 & 16) << (4 - 3)); +} + +static void tcg_out_insn_VRX(TCGContext *s, S390Opcode op, TCGReg v1, + TCGReg b2, TCGReg x2, intptr_t d2, int m3) +{ + tcg_debug_assert(v1 >= TCG_REG_V0 && v1 <= TCG_REG_V31); + tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); + tcg_debug_assert(x2 <= TCG_REG_R15); + tcg_debug_assert(b2 <= TCG_REG_R15); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | x2); + tcg_out16(s, (b2 << 12) | d2); + tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12)); +} + /* Emit an opcode with "type-checking" of the format. */ #define tcg_out_insn(S, FMT, OP, ...) \ glue(tcg_out_insn_,FMT)(S, glue(glue(FMT,_),OP), ## __VA_ARGS__) @@ -708,25 +734,92 @@ static void tcg_out_mem(TCGContext *s, S390Opcode opc_rx, S390Opcode opc_rxy, } } +static void tcg_out_vrx_mem(TCGContext *s, S390Opcode opc_vrx, + TCGReg data, TCGReg base, TCGReg index, + tcg_target_long ofs, int m3) +{ + if (ofs < 0 || ofs >= 0x1000) { + if (ofs >= -0x80000 && ofs < 0x80000) { + tcg_out_insn(s, RXY, LAY, TCG_TMP0, base, index, ofs); + base = TCG_TMP0; + index = TCG_REG_NONE; + ofs = 0; + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs); + if (index != TCG_REG_NONE) { + tcg_out_insn(s, RRE, AGR, TCG_TMP0, index); + } + index = TCG_TMP0; + ofs = 0; + } + } + tcg_out_insn_VRX(s, opc_vrx, data, base, index, ofs, m3); +} /* load data without address translation or endianness conversion */ -static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data, - TCGReg base, intptr_t ofs) +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg data, + TCGReg base, intptr_t ofs) { - if (type == TCG_TYPE_I32) { - tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs); - } else { - tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs); + switch (type) { + case TCG_TYPE_I32: + if (likely(data < 16)) { + tcg_out_mem(s, RX_L, RXY_LY, data, base, TCG_REG_NONE, ofs); + break; + } + tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_32); + break; + + case TCG_TYPE_I64: + if (likely(data < 16)) { + tcg_out_mem(s, 0, RXY_LG, data, base, TCG_REG_NONE, ofs); + break; + } + /* fallthru */ + + case TCG_TYPE_V64: + tcg_out_vrx_mem(s, VRX_VLLEZ, data, base, TCG_REG_NONE, ofs, MO_64); + break; + + case TCG_TYPE_V128: + /* Hint quadword aligned. */ + tcg_out_vrx_mem(s, VRX_VL, data, base, TCG_REG_NONE, ofs, 4); + break; + + default: + g_assert_not_reached(); } } -static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg data, - TCGReg base, intptr_t ofs) +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg data, + TCGReg base, intptr_t ofs) { - if (type == TCG_TYPE_I32) { - tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs); - } else { - tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs); + switch (type) { + case TCG_TYPE_I32: + if (likely(data < 16)) { + tcg_out_mem(s, RX_ST, RXY_STY, data, base, TCG_REG_NONE, ofs); + } else { + tcg_out_vrx_mem(s, VRX_VSTEF, data, base, TCG_REG_NONE, ofs, 1); + } + break; + + case TCG_TYPE_I64: + if (likely(data < 16)) { + tcg_out_mem(s, 0, RXY_STG, data, base, TCG_REG_NONE, ofs); + break; + } + /* fallthru */ + + case TCG_TYPE_V64: + tcg_out_vrx_mem(s, VRX_VSTEG, data, base, TCG_REG_NONE, ofs, 0); + break; + + case TCG_TYPE_V128: + /* Hint quadword aligned. */ + tcg_out_vrx_mem(s, VRX_VST, data, base, TCG_REG_NONE, ofs, 4); + break; + + default: + g_assert_not_reached(); } } From patchwork Mon Feb 8 02:50:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 378498 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp4335598jah; Sun, 7 Feb 2021 19:36:08 -0800 (PST) X-Google-Smtp-Source: ABdhPJyRNf2nMTIUfZPOlPFlxtxPH58Lfu+CiyV3kE/T4c8bMX9x+qo2Dnc2619B1Ev/M2Hgru1I X-Received: by 2002:a25:31c3:: with SMTP id x186mr22172061ybx.500.1612755368769; Sun, 07 Feb 2021 19:36:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612755368; cv=none; d=google.com; s=arc-20160816; b=Bn4QlLX4cZ2s7UZXFKPRKCnNImNwfzmjVHw9yVwp/oA069zZy4XRWnWlz6zMehlB2H +jE3QpSx9HwmyuLbR5FjTqgLZOBRzdMcDJ9sareM16/tOw8OxhLInc4IA0gLT798AFAZ smyhG5owLMHPu215SDl9zc2qq1Ia8WYVN9fDTOkCtCZdo9rc1IHMtCV5anfl/sbqi91Y 6WoIMKV8utuHIlMa0sYEFqTx2YK2RbROnbosztSu77+kF1GeH59pbTpWwhEho3JiM4kp t5/jRAZDj/L3P0feyUREMLJVjPrEVhsbBUYb/X4NVKvRzqSAn/8ZOHT/jFbC2nb1HtUX tzwQ== ARC-Message-Signature: i=1; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 06/16] tcg/s390x: Implement tcg_out_mov for vector types Date: Sun, 7 Feb 2021 18:50:51 -0800 Message-Id: <20210208025101.271726-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208025101.271726-1-richard.henderson@linaro.org> References: <20210208025101.271726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 72 +++++++++++++++++++++++++++++++++++--- 1 file changed, 68 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index df10ee0feb..fdf7475b2d 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -265,6 +265,11 @@ typedef enum S390Opcode { RX_STC = 0x42, RX_STH = 0x40, + VRRa_VLR = 0xe756, + + VRSb_VLVG = 0xe722, + VRSc_VLGV = 0xe721, + VRX_VL = 0xe706, VRX_VLLEZ = 0xe704, VRX_VST = 0xe70e, @@ -546,6 +551,39 @@ static int RXB(TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4) | ((v4 & 16) << (4 - 3)); } +static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op, + TCGReg v1, TCGReg v2, int m3) +{ + tcg_debug_assert(v1 >= TCG_REG_V0 && v1 <= TCG_REG_V31); + tcg_debug_assert(v2 >= TCG_REG_V0 && v2 <= TCG_REG_V31); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | (v2 & 15)); + tcg_out32(s, (op & 0x00ff) | RXB(v1, v2, 0, 0) | (m3 << 12)); +} + +static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1, + intptr_t d2, TCGReg b2, TCGReg r3, int m4) +{ + tcg_debug_assert(v1 >= TCG_REG_V0 && v1 <= TCG_REG_V31); + tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); + tcg_debug_assert(b2 <= TCG_REG_R15); + tcg_debug_assert(r3 <= TCG_REG_R15); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | r3); + tcg_out16(s, b2 << 12 | d2); + tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12)); +} + +static void tcg_out_insn_VRSc(TCGContext *s, S390Opcode op, TCGReg r1, + intptr_t d2, TCGReg b2, TCGReg v3, int m4) +{ + tcg_debug_assert(r1 <= TCG_REG_R15); + tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); + tcg_debug_assert(b2 <= TCG_REG_R15); + tcg_debug_assert(v3 >= TCG_REG_V0 && v3 <= TCG_REG_V31); + tcg_out16(s, (op & 0xff00) | (r1 << 4) | (v3 & 15)); + tcg_out16(s, b2 << 12 | d2); + tcg_out16(s, (op & 0x00ff) | RXB(0, 0, v3, 0) | (m4 << 12)); +} + static void tcg_out_insn_VRX(TCGContext *s, S390Opcode op, TCGReg v1, TCGReg b2, TCGReg x2, intptr_t d2, int m3) { @@ -579,12 +617,38 @@ static void tcg_out_sh32(TCGContext* s, S390Opcode op, TCGReg dest, static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src) { - if (src != dst) { - if (type == TCG_TYPE_I32) { + if (src == dst) { + return true; + } + switch (type) { + case TCG_TYPE_I32: + if (likely(dst < 16 && src < 16)) { tcg_out_insn(s, RR, LR, dst, src); - } else { - tcg_out_insn(s, RRE, LGR, dst, src); + break; } + /* fallthru */ + + case TCG_TYPE_I64: + if (likely(dst < 16)) { + if (likely(src < 16)) { + tcg_out_insn(s, RRE, LGR, dst, src); + } else { + tcg_out_insn(s, VRSc, VLGV, dst, 0, 0, src, 3); + } + break; + } else if (src < 16) { + tcg_out_insn(s, VRSb, VLVG, dst, 0, 0, src, 3); + break; + } + /* fallthru */ + + case TCG_TYPE_V64: + case TCG_TYPE_V128: + tcg_out_insn(s, VRRa, VLR, dst, src, 0); + break; + + default: + g_assert_not_reached(); } return true; } From patchwork Mon Feb 8 02:50:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 378493 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp4333879jah; Sun, 7 Feb 2021 19:32:38 -0800 (PST) X-Google-Smtp-Source: ABdhPJy1nnI8JP6N7azKV5rCT5LVhq1LCsxiCubzH87KPTd7+0kJwVeyRXWtBoOYp1txLE0GMcK+ X-Received: by 2002:a25:d6c2:: with SMTP id n185mr23333668ybg.71.1612755158359; Sun, 07 Feb 2021 19:32:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612755158; cv=none; d=google.com; s=arc-20160816; b=M6AEYdUcdX0nNpbi2jJktTTzbwx1PLSi0sPP5qVBbA8Ui3P5ikRSCn7IdHPX4ozgcR bAjkxVXeBCRjSuLpg6X+8mfoKe+9MnzrVGzrwkhDElCVP4xKtyv+tSGF4GAhtylbisFM wVJTdB9LH0OOMMkGE8tZ80XrzR2YbYPKZMr6Xj+nQ+rC0T8KOf8h78eanRkMiNzcUqhy eE9kWxReOOqJ9Pu2zw3jTpTLUXpxsukiOCQVvqJYFATnUQb8ARjonq2pn/X4x37EVHF6 M6eUwDaoxeezXse7+RRKGCuIvCcvU/vJBGid+Ztjmc7mDzW3zSvLNkoSI9fgiE39SaFf 0FpQ== ARC-Message-Signature: i=1; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 07/16] tcg/s390x: Implement tcg_out_dup*_vec Date: Sun, 7 Feb 2021 18:50:52 -0800 Message-Id: <20210208025101.271726-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208025101.271726-1-richard.henderson@linaro.org> References: <20210208025101.271726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 122 ++++++++++++++++++++++++++++++++++++- 1 file changed, 119 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index fdf7475b2d..01118d9993 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -265,13 +265,20 @@ typedef enum S390Opcode { RX_STC = 0x42, RX_STH = 0x40, + VRIa_VGBM = 0xe744, + VRIa_VREPI = 0xe745, + VRIb_VGM = 0xe746, + VRIc_VREP = 0xe74d, + VRRa_VLR = 0xe756, + VRRf_VLVGP = 0xe762, VRSb_VLVG = 0xe722, VRSc_VLGV = 0xe721, VRX_VL = 0xe706, VRX_VLLEZ = 0xe704, + VRX_VLREP = 0xe705, VRX_VST = 0xe70e, VRX_VSTEF = 0xe70b, VRX_VSTEG = 0xe70a, @@ -551,6 +558,34 @@ static int RXB(TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4) | ((v4 & 16) << (4 - 3)); } +static void tcg_out_insn_VRIa(TCGContext *s, S390Opcode op, + TCGReg v1, uint16_t i2, int m3) +{ + tcg_debug_assert(v1 >= TCG_REG_V0 && v1 <= TCG_REG_V31); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4)); + tcg_out16(s, i2); + tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m3 << 12)); +} + +static void tcg_out_insn_VRIb(TCGContext *s, S390Opcode op, + TCGReg v1, uint8_t i2, uint8_t i3, int m4) +{ + tcg_debug_assert(v1 >= TCG_REG_V0 && v1 <= TCG_REG_V31); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4)); + tcg_out16(s, (i2 << 8) | (i3 & 0xff)); + tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0) | (m4 << 12)); +} + +static void tcg_out_insn_VRIc(TCGContext *s, S390Opcode op, + TCGReg v1, uint16_t i2, TCGReg v3, int m4) +{ + tcg_debug_assert(v1 >= TCG_REG_V0 && v1 <= TCG_REG_V31); + tcg_debug_assert(v3 >= TCG_REG_V0 && v3 <= TCG_REG_V31); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | (v3 & 15)); + tcg_out16(s, i2); + tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, v3, 0) | (m4 << 12)); +} + static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op, TCGReg v1, TCGReg v2, int m3) { @@ -560,6 +595,17 @@ static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op, tcg_out32(s, (op & 0x00ff) | RXB(v1, v2, 0, 0) | (m3 << 12)); } +static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op, + TCGReg v1, TCGReg r2, TCGReg r3) +{ + tcg_debug_assert(v1 >= TCG_REG_V0 && v1 <= TCG_REG_V31); + tcg_debug_assert(r2 <= TCG_REG_R15); + tcg_debug_assert(r3 <= TCG_REG_R15); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | r2); + tcg_out16(s, r3 << 12); + tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0)); +} + static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1, intptr_t d2, TCGReg b2, TCGReg r3, int m4) { @@ -2466,19 +2512,89 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg src) { - g_assert_not_reached(); + if (src < 16) { + /* Replicate general register into two MO_64. */ + tcg_out_insn(s, VRRf, VLVGP, dst, src, src); + if (vece == MO_64) { + return true; + } + } + + /* + * Recall that the "standard" integer, within a vector, is the + * rightmost element of the leftmost doubleword, a-la VLLEZ. + */ + tcg_out_insn(s, VRIc, VREP, dst, (8 >> vece) - 1, src, vece); + return true; } static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, TCGReg base, intptr_t offset) { - g_assert_not_reached(); + tcg_out_vrx_mem(s, VRX_VLREP, dst, base, TCG_REG_NONE, offset, vece); + return true; } static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, TCGReg dst, int64_t val) { - g_assert_not_reached(); + int i, mask, msb, lsb; + + /* Look for int16_t elements. */ + if (vece <= MO_16 || + (vece == MO_32 ? (int32_t)val : val) == (int16_t)val) { + tcg_out_insn(s, VRIa, VREPI, dst, val, vece); + return; + } + + /* Look for bit masks. */ + if (vece == MO_32) { + if (risbg_mask((int32_t)val)) { + /* Handle wraparound by swapping msb and lsb. */ + if ((val & 0x80000001u) == 0x80000001u) { + msb = 32 - ctz32(~val); + lsb = clz32(~val) - 1; + } else { + msb = clz32(val); + lsb = 31 - ctz32(val); + } + tcg_out_insn(s, VRIb, VGM, dst, lsb, msb, MO_32); + return; + } + } else { + if (risbg_mask(val)) { + /* Handle wraparound by swapping msb and lsb. */ + if ((val & 0x8000000000000001ull) == 0x8000000000000001ull) { + /* Handle wraparound by swapping msb and lsb. */ + msb = 64 - ctz64(~val); + lsb = clz64(~val) - 1; + } else { + msb = clz64(val); + lsb = 63 - ctz64(val); + } + tcg_out_insn(s, VRIb, VGM, dst, lsb, msb, MO_64); + return; + } + } + + /* Look for all bytes 0x00 or 0xff. */ + for (i = mask = 0; i < 8; i++) { + uint8_t byte = val >> (i * 8); + if (byte == 0xff) { + mask |= 1 << i; + } else if (byte != 0) { + break; + } + } + if (i == 8) { + tcg_out_insn(s, VRIa, VGBM, dst, mask * 0x0101, 0); + return; + } + + /* Otherwise, stuff it in the constant pool. */ + tcg_out_insn(s, RIL, LARL, TCG_TMP0, 0); + new_pool_label(s, val, R_390_PC32DBL, s->code_ptr - 2, 2); + tcg_out_insn(s, VRX, VLREP, dst, TCG_TMP0, TCG_REG_NONE, 0, MO_64); } static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, From patchwork Mon Feb 8 02:50:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 378506 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp4338433jah; Sun, 7 Feb 2021 19:42:03 -0800 (PST) X-Google-Smtp-Source: ABdhPJyaME/owqJIKE4Px/6RKoNKPwapEz1ATRW8uas3uy3YXcHyGEKl8E99PqtZ11WOd3lLFEcf X-Received: by 2002:a25:7009:: with SMTP id l9mr24678354ybc.118.1612755723676; Sun, 07 Feb 2021 19:42:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612755723; cv=none; d=google.com; s=arc-20160816; b=gZ71U4FC45MzCC32VxP+FC9d+Mn9pPWngFvSXXw+W23YlLkZc46+ibmV18qT09wKJX L4z6A7gfNqv3PuimEl4YKnu146/kklc//6qMtRa0voaOejYhD0IFzGgojEkXV5b7qRRS UcA0Ao3Xx3Mi0NUkX6JKelMrpHY7EETscgiuv4bvBudrVQi37PEdVbLyfxj0AWHz+9HN adWnKCr0uOnMenPJSWQCtTcy16G22Vh9bzFdtBU74ry4cIkDxN9ikDXjmaKDE1dECUN+ 8/afW9IwcHjqmhaGt03r/jaUMCfGPyBKU1GrCIU0OaS83CLlOpy17I3LyoJw0AKzoGhy tFhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NFbhYgQUsjaFE+5Iajc9BElBoc4cCgBaEW1XyF0baro=; b=jR0GhIDfMqCOE0z40g/HVcELHmZ585n/NH8ZjZSpc3qdiO4VgKRf2m/55HTNi4jOgD vPBLI6tkCjRJAl6Nn/5IXwjd7MKL2gopimBOzOSIDl+1sjzX/WuqEkeBBJhMxxsIN8+M W8MSUkUZHpL7A8jXkt28qtev11U9WPc+oBsjt7UYojAfMfcKxDZR2a6LkvBAuBh9ruCj ZztgGH0L9LHDypYZ2A7GnyVq7qH5CbYZPQS86dD8f70ZcIFTobSwcK6+BEG8KxSkwmoR jM3XbVCM7F26JMt7I/u7hEbc5BhlMYbbNM4rizdxUv6Eg94gh63eHd6BaWdEdCnyGinG h1iQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zRpQYT2o; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 08/16] tcg/s390x: Implement minimal vector operations Date: Sun, 7 Feb 2021 18:50:53 -0800 Message-Id: <20210208025101.271726-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208025101.271726-1-richard.henderson@linaro.org> References: <20210208025101.271726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Implementing add, sub, and, or, xor as the minimal set. This allows us to actually enable vectors in query_s390_facilities. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 154 ++++++++++++++++++++++++++++++++++++- 1 file changed, 150 insertions(+), 4 deletions(-) -- 2.25.1 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 01118d9993..08315c7b05 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -271,6 +271,14 @@ typedef enum S390Opcode { VRIc_VREP = 0xe74d, VRRa_VLR = 0xe756, + VRRc_VA = 0xe7f3, + VRRc_VCEQ = 0xe7f8, /* we leave the m5 cs field 0 */ + VRRc_VCH = 0xe7fb, /* " */ + VRRc_VCHL = 0xe7f9, /* " */ + VRRc_VN = 0xe768, + VRRc_VO = 0xe76a, + VRRc_VS = 0xe7f7, + VRRc_VX = 0xe76d, VRRf_VLVGP = 0xe762, VRSb_VLVG = 0xe722, @@ -595,6 +603,17 @@ static void tcg_out_insn_VRRa(TCGContext *s, S390Opcode op, tcg_out32(s, (op & 0x00ff) | RXB(v1, v2, 0, 0) | (m3 << 12)); } +static void tcg_out_insn_VRRc(TCGContext *s, S390Opcode op, + TCGReg v1, TCGReg v2, TCGReg v3, int m4) +{ + tcg_debug_assert(v1 >= TCG_REG_V0 && v1 <= TCG_REG_V31); + tcg_debug_assert(v2 >= TCG_REG_V0 && v2 <= TCG_REG_V31); + tcg_debug_assert(v3 >= TCG_REG_V0 && v3 <= TCG_REG_V31); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | (v2 & 15)); + tcg_out16(s, v3 << 12); + tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, 0) | (m4 << 12)); +} + static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op, TCGReg v1, TCGReg r2, TCGReg r3) { @@ -2601,18 +2620,145 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, const TCGArg *args, const int *const_args) { - g_assert_not_reached(); + TCGType type = vecl + TCG_TYPE_V64; + TCGArg a0 = args[0], a1 = args[1], a2 = args[2]; + + switch (opc) { + case INDEX_op_ld_vec: + tcg_out_ld(s, type, a0, a1, a2); + break; + case INDEX_op_st_vec: + tcg_out_st(s, type, a0, a1, a2); + break; + case INDEX_op_dupm_vec: + tcg_out_dupm_vec(s, type, vece, a0, a1, a2); + break; + + case INDEX_op_add_vec: + tcg_out_insn(s, VRRc, VA, a0, a1, a2, vece); + break; + case INDEX_op_sub_vec: + tcg_out_insn(s, VRRc, VS, a0, a1, a2, vece); + break; + case INDEX_op_and_vec: + tcg_out_insn(s, VRRc, VN, a0, a1, a2, 0); + break; + case INDEX_op_or_vec: + tcg_out_insn(s, VRRc, VO, a0, a1, a2, 0); + break; + case INDEX_op_xor_vec: + tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0); + break; + + case INDEX_op_cmp_vec: + switch ((TCGCond)args[3]) { + case TCG_COND_EQ: + tcg_out_insn(s, VRRc, VCEQ, a0, a1, a2, vece); + break; + case TCG_COND_GT: + tcg_out_insn(s, VRRc, VCH, a0, a1, a2, vece); + break; + case TCG_COND_GTU: + tcg_out_insn(s, VRRc, VCHL, a0, a1, a2, vece); + break; + default: + g_assert_not_reached(); + } + break; + + case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ + case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ + default: + g_assert_not_reached(); + } } int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) { - return 0; + switch (opc) { + case INDEX_op_add_vec: + case INDEX_op_sub_vec: + case INDEX_op_and_vec: + case INDEX_op_or_vec: + case INDEX_op_xor_vec: + return 1; + case INDEX_op_cmp_vec: + return -1; + default: + return 0; + } +} + +static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGv_vec v2, TCGCond cond) +{ + bool need_swap = false, need_inv = false; + + switch (cond) { + case TCG_COND_EQ: + case TCG_COND_GT: + case TCG_COND_GTU: + break; + case TCG_COND_NE: + case TCG_COND_LE: + case TCG_COND_LEU: + need_inv = true; + break; + case TCG_COND_LT: + case TCG_COND_LTU: + need_swap = true; + break; + case TCG_COND_GE: + case TCG_COND_GEU: + need_swap = need_inv = true; + break; + default: + g_assert_not_reached(); + } + + if (need_inv) { + cond = tcg_invert_cond(cond); + } + if (need_swap) { + TCGv_vec t1; + t1 = v1, v1 = v2, v2 = t1; + cond = tcg_swap_cond(cond); + } + + vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0), + tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond); + + return need_inv; +} + +static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGv_vec v2, TCGCond cond) +{ + if (expand_vec_cmp_noinv(type, vece, v0, v1, v2, cond)) { + tcg_gen_not_vec(vece, v0, v0); + } } void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, TCGArg a0, ...) { - g_assert_not_reached(); + va_list va; + TCGv_vec v0, v1, v2; + + va_start(va, a0); + v0 = temp_tcgv_vec(arg_temp(a0)); + v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + v2 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + + switch (opc) { + case INDEX_op_cmp_vec: + expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); + break; + + default: + g_assert_not_reached(); + } + va_end(va); } static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) @@ -2804,7 +2950,7 @@ static void query_s390_facilities(void) * There is nothing else we currently care about in the 3rd word, so * disable VECTOR with one store. */ - if (1 || !(hwcap & HWCAP_S390_VXRS)) { + if (!(hwcap & HWCAP_S390_VXRS)) { s390_facilities[2] = 0; } } From patchwork Mon Feb 8 02:50:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 378528 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp4353302jah; Sun, 7 Feb 2021 20:11:48 -0800 (PST) X-Google-Smtp-Source: ABdhPJwDNUqNvbVmfwL8bm8Y1xnszBoPDApmJbfHgv9PXa0AlUODQzWDTNIh7yxsH+Rae2/+s+hu X-Received: by 2002:a25:946:: with SMTP id u6mr22718236ybm.231.1612757507992; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 09/16] tcg/s390x: Implement andc, orc, abs, neg, not vector operations Date: Sun, 7 Feb 2021 18:50:54 -0800 Message-Id: <20210208025101.271726-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208025101.271726-1-richard.henderson@linaro.org> References: <20210208025101.271726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These logical and arithmetic operations are optional but trivial. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target.h | 10 +++++----- tcg/s390x/tcg-target.c.inc | 34 +++++++++++++++++++++++++++++++++- 3 files changed, 39 insertions(+), 6 deletions(-) -- 2.25.1 diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index ce9432cfe3..cb953896d5 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -17,6 +17,7 @@ C_O0_I2(v, r) C_O1_I1(r, L) C_O1_I1(r, r) C_O1_I1(v, r) +C_O1_I1(v, v) C_O1_I1(v, vr) C_O1_I2(r, 0, ri) C_O1_I2(r, 0, rI) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index e8659bf576..dd11972ed2 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -140,11 +140,11 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_v128 HAVE_FACILITY(VECTOR) #define TCG_TARGET_HAS_v256 0 -#define TCG_TARGET_HAS_andc_vec 0 -#define TCG_TARGET_HAS_orc_vec 0 -#define TCG_TARGET_HAS_not_vec 0 -#define TCG_TARGET_HAS_neg_vec 0 -#define TCG_TARGET_HAS_abs_vec 0 +#define TCG_TARGET_HAS_andc_vec 1 +#define TCG_TARGET_HAS_orc_vec 1 +#define TCG_TARGET_HAS_not_vec 1 +#define TCG_TARGET_HAS_neg_vec 1 +#define TCG_TARGET_HAS_abs_vec 1 #define TCG_TARGET_HAS_roti_vec 0 #define TCG_TARGET_HAS_rots_vec 0 #define TCG_TARGET_HAS_rotv_vec 0 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 08315c7b05..23c25ff619 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -270,13 +270,18 @@ typedef enum S390Opcode { VRIb_VGM = 0xe746, VRIc_VREP = 0xe74d, + VRRa_VLC = 0xe7de, + VRRa_VLP = 0xe7df, VRRa_VLR = 0xe756, VRRc_VA = 0xe7f3, VRRc_VCEQ = 0xe7f8, /* we leave the m5 cs field 0 */ VRRc_VCH = 0xe7fb, /* " */ VRRc_VCHL = 0xe7f9, /* " */ VRRc_VN = 0xe768, + VRRc_VNC = 0xe769, + VRRc_VNO = 0xe76b, VRRc_VO = 0xe76a, + VRRc_VOC = 0xe76f, VRRc_VS = 0xe7f7, VRRc_VX = 0xe76d, VRRf_VLVGP = 0xe762, @@ -2634,6 +2639,16 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, tcg_out_dupm_vec(s, type, vece, a0, a1, a2); break; + case INDEX_op_abs_vec: + tcg_out_insn(s, VRRa, VLP, a0, a1, vece); + break; + case INDEX_op_neg_vec: + tcg_out_insn(s, VRRa, VLC, a0, a1, vece); + break; + case INDEX_op_not_vec: + tcg_out_insn(s, VRRc, VNO, a0, a1, a1, 0); + break; + case INDEX_op_add_vec: tcg_out_insn(s, VRRc, VA, a0, a1, a2, vece); break; @@ -2643,9 +2658,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, case INDEX_op_and_vec: tcg_out_insn(s, VRRc, VN, a0, a1, a2, 0); break; + case INDEX_op_andc_vec: + tcg_out_insn(s, VRRc, VNC, a0, a1, a2, 0); + break; case INDEX_op_or_vec: tcg_out_insn(s, VRRc, VO, a0, a1, a2, 0); break; + case INDEX_op_orc_vec: + tcg_out_insn(s, VRRc, VOC, a0, a1, a2, 0); + break; case INDEX_op_xor_vec: tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0); break; @@ -2676,10 +2697,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) { switch (opc) { + case INDEX_op_abs_vec: case INDEX_op_add_vec: - case INDEX_op_sub_vec: case INDEX_op_and_vec: + case INDEX_op_andc_vec: + case INDEX_op_neg_vec: + case INDEX_op_not_vec: case INDEX_op_or_vec: + case INDEX_op_orc_vec: + case INDEX_op_sub_vec: case INDEX_op_xor_vec: return 1; case INDEX_op_cmp_vec: @@ -2908,10 +2934,16 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) return C_O1_I1(v, r); case INDEX_op_dup_vec: return C_O1_I1(v, vr); + case INDEX_op_abs_vec: + case INDEX_op_neg_vec: + case INDEX_op_not_vec: + return C_O1_I1(v, v); case INDEX_op_add_vec: case INDEX_op_sub_vec: case INDEX_op_and_vec: + case INDEX_op_andc_vec: case INDEX_op_or_vec: + case INDEX_op_orc_vec: case INDEX_op_xor_vec: case INDEX_op_cmp_vec: return C_O1_I2(v, v, v); From patchwork Mon Feb 8 02:50:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 378529 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp4354262jah; Sun, 7 Feb 2021 20:14:01 -0800 (PST) X-Google-Smtp-Source: ABdhPJyDtDaLXzEzXIcprUkor8Ih0T5jvYhGgl3n05FuGQmPnsgQ7FTlefNljNBunbCHcZkK25KY X-Received: by 2002:a25:1387:: with SMTP id 129mr21309609ybt.423.1612757641141; Sun, 07 Feb 2021 20:14:01 -0800 (PST) ARC-Seal: i=1; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 10/16] tcg/s390x: Implement TCG_TARGET_HAS_mul_vec Date: Sun, 7 Feb 2021 18:50:55 -0800 Message-Id: <20210208025101.271726-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208025101.271726-1-richard.henderson@linaro.org> References: <20210208025101.271726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index dd11972ed2..13b9918276 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -151,7 +151,7 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_shi_vec 0 #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 0 -#define TCG_TARGET_HAS_mul_vec 0 +#define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 0 #define TCG_TARGET_HAS_minmax_vec 0 #define TCG_TARGET_HAS_bitsel_vec 0 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 23c25ff619..53d86268b6 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -277,6 +277,7 @@ typedef enum S390Opcode { VRRc_VCEQ = 0xe7f8, /* we leave the m5 cs field 0 */ VRRc_VCH = 0xe7fb, /* " */ VRRc_VCHL = 0xe7f9, /* " */ + VRRc_VML = 0xe7a2, VRRc_VN = 0xe768, VRRc_VNC = 0xe769, VRRc_VNO = 0xe76b, @@ -2661,6 +2662,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, case INDEX_op_andc_vec: tcg_out_insn(s, VRRc, VNC, a0, a1, a2, 0); break; + case INDEX_op_mul_vec: + tcg_out_insn(s, VRRc, VML, a0, a1, a2, vece); + break; case INDEX_op_or_vec: tcg_out_insn(s, VRRc, VO, a0, a1, a2, 0); break; @@ -2710,6 +2714,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) return 1; case INDEX_op_cmp_vec: return -1; + case INDEX_op_mul_vec: + return vece < MO_64; default: return 0; } @@ -2946,6 +2952,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_orc_vec: case INDEX_op_xor_vec: case INDEX_op_cmp_vec: + case INDEX_op_mul_vec: return C_O1_I2(v, v, v); default: From patchwork Mon Feb 8 02:50:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 378530 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp4355063jah; Sun, 7 Feb 2021 20:15:42 -0800 (PST) X-Google-Smtp-Source: ABdhPJwbBhMnYw0IyRylsgojlqPlGckln7Ng9M+eFJ4tg+ps5p20PZY+VDYE5mGzEEmERXGRBXjV X-Received: by 2002:a25:33d5:: with SMTP id z204mr22549828ybz.78.1612757742249; Sun, 07 Feb 2021 20:15:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612757742; cv=none; d=google.com; s=arc-20160816; b=I5mdgDYhR7gfhKzwb6QVFLHp8bEyMpS2k31NDvzhjaQh9kFptb1e9c7D+CklAFSeMy ieaJum4CQ7Bayc3I0+EenTtUPVRWD/riTLtWLqbq2eEHvz4OmzKIsmNQySL4DyrckhoD YqRQLEfQppnU4HABCoGNNDm4/k2yk8MNlyUu5+FQP22VjhDVK7/Gvf/DIvfifWDGkxIP tUNO+Tk5AR+mlNmnZe9qvgdZUmAmqXHVIH00XmaW+XBhiZuB6gQpPDaItJcPi9QHMD+8 KqmUsFHNLq0lBIeWH6WlVAYpjqwMyVFTKEQ9fBAgBJtSqTjBu/6p0yR5xZ6uoVNgmT9D U23w== ARC-Message-Signature: i=1; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 11/16] tcg/s390x: Implement vector shift operations Date: Sun, 7 Feb 2021 18:50:56 -0800 Message-Id: <20210208025101.271726-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208025101.271726-1-richard.henderson@linaro.org> References: <20210208025101.271726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target.h | 12 ++--- tcg/s390x/tcg-target.c.inc | 93 +++++++++++++++++++++++++++++++++- 3 files changed, 99 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index cb953896d5..49b98f33b9 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -24,6 +24,7 @@ C_O1_I2(r, 0, rI) C_O1_I2(r, 0, rJ) C_O1_I2(r, r, ri) C_O1_I2(r, rZ, r) +C_O1_I2(v, v, r) C_O1_I2(v, v, v) C_O1_I4(r, r, ri, r, 0) C_O1_I4(r, r, ri, rI, 0) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 13b9918276..3026a4d8c4 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -145,12 +145,12 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_not_vec 1 #define TCG_TARGET_HAS_neg_vec 1 #define TCG_TARGET_HAS_abs_vec 1 -#define TCG_TARGET_HAS_roti_vec 0 -#define TCG_TARGET_HAS_rots_vec 0 -#define TCG_TARGET_HAS_rotv_vec 0 -#define TCG_TARGET_HAS_shi_vec 0 -#define TCG_TARGET_HAS_shs_vec 0 -#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_roti_vec 1 +#define TCG_TARGET_HAS_rots_vec 1 +#define TCG_TARGET_HAS_rotv_vec 1 +#define TCG_TARGET_HAS_shi_vec 1 +#define TCG_TARGET_HAS_shs_vec 1 +#define TCG_TARGET_HAS_shv_vec 1 #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 0 #define TCG_TARGET_HAS_minmax_vec 0 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 53d86268b6..22a6f18cc4 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -277,6 +277,10 @@ typedef enum S390Opcode { VRRc_VCEQ = 0xe7f8, /* we leave the m5 cs field 0 */ VRRc_VCH = 0xe7fb, /* " */ VRRc_VCHL = 0xe7f9, /* " */ + VRRc_VERLLV = 0xe773, + VRRc_VESLV = 0xe770, + VRRc_VESRAV = 0xe77a, + VRRc_VESRLV = 0xe778, VRRc_VML = 0xe7a2, VRRc_VN = 0xe768, VRRc_VNC = 0xe769, @@ -287,6 +291,10 @@ typedef enum S390Opcode { VRRc_VX = 0xe76d, VRRf_VLVGP = 0xe762, + VRSa_VERLL = 0xe733, + VRSa_VESL = 0xe730, + VRSa_VESRA = 0xe73a, + VRSa_VESRL = 0xe738, VRSb_VLVG = 0xe722, VRSc_VLGV = 0xe721, @@ -631,6 +639,18 @@ static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op, tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, 0, 0)); } +static void tcg_out_insn_VRSa(TCGContext *s, S390Opcode op, TCGReg v1, + intptr_t d2, TCGReg b2, TCGReg v3, int m4) +{ + tcg_debug_assert(v1 >= TCG_REG_V0 && v1 <= TCG_REG_V31); + tcg_debug_assert(d2 >= 0 && d2 <= 0xfff); + tcg_debug_assert(b2 <= TCG_REG_R15); + tcg_debug_assert(v3 >= TCG_REG_V0 && v3 <= TCG_REG_V31); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | (v3 & 15)); + tcg_out16(s, b2 << 12 | d2); + tcg_out16(s, (op & 0x00ff) | RXB(v1, 0, v3, 0) | (m4 << 12)); +} + static void tcg_out_insn_VRSb(TCGContext *s, S390Opcode op, TCGReg v1, intptr_t d2, TCGReg b2, TCGReg r3, int m4) { @@ -2675,6 +2695,43 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0); break; + case INDEX_op_shli_vec: + tcg_out_insn(s, VRSa, VESL, a0, a2, TCG_REG_NONE, a1, vece); + break; + case INDEX_op_shri_vec: + tcg_out_insn(s, VRSa, VESRL, a0, a2, TCG_REG_NONE, a1, vece); + break; + case INDEX_op_sari_vec: + tcg_out_insn(s, VRSa, VESRA, a0, a2, TCG_REG_NONE, a1, vece); + break; + case INDEX_op_rotli_vec: + tcg_out_insn(s, VRSa, VERLL, a0, a2, TCG_REG_NONE, a1, vece); + break; + case INDEX_op_shls_vec: + tcg_out_insn(s, VRSa, VESL, a0, 0, a2, a1, vece); + break; + case INDEX_op_shrs_vec: + tcg_out_insn(s, VRSa, VESRL, a0, 0, a2, a1, vece); + break; + case INDEX_op_sars_vec: + tcg_out_insn(s, VRSa, VESRA, a0, 0, a2, a1, vece); + break; + case INDEX_op_rotls_vec: + tcg_out_insn(s, VRSa, VERLL, a0, 0, a2, a1, vece); + break; + case INDEX_op_shlv_vec: + tcg_out_insn(s, VRRc, VESLV, a0, a1, a2, vece); + break; + case INDEX_op_shrv_vec: + tcg_out_insn(s, VRRc, VESRLV, a0, a1, a2, vece); + break; + case INDEX_op_sarv_vec: + tcg_out_insn(s, VRRc, VESRAV, a0, a1, a2, vece); + break; + case INDEX_op_rotlv_vec: + tcg_out_insn(s, VRRc, VERLLV, a0, a1, a2, vece); + break; + case INDEX_op_cmp_vec: switch ((TCGCond)args[3]) { case TCG_COND_EQ: @@ -2709,10 +2766,23 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_not_vec: case INDEX_op_or_vec: case INDEX_op_orc_vec: + case INDEX_op_rotli_vec: + case INDEX_op_rotls_vec: + case INDEX_op_rotlv_vec: + case INDEX_op_sari_vec: + case INDEX_op_sars_vec: + case INDEX_op_sarv_vec: + case INDEX_op_shli_vec: + case INDEX_op_shls_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shri_vec: + case INDEX_op_shrs_vec: + case INDEX_op_shrv_vec: case INDEX_op_sub_vec: case INDEX_op_xor_vec: return 1; case INDEX_op_cmp_vec: + case INDEX_op_rotrv_vec: return -1; case INDEX_op_mul_vec: return vece < MO_64; @@ -2775,7 +2845,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, TCGArg a0, ...) { va_list va; - TCGv_vec v0, v1, v2; + TCGv_vec v0, v1, v2, t0; va_start(va, a0); v0 = temp_tcgv_vec(arg_temp(a0)); @@ -2787,6 +2857,13 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); break; + case INDEX_op_rotrv_vec: + t0 = tcg_temp_new_vec(type); + tcg_gen_neg_vec(vece, t0, v2); + tcg_gen_rotlv_vec(vece, v0, v1, t0); + tcg_temp_free_vec(t0); + break; + default: g_assert_not_reached(); } @@ -2943,6 +3020,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_abs_vec: case INDEX_op_neg_vec: case INDEX_op_not_vec: + case INDEX_op_rotli_vec: + case INDEX_op_sari_vec: + case INDEX_op_shli_vec: + case INDEX_op_shri_vec: return C_O1_I1(v, v); case INDEX_op_add_vec: case INDEX_op_sub_vec: @@ -2953,7 +3034,17 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_xor_vec: case INDEX_op_cmp_vec: case INDEX_op_mul_vec: + case INDEX_op_rotlv_vec: + case INDEX_op_rotrv_vec: + case INDEX_op_shlv_vec: + case INDEX_op_shrv_vec: + case INDEX_op_sarv_vec: return C_O1_I2(v, v, v); + case INDEX_op_rotls_vec: + case INDEX_op_shls_vec: + case INDEX_op_shrs_vec: + case INDEX_op_sars_vec: + return C_O1_I2(v, v, r); default: g_assert_not_reached(); From patchwork Mon Feb 8 02:50:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 378510 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp4339857jah; Sun, 7 Feb 2021 19:44:58 -0800 (PST) X-Google-Smtp-Source: ABdhPJwLlKW8Avx9J7QECwSIpdwOwdxxb5wgmuVVpSdwbhgEkjV416ubA1OEzZiyR1QysTjTfvI8 X-Received: by 2002:a25:3387:: with SMTP id z129mr23923093ybz.239.1612755898641; Sun, 07 Feb 2021 19:44:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612755898; cv=none; d=google.com; s=arc-20160816; b=WdjOUTgzPTQKVKFkOvwEPrpTwCRYv18X+fLSp7pNdmn1E9REDAjPvqIu6mGiXADQxA UxA+k8NcYEZi4iZAXFohjkN999FwAZoX1NQ10dcSJxVHsLexa5NX2pxNHKSslPWrdBvx 0KZ+qpLBvNE7RLCpYa5kFPgJ24yeumB1E2hWwyz+a698D7+lvhUGUi8ggQwnn1QUwtoC r7g2uFWf9lbyHN7DwGlaKl+Y0L3ZB2fS0KU35os92ydodKmsztzYQxbzpgp7WXgmP9lv zTiZ0MqP4Z6al7uy5gRYaIpebbjylUjzuOhLCYRndXMiBV1LkTXB+DOFbn1b9Oyb+gvI LCdg== ARC-Message-Signature: i=1; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 12/16] tcg/s390x: Implement TCG_TARGET_HAS_minmax_vec Date: Sun, 7 Feb 2021 18:50:57 -0800 Message-Id: <20210208025101.271726-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208025101.271726-1-richard.henderson@linaro.org> References: <20210208025101.271726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 25 +++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 3026a4d8c4..efa32f348c 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -153,7 +153,7 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_shv_vec 1 #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 0 -#define TCG_TARGET_HAS_minmax_vec 0 +#define TCG_TARGET_HAS_minmax_vec 1 #define TCG_TARGET_HAS_bitsel_vec 0 #define TCG_TARGET_HAS_cmpsel_vec 0 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 22a6f18cc4..3bf49e6c90 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -282,6 +282,10 @@ typedef enum S390Opcode { VRRc_VESRAV = 0xe77a, VRRc_VESRLV = 0xe778, VRRc_VML = 0xe7a2, + VRRc_VMN = 0xe7fe, + VRRc_VMNL = 0xe7fc, + VRRc_VMX = 0xe7ff, + VRRc_VMXL = 0xe7fd, VRRc_VN = 0xe768, VRRc_VNC = 0xe769, VRRc_VNO = 0xe76b, @@ -2732,6 +2736,19 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, tcg_out_insn(s, VRRc, VERLLV, a0, a1, a2, vece); break; + case INDEX_op_smin_vec: + tcg_out_insn(s, VRRc, VMN, a0, a1, a2, vece); + break; + case INDEX_op_smax_vec: + tcg_out_insn(s, VRRc, VMX, a0, a1, a2, vece); + break; + case INDEX_op_umin_vec: + tcg_out_insn(s, VRRc, VMNL, a0, a1, a2, vece); + break; + case INDEX_op_umax_vec: + tcg_out_insn(s, VRRc, VMXL, a0, a1, a2, vece); + break; + case INDEX_op_cmp_vec: switch ((TCGCond)args[3]) { case TCG_COND_EQ: @@ -2778,7 +2795,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_shri_vec: case INDEX_op_shrs_vec: case INDEX_op_shrv_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: case INDEX_op_sub_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: case INDEX_op_xor_vec: return 1; case INDEX_op_cmp_vec: @@ -3039,6 +3060,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_shlv_vec: case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: + case INDEX_op_smax_vec: + case INDEX_op_smin_vec: + case INDEX_op_umax_vec: + case INDEX_op_umin_vec: return C_O1_I2(v, v, v); case INDEX_op_rotls_vec: case INDEX_op_shls_vec: From patchwork Mon Feb 8 02:50:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 378514 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp4341708jah; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 13/16] tcg: Expand usadd/ussub with umin/umax Date: Sun, 7 Feb 2021 18:50:58 -0800 Message-Id: <20210208025101.271726-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208025101.271726-1-richard.henderson@linaro.org> References: <20210208025101.271726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For usadd, we only have to consider overflow. Since ~B + B == -1, the maximum value for A that saturates is ~B. For ussub, we only have to consider underflow. The minimum value that saturates to 0 from A - B is B. Signed-off-by: Richard Henderson --- tcg/tcg-op-vec.c | 37 +++++++++++++++++++++++++++++++++++-- 1 file changed, 35 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index d19aa7373e..9747b7bb06 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -120,6 +120,18 @@ bool tcg_can_emit_vecop_list(const TCGOpcode *list, continue; } break; + case INDEX_op_usadd_vec: + if (tcg_can_emit_vec_op(INDEX_op_umin_vec, type, vece) || + tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece)) { + continue; + } + break; + case INDEX_op_ussub_vec: + if (tcg_can_emit_vec_op(INDEX_op_umax_vec, type, vece) || + tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece)) { + continue; + } + break; case INDEX_op_cmpsel_vec: case INDEX_op_smin_vec: case INDEX_op_smax_vec: @@ -604,7 +616,18 @@ void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { - do_op3_nofail(vece, r, a, b, INDEX_op_usadd_vec); + if (!do_op3(vece, r, a, b, INDEX_op_usadd_vec)) { + const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL); + TCGv_vec t = tcg_temp_new_vec_matching(r); + + /* usadd(a, b) = min(a, ~b) + b */ + tcg_gen_not_vec(vece, t, b); + tcg_gen_umin_vec(vece, t, t, a); + tcg_gen_add_vec(vece, r, r, b); + + tcg_temp_free_vec(t); + tcg_swap_vecop_list(hold_list); + } } void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) @@ -614,7 +637,17 @@ void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) { - do_op3_nofail(vece, r, a, b, INDEX_op_ussub_vec); + if (!do_op3(vece, r, a, b, INDEX_op_ussub_vec)) { + const TCGOpcode *hold_list = tcg_swap_vecop_list(NULL); + TCGv_vec t = tcg_temp_new_vec_matching(r); + + /* ussub(a, b) = max(a, b) - b */ + tcg_gen_umax_vec(vece, t, a, b); + tcg_gen_sub_vec(vece, r, t, b); + + tcg_temp_free_vec(t); + tcg_swap_vecop_list(hold_list); + } } static void do_minmax(unsigned vece, TCGv_vec r, TCGv_vec a, From patchwork Mon Feb 8 02:50:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 378531 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp4355629jah; Sun, 7 Feb 2021 20:16:41 -0800 (PST) X-Google-Smtp-Source: ABdhPJzf4jjIt8Nax70PwlJWgAxUliAoEPvDmFjDCCGp0b93sfXKfcryTICGAOmM4p0TDI913KZz X-Received: by 2002:a25:5f46:: with SMTP id h6mr8947645ybm.255.1612757801557; Sun, 07 Feb 2021 20:16:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612757801; cv=none; d=google.com; s=arc-20160816; b=M4zjGs7DWylNX51P1y1d5XqQv8rlj+wrwMgoue+Kx/t9b0kd6kDv+rgw7TDT5yK80Q ZmZfMaj55tzp85HjtAGy359H3lIbLcLNsybmd0CGpTj9LKwSutOHzCj1L2UsHGVz96D3 gHA9+Oj4ajm/ISY75ZLgbtPJUcsIqOBBbqKIUwjT/Te7ZW3k4g84MrkE4wtNHJitbAzV 3q0e3uHasS6Sd+pSaYvie9WgDd2+zOl145wumpLeNyuIbyA2Hrgj70EMXMoPZPzk9WsL YOX/H3706FZ64b2DLlvm4JT+9hIJ9fmJ562lTKR+W32QMb6BYCDGIOVewhgr0OnaVIp3 xH5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=oMSoefukScEf8fPG2WpWUUHe7GtaNiNm3/VqmCKdoJ0=; b=sD5Ya+GoL9eF8SdyUwV5an0JT9VIonusNY0FJQ635XnBE93cUvheTZNoYRPXxyia2f 37LN/FYT8rQc3SKOYVw7AjcTBjNeQwNDR28kUOApUmyXrV5592X9n80IJQgTtr2F1RTM zbPQX4GjDl4VHwbxPpmQvxUvuAibeO3i2sL3aML+NS5xwi7T0mS411kxgQ/pxx6Q0mtf vru0ctFId7p3YeSVqc/8dvsrFPhDR3QMxhagcEiuB97uP6jqxea8X5igOaP98l4HF79z U8jwNW94GaSuFaE3QD5rVuFc33k76y5BSA/PHWM83iJ47u1Z/ewQtaoQa45DFnf4q9bh hwCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=t+Q4Nvr6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 14/16] tcg/s390x: Implement TCG_TARGET_HAS_sat_vec Date: Sun, 7 Feb 2021 18:50:59 -0800 Message-Id: <20210208025101.271726-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208025101.271726-1-richard.henderson@linaro.org> References: <20210208025101.271726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The unsigned saturations are handled via generic code using min/max. The signed saturations are expanded using double-sized arithmetic and a saturating pack. Since all operations are done via expansion, do not actually set TCG_TARGET_HAS_sat_vec. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.opc.h | 3 ++ tcg/s390x/tcg-target.c.inc | 63 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) -- 2.25.1 diff --git a/tcg/s390x/tcg-target.opc.h b/tcg/s390x/tcg-target.opc.h index 67afc82a93..0eb2350fb3 100644 --- a/tcg/s390x/tcg-target.opc.h +++ b/tcg/s390x/tcg-target.opc.h @@ -10,3 +10,6 @@ * emitted by tcg_expand_vec_op. For those familiar with GCC internals, * consider these to be UNSPEC with names. */ +DEF(s390_vuph_vec, 1, 1, 0, IMPLVEC) +DEF(s390_vupl_vec, 1, 1, 0, IMPLVEC) +DEF(s390_vpks_vec, 1, 2, 0, IMPLVEC) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 3bf49e6c90..d4877dcf67 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -291,7 +291,10 @@ typedef enum S390Opcode { VRRc_VNO = 0xe76b, VRRc_VO = 0xe76a, VRRc_VOC = 0xe76f, + VRRc_VPKS = 0xe797, /* we leave the m5 cs field 0 */ VRRc_VS = 0xe7f7, + VRRa_VUPH = 0xe7d7, + VRRa_VUPL = 0xe7d6, VRRc_VX = 0xe76d, VRRf_VLVGP = 0xe762, @@ -2765,6 +2768,16 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, } break; + case INDEX_op_s390_vuph_vec: + tcg_out_insn(s, VRRa, VUPH, a0, a1, vece); + break; + case INDEX_op_s390_vupl_vec: + tcg_out_insn(s, VRRa, VUPL, a0, a1, vece); + break; + case INDEX_op_s390_vpks_vec: + tcg_out_insn(s, VRRc, VPKS, a0, a1, a2, vece); + break; + case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ default: @@ -2807,6 +2820,9 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) return -1; case INDEX_op_mul_vec: return vece < MO_64; + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: + return vece < MO_64 ? -1 : 0; default: return 0; } @@ -2862,6 +2878,43 @@ static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, } } +static void expand_vec_sat(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec v1, TCGv_vec v2, TCGOpcode add_sub_opc) +{ + TCGv_vec h1 = tcg_temp_new_vec(type); + TCGv_vec h2 = tcg_temp_new_vec(type); + TCGv_vec l1 = tcg_temp_new_vec(type); + TCGv_vec l2 = tcg_temp_new_vec(type); + + tcg_debug_assert (vece < MO_64); + + /* Unpack with sign-extension. */ + vec_gen_2(INDEX_op_s390_vuph_vec, type, vece, + tcgv_vec_arg(h1), tcgv_vec_arg(v1)); + vec_gen_2(INDEX_op_s390_vuph_vec, type, vece, + tcgv_vec_arg(h2), tcgv_vec_arg(v2)); + + vec_gen_2(INDEX_op_s390_vupl_vec, type, vece, + tcgv_vec_arg(l1), tcgv_vec_arg(v1)); + vec_gen_2(INDEX_op_s390_vupl_vec, type, vece, + tcgv_vec_arg(l2), tcgv_vec_arg(v2)); + + /* Arithmetic on a wider element size. */ + vec_gen_3(add_sub_opc, type, vece + 1, tcgv_vec_arg(h1), + tcgv_vec_arg(h1), tcgv_vec_arg(h2)); + vec_gen_3(add_sub_opc, type, vece + 1, tcgv_vec_arg(l1), + tcgv_vec_arg(l1), tcgv_vec_arg(l2)); + + /* Pack with saturation. */ + vec_gen_3(INDEX_op_s390_vpks_vec, type, vece + 1, + tcgv_vec_arg(v0), tcgv_vec_arg(h1), tcgv_vec_arg(l1)); + + tcg_temp_free_vec(h1); + tcg_temp_free_vec(h2); + tcg_temp_free_vec(l1); + tcg_temp_free_vec(l2); +} + void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, TCGArg a0, ...) { @@ -2885,6 +2938,13 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, tcg_temp_free_vec(t0); break; + case INDEX_op_ssadd_vec: + expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_add_vec); + break; + case INDEX_op_sssub_vec: + expand_vec_sat(type, vece, v0, v1, v2, INDEX_op_sub_vec); + break; + default: g_assert_not_reached(); } @@ -3045,6 +3105,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_sari_vec: case INDEX_op_shli_vec: case INDEX_op_shri_vec: + case INDEX_op_s390_vuph_vec: + case INDEX_op_s390_vupl_vec: return C_O1_I1(v, v); case INDEX_op_add_vec: case INDEX_op_sub_vec: @@ -3064,6 +3126,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_smin_vec: case INDEX_op_umax_vec: case INDEX_op_umin_vec: + case INDEX_op_s390_vpks_vec: return C_O1_I2(v, v, v); case INDEX_op_rotls_vec: case INDEX_op_shls_vec: From patchwork Mon Feb 8 02:51:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 378502 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp4336885jah; Sun, 7 Feb 2021 19:38:54 -0800 (PST) X-Google-Smtp-Source: ABdhPJzSs6y5g60DEhBUU8EuYQNejo2qsymdiu+3MaHyPLPTs1neGIk1dZIflCrRnrZ2iKPbaAJs X-Received: by 2002:a25:a062:: with SMTP id x89mr23571893ybh.88.1612755534652; Sun, 07 Feb 2021 19:38:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612755534; cv=none; d=google.com; s=arc-20160816; b=C4K35Bf7n3FLJ+f9y68Xxfr3HZ7vfcatUnJigd54EjeNzOSk3KP/PPEAVN65s63ldM DYxiKV46X9gWddvY+lFu0U4kNj35SR16MdcpjiCDT03ATxTatpfjxjvwb/B8Ba3/4yC/ OKBk3D1HnrkYyprF/JnhVzdi5rFFujr790Uzgq1kK+DEBq5vVUowHX0p4pLDtKn2i4zE kq7VGsASnE4lTiGlZx5/+Wr++InFEWNZnJR2Siigx3pkhDayVBWhWA+8XImDwJGtlYAi Fts3HsgmpJFEUZH3NfrpRKQNYc6In3ERFrE3XsGAQpEVp+MK9GxuQ2X2fG0DPWtfvJYN 8Qtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=YmDqe/82SlyxP6c0GtyFsHwbtixl9cebfPdkUT3Hqik=; b=Ckt7ORBmt6odyzjBGvH8pWvtq5tV0NraCFJk/aFeXf1VLMv0Ot63Z5G5eCR2VcPbJ0 ez8b+asmEhGH7BXpmb1Gs4Uk8SMtPLFdT6a5i1jf0+mDJWVzDO0BO2YKL0s6g42uLmAB gmuKCo0muo2Z483C3UTB9EvwbB6lZ0y3Y0Vji4V6JnSqhKZrNu6vrOQVDTn+I1tBYMez S/6dnAeLUZkHZLX5/WXd+OhAkcy2/5Dbbt2mkL7Enb0SPSYcvpCqlidU/79S2N4d21Lj hKybZMBGsY4awd4DPkQRNHuQG48w6/9R9MkU0BKJIUVZhbm5stiqtXe+CIze46v0DM7t PEoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sqW2NuHd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 15/16] tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec Date: Sun, 7 Feb 2021 18:51:00 -0800 Message-Id: <20210208025101.271726-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208025101.271726-1-richard.henderson@linaro.org> References: <20210208025101.271726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 1 + tcg/s390x/tcg-target.h | 2 +- tcg/s390x/tcg-target.c.inc | 20 ++++++++++++++++++++ 3 files changed, 22 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h index 49b98f33b9..426dd92e51 100644 --- a/tcg/s390x/tcg-target-con-set.h +++ b/tcg/s390x/tcg-target-con-set.h @@ -26,6 +26,7 @@ C_O1_I2(r, r, ri) C_O1_I2(r, rZ, r) C_O1_I2(v, v, r) C_O1_I2(v, v, v) +C_O1_I3(v, v, v, v) C_O1_I4(r, r, ri, r, 0) C_O1_I4(r, r, ri, rI, 0) C_O2_I2(b, a, 0, r) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index efa32f348c..127ccd30af 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -154,7 +154,7 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_mul_vec 1 #define TCG_TARGET_HAS_sat_vec 0 #define TCG_TARGET_HAS_minmax_vec 1 -#define TCG_TARGET_HAS_bitsel_vec 0 +#define TCG_TARGET_HAS_bitsel_vec 1 #define TCG_TARGET_HAS_cmpsel_vec 0 /* used for function call generation */ diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index d4877dcf67..3c86b233b0 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -296,6 +296,7 @@ typedef enum S390Opcode { VRRa_VUPH = 0xe7d7, VRRa_VUPL = 0xe7d6, VRRc_VX = 0xe76d, + VRRe_VSEL = 0xe78d, VRRf_VLVGP = 0xe762, VRSa_VERLL = 0xe733, @@ -635,6 +636,18 @@ static void tcg_out_insn_VRRc(TCGContext *s, S390Opcode op, tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, 0) | (m4 << 12)); } +static void tcg_out_insn_VRRe(TCGContext *s, S390Opcode op, + TCGReg v1, TCGReg v2, TCGReg v3, TCGReg v4) +{ + tcg_debug_assert(v1 >= TCG_REG_V0 && v1 <= TCG_REG_V31); + tcg_debug_assert(v2 >= TCG_REG_V0 && v2 <= TCG_REG_V31); + tcg_debug_assert(v3 >= TCG_REG_V0 && v3 <= TCG_REG_V31); + tcg_debug_assert(v4 >= TCG_REG_V0 && v4 <= TCG_REG_V31); + tcg_out16(s, (op & 0xff00) | ((v1 & 15) << 4) | (v2 & 15)); + tcg_out16(s, v3 << 12); + tcg_out16(s, (op & 0x00ff) | RXB(v1, v2, v3, v4) | ((v4 & 15) << 12)); +} + static void tcg_out_insn_VRRf(TCGContext *s, S390Opcode op, TCGReg v1, TCGReg r2, TCGReg r3) { @@ -2752,6 +2765,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, tcg_out_insn(s, VRRc, VMXL, a0, a1, a2, vece); break; + case INDEX_op_bitsel_vec: + tcg_out_insn(s, VRRe, VSEL, a0, a1, a2, args[3]); + break; + case INDEX_op_cmp_vec: switch ((TCGCond)args[3]) { case TCG_COND_EQ: @@ -2792,6 +2809,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_add_vec: case INDEX_op_and_vec: case INDEX_op_andc_vec: + case INDEX_op_bitsel_vec: case INDEX_op_neg_vec: case INDEX_op_not_vec: case INDEX_op_or_vec: @@ -3133,6 +3151,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_shrs_vec: case INDEX_op_sars_vec: return C_O1_I2(v, v, r); + case INDEX_op_bitsel_vec: + return C_O1_I3(v, v, v, v); default: g_assert_not_reached(); From patchwork Mon Feb 8 02:51:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 378512 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp4341054jah; Sun, 7 Feb 2021 19:47:21 -0800 (PST) X-Google-Smtp-Source: ABdhPJzhkPMh91vFPXi1wo7tAgKz2aFvFA8jRPBrGS0kT+l/GhH2/GLbG7YdgooMbGw/5uKedXaV X-Received: by 2002:a25:4b02:: with SMTP id y2mr22184286yba.353.1612756041684; Sun, 07 Feb 2021 19:47:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612756041; cv=none; d=google.com; s=arc-20160816; b=PIZnLmMPw3QxlzWKOwb8yuvrsB5Z+mjb6uLTKLkn8gxTJHMEwDRWJ2d+rxgJuKGvUw ELidEbbd87u/6ZknkpdqSvQ2+3t0OmHzdK7JMJp1tQ0DqS3lFUvxrM94HWcxwgaUVmvg JTEQ6N08Dy6cE6Ev5gP6V20I+BOMY5/kRKCWqhnenn4/bb8vXvkPwqrLfo+TfAuzDmJd D2eMQI9gY4jIOkINNh1o9U1gRw1l0hregLQmAIcmFt/CKUTFnLqzElWf2jaY1p9Hh0tx Uc8YMrd6l9HPoDdvyT7gdTsyP0OCozyYTTK+NwulvH/drJuubPs/tb9E+tgtukV1wG/w B7BA== ARC-Message-Signature: i=1; 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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id p12sm10308690pju.35.2021.02.07.18.51.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 18:51:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 16/16] tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vec Date: Sun, 7 Feb 2021 18:51:01 -0800 Message-Id: <20210208025101.271726-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210208025101.271726-1-richard.henderson@linaro.org> References: <20210208025101.271726-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is via expansion; don't actually set TCG_TARGET_HAS_cmpsel_vec. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) -- 2.25.1 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 3c86b233b0..1888c7a5b4 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -2834,6 +2834,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_xor_vec: return 1; case INDEX_op_cmp_vec: + case INDEX_op_cmpsel_vec: case INDEX_op_rotrv_vec: return -1; case INDEX_op_mul_vec: @@ -2896,6 +2897,21 @@ static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, } } +static void expand_vec_cmpsel(TCGType type, unsigned vece, TCGv_vec v0, + TCGv_vec c1, TCGv_vec c2, + TCGv_vec v3, TCGv_vec v4, TCGCond cond) +{ + TCGv_vec t = tcg_temp_new_vec(type); + + if (expand_vec_cmp_noinv(type, vece, t, c1, c2, cond)) { + /* Invert the sense of the compare by swapping arguments. */ + tcg_gen_bitsel_vec(vece, v0, t, v4, v3); + } else { + tcg_gen_bitsel_vec(vece, v0, t, v3, v4); + } + tcg_temp_free_vec(t); +} + static void expand_vec_sat(TCGType type, unsigned vece, TCGv_vec v0, TCGv_vec v1, TCGv_vec v2, TCGOpcode add_sub_opc) { @@ -2937,7 +2953,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, TCGArg a0, ...) { va_list va; - TCGv_vec v0, v1, v2, t0; + TCGv_vec v0, v1, v2, v3, v4, t0; va_start(va, a0); v0 = temp_tcgv_vec(arg_temp(a0)); @@ -2949,6 +2965,12 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); break; + case INDEX_op_cmpsel_vec: + v3 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + v4 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); + expand_vec_cmpsel(type, vece, v0, v1, v2, v3, v4, va_arg(va, TCGArg)); + break; + case INDEX_op_rotrv_vec: t0 = tcg_temp_new_vec(type); tcg_gen_neg_vec(vece, t0, v2);