From patchwork Tue Feb 9 09:51:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 379297 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp65172jah; Tue, 9 Feb 2021 01:47:24 -0800 (PST) X-Google-Smtp-Source: ABdhPJyFYIEb1VTWrzDvmkNl6c0MtuLLSL0+QAtWjfQvoaJX2h+uKJ49cQFznK1NG6ZGggFZh/KD X-Received: by 2002:a17:906:d935:: with SMTP id rn21mr21541021ejb.443.1612864044796; Tue, 09 Feb 2021 01:47:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612864044; cv=none; d=google.com; s=arc-20160816; b=qThozBW8x/Kh2olB4Dz3IJgUJELfj6uOPgeSwXEIg4AjcIBUIuEmn99fGdrEUohfrP 4YOilxv51DOZYjFDHG73UBczv92r+MVg5ahZSki3iX0uZMMy/0jXjECwbakrsJAcLeKj odM8bXWWPpxpzeCMkoixpxYLghMr3mCRhWht8z3XgZHgQ2a6OrO8TFfSvr+J27KJ4qMR tYXDFIIZgGUkNphKMpBOqHNgjhbdB3B8mU6qomjWiZKBpmIPqb2RWjPcaKixT5TRTR86 Et0Eo+lQYNwmqhT5nICh4GwjOik8Ft7LcgrWEnsKpXnghVY++urFMANsTbMre2aAI6Gx aLRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:message-id:date:subject:cc:to:from :dkim-signature; bh=5XAWwQ+uVP5pL2TbZZCQGiFx0hS1pDt93D8wDUbYErw=; b=EOxrt595WnFFaYL2vDqykWLvSZ6WbI65ve7XqRarkFlgnmxQ6XbF/PrFnVNNE/WAPR RgBbBrRFnfYwYFNbMWgYKj/xJyZkmU0g1L1P1isSGDoRxPWVfWfbhLl6sZVaTjoO/l3R a69ufIWVE89TFGyUatiJrA0D+PNxQ1EuiR4SW/8iv4nGjlJYSnsDnDpF7P0pbb+Y0360 KqI78D73A7bYYCvHZKgUkH6dkr150phjGnwZeqSAIXj/28FA+WEP4NCAsQ5mOUbW9dR+ uwzRWyaKh4Y+sbaglmQNFp5+pKyjeQdHe4fpgUBGPkIK0cljfy4DwceYnHV6dgLDjezM FXlA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KEY1CUzr; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id hq38si12262318ejc.21.2021.02.09.01.47.24; Tue, 09 Feb 2021 01:47:24 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KEY1CUzr; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230256AbhBIJq2 (ORCPT + 16 others); Tue, 9 Feb 2021 04:46:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36502 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230363AbhBIJoY (ORCPT ); Tue, 9 Feb 2021 04:44:24 -0500 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3AB2BC061793 for ; Tue, 9 Feb 2021 01:43:44 -0800 (PST) Received: by mail-wr1-x42f.google.com with SMTP id g6so7799054wrs.11 for ; Tue, 09 Feb 2021 01:43:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=5XAWwQ+uVP5pL2TbZZCQGiFx0hS1pDt93D8wDUbYErw=; b=KEY1CUzrkh5YnoT1x+qo4clOUvxyclwMfw7XKgKpWYLMV/OpwnL1X7xccdEJo92qiu xC2NaJqHTH2kGd0EigMdTvM9IbM2nLmqF9mdtTAQW2dc8OMNJQZsoghI0f55L1G0VFey hCCUAYQNVBfZRrsSQc2x7emVLjVJuhzNyYtNgMEisSQ4T2WdkpnPeib++79e/WKbFf1y S3T+GL6k3T4pnrr4Y537nnKPBmZsLLetoF81IQqyXMh6zJeiPo2cTN2Eb1fiPr3sNxis tzKXXgdBeHuZuKmpIjXE4MBOGh2C5AavSrNZgoLDp/hn8MymWXdS5CUsCM9zj0T2IAf5 +BkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=5XAWwQ+uVP5pL2TbZZCQGiFx0hS1pDt93D8wDUbYErw=; b=NQU1q4JIzooypZlEyc8Hr1xKULM+derND2hqc47dRchwTgMAJ61Etx/u+G7Z1dQLBp yUfesXwxQQu/GMjwAAsWRhBfu+Oe210XXH0A5k/UO/DNSACd6PiMe6zybhS0qWkjzTIu v2H4iBPMQlqPMKFOxAvGgkWMeksru3kuw9JU8dcs2MTJLDmjWJn8TvFuKE7F520NlYLa PIhJTsutcK5Oy20a2Ob0qQe8/sMj3sym7ppcGeN8wxmSgorpmiLpgducsi29GD4BH4hL hFa0fuhr8ldAj9g92lYDEF0416T8giOfAv5jeQvNCTfnI0PyZFMQndT0Em11OI2VFf6K TM0A== X-Gm-Message-State: AOAM530fnZTAahfdThoYIcMI5fu8mqkK0eMKXp+bwWvA8vLry/CrEZVh 42w/6QxvjhRNhHR50Q28glanZg== X-Received: by 2002:a05:6000:192:: with SMTP id p18mr1777663wrx.403.1612863822898; Tue, 09 Feb 2021 01:43:42 -0800 (PST) Received: from localhost.localdomain ([88.122.66.28]) by smtp.gmail.com with ESMTPSA id u3sm39444168wre.54.2021.02.09.01.43.42 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 09 Feb 2021 01:43:42 -0800 (PST) From: Loic Poulain To: manivannan.sadhasivam@linaro.org, hemantk@codeaurora.org Cc: linux-arm-msm@vger.kernel.org, carl.yin@quectel.com, mpearson@lenovo.com, cchen50@lenovo.com, jwjiang@lenovo.com, ivan.zhang@quectel.com, naveen.kumar@quectel.com, ivan.mikhanchuk@quectel.com, Loic Poulain Subject: [PATCH v2 1/2] mhi: pci_generic: Parametrable element count for events Date: Tue, 9 Feb 2021 10:51:45 +0100 Message-Id: <1612864306-10108-1-git-send-email-loic.poulain@linaro.org> X-Mailer: git-send-email 2.7.4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Not all hardwares need to use the same number of event ring elements. This change makes this parametrable. Signed-off-by: Loic Poulain --- v2: add this change to the series drivers/bus/mhi/pci_generic.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index 8187fcf..c58bf96 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -71,9 +71,9 @@ struct mhi_pci_dev_info { .doorbell_mode_switch = false, \ } -#define MHI_EVENT_CONFIG_CTRL(ev_ring) \ +#define MHI_EVENT_CONFIG_CTRL(ev_ring, el_count) \ { \ - .num_elements = 64, \ + .num_elements = el_count, \ .irq_moderation_ms = 0, \ .irq = (ev_ring) + 1, \ .priority = 1, \ @@ -114,9 +114,9 @@ struct mhi_pci_dev_info { .doorbell_mode_switch = true, \ } -#define MHI_EVENT_CONFIG_DATA(ev_ring) \ +#define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \ { \ - .num_elements = 128, \ + .num_elements = el_count, \ .irq_moderation_ms = 5, \ .irq = (ev_ring) + 1, \ .priority = 1, \ @@ -127,9 +127,9 @@ struct mhi_pci_dev_info { .offload_channel = false, \ } -#define MHI_EVENT_CONFIG_HW_DATA(ev_ring, ch_num) \ +#define MHI_EVENT_CONFIG_HW_DATA(ev_ring, el_count, ch_num) \ { \ - .num_elements = 2048, \ + .num_elements = el_count, \ .irq_moderation_ms = 1, \ .irq = (ev_ring) + 1, \ .priority = 1, \ @@ -156,12 +156,12 @@ static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { static struct mhi_event_config modem_qcom_v1_mhi_events[] = { /* first ring is control+data ring */ - MHI_EVENT_CONFIG_CTRL(0), + MHI_EVENT_CONFIG_CTRL(0, 64), /* DIAG dedicated event ring */ - MHI_EVENT_CONFIG_DATA(1), + MHI_EVENT_CONFIG_DATA(1, 128), /* Hardware channels request dedicated hardware event rings */ - MHI_EVENT_CONFIG_HW_DATA(2, 100), - MHI_EVENT_CONFIG_HW_DATA(3, 101) + MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), + MHI_EVENT_CONFIG_HW_DATA(3, 2048, 101) }; static struct mhi_controller_config modem_qcom_v1_mhiv_config = { From patchwork Tue Feb 9 09:51:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Loic Poulain X-Patchwork-Id: 379298 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp65184jah; Tue, 9 Feb 2021 01:47:25 -0800 (PST) X-Google-Smtp-Source: ABdhPJxkkMBne2Bf24BMNPB+jmj9MoSspjfAF8AdwGe3PgPNgGz48IPEA7zgc09NijSHmZoPylME X-Received: by 2002:a17:906:e104:: with SMTP id gj4mr21244772ejb.349.1612864045621; Tue, 09 Feb 2021 01:47:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612864045; cv=none; d=google.com; s=arc-20160816; b=B7TJkklLl+gnQ+nuWX/m/XGhtxJK5w6bQ1lNnmNylTQOLchMqsNNcWeK82oeZzgkId oIStPfkKMEU1GX86hjPg894KpZQMvts8xUCVcNUjLehQoHn69gO+4ytGj1fWltBO2qql Q9oLGdcexQ2o2MNdgAmowl2XsnE7o3P6qwYS14Z+SOJh7pittcwZyLuxtI/C3yS4CQlN 7u5w+5Ec3ZihUkDBD2iVQIIfDSHP0aZcF8Wd8hFKPO79VJWRGtBbNiPkWUwjztg5qUMv uriizxNUfTUzeHaNWPZfLZpu83SXNkjBY3KUDqOk6xmna7jjBJCGljoD7pCDa6cssist WQ7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=/vf1mB4T1/394CEX0VM8YVRJCvYayOVx/u5Plqvs+cE=; b=1K1TGK0Pur7vNOjWPscXrHiqFWraz1Y2vLNyLDse1v13qYEL74NaEpbW3eGfjxSXyz mfFVCX5NZiRF8yrmHGd+6Pra9laxXb+FiGDOdNcJr705FraIghUUz36/pXldrI7xAoqG iSsccm2KJk1HEucJ6kLJb+b6On4zO3/G8Sh47pDLxbk3vpMQLjrEBpzvjhbPIopLZYLo dBnxU8RiR5SGBsKTo1LtJ93MXLOj2j6Hjeqt9PW3AyDHEPjHRbJ5YF8QGnqtdtwdKH1U E43DrrdJGriA3FgL7QRoUkfX/Ycx7rUamlbAXLCxDr2Ggu+W2PqxANhdGwmx1pR5vH/9 W2RA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MwkMTrh+; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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The modem is mainly based on MBIM protocol for both the data and control path. The drivers for these channels (mhi-net-mbim and mhi_uci) are not yet part of the kernel but will be integrated by different series. Signed-off-by: Loic Poulain --- v2: Specify 256 elements for the hardware event rings drivers/bus/mhi/pci_generic.c | 73 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) -- 2.7.4 diff --git a/drivers/bus/mhi/pci_generic.c b/drivers/bus/mhi/pci_generic.c index c58bf96..56bd9ed 100644 --- a/drivers/bus/mhi/pci_generic.c +++ b/drivers/bus/mhi/pci_generic.c @@ -114,6 +114,36 @@ struct mhi_pci_dev_info { .doorbell_mode_switch = true, \ } +#define MHI_CHANNEL_CONFIG_UL_SBL(ch_num, ch_name, el_count, ev_ring) \ + { \ + .num = ch_num, \ + .name = ch_name, \ + .num_elements = el_count, \ + .event_ring = ev_ring, \ + .dir = DMA_TO_DEVICE, \ + .ee_mask = BIT(MHI_EE_SBL), \ + .pollcfg = 0, \ + .doorbell = MHI_DB_BRST_DISABLE, \ + .lpm_notify = false, \ + .offload_channel = false, \ + .doorbell_mode_switch = false, \ + } \ + +#define MHI_CHANNEL_CONFIG_DL_SBL(ch_num, ch_name, el_count, ev_ring) \ + { \ + .num = ch_num, \ + .name = ch_name, \ + .num_elements = el_count, \ + .event_ring = ev_ring, \ + .dir = DMA_FROM_DEVICE, \ + .ee_mask = BIT(MHI_EE_SBL), \ + .pollcfg = 0, \ + .doorbell = MHI_DB_BRST_DISABLE, \ + .lpm_notify = false, \ + .offload_channel = false, \ + .doorbell_mode_switch = false, \ + } + #define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \ { \ .num_elements = el_count, \ @@ -182,9 +212,52 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { .dma_data_width = 32 }; +static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = { + MHI_CHANNEL_CONFIG_UL(0, "NMEA", 16, 0), + MHI_CHANNEL_CONFIG_DL(1, "NMEA", 16, 0), + MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 16, 0), + MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 16, 0), + MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1), + MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1), + MHI_CHANNEL_CONFIG_UL(12, "MBIM", 16, 0), + MHI_CHANNEL_CONFIG_DL(13, "MBIM", 16, 0), + MHI_CHANNEL_CONFIG_UL(32, "DUN", 8, 0), + MHI_CHANNEL_CONFIG_DL(33, "DUN", 8, 0), + MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), + MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), +}; + +static struct mhi_event_config mhi_quectel_em1xx_events[] = { + MHI_EVENT_CONFIG_CTRL(0, 128), + MHI_EVENT_CONFIG_DATA(1, 128), + MHI_EVENT_CONFIG_HW_DATA(2, 256, 100), + MHI_EVENT_CONFIG_HW_DATA(3, 256, 101) +}; + +static struct mhi_controller_config modem_quectel_em1xx_config = { + .max_channels = 128, + .timeout_ms = 8000, + .num_channels = ARRAY_SIZE(mhi_quectel_em1xx_channels), + .ch_cfg = mhi_quectel_em1xx_channels, + .num_events = ARRAY_SIZE(mhi_quectel_em1xx_events), + .event_cfg = mhi_quectel_em1xx_events, +}; + +static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { + .name = "quectel-em1xx", + .edl = "quectel/prog_firehose_sdx24.mbn", + .config = &modem_quectel_em1xx_config, + .bar_num = MHI_PCI_DEFAULT_BAR_NUM, + .dma_data_width = 32 +}; + static const struct pci_device_id mhi_pci_id_table[] = { { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306), .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info }, + { PCI_DEVICE(0x1eac, 0x1001), /* EM120R-GL (sdx24) */ + .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, + { PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL (sdx24) */ + .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, { } }; MODULE_DEVICE_TABLE(pci, mhi_pci_id_table);