From patchwork Tue Feb 9 12:47:55 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 379346 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp192040jah; Tue, 9 Feb 2021 04:50:33 -0800 (PST) X-Google-Smtp-Source: ABdhPJz5buGSGp6bnkQJE6BgVQyN+C0H129aayY8/nc/8ajP/39uLMYc9no6EEvp2C6faf0L46VO X-Received: by 2002:aa7:de8f:: with SMTP id j15mr22797050edv.268.1612875033386; Tue, 09 Feb 2021 04:50:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612875033; cv=none; d=google.com; s=arc-20160816; b=Jw4tQiz+gJfq7wqKykGcLJ6G+DOen8jayQttA9zlQ6eFkhpENJKOgEOxcD7bP+E3If 2D8KDHXbo3Oqxp6Vz/mIxxOfl6boEd1Zgdbm5YZUCpEWx8oPe/GPFYDuWZBb6kuo1x0R Hx8vyL/QqfY8PfI/wWShYTDM/wxBTpAysOhARcbeaCSXhLl1mhWWNul33yd2DeXOmFt8 W/BWXOGonpaJ5l6KUbe/U5VHPuRMT0wbboGHo8D8MWM20qFmjqERVxacXUzhu0dOeS2N rsB+h04J5a6jb10Sb0fUNK5QciEwgW7YTUUuMvRhPv68zmjn6o8mwEjOHgQwgGPKiaGR qGcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Xp4VsyxHOqEhAHKGKETwGM5yW+arT2DW9ndgALlXFUI=; b=RrpYlDbbif0gZUvJ2C8ymfluUw2QULuRJXyZLodVIQHqrJcWIsWVcNU4PpuVRVomGx Lon1XX/dzSG1Sr9g+3G8NeeqxbkSovtmoQTxvVegf1Z53NqEgiYHjMNOjRFLLztWovGy SRlKCjokromyIOEiJw0IGgPP+fKYQDKTM9b4kTjvJcDrfL+nlwoYvuSGSW05M8kW5ars sBBA9l1M7PYl/cYP3SQcKxbk1BPfhsjuovdX9df4wbJM+0K/yzEPelFHy9W2o52HyA6E TzZE9Bya3DGOJD3I2xztAhVde2qQVVbVcB4gUWQ0LL8xQB+k4dv1jE561vL53a2e5nBz S9Ew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VJQgEYgh; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id q7si14328136edt.86.2021.02.09.04.50.33; Tue, 09 Feb 2021 04:50:33 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VJQgEYgh; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229626AbhBIMtu (ORCPT + 16 others); Tue, 9 Feb 2021 07:49:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229880AbhBIMsw (ORCPT ); Tue, 9 Feb 2021 07:48:52 -0500 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E8F8AC06178A for ; Tue, 9 Feb 2021 04:48:10 -0800 (PST) Received: by mail-lf1-x12c.google.com with SMTP id j19so7798476lfr.12 for ; Tue, 09 Feb 2021 04:48:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Xp4VsyxHOqEhAHKGKETwGM5yW+arT2DW9ndgALlXFUI=; b=VJQgEYgh/6TlrvPjTOFLEaycDf/O++jvI4hnbuHqHs4c4ucVlCf7Q7c1A18kwLLPqT IYhxk9rQiRsFYqt5OpupEgTcf6LK9plghgxO/r+31vKhcZKQzPBHy7NzhAzSTHePQblK 0m+78GAXYNlse6Oizy8BvnRxlPsVGd41EG0hfNjO4v+DtTYioZfnl4qgYHQAWQCgogUH 75u//HxfjT1o0l5pqartI4tJH+ve40HkQ+pv4Ylk69L3PfzM22sDTqduc8tLKp0wRFUv nCiD4bls5m5WUcc/rK88wgMu5r48x8qtnLhZghDbQddFDY6lbnAdgzUrX8BWDQJk8+oP kf+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Xp4VsyxHOqEhAHKGKETwGM5yW+arT2DW9ndgALlXFUI=; b=taiziAVFVYaXI9kLjuzNFq9h5mD3eR91fwmXNcGE3ESpc1BMWeIKeDl+uQXRExVv9d HjbnAF9Le5R4uZjg0OVh2XeW6YNh5ERaZfW9QE1xysiV3jskcU5KhkeQghNrnQniso5C pYT496492c5t3zphSOdNNAEzjqANggwUWHteXu2xv7x8E/PVoYLWJKUyD+2p5sGm+Vcr cOcjfmIXCb1JUrso3OugWof3ahWsnKpdnov95eenAtDNlvqSNRIvUTxyBw4ORFzADOQL mgNyz7gxcOQ4ybxH9BT39sE+JKtZRuT6S5Dt5jAVdtDc7byIB67IxhnKs7VI4PXCcJsH xm0g== X-Gm-Message-State: AOAM533DdBFeJ8Qz1qMu1qdLZ7JXIZFeLFTv3dpscFa1PuNZ3mTaGFGl hF+GyTG/ielrXTemdas4K+TcAHiFoqevW7aZ X-Received: by 2002:a19:88d7:: with SMTP id k206mr13344264lfd.476.1612874889251; Tue, 09 Feb 2021 04:48:09 -0800 (PST) Received: from eriador.lan ([94.25.229.138]) by smtp.gmail.com with ESMTPSA id e16sm1220653ljn.105.2021.02.09.04.48.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Feb 2021 04:48:08 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Doug Anderson Cc: linux-arm-msm@vger.kernel.org Subject: [PATCH v2 1/4] arm64: dts: qcom: sm8250: split spi pinctrl config Date: Tue, 9 Feb 2021 15:47:55 +0300 Message-Id: <20210209124758.990681-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210209124758.990681-1-dmitry.baryshkov@linaro.org> References: <20210209124758.990681-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org As discussed on linux-arm-msm list, start splitting sm8250 pinctrl settings into generic and board-specific parts. The first part to receive such treatment is the spi, so split spi pinconf to the board device tree. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 5 + arch/arm64/boot/dts/qcom/sm8250.dtsi | 300 +++++------------------ 2 files changed, 65 insertions(+), 240 deletions(-) -- 2.30.0 diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 2f0528d01299..787da8ccba54 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -815,6 +815,11 @@ &pm8150_rtc { status = "okay"; }; +&qup_spi0_default { + drive-strength = <6>; + bias-disable; +}; + &qupv3_id_0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 947e1accae3a..51d103671759 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2984,303 +2984,123 @@ config { }; qup_spi0_default: qup-spi0-default { - mux { - pins = "gpio28", "gpio29", - "gpio30", "gpio31"; - function = "qup0"; - }; - - config { - pins = "gpio28", "gpio29", - "gpio30", "gpio31"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio28", "gpio29", + "gpio30", "gpio31"; + function = "qup0"; }; qup_spi1_default: qup-spi1-default { - mux { - pins = "gpio4", "gpio5", - "gpio6", "gpio7"; - function = "qup1"; - }; - - config { - pins = "gpio4", "gpio5", - "gpio6", "gpio7"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "qup1"; }; qup_spi2_default: qup-spi2-default { - mux { - pins = "gpio115", "gpio116", - "gpio117", "gpio118"; - function = "qup2"; - }; - - config { - pins = "gpio115", "gpio116", - "gpio117", "gpio118"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio115", "gpio116", + "gpio117", "gpio118"; + function = "qup2"; }; qup_spi3_default: qup-spi3-default { - mux { - pins = "gpio119", "gpio120", - "gpio121", "gpio122"; - function = "qup3"; - }; - - config { - pins = "gpio119", "gpio120", - "gpio121", "gpio122"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio119", "gpio120", + "gpio121", "gpio122"; + function = "qup3"; }; qup_spi4_default: qup-spi4-default { - mux { - pins = "gpio8", "gpio9", - "gpio10", "gpio11"; - function = "qup4"; - }; - - config { - pins = "gpio8", "gpio9", - "gpio10", "gpio11"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "qup4"; }; qup_spi5_default: qup-spi5-default { - mux { - pins = "gpio12", "gpio13", - "gpio14", "gpio15"; - function = "qup5"; - }; - - config { - pins = "gpio12", "gpio13", - "gpio14", "gpio15"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio12", "gpio13", + "gpio14", "gpio15"; + function = "qup5"; }; qup_spi6_default: qup-spi6-default { - mux { - pins = "gpio16", "gpio17", - "gpio18", "gpio19"; - function = "qup6"; - }; - - config { - pins = "gpio16", "gpio17", - "gpio18", "gpio19"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + function = "qup6"; }; qup_spi7_default: qup-spi7-default { - mux { - pins = "gpio20", "gpio21", - "gpio22", "gpio23"; - function = "qup7"; - }; - - config { - pins = "gpio20", "gpio21", - "gpio22", "gpio23"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio20", "gpio21", + "gpio22", "gpio23"; + function = "qup7"; }; qup_spi8_default: qup-spi8-default { - mux { - pins = "gpio24", "gpio25", - "gpio26", "gpio27"; - function = "qup8"; - }; - - config { - pins = "gpio24", "gpio25", - "gpio26", "gpio27"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio24", "gpio25", + "gpio26", "gpio27"; + function = "qup8"; }; qup_spi9_default: qup-spi9-default { - mux { - pins = "gpio125", "gpio126", - "gpio127", "gpio128"; - function = "qup9"; - }; - - config { - pins = "gpio125", "gpio126", - "gpio127", "gpio128"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio125", "gpio126", + "gpio127", "gpio128"; + function = "qup9"; }; qup_spi10_default: qup-spi10-default { - mux { - pins = "gpio129", "gpio130", - "gpio131", "gpio132"; - function = "qup10"; - }; - - config { - pins = "gpio129", "gpio130", - "gpio131", "gpio132"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio129", "gpio130", + "gpio131", "gpio132"; + function = "qup10"; }; qup_spi11_default: qup-spi11-default { - mux { - pins = "gpio60", "gpio61", - "gpio62", "gpio63"; - function = "qup11"; - }; - - config { - pins = "gpio60", "gpio61", - "gpio62", "gpio63"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio60", "gpio61", + "gpio62", "gpio63"; + function = "qup11"; }; qup_spi12_default: qup-spi12-default { - mux { - pins = "gpio32", "gpio33", - "gpio34", "gpio35"; - function = "qup12"; - }; - - config { - pins = "gpio32", "gpio33", - "gpio34", "gpio35"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio32", "gpio33", + "gpio34", "gpio35"; + function = "qup12"; }; qup_spi13_default: qup-spi13-default { - mux { - pins = "gpio36", "gpio37", - "gpio38", "gpio39"; - function = "qup13"; - }; - - config { - pins = "gpio36", "gpio37", - "gpio38", "gpio39"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio36", "gpio37", + "gpio38", "gpio39"; + function = "qup13"; }; qup_spi14_default: qup-spi14-default { - mux { - pins = "gpio40", "gpio41", - "gpio42", "gpio43"; - function = "qup14"; - }; - - config { - pins = "gpio40", "gpio41", - "gpio42", "gpio43"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio40", "gpio41", + "gpio42", "gpio43"; + function = "qup14"; }; qup_spi15_default: qup-spi15-default { - mux { - pins = "gpio44", "gpio45", - "gpio46", "gpio47"; - function = "qup15"; - }; - - config { - pins = "gpio44", "gpio45", - "gpio46", "gpio47"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio44", "gpio45", + "gpio46", "gpio47"; + function = "qup15"; }; qup_spi16_default: qup-spi16-default { - mux { - pins = "gpio48", "gpio49", - "gpio50", "gpio51"; - function = "qup16"; - }; - - config { - pins = "gpio48", "gpio49", - "gpio50", "gpio51"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio48", "gpio49", + "gpio50", "gpio51"; + function = "qup16"; }; qup_spi17_default: qup-spi17-default { - mux { - pins = "gpio52", "gpio53", - "gpio54", "gpio55"; - function = "qup17"; - }; - - config { - pins = "gpio52", "gpio53", - "gpio54", "gpio55"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio52", "gpio53", + "gpio54", "gpio55"; + function = "qup17"; }; qup_spi18_default: qup-spi18-default { - mux { - pins = "gpio56", "gpio57", - "gpio58", "gpio59"; - function = "qup18"; - }; - - config { - pins = "gpio56", "gpio57", - "gpio58", "gpio59"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio56", "gpio57", + "gpio58", "gpio59"; + function = "qup18"; }; qup_spi19_default: qup-spi19-default { - mux { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - function = "qup19"; - }; - - config { - pins = "gpio0", "gpio1", - "gpio2", "gpio3"; - drive-strength = <6>; - bias-disable; - }; + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "qup19"; }; qup_uart2_default: qup-uart2-default { From patchwork Tue Feb 9 12:47:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 379347 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp192056jah; Tue, 9 Feb 2021 04:50:34 -0800 (PST) X-Google-Smtp-Source: ABdhPJz80pdsr0fk3lnjdqeOmruSANb0TJZmmfnbb00Cb9edp79YK5Z4uFwCDvPNoAQ7GCBvm22m X-Received: by 2002:aa7:d656:: with SMTP id v22mr22639333edr.349.1612875033787; Tue, 09 Feb 2021 04:50:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612875033; cv=none; d=google.com; s=arc-20160816; b=Vsrz9YJh5AvC359T4LWlWHUecVpiCJtgKtf7Us54l7nRxjNeCbkkm4CWCF0p2mZ+CZ ftEk/20cA3ek65G61/f/2Jms0vpZjdLg4oD11cyB4VqCC/SOvTsauVBDaukE28U25e2p 6t7FuuCTftRmLxhYm1uRyRVccxCVMrxpNsssJ40t4DhWljnyh0dxEYWx6+UocHF1LTPt FKE6uMuKGlW94cAu3f8P/VVrBEBU6Z1sqcVGdWoG7pkWlI1YO4DRIhYPp7U00KAfo8tV /dkeVTgDB0uz8vRtHa6aI1JQMaATBbGZyPBI41qOiZMTNbUz9v1MpgXeTpzi3mMB6NYc OYVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9yYw/slrRYfwVyi4Hj3132ZZePkYuPCoZKyUqImDgNM=; b=FSjbXf6CpoMpAxG+v5ZuqTTgUbRdyY1lcKRYUlNq0T4z9dEDNGelKP/H2bxo14Zhvd NLQE+pttphxIwr0QWjgJB4g48JqxzYPLkkpPHzA8puxbVl5DxfXbodlJtOhW2eCWmUe+ QmIOHFFkPxv/dZK98gyWbNrLd4YjtbSg/kwaIr7n/6pDpByHYUr/kqZ1+IFDzTjUdEc4 p6cYARvjGZrZS3rlleCUbeYEi/w1xxCUsjSrAvKmEwcOY2eiGeZeyRKZkpDa+jXl1/jC JO/ETHW0Td4tybI4/GCzTkfkDRerFJjOU2utckrn/gaIsNxnNE8U8EoQ/edHNY3tFmLY V8mg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Xe2/UBTz"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id q7si14328136edt.86.2021.02.09.04.50.33; Tue, 09 Feb 2021 04:50:33 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Xe2/UBTz"; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230145AbhBIMty (ORCPT + 16 others); Tue, 9 Feb 2021 07:49:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229976AbhBIMs4 (ORCPT ); Tue, 9 Feb 2021 07:48:56 -0500 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A425C06178B for ; Tue, 9 Feb 2021 04:48:15 -0800 (PST) Received: by mail-lf1-x132.google.com with SMTP id v24so28136702lfr.7 for ; Tue, 09 Feb 2021 04:48:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9yYw/slrRYfwVyi4Hj3132ZZePkYuPCoZKyUqImDgNM=; b=Xe2/UBTz2oxBtf9tTYF5wjKIvaRwSAwc6LgM+3AdeD4RCVgaxBhfqaSNXzPo8KKwio zoBuXCCac3IJ3yrBFWpfSEgKxWTI8NijnG28KUSXrSXeYywum7hHauk69uxkpUFWIPxc sQU+WRMPtcWLqfQqEos1AMEzxe5D47EWFVL5kPQPOkT2ej1c0BgylXGCoffv4ypiomZj wmU6gcL/t9b5RyDeHqpyldgoCeDabFOrFjwVrMZ8YpKMwQamFSeChN9OBBOxddo10zoI 4UyZZ8pg4Njfqxzg5AOhj9r+GGuW3TwsvIcG8Gi3h+Znlrec0Em14OcdhovhSOVx6oEb 31Zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9yYw/slrRYfwVyi4Hj3132ZZePkYuPCoZKyUqImDgNM=; b=HYE/5ByK58ZEyy0w4C+0bdhHR4TNdK08gTcPRkYveLJUTUDZF1CKr1w4VaEbyOOb9P XFkouSvY2LeJQuxrw8mxr4crHHFhH/LPzfiBVICbi/dKp8RtDPBRmyan4Vh3mgWQ6nZj pJN38TQOPMnpKowC7aBUWTyd0HBcgpSoT3EOsdHse1RLXTQYsBv6j0IlzoXK2zXdON/e pstzqFt0Tapj//ysWgWLrxvQH/A8O6AwJT+HDUXu1XcwU+7vjaEHeNjPaRfqV9ElZORl T4vYxO+6JlTqGKOTwSI0q7nXIJPGRTC5+KJwNG62jjAwj35GmzMfiYs8b5feHWXpyVVw Mg8g== X-Gm-Message-State: AOAM530pEJNoCTZSYjqjGzYshYUu7b7FzWveM2yFmLmzxY1L0t6Cr3tK 2fKNuX8jtHeEO0zMS804fuIYxg== X-Received: by 2002:a05:6512:1311:: with SMTP id x17mr13317844lfu.307.1612874893942; Tue, 09 Feb 2021 04:48:13 -0800 (PST) Received: from eriador.lan ([94.25.229.138]) by smtp.gmail.com with ESMTPSA id e16sm1220653ljn.105.2021.02.09.04.48.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Feb 2021 04:48:13 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Doug Anderson Cc: linux-arm-msm@vger.kernel.org Subject: [PATCH v2 2/4] arm64: dts: qcom: sm8250: further split of spi pinctrl config Date: Tue, 9 Feb 2021 15:47:56 +0300 Message-Id: <20210209124758.990681-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210209124758.990681-1-dmitry.baryshkov@linaro.org> References: <20210209124758.990681-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Split "default" device tree nodes into common "data-clk" nodes and "cs" nodes which might differ from board to board depending on how the slave chips are wired. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 8 +- arch/arm64/boot/dts/qcom/sm8250.dtsi | 200 ++++++++++++++++------- 2 files changed, 147 insertions(+), 61 deletions(-) -- 2.30.0 diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 787da8ccba54..dd0ec0676258 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -815,7 +815,12 @@ &pm8150_rtc { status = "okay"; }; -&qup_spi0_default { +&qup_spi0_cs { + drive-strength = <6>; + bias-disable; +}; + +&qup_spi0_data_clk { drive-strength = <6>; bias-disable; }; @@ -957,6 +962,7 @@ codec { /* CAN */ &spi0 { status = "okay"; + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; can@0 { compatible = "microchip,mcp2518fd"; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 51d103671759..e43e1367ceb7 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -549,7 +549,6 @@ spi14: spi@880000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi14_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -577,7 +576,6 @@ spi15: spi@884000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi15_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -605,7 +603,6 @@ spi16: spi@888000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi16_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -633,7 +630,6 @@ spi17: spi@88c000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi17_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -674,7 +670,6 @@ spi18: spi@890000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi18_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -715,7 +710,6 @@ spi19: spi@894000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi19_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -756,7 +750,6 @@ spi0: spi@980000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi0_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -784,7 +777,6 @@ spi1: spi@984000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi1_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -812,7 +804,6 @@ spi2: spi@988000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi2_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -853,7 +844,6 @@ spi3: spi@98c000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi3_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -881,7 +871,6 @@ spi4: spi@990000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi4_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -909,7 +898,6 @@ spi5: spi@994000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi5_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -937,7 +925,6 @@ spi6: spi@998000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi6_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -978,7 +965,6 @@ spi7: spi@99c000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi7_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -1019,7 +1005,6 @@ spi8: spi@a80000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi8_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -1047,7 +1032,6 @@ spi9: spi@a84000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi9_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -1075,7 +1059,6 @@ spi10: spi@a88000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi10_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -1103,7 +1086,6 @@ spi11: spi@a8c000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi11_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -1131,7 +1113,6 @@ spi12: spi@a90000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi12_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -1172,7 +1153,6 @@ spi13: spi@a94000 { clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_spi13_default>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -2983,123 +2963,223 @@ config { }; }; - qup_spi0_default: qup-spi0-default { + qup_spi0_cs: qup-spi0-cs { + pins = "gpio31"; + function = "qup0"; + }; + + qup_spi1_cs: qup-spi1-cs { + pins = "gpio7"; + function = "qup1"; + }; + + qup_spi2_cs: qup-spi2-cs { + pins = "gpio118"; + function = "qup2"; + }; + + qup_spi3_cs: qup-spi3-cs { + pins = "gpio122"; + function = "qup3"; + }; + + qup_spi4_cs: qup-spi4-cs { + pins = "gpio11"; + function = "qup4"; + }; + + qup_spi5_cs: qup-spi5-cs { + pins = "gpio15"; + function = "qup5"; + }; + + qup_spi6_cs: qup-spi6-cs { + pins = "gpio19"; + function = "qup6"; + }; + + qup_spi7_cs: qup-spi7-cs { + pins = "gpio23"; + function = "qup7"; + }; + + qup_spi8_cs: qup-spi8-cs { + pins = "gpio27"; + function = "qup8"; + }; + + qup_spi9_cs: qup-spi9-cs { + pins = "gpio128"; + function = "qup9"; + }; + + qup_spi10_cs: qup-spi10-cs { + pins = "gpio132"; + function = "qup10"; + }; + + qup_spi11_cs: qup-spi11-cs { + pins = "gpio63"; + function = "qup11"; + }; + + qup_spi12_cs: qup-spi12-cs { + pins = "gpio35"; + function = "qup12"; + }; + + qup_spi13_cs: qup-spi13-cs { + pins = "gpio39"; + function = "qup13"; + }; + + qup_spi14_cs: qup-spi14-cs { + pins = "gpio43"; + function = "qup14"; + }; + + qup_spi15_cs: qup-spi15-cs { + pins = "gpio47"; + function = "qup15"; + }; + + qup_spi16_cs: qup-spi16-cs { + pins = "gpio51"; + function = "qup16"; + }; + + qup_spi17_cs: qup-spi17-cs { + pins = "gpio55"; + function = "qup17"; + }; + + qup_spi18_cs: qup-spi18-cs { + pins = "gpio59"; + function = "qup18"; + }; + + qup_spi19_cs: qup-spi19-cs { + pins = "gpio3"; + function = "qup19"; + }; + + qup_spi0_data_clk: qup-spi0-data-clk { pins = "gpio28", "gpio29", - "gpio30", "gpio31"; + "gpio30"; function = "qup0"; }; - qup_spi1_default: qup-spi1-default { + qup_spi1_data_clk: qup-spi1-data-clk { pins = "gpio4", "gpio5", - "gpio6", "gpio7"; + "gpio6"; function = "qup1"; }; - qup_spi2_default: qup-spi2-default { + qup_spi2_data_clk: qup-spi2-data-clk { pins = "gpio115", "gpio116", - "gpio117", "gpio118"; + "gpio117"; function = "qup2"; }; - qup_spi3_default: qup-spi3-default { + qup_spi3_data_clk: qup-spi3-data-clk { pins = "gpio119", "gpio120", - "gpio121", "gpio122"; + "gpio121"; function = "qup3"; }; - qup_spi4_default: qup-spi4-default { + qup_spi4_data_clk: qup-spi4-data-clk { pins = "gpio8", "gpio9", - "gpio10", "gpio11"; + "gpio10"; function = "qup4"; }; - qup_spi5_default: qup-spi5-default { + qup_spi5_data_clk: qup-spi5-data-clk { pins = "gpio12", "gpio13", - "gpio14", "gpio15"; + "gpio14"; function = "qup5"; }; - qup_spi6_default: qup-spi6-default { + qup_spi6_data_clk: qup-spi6-data-clk { pins = "gpio16", "gpio17", - "gpio18", "gpio19"; + "gpio18"; function = "qup6"; }; - qup_spi7_default: qup-spi7-default { + qup_spi7_data_clk: qup-spi7-data-clk { pins = "gpio20", "gpio21", - "gpio22", "gpio23"; + "gpio22"; function = "qup7"; }; - qup_spi8_default: qup-spi8-default { + qup_spi8_data_clk: qup-spi8-data-clk { pins = "gpio24", "gpio25", - "gpio26", "gpio27"; + "gpio26"; function = "qup8"; }; - qup_spi9_default: qup-spi9-default { + qup_spi9_data_clk: qup-spi9-data-clk { pins = "gpio125", "gpio126", - "gpio127", "gpio128"; + "gpio127"; function = "qup9"; }; - qup_spi10_default: qup-spi10-default { + qup_spi10_data_clk: qup-spi10-data-clk { pins = "gpio129", "gpio130", - "gpio131", "gpio132"; + "gpio131"; function = "qup10"; }; - qup_spi11_default: qup-spi11-default { + qup_spi11_data_clk: qup-spi11-data-clk { pins = "gpio60", "gpio61", - "gpio62", "gpio63"; + "gpio62"; function = "qup11"; }; - qup_spi12_default: qup-spi12-default { + qup_spi12_data_clk: qup-spi12-data-clk { pins = "gpio32", "gpio33", - "gpio34", "gpio35"; + "gpio34"; function = "qup12"; }; - qup_spi13_default: qup-spi13-default { + qup_spi13_data_clk: qup-spi13-data-clk { pins = "gpio36", "gpio37", - "gpio38", "gpio39"; + "gpio38"; function = "qup13"; }; - qup_spi14_default: qup-spi14-default { + qup_spi14_data_clk: qup-spi14-data-clk { pins = "gpio40", "gpio41", - "gpio42", "gpio43"; + "gpio42"; function = "qup14"; }; - qup_spi15_default: qup-spi15-default { + qup_spi15_data_clk: qup-spi15-data-clk { pins = "gpio44", "gpio45", - "gpio46", "gpio47"; + "gpio46"; function = "qup15"; }; - qup_spi16_default: qup-spi16-default { + qup_spi16_data_clk: qup-spi16-data-clk { pins = "gpio48", "gpio49", - "gpio50", "gpio51"; + "gpio50"; function = "qup16"; }; - qup_spi17_default: qup-spi17-default { + qup_spi17_data_clk: qup-spi17-data-clk { pins = "gpio52", "gpio53", - "gpio54", "gpio55"; + "gpio54"; function = "qup17"; }; - qup_spi18_default: qup-spi18-default { + qup_spi18_data_clk: qup-spi18-data-clk { pins = "gpio56", "gpio57", - "gpio58", "gpio59"; + "gpio58"; function = "qup18"; }; - qup_spi19_default: qup-spi19-default { + qup_spi19_data_clk: qup-spi19-data-clk { pins = "gpio0", "gpio1", - "gpio2", "gpio3"; + "gpio2"; function = "qup19"; }; From patchwork Tue Feb 9 12:47:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 379348 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp192059jah; Tue, 9 Feb 2021 04:50:35 -0800 (PST) X-Google-Smtp-Source: ABdhPJx++NsmJMagufTsZR/63ndUNczq1zyyVO551Snnrj7JJhrnWsmTqtGh+BlwyhdpA+1rLnxh X-Received: by 2002:a05:6402:6cc:: with SMTP id n12mr22328934edy.297.1612875035027; Tue, 09 Feb 2021 04:50:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612875035; cv=none; d=google.com; s=arc-20160816; b=zI/gk7G5f5S+vVWS97SNnzjW8XdSslOH5RdR4tCx0St6Nd/aBUAvuLEYki05i23D7Q 6eijxGSl/XoMyg2B2Spdr1LmWxwpulAJ7GxVIoH0IF0FwvDhciDotbiw1CJW5g7PIhRK bSSF3q7ArMbkRridgvKVsA4XLvbN5FuFe/KuSvZ/bBSCzOiHDNR7Y6WqliQZF4WdWnq3 1kwnQuMgpJbv5lhl3G2DUPkktqn4mG6RPFYcsQhOgHHav7cKxotEKKNRrReMEYIQgJ5U DFfReF9SeQI33/pXEegCSKr3gxM3FYnh/fMPEkuwHpdLSQ2EHJJ8dex97L8MHxJ6kt5v wjCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=CkMqtRiTtrh3rDzNk9MszUw8gNTXkM+DptzGY6xVabA=; b=GKGBKt6XWs7q9wpHYT2dpKlOAn7OXAqRmATO98QnaQmabI4qCSMmmo9zAV9xoFCKoC uYc3othDYb7yxw2IQVvTBjeiECO20AZMZJYdqfElNIsmTFJXpLKLQVLJfnUaZxJQhtcd /l6Fln2PqNsfXxBQ30n6eBUFVb7LqAj7rUoaCAzL62eySaOwVfoXqfqNPQIXquZGipja fJsnKhMV8FVrOi+jvb5VjgdJ+cw+00ZIuVdsfY82pj9OxmgAG4NUDevfm795fcnBiY2l 672y0nkizP/Sss7pFo66Y4wXNeo2YGxA2qLxterLE9JIwZblfD09xoKuD4zjxXU84E8A 3HVQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dj2YU+XJ; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id q7si14328136edt.86.2021.02.09.04.50.34; Tue, 09 Feb 2021 04:50:35 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dj2YU+XJ; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229976AbhBIMtz (ORCPT + 16 others); Tue, 9 Feb 2021 07:49:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230050AbhBIMs6 (ORCPT ); Tue, 9 Feb 2021 07:48:58 -0500 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F2489C06178C for ; Tue, 9 Feb 2021 04:48:17 -0800 (PST) Received: by mail-lf1-x12b.google.com with SMTP id r65so4624151lff.6 for ; Tue, 09 Feb 2021 04:48:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CkMqtRiTtrh3rDzNk9MszUw8gNTXkM+DptzGY6xVabA=; b=dj2YU+XJgH33FouhY8L+yGx3RxrVqvklVk6C2GasZUduPX1hbaXZW7Au5vUtb9ZjCl 32j7ms+DmOLAFYbNSP1+0ijQmuXj1p/8AuVAiD5jbHCNlItDhWC8RKpKpW9wclWaKzvc tgd+0TFL45uAIQBIFus6va5XY71Pb+fsVkvtxL5CAOFoT3koW9+nCb7sQhA6gTcdvQw3 XrjSrixao0LkvAR53Lox7q8JnnlYsMMSa9W8fnrDH7lEPQznug/mt1QeN7mNf7qDecv9 AGxnvTapLFhg1eU/EMbemdIVjoR4eEqVlKVHDxaxzkeXpB0S5bxZly9ixP2xvATCQWTu 0DsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CkMqtRiTtrh3rDzNk9MszUw8gNTXkM+DptzGY6xVabA=; b=W7y2MWtzJLKO6e783z6xNfP6/CIrCdDiSrpRSIDfUiEjmGrMv4C7Wt5gD0bqU5NS7P n5YV56h6bJxCf7p7BOcjnmj3kpaa/fqfYsF5ZxYdtVKwylzl3AyXeS3LVHRulE382tSJ hGCY2hD/iAiAt2NPHmQPc6h4n8l6m/xXrhktgRAhd8crOqjgS0XZNpKud7ZSJeASsZxU 7K2fYY60a5ijTM6eoasOcey8TJMFsGGnJFoVLZtDlCWjCWsTX5GvuMDWfzycTp1UpiGr OtgqkJamqKl9YbbrJsmcZKbyWQxS9Cc6BFujwMwwixU94bWmYBQghaC4kPTiZpKqOgsi MvRQ== X-Gm-Message-State: AOAM5319SKp3VBdsQksWvaLaE3mBKFuJrsAeKc9qBLYqQh8mdLXcDrF/ 0j1ePp3DVl6ivabmztdglCD9rA== X-Received: by 2002:a19:441:: with SMTP id 62mr828605lfe.274.1612874896532; Tue, 09 Feb 2021 04:48:16 -0800 (PST) Received: from eriador.lan ([94.25.229.138]) by smtp.gmail.com with ESMTPSA id e16sm1220653ljn.105.2021.02.09.04.48.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Feb 2021 04:48:16 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Doug Anderson Cc: linux-arm-msm@vger.kernel.org Subject: [PATCH v2 3/4] arm64: dts: qcom: sm8250: add pinctrl for SPI using GPIO as a CS Date: Tue, 9 Feb 2021 15:47:57 +0300 Message-Id: <20210209124758.990681-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210209124758.990681-1-dmitry.baryshkov@linaro.org> References: <20210209124758.990681-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org GENI SPI controller shows several issues if it manages the CS on its own (see 37dd4b777942 ("arm64: dts: qcom: sc7180: Provide pinconf for SPI to use GPIO for CS")) for the details. Provide pinctrl entries for SPI controllers using the same CS pin but in GPIO mode. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 100 +++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) -- 2.30.0 diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index e43e1367ceb7..0044911f7790 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3063,6 +3063,106 @@ qup_spi19_cs: qup-spi19-cs { function = "qup19"; }; + qup_spi0_cs_gpio: qup-spi0-cs-gpio { + pins = "gpio31"; + function = "gpio"; + }; + + qup_spi1_cs_gpio: qup-spi1-cs-gpio { + pins = "gpio7"; + function = "gpio"; + }; + + qup_spi2_cs_gpio: qup-spi2-cs-gpio { + pins = "gpio118"; + function = "gpio"; + }; + + qup_spi3_cs_gpio: qup-spi3-cs-gpio { + pins = "gpio122"; + function = "gpio"; + }; + + qup_spi4_cs_gpio: qup-spi4-cs-gpio { + pins = "gpio11"; + function = "gpio"; + }; + + qup_spi5_cs_gpio: qup-spi5-cs-gpio { + pins = "gpio15"; + function = "gpio"; + }; + + qup_spi6_cs_gpio: qup-spi6-cs-gpio { + pins = "gpio19"; + function = "gpio"; + }; + + qup_spi7_cs_gpio: qup-spi7-cs-gpio { + pins = "gpio23"; + function = "gpio"; + }; + + qup_spi8_cs_gpio: qup-spi8-cs-gpio { + pins = "gpio27"; + function = "gpio"; + }; + + qup_spi9_cs_gpio: qup-spi9-cs-gpio { + pins = "gpio128"; + function = "gpio"; + }; + + qup_spi10_cs_gpio: qup-spi10-cs-gpio { + pins = "gpio132"; + function = "gpio"; + }; + + qup_spi11_cs_gpio: qup-spi11-cs-gpio { + pins = "gpio63"; + function = "gpio"; + }; + + qup_spi12_cs_gpio: qup-spi12-cs-gpio { + pins = "gpio35"; + function = "gpio"; + }; + + qup_spi13_cs_gpio: qup-spi13-cs-gpio { + pins = "gpio39"; + function = "gpio"; + }; + + qup_spi14_cs_gpio: qup-spi14-cs-gpio { + pins = "gpio43"; + function = "gpio"; + }; + + qup_spi15_cs_gpio: qup-spi15-cs-gpio { + pins = "gpio47"; + function = "gpio"; + }; + + qup_spi16_cs_gpio: qup-spi16-cs-gpio { + pins = "gpio51"; + function = "gpio"; + }; + + qup_spi17_cs_gpio: qup-spi17-cs-gpio { + pins = "gpio55"; + function = "gpio"; + }; + + qup_spi18_cs_gpio: qup-spi18-cs-gpio { + pins = "gpio59"; + function = "gpio"; + }; + + qup_spi19_cs_gpio: qup-spi19-cs-gpio { + pins = "gpio3"; + function = "gpio"; + }; + qup_spi0_data_clk: qup-spi0-data-clk { pins = "gpio28", "gpio29", "gpio30"; From patchwork Tue Feb 9 12:47:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 379349 Delivered-To: patch@linaro.org Received: by 2002:a02:b18a:0:0:0:0:0 with SMTP id t10csp192071jah; Tue, 9 Feb 2021 04:50:36 -0800 (PST) X-Google-Smtp-Source: ABdhPJzwUnCa9ntUgS1TpiEEZ13/5A3s5wH+7UUWtsLGXrEXmY4bJTvX8QMcO+MttLt8QzkqVqKb X-Received: by 2002:a05:6402:b8c:: with SMTP id cf12mr22412948edb.320.1612875036237; Tue, 09 Feb 2021 04:50:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1612875036; cv=none; d=google.com; s=arc-20160816; b=yTFB8g3JUEVrARaaimTtwtOxeylEZakVPmnjhaDoKqUsKMlSeWAuScAN5DPBT3n73H huJ+x95OiJpFcIhP7DHhrfitMKAOBnz/kSiYCvk+1GrppOGDEuC9eroUSi2wFbPXpWlr aDYoCUug7UI+uWa3Yrk8yDp8nmV4ZqoagCIIhY+FwBy7ncblc77lktAEFTX5w+uzc745 /epI08oLF8/Rwvqc5LtvuSkMVWnIuG9mDk9TdIVKl2ZXC2x7SBEjRaQGLqSFFLcSWrcn Le2ga9h2fePgJCLW437Bf8edd0nCPnuMvcHdbGxh+kipLAngaK5bjz+i3PTb9YKEa6B7 LS6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=D4TIjkothfdEPJmp+jtQjnJHdWaAiiHT9uw9NxP1nxU=; b=L1kuBdl+rgdhKIqIiROi17ImunWyvUqg7ZNb7RQpXEdL5vo7RtOLTNq/0bZW3+ysm6 YDjcwO9TQVPWWQenBRLiLMr2OEfJ+tSR16qSoSQ/Z52sZuIuftseYqTCSsbk1aSzGI2J 4EuctU63aqc+M9h4L6vvlNWMNnTrVtcmCPCnCo+P/ZItUYAHP80LpRtaD1KGLFnSKPMO GNdu5eiqjC1YD9nfNPZjkvc3/tgnpiugsKh02vNhvujBFCVkp8k2HQRwPyQdUSSOtV1D HweYEEpaL0OcBJHs5YvMXg2r9jVaP93ZF2lhosKVJT22IBA6KW2Pv73sNlcTtwQWlY4F Nm+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Rbf2dZTJ; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id q7si14328136edt.86.2021.02.09.04.50.36; Tue, 09 Feb 2021 04:50:36 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Rbf2dZTJ; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230077AbhBIMua (ORCPT + 16 others); Tue, 9 Feb 2021 07:50:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230155AbhBIMtF (ORCPT ); Tue, 9 Feb 2021 07:49:05 -0500 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3ADEDC061793 for ; Tue, 9 Feb 2021 04:48:21 -0800 (PST) Received: by mail-lf1-x12c.google.com with SMTP id w36so14515342lfu.4 for ; Tue, 09 Feb 2021 04:48:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D4TIjkothfdEPJmp+jtQjnJHdWaAiiHT9uw9NxP1nxU=; b=Rbf2dZTJHnSqnhP5r8mq8jFsiFlTvtGHjFEpEfqqMFx5cZKTcam+1cL3esN7cCwWq+ F7krbkkzlSOuZtkWR+JC/VPDaALlT+tYIDaS3NzAfpCjOB0jBncirMraoUIVfC4B9lz4 /MR2eHah9uuaKfGTZ6McedDx/ohc+Me7GFE9Ulkhn+0JzPab+Mz4oP11pf4Xf7LSjRUU TKTh/uT6tpwck66VGbmy/X6tpND+Yfok1tS/YBttuQqATCxSoheKFEbVmueJNUnxhKZJ QOe7izNzL2IHYj/gWitedk79MR6IVWKfAaW/WUVwzyU0frVVmKMjR7/TERqKmxz8XVdh 2CGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D4TIjkothfdEPJmp+jtQjnJHdWaAiiHT9uw9NxP1nxU=; b=NnmwkiGxWYSrKWIjow/INiWBVBHjJCdzvSrhlirMCLxWwKj54yW/0Bge1TJ5Ejtl6q r2ErrcCxhxBdoxI5ESsG0bxhZ669Zk5t+KOy+2Rd2cyRLk0wQ4vW3xICPIWv8fuXbVLA hohj/yJKRBXPZoLt3lej/wpuu1OBt1+VuIbIogg+RMoWZNr6QOvGXn2sMmTAIVBQP7M8 uBHe5amRTtG8dlsVWXZurxg3lF0J7G0yhF56B2SJjIQ+G315NZx2iElJZ6ECBHrHBQqE 9nVmIv8AeqgK+vnvZrT9wK9nPxgcFm2dkoM5etVHldq0oKFZpo+QtN8GuqhwwEQcjs6t NZSw== X-Gm-Message-State: AOAM531Ypteb+DXl50cIoTZU88bFEp19hB5poYfQ9uPNoVmYuXonuDIu rjd1bfyhE087EuPTR8gEeZyOCg== X-Received: by 2002:ac2:5e90:: with SMTP id b16mr12790403lfq.122.1612874899716; Tue, 09 Feb 2021 04:48:19 -0800 (PST) Received: from eriador.lan ([94.25.229.138]) by smtp.gmail.com with ESMTPSA id e16sm1220653ljn.105.2021.02.09.04.48.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Feb 2021 04:48:19 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Doug Anderson Cc: linux-arm-msm@vger.kernel.org Subject: [PATCH v2 4/4] arm64: dts: qcom: qrb5165-rb5: switch into using GPIO for SPI0 CS Date: Tue, 9 Feb 2021 15:47:58 +0300 Message-Id: <20210209124758.990681-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210209124758.990681-1-dmitry.baryshkov@linaro.org> References: <20210209124758.990681-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org GENI SPI controller shows several issues if it manages the CS on its own (see 37dd4b777942 ("arm64: dts: qcom: sc7180: Provide pinconf for SPI to use GPIO for CS")) for the details. Configure SPI0 CS pin as a GPIO. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.30.0 diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index dd0ec0676258..4888ac47cc1d 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -815,7 +815,7 @@ &pm8150_rtc { status = "okay"; }; -&qup_spi0_cs { +&qup_spi0_cs_gpio { drive-strength = <6>; bias-disable; }; @@ -962,7 +962,8 @@ codec { /* CAN */ &spi0 { status = "okay"; - pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs_gpio>; + cs-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>; can@0 { compatible = "microchip,mcp2518fd";