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[23.128.96.18]) by mx.google.com with ESMTP id l16si851986ejd.683.2021.02.10.00.20.58; Wed, 10 Feb 2021 00:20:58 -0800 (PST) Received-SPF: pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jtURhRlk; spf=pass (google.com: domain of linux-arm-msm-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233730AbhBJITh (ORCPT + 16 others); Wed, 10 Feb 2021 03:19:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233530AbhBJITe (ORCPT ); Wed, 10 Feb 2021 03:19:34 -0500 Received: from mail-pg1-x535.google.com (mail-pg1-x535.google.com [IPv6:2607:f8b0:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E82CAC061574 for ; Wed, 10 Feb 2021 00:18:53 -0800 (PST) Received: by mail-pg1-x535.google.com with SMTP id o7so752442pgl.1 for ; Wed, 10 Feb 2021 00:18:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=3TY7Cims/zXIVET72hDHwG85GzF++wOgb0qceb5a5HA=; b=jtURhRlkMrMcNUS3JXa9PWeWl9t4137oHU+kdSMF4HEMAUKF2zEzZJ37ql+SoaWSMs gbXJRIZsjDsNf7r4FKFEyG0uE1D5YPjkT8ybju3oD1tbkwmG9Fqoa3csyPyZf+mhG8J0 NuA6VV1IcPhqN9BhQxclaf+PmWk5JljnU7BBzjF27r0CNZw+buhdksMxlgOfPAn3Yk97 bsMSCCCyI2flQ3BdVBsDyptoLxkSNhY7BEKd0XFacCPHYXpAZkQlsrqRjMDcXBIKWAqV BtBqAgHwkSbilcbBjubgfQCKI70xgsIwANJyVfH0eaCd+0itjwCX2efbTxiGpD7aJ/3u mX6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=3TY7Cims/zXIVET72hDHwG85GzF++wOgb0qceb5a5HA=; b=azEMmmL0A/9+cw8p0wUAh7IFN+XjoJN/6ZboYZb7ojAz49lFuEgbub/H4f8iWeZww0 sSJh/otNHCzLzQIE72ko2RWdDO+BzAmqAVcNOUFinAu/ukayirDsz2dG/1G4ZpquuGH9 wARyjgh1qCssKPA/BEDeJemcPtK2YJcddSQ6fKHFd9vec38XlRnu22MDr/eAq1pkQn7b ZIrYEcZJ45VfR6zImd441ZWU9ekyikSeLfwA0aPmHbQlVVnEWtdnBm2FQrJjeglNsWzN vgGb1WYkkrXtohhM8PGRbfIWvFAI/M5J0VqQtUWm0BVOwnWOWMSrallvkcVFEwG8P1KV BWJQ== X-Gm-Message-State: AOAM533bi5lSnBO81G22S5ZpDHbS1cM/LgliP0ihm6wWdOt4vPTxUF/E qb+Y6iNav8mRQwai7ldLPJcjhw== X-Received: by 2002:aa7:800d:0:b029:1d5:6701:68f with SMTP id j13-20020aa7800d0000b02901d56701068fmr2372207pfi.30.1612945133458; Wed, 10 Feb 2021 00:18:53 -0800 (PST) Received: from localhost.localdomain ([49.207.221.41]) by smtp.gmail.com with ESMTPSA id e26sm1397290pfm.87.2021.02.10.00.18.50 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 10 Feb 2021 00:18:53 -0800 (PST) From: Amit Pundir To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , John Stultz , Sumit Semwal , AngeloGioacchino Del Regno Cc: linux-arm-msm , dt , lkml , phone-devel@vger.kernel.org Subject: [PATCH v3] arm64: dts: qcom: sdm845-xiaomi-beryllium: Add DSI and panel bits Date: Wed, 10 Feb 2021 13:48:48 +0530 Message-Id: <1612945128-23174-1-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Sumit Semwal Enabling the Display panel for beryllium requires DSI labibb regulators and panel dts nodes to be added. It is also required to keep some of the regulators as always-on. Signed-off-by: Sumit Semwal Signed-off-by: Amit Pundir --- v3: Addressed Konrad's concerns. Configured labibb regulators explicitly based on downstream microvolt values. Display comes up fine with default discharge-resistor-kohms and soft-start-us properties, so didn't touch them. Smoke tested on next-20210209. v2: Rebased to mainline (v5.11-rc6) and fixed build warnings. .../boot/dts/qcom/sdm845-xiaomi-beryllium.dts | 64 ++++++++++++++++++++++ 1 file changed, 64 insertions(+) -- 2.7.4 Reviewed-by: Konrad Dybcio diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts index 86cbae63eaf7..5ac049a247e1 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts @@ -157,6 +157,14 @@ regulator-initial-mode = ; }; + vreg_l14a_1p8: ldo14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = ; + regulator-boot-on; + regulator-always-on; + }; + vreg_l17a_1p3: ldo17 { regulator-min-microvolt = <1304000>; regulator-max-microvolt = <1304000>; @@ -191,6 +199,7 @@ regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-initial-mode = ; + regulator-boot-on; }; }; }; @@ -200,6 +209,43 @@ firmware-name = "qcom/sdm845/cdsp.mdt"; }; +&dsi0 { + status = "okay"; + vdda-supply = <&vreg_l26a_1p2>; + + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "tianma,fhd-video"; + reg = <0>; + vddi0-supply = <&vreg_l14a_1p8>; + vddpos-supply = <&lab>; + vddneg-supply = <&ibb>; + + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + port { + tianma_nt36672a_in_0: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +}; + +&dsi0_out { + remote-endpoint = <&tianma_nt36672a_in_0>; + data-lanes = <0 1 2 3>; +}; + +&dsi0_phy { + status = "okay"; + vdds-supply = <&vreg_l1a_0p875>; +}; + &gcc { protected-clocks = , , @@ -215,6 +261,24 @@ }; }; +&ibb { + regulator-min-microvolt = <4600000>; + regulator-max-microvolt = <6000000>; +}; + +&lab { + regulator-min-microvolt = <4600000>; + regulator-max-microvolt = <6000000>; +}; + +&mdss { + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + &mss_pil { status = "okay"; firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mdt";