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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.32.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:32:48 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:31:57 +0000 Message-Id: <20180321163235.12529-2-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 01/39] xen/arm: gic: Read unconditionally the source from the LRs X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Julien Grall Commit 5cb00d1 "ARM: GIC: extend LR read/write functions to cover EOI and source" extended gic_lr to cover the source. The new field was only set for SGIs interrupt in the read function. However, the write function is writing the field unconditionally for virtual interrupt. This means that if the caller was combining the 2 functions (e.g to update the LR), the source need to be set to 0 by the caller. Unfortunately, gic_update_one_lr is not zeroing the structure before reading the LRs. This will lead to trigger the assert randomly. Instead of zeroing the structure in gic_update_one_lr, make sure that the source is written unconditionally on read. This is also simplifying the code to avoid an if statement in the read path. Lastly, properly update the comments in write_lr that was mistakenly speaking about the read lr path. Signed-off-by: Julien Grall Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- xen/arch/arm/gic-v2.c | 15 ++++++++------- xen/arch/arm/gic-v3.c | 13 ++++++++----- 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 7dfe6fc68d..aa0fc6c1a1 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -480,11 +480,12 @@ static void gicv2_read_lr(int lr, struct gic_lr *lr_reg) else { lr_reg->virt.eoi = (lrv & GICH_V2_LR_MAINTENANCE_IRQ); - if ( lr_reg->virq < NR_GIC_SGI ) - { - lr_reg->virt.source = (lrv >> GICH_V2_LR_CPUID_SHIFT) - & GICH_V2_LR_CPUID_MASK; - } + /* + * This is only valid for SGI, but it does not matter to always + * read it as it should be 0 by default. + */ + lr_reg->virt.source = (lrv >> GICH_V2_LR_CPUID_SHIFT) + & GICH_V2_LR_CPUID_MASK; } } @@ -512,8 +513,8 @@ static void gicv2_write_lr(int lr, const struct gic_lr *lr_reg) if ( lr_reg->virt.eoi ) lrv |= GICH_V2_LR_MAINTENANCE_IRQ; /* - * This is only valid for SGI, but it does not matter to always - * read it as it should be 0 by default. + * Source is only valid for SGIs, the caller should make sure + * the field virt.source is always 0 for non-SGI. */ ASSERT(!lr_reg->virt.source || lr_reg->virq < NR_GIC_SGI); lrv |= (uint32_t)lr_reg->virt.source << GICH_V2_LR_CPUID_SHIFT; diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 392cf91b58..cb41844af2 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1018,10 +1018,13 @@ static void gicv3_read_lr(int lr, struct gic_lr *lr_reg) else { lr_reg->virt.eoi = (lrv & ICH_LR_MAINTENANCE_IRQ); - /* Source only exists for SGI and in GICv2 compatible mode */ - if ( lr_reg->virq < NR_GIC_SGI && - current->domain->arch.vgic.version == GIC_V2 ) + /* Source only exists in GICv2 compatible mode */ + if ( current->domain->arch.vgic.version == GIC_V2 ) { + /* + * This is only valid for SGI, but it does not matter to always + * read it as it should be 0 by default. + */ lr_reg->virt.source = (lrv >> ICH_LR_CPUID_SHIFT) & ICH_LR_CPUID_MASK; } @@ -1056,8 +1059,8 @@ static void gicv3_write_lr(int lr_reg, const struct gic_lr *lr) if ( vgic_version == GIC_V2 ) { /* - * This is only valid for SGI, but it does not matter to always - * read it as it should be 0 by default. + * Source is only valid for SGIs, the caller should make + * sure the field virt.source is always 0 for non-SGI. */ ASSERT(!lr->virt.source || lr->virq < NR_GIC_SGI); lrv |= (uint64_t)lr->virt.source << ICH_LR_CPUID_SHIFT; From patchwork Wed Mar 21 16:31:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132213 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356005ljb; Wed, 21 Mar 2018 09:34:57 -0700 (PDT) X-Google-Smtp-Source: AG47ELsu8Fn0r1d3AdJlY9pL8L30yA6vuaJbddhtnieEHwhjY1FMWPh0zkDmw4M6PIDQt2rpFMmn X-Received: by 10.107.184.198 with SMTP id i189mr20463563iof.228.1521650097086; Wed, 21 Mar 2018 09:34:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650097; cv=none; d=google.com; s=arc-20160816; b=mr5wZ6ezc9PXK6C4EPdZcFrcHcK4AMIGlMe09Pm2zFeAZ7/HFDgw1+VeeJ30lsIDMQ gym97t3Y7tdZMCdYGQXge2jz01x7Q6BcCuzWGA3G6Ygj9sG6HJePyDZx89i5R0gL/Xxw P9VNhqzOCSONfSOkZYz37ggVkeWhAP6yMkCJw8StwS2dpHEQCrBp07Kjej0eKNG4XVh6 wE+gG261Ozh28BFLabw5u0lkWdz4Zs8WMSG51h4RGDKBpG1/1l+8WIIe0hF4dj0D/BlG y9p4355wSKZeUxCkisGjZ1giTfjXDQMJuQsWnt41Fc2CJWXWAVpHYX9Sceu3pmnyZM3L N8jQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=2Akjv4zUO6HBrmNrOryGmz5XgHPNjPcmaGEBJJ9a7X0=; b=l8b34zX3NF8HNqq9ppnvaayV8l6IHmW8Hm4EurOtRWI+NkPApZZbbDf00ScFqsqCC5 Vt0WKWynj/TGCgdxMCdxyNxnJfm2cQK4r9Cdg9Hp2Ly7CbnrVNKcSGGwz4NJhwpVuLsj zRKAJNQOXFoC7qeK9Q7nfLHhZqfirsXxrwd1wrlwCGOoOy0dukyB8T8JiUIAes/iGqJ0 TFKTo3Zp5Iua0TXNgtWN/SX7OTRn2x7kF68n1WRwt3lL/NOIdZTH7JHP5q7+OQetuCxH Sipz4FhJEuNhTd/Qmrb1RfLpJBFofwKZpWgu925lrKEIkgMMJKXuwXElCRt2JTe1blzs BIkQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=BZHBlomk; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.32.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:32:49 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:31:58 +0000 Message-Id: <20180321163235.12529-3-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 02/39] ARM: GIC: add GIC_INVALID to enum gic_version X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The enum gic_version at the moment just contains GIC_V2 and GIC_V3, where GIC_V2 happens to map to 0. So without having initialised a variable of that type, we will read back GIC_V2 (when allocated with zeroing the memory). To prevent ambiguities and to give an explicitly uninitialised state, add a new first member: GIC_INVALID. Also make it obvious that this has a "0" encoding. Signed-off-by: Andre Przywara Acked-by: Julien Grall Acked-by: Stefano Stabellini --- xen/include/asm-arm/gic.h | 1 + 1 file changed, 1 insertion(+) diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 565b0875ca..3079387e06 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -227,6 +227,7 @@ struct gic_lr { }; enum gic_version { + GIC_INVALID = 0, /* the default until explicitly set up */ GIC_V2, GIC_V3, }; From patchwork Wed Mar 21 16:31:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132225 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356203ljb; Wed, 21 Mar 2018 09:35:07 -0700 (PDT) X-Google-Smtp-Source: AG47ELss0WfDGkEypy2Sj3d3SR60bsnifg8tqfjGVJwVM2rqy+OfNA0z1yBhljIEtFpP4rzPNgKQ X-Received: by 10.107.136.33 with SMTP id k33mr20668608iod.4.1521650107151; Wed, 21 Mar 2018 09:35:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650107; cv=none; d=google.com; s=arc-20160816; b=kIavBP6cbACunBo6UoR4wrqWICl0W1YIzW1oV7xVuL7X8PPd1y4E3DsMVFdwGo84Hs xG4VSQHkIDPQyNKq2DD1edSojSIX5gIxt3gU1t+y7NcJXZgG4z6xEg49h9e+/75c10oS HEuKai5q7Wd4dOscYpsj/uhbI+JzHCCNhhgncnMp4JvQgKUoCDipImw+67JBYEWB6lyn aBGhkJTYwy7K789xwu+yIgRubX/1YXJxNzJ0/kbWaFPU0P53K1hKC8Cxof7MlaEs9ib3 2vfCrTshShOgaGNqJ7kyvBAS8EaK79LKZpyPLJhRflfvliePFjLuxgQbX8Z8DwZEWlty 1IIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=ypkU3MtlY5vwmXC2iPCe7XIAcbqFHq/i68B2OOyeJvE=; b=Uk/g/4Ztkigr1ng2zcDFjAE3yb9Z+9BMbyM/ql0EQLwhnP+Y8XhJxDJxH3Shu7tRJu Rpnia1ghWEWUZCtEFL1VwTPXSQUHUk3iaIDhl7c6VnameWGg6R8f80vbA4uZVRlydFQq z3ChaNpOdlTFXvSu+BPiBjUw8AJllo2uOhaKH18B9uyJJOae+31iDQ0KztAATBnxNxaI WcEfS94fJ0iMxDIkgMY2itTjVjWSm89dUWxVNqv9EEvKrrOW694h85sfaW0P6WAEqSxF QiAKhS0ii4oWKjxkXwZJFrJzBScG6IXEIG2Cn9qXaoRnNU6eSNcNJW5MKznQyRPD9VFU NLDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=b4O8Kdci; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.32.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:32:50 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:31:59 +0000 Message-Id: <20180321163235.12529-4-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 03/39] ARM: GIC: Allow tweaking the active and pending state of an IRQ X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" When playing around with hardware mapped, level triggered virtual IRQs, there is the need to explicitly set the active or pending state of an interrupt at some point. To prepare the GIC for that, we introduce a set_active_state() and a set_pending_state() function to let the VGIC manipulate the state of an associated hardware IRQ. This takes care of properly setting the _IRQ_INPROGRESS bit. Signed-off-by: Andre Przywara --- Changelog v2 ... v3: - rework setting _IRQ_INPROGRESS bit: - no change when changing active state - unconditional set/clear on changing pending state - drop introduction of gicv[23]_peek_irq() (only needed in the next patch now) Changelog v1 ... v2: - properly set _IRQ_INPROGRESS bit - add gicv[23]_peek_irq() (pulled in from later patch) - move wrappers functions into gic.h xen/arch/arm/gic-v2.c | 36 ++++++++++++++++++++++++++++++++++++ xen/arch/arm/gic-v3.c | 32 ++++++++++++++++++++++++++++++++ xen/include/asm-arm/gic.h | 24 ++++++++++++++++++++++++ 3 files changed, 92 insertions(+) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index aa0fc6c1a1..d1f1578c05 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -243,6 +243,40 @@ static void gicv2_poke_irq(struct irq_desc *irqd, uint32_t offset) writel_gicd(1U << (irqd->irq % 32), offset + (irqd->irq / 32) * 4); } +static void gicv2_set_active_state(struct irq_desc *irqd, bool active) +{ + ASSERT(spin_is_locked(&irqd->lock)); + + if ( active ) + { + if ( test_bit(_IRQ_GUEST, &irqd->status) ) + set_bit(_IRQ_INPROGRESS, &irqd->status); + gicv2_poke_irq(irqd, GICD_ISACTIVER); + } + else + { + if ( test_bit(_IRQ_GUEST, &irqd->status) ) + clear_bit(_IRQ_INPROGRESS, &irqd->status); + gicv2_poke_irq(irqd, GICD_ICACTIVER); + } +} + +static void gicv2_set_pending_state(struct irq_desc *irqd, bool pending) +{ + ASSERT(spin_is_locked(&irqd->lock)); + + if ( pending ) + { + /* The _IRQ_INPROGRESS bit will be set when the interrupt fires. */ + gicv2_poke_irq(irqd, GICD_ISPENDR); + } + else + { + /* The _IRQ_INPROGRESS remains unchanged. */ + gicv2_poke_irq(irqd, GICD_ICPENDR); + } +} + static void gicv2_set_irq_type(struct irq_desc *desc, unsigned int type) { uint32_t cfg, actual, edgebit; @@ -1278,6 +1312,8 @@ const static struct gic_hw_operations gicv2_ops = { .eoi_irq = gicv2_eoi_irq, .deactivate_irq = gicv2_dir_irq, .read_irq = gicv2_read_irq, + .set_active_state = gicv2_set_active_state, + .set_pending_state = gicv2_set_pending_state, .set_irq_type = gicv2_set_irq_type, .set_irq_priority = gicv2_set_irq_priority, .send_SGI = gicv2_send_SGI, diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index cb41844af2..f244d51661 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -477,6 +477,36 @@ static unsigned int gicv3_read_irq(void) return irq; } +static void gicv3_set_active_state(struct irq_desc *irqd, bool active) +{ + ASSERT(spin_is_locked(&irqd->lock)); + + if ( active ) + { + if ( test_bit(_IRQ_GUEST, &irqd->status) ) + set_bit(_IRQ_INPROGRESS, &irqd->status); + gicv3_poke_irq(irqd, GICD_ISACTIVER, false); + } + else + { + if ( test_bit(_IRQ_GUEST, &irqd->status) ) + clear_bit(_IRQ_INPROGRESS, &irqd->status); + gicv3_poke_irq(irqd, GICD_ICACTIVER, false); + } +} + +static void gicv3_set_pending_state(struct irq_desc *irqd, bool pending) +{ + ASSERT(spin_is_locked(&irqd->lock)); + + if ( pending ) + /* The _IRQ_INPROGRESS bit will be set when the interrupt fires. */ + gicv3_poke_irq(irqd, GICD_ISPENDR, false); + else + /* The _IRQ_INPROGRESS bit will remain unchanged. */ + gicv3_poke_irq(irqd, GICD_ICPENDR, false); +} + static inline uint64_t gicv3_mpidr_to_affinity(int cpu) { uint64_t mpidr = cpu_logical_map(cpu); @@ -1769,6 +1799,8 @@ static const struct gic_hw_operations gicv3_ops = { .eoi_irq = gicv3_eoi_irq, .deactivate_irq = gicv3_dir_irq, .read_irq = gicv3_read_irq, + .set_active_state = gicv3_set_active_state, + .set_pending_state = gicv3_set_pending_state, .set_irq_type = gicv3_set_irq_type, .set_irq_priority = gicv3_set_irq_priority, .send_SGI = gicv3_send_sgi, diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 3079387e06..2aca243ac3 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -345,6 +345,10 @@ struct gic_hw_operations { void (*deactivate_irq)(struct irq_desc *irqd); /* Read IRQ id and Ack */ unsigned int (*read_irq)(void); + /* Force the active state of an IRQ by accessing the distributor */ + void (*set_active_state)(struct irq_desc *irqd, bool state); + /* Force the pending state of an IRQ by accessing the distributor */ + void (*set_pending_state)(struct irq_desc *irqd, bool state); /* Set IRQ type */ void (*set_irq_type)(struct irq_desc *desc, unsigned int type); /* Set IRQ priority */ @@ -393,6 +397,26 @@ static inline unsigned int gic_get_nr_lrs(void) return gic_hw_ops->info->nr_lrs; } +/* + * Set the active state of an IRQ. This should be used with care, as this + * directly forces the active bit, without considering the GIC state machine. + * For private IRQs this only works for those of the current CPU. + */ +static inline void gic_set_active_state(struct irq_desc *irqd, bool state) +{ + gic_hw_ops->set_active_state(irqd, state); +} + +/* + * Set the pending state of an IRQ. This should be used with care, as this + * directly forces the pending bit, without considering the GIC state machine. + * For private IRQs this only works for those of the current CPU. + */ +static inline void gic_set_pending_state(struct irq_desc *irqd, bool state) +{ + gic_hw_ops->set_pending_state(irqd, state); +} + void register_gic_ops(const struct gic_hw_operations *ops); int gic_make_hwdom_dt_node(const struct domain *d, const struct dt_device_node *gic, From patchwork Wed Mar 21 16:32:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132226 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356211ljb; Wed, 21 Mar 2018 09:35:07 -0700 (PDT) X-Google-Smtp-Source: AG47ELvz8EX8EBpf2TIDyHqJQ7qMTrZ7aj8DHuzYPvfYF/CkqQvNNomzA05XqZqqxAYwmA1qv4uZ X-Received: by 2002:a24:2b50:: with SMTP id h77-v6mr4887255ita.103.1521650107389; Wed, 21 Mar 2018 09:35:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650107; cv=none; d=google.com; s=arc-20160816; b=L365USwAHaciNYTY1rSD2/gLryk+I5Z3idXgFLqa0iIwZmEXuAo4kLIrzhOpQdcDWa NdnArM85E2bK2wF8XCOgXN+8ZtGYaVzxU5iiwqNsRy7POgrseywgXuC+LnHP4LRgAwGg LgOUVRqRuAKpk/ChI0xW6YJkk8P8d5WKFKLlDiic3wdFnL85exIULnl1e9luwt++IKtE Sp3D1rvSsvNW8O+L56qDNlutvAfBXoZgr5eBdrocG7n/zFC6qZKPTZB8yKWZJCVVCTrb jXacLZirBHUpWUL0LJ/4OGr/Qvkx/ej8Pd9xXUr/85IXVNYj068KgFhD8ZNXB/kNulxu 7iTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=sHuy/BLU83cKCDKuwlPJsjOpGYjEJMGu/rEqfHEIt1g=; b=ksZeHpdXnu+rtlk+WxMKHMlRheXF3y0VWroP8/L5eD9K0hoGLDBn97KOJnWsoevIAU Zube5wn3c7+oVH/B1/UJwv1XuYqPEoprXm/GJtv7w3w5YR+71JapibqXSLJIgWYVnSf0 wIFKw2sv0qYXNN222TCC75GE39ndKHhuk2bmZJZb9LZRf0znVFHlKXEFEfZxA/TyL+Uy oBc18cHEBT/w8lbscGg/EnL16ONztMpiUk8A/4He2xyYW8qMICt7b/S5WDNhkMXIZHZm O6Ns0mLXMWJle949k6ZuaffRAJpNz367hqjQz/Kd8XY3Kt63qiHQU/w3XBlC/ePS03XR eeQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=G9HdBZa7; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.32.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:32:51 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:00 +0000 Message-Id: <20180321163235.12529-5-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 04/39] ARM: GIC: Allow reading pending state of a hardware IRQ X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" To synchronize level triggered interrupts which are mapped into a guest, we need to update the virtual line level at certain points in time. For a hardware mapped interrupt the GIC is the only place where we can easily access this information. Implement a gic_hw_operations member to return the pending state of a particular interrupt. Due to hardware limitations this only works for private interrupts of the current CPU, so there is no CPU field in the prototype. This adds gicv2/3_peek_irq() helper functions, to read a bit in a bitmap spread over several MMIO registers. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall Acked-by: Stefano Stabellini --- Changelog v2 ... v3: - introduce gicv[23]_peek_irq() (moved from patch before) xen/arch/arm/gic-v2.c | 15 +++++++++++++++ xen/arch/arm/gic-v3.c | 19 +++++++++++++++++++ xen/include/asm-arm/gic.h | 11 +++++++++++ 3 files changed, 45 insertions(+) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index d1f1578c05..b440a45e8e 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -243,6 +243,15 @@ static void gicv2_poke_irq(struct irq_desc *irqd, uint32_t offset) writel_gicd(1U << (irqd->irq % 32), offset + (irqd->irq / 32) * 4); } +static bool gicv2_peek_irq(struct irq_desc *irqd, uint32_t offset) +{ + uint32_t reg; + + reg = readl_gicd(offset + (irqd->irq / 32) * 4) & (1U << (irqd->irq % 32)); + + return reg; +} + static void gicv2_set_active_state(struct irq_desc *irqd, bool active) { ASSERT(spin_is_locked(&irqd->lock)); @@ -580,6 +589,11 @@ static unsigned int gicv2_read_apr(int apr_reg) return readl_gich(GICH_APR); } +static bool gicv2_read_pending_state(struct irq_desc *irqd) +{ + return gicv2_peek_irq(irqd, GICD_ISPENDR); +} + static void gicv2_irq_enable(struct irq_desc *desc) { unsigned long flags; @@ -1325,6 +1339,7 @@ const static struct gic_hw_operations gicv2_ops = { .write_lr = gicv2_write_lr, .read_vmcr_priority = gicv2_read_vmcr_priority, .read_apr = gicv2_read_apr, + .read_pending_state = gicv2_read_pending_state, .make_hwdom_dt_node = gicv2_make_hwdom_dt_node, .make_hwdom_madt = gicv2_make_hwdom_madt, .get_hwdom_extra_madt_size = gicv2_get_hwdom_extra_madt_size, diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index f244d51661..5c9a783968 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -444,6 +444,19 @@ static void gicv3_poke_irq(struct irq_desc *irqd, u32 offset, bool wait_for_rwp) gicv3_wait_for_rwp(irqd->irq); } +static bool gicv3_peek_irq(struct irq_desc *irqd, u32 offset) +{ + void __iomem *base; + unsigned int irq = irqd->irq; + + if ( irq >= NR_GIC_LOCAL_IRQS) + base = GICD + (irq / 32) * 4; + else + base = GICD_RDIST_SGI_BASE; + + return !!(readl(base + offset) & (1U << (irq % 32))); +} + static void gicv3_unmask_irq(struct irq_desc *irqd) { gicv3_poke_irq(irqd, GICD_ISENABLER, false); @@ -1144,6 +1157,11 @@ static unsigned int gicv3_read_apr(int apr_reg) } } +static bool gicv3_read_pending_state(struct irq_desc *irqd) +{ + return gicv3_peek_irq(irqd, GICD_ISPENDR); +} + static void gicv3_irq_enable(struct irq_desc *desc) { unsigned long flags; @@ -1812,6 +1830,7 @@ static const struct gic_hw_operations gicv3_ops = { .write_lr = gicv3_write_lr, .read_vmcr_priority = gicv3_read_vmcr_priority, .read_apr = gicv3_read_apr, + .read_pending_state = gicv3_read_pending_state, .secondary_init = gicv3_secondary_cpu_init, .make_hwdom_dt_node = gicv3_make_hwdom_dt_node, .make_hwdom_madt = gicv3_make_hwdom_madt, diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 2aca243ac3..58b910fe6a 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -373,6 +373,8 @@ struct gic_hw_operations { unsigned int (*read_vmcr_priority)(void); /* Read APRn register */ unsigned int (*read_apr)(int apr_reg); + /* Query the pending state of an interrupt at the distributor level. */ + bool (*read_pending_state)(struct irq_desc *irqd); /* Secondary CPU init */ int (*secondary_init)(void); /* Create GIC node for the hardware domain */ @@ -417,6 +419,15 @@ static inline void gic_set_pending_state(struct irq_desc *irqd, bool state) gic_hw_ops->set_pending_state(irqd, state); } +/* + * Read the pending state of an interrupt from the distributor. + * For private IRQs this only works for those of the current CPU. + */ +static inline bool gic_read_pending_state(struct irq_desc *irqd) +{ + return gic_hw_ops->read_pending_state(irqd); +} + void register_gic_ops(const struct gic_hw_operations *ops); int gic_make_hwdom_dt_node(const struct domain *d, const struct dt_device_node *gic, From patchwork Wed Mar 21 16:32:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132217 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356053ljb; 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.32.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:32:52 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:01 +0000 Message-Id: <20180321163235.12529-6-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 05/39] ARM: timer: Handle level triggered IRQs correctly X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The ARM Generic Timer uses a level-sensitive interrupt semantic. We easily catch when the line goes high, as this triggers the hardware IRQ. However we also have to keep track of when the line lowers, as the emulation depends on it: Upon entering the guest, the new VGIC will *clear* the virtual interrupt line, so it needs to re-sample the actual state after returning from the guest. So we have to sync the state of the interrupt condition at certain points to catch when the line goes low and we can remove the vtimer vIRQ from the vGIC (and the LR). The VGIC in Xen so far only implemented edge triggered vIRQs, really, so we need to add new functionality to re-sample the interrupt state. Do this only when the new VGIC is in use. Signed-off-by: Andre Przywara Acked-by: Julien Grall Acked-by: Stefano Stabellini --- Changelog v2 ... v3: - move vtimer_sync() from time.c into vtimer.c - rename function to vtimer_update_irqs() - refactor functionality into new static function, to ... - handle physical timer as well - extending comments Changelog v1 ... v2: - restrict to new VGIC - add TODO: comment xen/arch/arm/traps.c | 11 ++++++++++ xen/arch/arm/vtimer.c | 49 ++++++++++++++++++++++++++++++++++++++++++++ xen/include/asm-arm/vtimer.h | 1 + 3 files changed, 61 insertions(+) diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 7411bff7a7..2638446693 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -2024,6 +2024,17 @@ static void enter_hypervisor_head(struct cpu_user_regs *regs) if ( current->arch.hcr_el2 & HCR_VA ) current->arch.hcr_el2 = READ_SYSREG(HCR_EL2); +#ifdef CONFIG_NEW_VGIC + /* + * We need to update the state of our emulated devices using level + * triggered interrupts before syncing back the VGIC state. + * + * TODO: Investigate whether this is necessary to do on every + * trap and how it can be optimised. + */ + vtimer_update_irqs(current); +#endif + vgic_sync_from_lrs(current); } } diff --git a/xen/arch/arm/vtimer.c b/xen/arch/arm/vtimer.c index 8164f6c7f1..c99dd237d1 100644 --- a/xen/arch/arm/vtimer.c +++ b/xen/arch/arm/vtimer.c @@ -334,6 +334,55 @@ bool vtimer_emulate(struct cpu_user_regs *regs, union hsr hsr) } } +static void vtimer_update_irq(struct vcpu *v, struct vtimer *vtimer, + uint32_t vtimer_ctl) +{ + bool level; + + /* Filter for the three bits that determine the status of the timer */ + vtimer_ctl &= (CNTx_CTL_ENABLE | CNTx_CTL_PENDING | CNTx_CTL_MASK); + + /* The level is high if the timer is pending and enabled, but not masked. */ + level = (vtimer_ctl == (CNTx_CTL_ENABLE | CNTx_CTL_PENDING)); + + /* + * This is mostly here to *lower* the virtual interrupt line if the timer + * is no longer pending. + * We would have injected an IRQ already via SOFTIRQ when the timer expired. + * Doing it here again is basically a NOP if the line was already high. + */ + vgic_inject_irq(v->domain, v, vtimer->irq, level); +} + +/** + * vtimer_update_irqs() - update the virtual timers' IRQ lines after a guest run + * @vcpu: The VCPU to sync the timer state + * + * After returning from a guest, update the state of the timers' virtual + * interrupt lines, to model the level triggered interrupts correctly. + * If the guest has handled a timer interrupt, the virtual interrupt line + * needs to be lowered explicitly. vgic_inject_irq() takes care of that. + */ +void vtimer_update_irqs(struct vcpu *v) +{ + /* + * For the virtual timer we read the current state from the hardware. + * Technically we should keep the CNTx_CTL_MASK bit here, to catch if + * the timer interrupt is masked. However Xen *always* masks the timer + * upon entering the hypervisor, leaving it up to the guest to un-mask it. + * So we would always read a "low" level, despite the condition being + * actually "high". Ignoring the mask bit solves this (for now). + * + * TODO: The proper fix for this is to make vtimer vIRQ hardware mapped, + * but this requires reworking the arch timer to implement this. + */ + vtimer_update_irq(v, &v->arch.virt_timer, + READ_SYSREG32(CNTV_CTL_EL0) & ~CNTx_CTL_MASK); + + /* For the physical timer we rely on our emulated state. */ + vtimer_update_irq(v, &v->arch.phys_timer, v->arch.phys_timer.ctl); +} + /* * Local variables: * mode: C diff --git a/xen/include/asm-arm/vtimer.h b/xen/include/asm-arm/vtimer.h index 5aaddc6f63..91d88b377f 100644 --- a/xen/include/asm-arm/vtimer.h +++ b/xen/include/asm-arm/vtimer.h @@ -27,6 +27,7 @@ extern bool vtimer_emulate(struct cpu_user_regs *regs, union hsr hsr); extern int virt_timer_save(struct vcpu *v); extern int virt_timer_restore(struct vcpu *v); extern void vcpu_timer_destroy(struct vcpu *v); +void vtimer_update_irqs(struct vcpu *v); #endif From patchwork Wed Mar 21 16:32:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132228 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356277ljb; Wed, 21 Mar 2018 09:35:10 -0700 (PDT) X-Google-Smtp-Source: AG47ELum3bM7Dl3Hj38eCvAgZJDWV9c6ebkeVUuTHzrCMOA9EPSPzzi8fR1Kmqc4pByoq+M1zISj X-Received: by 2002:a24:3715:: with SMTP id r21-v6mr4941946itr.110.1521650110667; Wed, 21 Mar 2018 09:35:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650110; cv=none; d=google.com; s=arc-20160816; b=eAgmxyEVoa+SmALfj9Suw/hQjC81qbLj6IZD0GSUXW+vxnwxRMmYX0HVi0f+AGpMc/ OdeYwG7hSZmAp8FD+cK9On9Kpqb5nuajLMJhFF2Z/v44B+PpS3jPlOqfhxPjyMeNeRrQ f4PLATlNwEtWDWhXOwHu3CnotvFk9tYWcas/LfOXiRKxdYmRpmU7Ua162/p6z29pg4Iw VXGy+zTr1UBzdFxG3y8U6r7leneYZGMK4W31+jhUzxaMGXJg7Tt/xSts6tXZ+ErbMNO5 HXyWzMX9DBwPbWXzQSg6/pK3vRKQ/BE+9X7eBS+i9x3xepOA0PxbPZuvv+3qK4NGciw8 iQmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=cNKVCaWTEtPEv1p9IQW2Y+2RrZOv4AU4ANXWqmMXiB0=; b=qWLLAR7TNWz98dSIoMyr7tEKtTfTepKyNKBm1yeBIwY8yQZmt2/MzJO3mqF9R0LFmN Zrsz0BAyuwQwtYcHcc6tZ5JQcWbXBfnes0sjrsSoUvcSuXvEcmq9fXAdSOaXlJfIXyRr COpYMhcMcn0PIYdr//z7Hyw9bG0ZbsDgOOLBFmzYxpDjpDRH3K/PsMjt4sDXp+MDUcrG x25fEIZeoyCipSqdoAOkTacQPmSd71RW9aprXJKO1hu5FzEfuz7tsv4at4b6rsGhSqgc 2gWGrg7h47gtTdcNPQVEm1aj3brLGcddH6dTYvakoNfwXjhxbyvtlaaJDz5U0XxPGDfq OlQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=D+eiZMTZ; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.32.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:32:53 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:02 +0000 Message-Id: <20180321163235.12529-7-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 06/39] ARM: evtchn: Handle level triggered IRQs correctly X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The event channel IRQ has level triggered semantics, however the current VGIC treats everything as edge triggered. To correctly process those IRQs, we have to lower the (virtual) IRQ line at some point in time, depending on whether ther interrupt condition still prevails. Check the per-VCPU evtchn_upcall_pending variable to make the interrupt line match its status, and call this function upon every hypervisor entry. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall Acked-by: Stefano Stabellini --- xen/arch/arm/domain.c | 7 +++++++ xen/arch/arm/traps.c | 1 + xen/include/asm-arm/event.h | 1 + 3 files changed, 9 insertions(+) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index ff97f2bc76..9688e62f78 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -953,6 +953,13 @@ void vcpu_mark_events_pending(struct vcpu *v) vgic_inject_irq(v->domain, v, v->domain->arch.evtchn_irq, true); } +void vcpu_update_evtchn_irq(struct vcpu *v) +{ + bool pending = vcpu_info(v, evtchn_upcall_pending); + + vgic_inject_irq(v->domain, v, v->domain->arch.evtchn_irq, pending); +} + /* The ARM spec declares that even if local irqs are masked in * the CPSR register, an irq should wake up a cpu from WFI anyway. * For this reason we need to check for irqs that need delivery, diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index 2638446693..5c18e918b0 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -2033,6 +2033,7 @@ static void enter_hypervisor_head(struct cpu_user_regs *regs) * trap and how it can be optimised. */ vtimer_update_irqs(current); + vcpu_update_evtchn_irq(current); #endif vgic_sync_from_lrs(current); diff --git a/xen/include/asm-arm/event.h b/xen/include/asm-arm/event.h index c7a415ef57..2f51864043 100644 --- a/xen/include/asm-arm/event.h +++ b/xen/include/asm-arm/event.h @@ -6,6 +6,7 @@ void vcpu_kick(struct vcpu *v); void vcpu_mark_events_pending(struct vcpu *v); +void vcpu_update_evtchn_irq(struct vcpu *v); void vcpu_block_unless_event_pending(struct vcpu *v); static inline int vcpu_event_delivery_is_enabled(struct vcpu *v) From patchwork Wed Mar 21 16:32:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132238 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356177ljb; Wed, 21 Mar 2018 09:35:06 -0700 (PDT) X-Google-Smtp-Source: AG47ELtbs7k5xNNRZoAArwgiDAZ5/NmsX6Ouho0PaoGsD1pIpeo/V2WEGxk+6jfMqy/+iOMhzqoS X-Received: by 10.107.11.91 with SMTP id v88mr22805089ioi.28.1521650106013; Wed, 21 Mar 2018 09:35:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650106; cv=none; d=google.com; s=arc-20160816; b=pMxQBJx+jkC3H+/cXsB/IzxbwR331uLTu2vioggExDJH3dHNxWrQ0OGGdQoIjFrpyy XqH2HJRkO3lTw2S5m5v39WFOsYYlW9zLNcHv5jznbymEGBmAXl6aomA1mNfCzDrGI4Xj 9pIoesJRa3DMvGGTWr79R1oNq3D+pH7fkpV4ju/2wjUXTDaz/h8qTrC2vmmayOZz0h4z DY8+ieq9p0xBwIt+zGs0bzG0OtguJ6RsO3MUp+ifi365G3AqRp+FvE+echq/ecWImkcn OOc/QiXDTp4Vk3ufPoOEURdv5LPkbN8r69grJK+OI3tL0cS84ITDi+dl4ucXLp7aHOHD 7n9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=w+ryh0V/sZt9hJGxrcEdh/i65PFc05E3EXj664gwD1c=; b=UlUgaAq/9ZixDYNwX7zF3C4xfAC02RH7+wYDGa/EnRoCLlpViJT646scraZ9kFONeR dIjI1hs8EZq+bdbZfQYXzt+D+5VD2ffae55YpQJfJL7x67K+vP/OMDx70WgDo4aubxr2 RBhkyIyzGDwB6U0RiswAZF5oIE894FXifqCH8E7xe4KmSgWaKB15w4Beo+IcBWeFjOCx rWT5dSl6avf5cBE0DJTXfxTKBNbscF6dl98MOm9xcbK+oiY5/Lv4fZyFHC65ZP9yC0uh hu/5i4eGMaOWj3HcQBbk+t5wKVDPj8STXZ3s0YSwzuZg6jX326b5levieIDqs40TCR/P r/cw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=WmXEdbYZ; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.32.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:32:54 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:03 +0000 Message-Id: <20180321163235.12529-8-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 07/39] ARM: vPL011: Use the VGIC's level triggered IRQs handling if available X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The emulated ARM SBSA UART is using level triggered IRQ semantics, however the current VGIC can only handle edge triggered IRQs, really. Disable the existing workaround for this problem in case we have the new VGIC in place, which can properly handle level triggered IRQs. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall Acked-by: Stefano Stabellini --- xen/arch/arm/vpl011.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/xen/arch/arm/vpl011.c b/xen/arch/arm/vpl011.c index 5dcf4bec18..a281eabd7e 100644 --- a/xen/arch/arm/vpl011.c +++ b/xen/arch/arm/vpl011.c @@ -54,6 +54,7 @@ static void vpl011_update_interrupt_status(struct domain *d) */ ASSERT(spin_is_locked(&vpl011->lock)); +#ifndef CONFIG_NEW_VGIC /* * TODO: PL011 interrupts are level triggered which means * that interrupt needs to be set/clear instead of being @@ -71,6 +72,9 @@ static void vpl011_update_interrupt_status(struct domain *d) vgic_inject_irq(d, NULL, GUEST_VPL011_SPI, true); vpl011->shadow_uartmis = uartmis; +#else + vgic_inject_irq(d, NULL, GUEST_VPL011_SPI, uartmis); +#endif } static uint8_t vpl011_read_data(struct domain *d) From patchwork Wed Mar 21 16:32:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132244 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2357952ljb; Wed, 21 Mar 2018 09:36:44 -0700 (PDT) X-Google-Smtp-Source: AG47ELsUx79wWWvQA8BM52kVOO2Fa+0M70CcgAbU1qHAiqgPRSTfKIc65lyUsrUAPU6czH3RL5Tm X-Received: by 2002:a24:2595:: with SMTP id g143-v6mr4968289itg.85.1521650112222; Wed, 21 Mar 2018 09:35:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650112; cv=none; d=google.com; s=arc-20160816; b=Xnikk/Wlm3sLKr7V4MMrPaSLK2cjHjZoH803n3+6+sVu7n6CzAGWI6cK+psOKmAvcI rZidiixN+74+DA/ZYWyKuc92KkQuF2mCtG7KwZHYMvF+8+Qaix6R+f0YT8CZAP/2seQQ NhY/HjsLdxHzRaSzT8Ta6wHSF21t8IchChEl0FoF6Z37suDvKokubs6SisP9IUKFNDW7 EHl64y3uUH1+pRWQ2sNBUBdYC403Mc7twJhuoPV4lPKFb3U0sfgxNwkhtlfCITJrN7ub iuTywgWy88pUvf/xBhJU9Sx7QF1EOc0Q3u/iHZ5UwSJBpqSF2pbUCUp8JUJMiYqVEXnY Yaog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=8QDQ3/9+iOPmUkA137XtdiWK/aIWvb0NeW+dZghfzVs=; b=MrYoXBHwn7C1lQcVaLv+9gYgPvniV5VRDJy3V6pQkIPZfdM2SKlnEfmU+pomFNcXM6 Eu9fXKWg5X8MyHBPXhJhODpCaCR77GZrJFDTWqMQd+ou+n/3W5BDJ9Rk8ygVbvCUEwEp gS9D2P9vJOlwxAZkygeNRUMEiZcE0AAJ0omRHhtPacPKTaeJyehDU23arZcipPR379kA V5w1KTKToAuZjtDNHLuLGmXJyqtCGLGhXh0Q6orI7kvfcHRdcn+sK7l1/I5Q/wpjYeMm tXMu4mUaB+5sSqTxqRQSi1jS9eJAUP1ZulD4zmoP8DApjuh7wCNMYhoOIk49lkQUqNPO zr3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Mb0AAmZ4; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.32.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:32:55 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:04 +0000 Message-Id: <20180321163235.12529-9-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 08/39] ARM: new VGIC: Add data structure definitions X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Add a new header file for the new and improved GIC implementation. The big change is that we now have a struct vgic_irq per IRQ instead of spreading all the information over various bitmaps in the ranks. We include this new header conditionally from within the old header file for the time being to avoid touching all the users. This is based on Linux commit b18b57787f5e, written by Christoffer Dall. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall Acked-by: Stefano Stabellini --- xen/include/asm-arm/new_vgic.h | 198 +++++++++++++++++++++++++++++++++++++++++ xen/include/asm-arm/vgic.h | 6 ++ 2 files changed, 204 insertions(+) create mode 100644 xen/include/asm-arm/new_vgic.h diff --git a/xen/include/asm-arm/new_vgic.h b/xen/include/asm-arm/new_vgic.h new file mode 100644 index 0000000000..97d622bff6 --- /dev/null +++ b/xen/include/asm-arm/new_vgic.h @@ -0,0 +1,198 @@ +/* + * Copyright (C) 2015, 2016 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __ASM_ARM_NEW_VGIC_H +#define __ASM_ARM_NEW_VGIC_H + +#include +#include +#include +#include +#include + +#define VGIC_V3_MAX_CPUS 255 +#define VGIC_V2_MAX_CPUS 8 +#define VGIC_NR_SGIS 16 +#define VGIC_NR_PPIS 16 +#define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS) +#define VGIC_MAX_PRIVATE (VGIC_NR_PRIVATE_IRQS - 1) +#define VGIC_MAX_SPI 1019 +#define VGIC_MAX_RESERVED 1023 +#define VGIC_MIN_LPI 8192 + +#define irq_is_ppi(irq) ((irq) >= VGIC_NR_SGIS && (irq) < VGIC_NR_PRIVATE_IRQS) +#define irq_is_spi(irq) ((irq) >= VGIC_NR_PRIVATE_IRQS && \ + (irq) <= VGIC_MAX_SPI) + +enum vgic_type { + VGIC_V2, /* Good ol' GICv2 */ + VGIC_V3, /* New fancy GICv3 */ +}; + +#define VGIC_V2_MAX_LRS (1 << 6) +#define VGIC_V3_MAX_LRS 16 +#define VGIC_V3_LR_INDEX(lr) (VGIC_V3_MAX_LRS - 1 - lr) + +#define VGIC_CONFIG_EDGE false +#define VGIC_CONFIG_LEVEL true + +struct vgic_irq { + struct list_head ap_list; + + struct vcpu *vcpu; /* + * SGIs and PPIs: The VCPU + * SPIs and LPIs: The VCPU whose ap_list + * this is queued on. + */ + + struct vcpu *target_vcpu; /* + * The VCPU that this interrupt should + * be sent to, as a result of the + * targets reg (v2) or the affinity reg (v3). + */ + + spinlock_t irq_lock; /* Protects the content of the struct */ + uint32_t intid; /* Guest visible INTID */ + atomic_t refcount; /* Used for LPIs */ + uint32_t hwintid; /* HW INTID number */ + union + { + struct { + uint8_t targets; /* GICv2 target VCPUs mask */ + uint8_t source; /* GICv2 SGIs only */ + }; + uint32_t mpidr; /* GICv3 target VCPU */ + }; + uint8_t priority; + bool line_level:1; /* Level only */ + bool pending_latch:1; /* + * The pending latch state used to + * calculate the pending state for both + * level and edge triggered IRQs. + */ + bool active:1; /* not used for LPIs */ + bool enabled:1; + bool hw:1; /* Tied to HW IRQ */ + bool config:1; /* Level or edge */ + struct list_head lpi_list; /* Used to link all LPIs together */ +}; + +enum iodev_type { + IODEV_DIST, + IODEV_REDIST, +}; + +struct vgic_io_device { + gfn_t base_fn; + struct vcpu *redist_vcpu; + const struct vgic_register_region *regions; + enum iodev_type iodev_type; + unsigned int nr_regions; +}; + +struct vgic_dist { + bool ready; + bool initialized; + + /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */ + uint32_t version; + + /* Do injected MSIs require an additional device ID? */ + bool msis_require_devid; + + unsigned int nr_spis; + + /* base addresses in guest physical address space: */ + paddr_t vgic_dist_base; /* distributor */ + union + { + /* either a GICv2 CPU interface */ + paddr_t vgic_cpu_base; + /* or a number of GICv3 redistributor regions */ + struct + { + paddr_t vgic_redist_base; + paddr_t vgic_redist_free_offset; + }; + }; + + /* distributor enabled */ + bool enabled; + + struct vgic_irq *spis; + unsigned long *allocated_irqs; /* bitmap of IRQs allocated */ + + struct vgic_io_device dist_iodev; + + bool has_its; + + /* + * Contains the attributes and gpa of the LPI configuration table. + * Since we report GICR_TYPER.CommonLPIAff as 0b00, we can share + * one address across all redistributors. + * GICv3 spec: 6.1.2 "LPI Configuration tables" + */ + uint64_t propbaser; + + /* Protects the lpi_list and the count value below. */ + spinlock_t lpi_list_lock; + struct list_head lpi_list_head; + unsigned int lpi_list_count; +}; + +struct vgic_cpu { + struct vgic_irq private_irqs[VGIC_NR_PRIVATE_IRQS]; + + struct list_head ap_list_head; + spinlock_t ap_list_lock; /* Protects the ap_list */ + + unsigned int used_lrs; + + /* + * List of IRQs that this VCPU should consider because they are either + * Active or Pending (hence the name; AP list), or because they recently + * were one of the two and need to be migrated off this list to another + * VCPU. + */ + + /* + * Members below are used with GICv3 emulation only and represent + * parts of the redistributor. + */ + struct vgic_io_device rd_iodev; + struct vgic_io_device sgi_iodev; + + /* Contains the attributes and gpa of the LPI pending tables. */ + uint64_t pendbaser; + + bool lpis_enabled; + + /* Cache guest priority bits */ + uint32_t num_pri_bits; + + /* Cache guest interrupt ID bits */ + uint32_t num_id_bits; +}; + +#endif /* __ASM_ARM_NEW_VGIC_H */ + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 0787ba9549..2a58ea30fe 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -18,6 +18,10 @@ #ifndef __ASM_ARM_VGIC_H__ #define __ASM_ARM_VGIC_H__ +#ifdef CONFIG_NEW_VGIC +#include +#else + #include #include #include @@ -299,6 +303,8 @@ extern bool vgic_to_sgi(struct vcpu *v, register_t sgir, const struct sgi_target *target); extern bool vgic_migrate_irq(struct vcpu *old, struct vcpu *new, unsigned int irq); +#endif /* !CONFIG_NEW_VGIC */ + /*** Common VGIC functions used by Xen arch code ****/ /* From patchwork Wed Mar 21 16:32:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132243 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2357908ljb; Wed, 21 Mar 2018 09:36:41 -0700 (PDT) X-Google-Smtp-Source: AIpwx4/0c4eSPiwMnHa+EnVmSJejYdL7I0Ook0thBYSKkJin3Hsxa0+8wHXIpkpFmwcwudGlati7 X-Received: by 2002:a24:f246:: with SMTP id j67-v6mr4894686ith.90.1521650107345; Wed, 21 Mar 2018 09:35:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650107; cv=none; d=google.com; s=arc-20160816; b=oHPrJsm/lQH55viUEbyDTcTsQPVh64ZucL2CqXICYmieD/b4fpjb2lVS4/ibqzDBjQ 9Lr4fz7Xmx8YxESgWwHPZ92kbrsxnjn9PnDsm6+PugNeqm6pGgSXGHJuRSihNTNn91Dh VAHoXAn/rd2PajK5bUrAdaLNY7EXlRUH/xDWHRS6l1sxfYzNlklsxmrrh69j5fuZ10XE 2SLhEU1n9t5GtAcKdewZsKdMVxU5JA2UHokPvtAS7oI2/S2TNodR1mXtwluUW3tlgO3c mtih2jDfUx8eLB1RBoSPL2UWAvREgx+q7My374MxTCZQyFhpT/2F2YZYDR02IEA7WTPe 0TTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=4ebOFkyQq5nFSB15PJg4KFJJ2zIj/FGQtUajA7ukrL0=; b=tmUvP0EJu1DMRogUkMH2doSZDISxe7ylsWT/QNpd8/zcb+4QNcVvzPxatO8WLXsNE3 jsXvvtbrVoilQuugMUVJZVtuz2AAFTQP4XnBus3nTY/b0+eCHBx7wQFZRqm5Bk+D6ldi zo1e6SdKZoJ1Ed2X4fn64B49xjWAV6bM2fe/PI6lEpKwQihxtpWtv6vyQ1S8ZwC6t3sF V/1DfjI6Vk2dZajZTFs1KRBltINOWXJonnJXf0XMLUWNs56ZUsLeutCdUhLYOpbVaQiA pjthb2CpxOTBdzln4NYmyKesKhYyuE1NXwE5AUdSirYzaspTMH54v0rLksEQZyEy0P/5 1JcA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=HFxOAzZr; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id p187-v6si3496810itp.51.2018.03.21.09.35.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 21 Mar 2018 09:35:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=HFxOAzZr; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1eygfd-00027y-21; Wed, 21 Mar 2018 16:33:01 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1eygfc-00026o-7S for xen-devel@lists.xenproject.org; Wed, 21 Mar 2018 16:33:00 +0000 X-Inumbo-ID: 7adf377d-2d25-11e8-9728-bc764e045a96 Received: from mail-wm0-x243.google.com (unknown [2a00:1450:400c:c09::243]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 7adf377d-2d25-11e8-9728-bc764e045a96; Wed, 21 Mar 2018 17:32:44 +0100 (CET) Received: by mail-wm0-x243.google.com with SMTP id t6so11002355wmt.5 for ; Wed, 21 Mar 2018 09:32:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pb+lFVnLmibx8iRrLO0D4BtbZS8Rty6LQ+4Pq/SfDk0=; b=HFxOAzZrXUIgauG1KkKScWrtkkH+soXEYzdPLCdO+KCu0LU4UxgZ86sTVezYHuSXzN aP8M9nsQJorl82y2gncBvfM7iIB6YEllPGkIbqDrwpDe4oqLnrHC8UyRftaP3QzeHyPt NnW9SCGflOhPR3irDHkETJI6apR4D8hZ1Zczo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pb+lFVnLmibx8iRrLO0D4BtbZS8Rty6LQ+4Pq/SfDk0=; b=HhTs7Xtc72QNCCS1B3zXidIu25chbHoF+tIN8TtSe3QmbLauN6Ebz2yJB60N+p4QkO raitxuMJtIlk7e6d3/2QmMtilfX4KX7yw1Z5rmxBYxFrvrvi2wPuxw9sG/bpUR6DIaEr zJ4MnMGLPO6TM3nWAaXHQY82YLbCEKv9jjBqjqoFVmACB/5h3GrRzYLSXfSz0tTpkdY4 fc9lfZzrEGabmJvwBAidVexSbqcRS8Er1+NoP3mK0ACmuPyA9hBRioHSb097MiZPaSmz ScEQbdZ9JfzfulUm6ejJeXxlgDD/Jx7Df8ZWwt4uZInS+365U5fgJDfbCIIVvs4OlCJc mQog== X-Gm-Message-State: AElRT7FvsuDWELkD42PIs+PAPYessrgJKylC8ORf1gU8OCtyyH55UNXi Asn4838+iPv+QgMedLYL/kg26w== X-Received: by 10.28.190.19 with SMTP id o19mr3190985wmf.53.1521649977448; Wed, 21 Mar 2018 09:32:57 -0700 (PDT) Received: from e104803-lin.lan (mail.andrep.de. [217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.32.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:32:56 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:05 +0000 Message-Id: <20180321163235.12529-10-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 09/39] ARM: new VGIC: Add accessor to new struct vgic_irq instance X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The new VGIC implementation centers around a struct vgic_irq instance per virtual IRQ. Provide a function to retrieve the right instance for a given IRQ number and (in case of private interrupts) the right VCPU. This also includes the corresponding put function, which does nothing for private interrupts and SPIs, but handles the ref-counting for LPIs. This is based on Linux commit 64a959d66e47, written by Christoffer Dall. Signed-off-by: Andre Przywara Acked-by: Julien Grall Acked-by: Stefano Stabellini --- Changelog v2 ... v3: - extend comments to note preliminary nature of vgic_get_lpi() Changelog v1 ... v2: - reorder header file inclusion xen/arch/arm/vgic/vgic.c | 134 +++++++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic.h | 41 +++++++++++++++ 2 files changed, 175 insertions(+) create mode 100644 xen/arch/arm/vgic/vgic.c create mode 100644 xen/arch/arm/vgic/vgic.h diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c new file mode 100644 index 0000000000..a818e382b1 --- /dev/null +++ b/xen/arch/arm/vgic/vgic.c @@ -0,0 +1,134 @@ +/* + * Copyright (C) 2015, 2016 ARM Ltd. + * Imported from Linux ("new" KVM VGIC) and heavily adapted to Xen. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include + +#include "vgic.h" + +/* + * Iterate over the VM's list of mapped LPIs to find the one with a + * matching interrupt ID and return a reference to the IRQ structure. + * + * TODO: This is more documentation of how it should be done. A list is + * not a good data structure for Dom0's LPIs, it merely serves as an + * example here how to properly do the locking, allocation and refcounting. + * So lpi_list_head should be replaced with something more appropriate. + */ +static struct vgic_irq *vgic_get_lpi(struct domain *d, u32 intid) +{ + struct vgic_dist *dist = &d->arch.vgic; + struct vgic_irq *irq = NULL; + + spin_lock(&dist->lpi_list_lock); + + list_for_each_entry( irq, &dist->lpi_list_head, lpi_list ) + { + if ( irq->intid != intid ) + continue; + + /* + * This increases the refcount, the caller is expected to + * call vgic_put_irq() later once it's finished with the IRQ. + */ + vgic_get_irq_kref(irq); + goto out_unlock; + } + irq = NULL; + +out_unlock: + spin_unlock(&dist->lpi_list_lock); + + return irq; +} + +/** + * vgic_get_irq() - obtain a reference to a virtual IRQ + * @d: The domain the virtual IRQ belongs to. + * @vcpu: For private IRQs (SGIs, PPIs) the virtual CPU this IRQ + * is associated with. Will be ignored for SPIs and LPIs. + * @intid: The virtual IRQ number. + * + * This looks up the virtual interrupt ID to get the corresponding + * struct vgic_irq. It also increases the refcount, so any caller is expected + * to call vgic_put_irq() once it's finished with this IRQ. + * + * Return: The pointer to the requested struct vgic_irq. + */ +struct vgic_irq *vgic_get_irq(struct domain *d, struct vcpu *vcpu, + u32 intid) +{ + /* SGIs and PPIs */ + if ( intid <= VGIC_MAX_PRIVATE ) + return &vcpu->arch.vgic.private_irqs[intid]; + + /* SPIs */ + if ( intid <= VGIC_MAX_SPI ) + return &d->arch.vgic.spis[intid - VGIC_NR_PRIVATE_IRQS]; + + /* LPIs */ + if ( intid >= VGIC_MIN_LPI ) + return vgic_get_lpi(d, intid); + + ASSERT_UNREACHABLE(); + + return NULL; +} + +/** + * vgic_put_irq() - drop the reference to a virtual IRQ + * @d: The domain the virtual IRQ belongs to. + * @irq: The pointer to struct vgic_irq, as obtained from vgic_get_irq(). + * + * This drops the reference to a virtual IRQ. It decreases the refcount + * of the pointer, so dynamic IRQs can be freed when no longer needed. + * This should always be called after a vgic_get_irq(), though the reference + * can be deliberately held for longer periods, if needed. + * + * TODO: A linked list is not a good data structure for LPIs in Dom0. + * Replace this with proper data structure once we get proper LPI support. + */ +void vgic_put_irq(struct domain *d, struct vgic_irq *irq) +{ + struct vgic_dist *dist = &d->arch.vgic; + + if ( irq->intid < VGIC_MIN_LPI ) + return; + + spin_lock(&dist->lpi_list_lock); + if ( !atomic_dec_and_test(&irq->refcount) ) + { + spin_unlock(&dist->lpi_list_lock); + return; + }; + + list_del(&irq->lpi_list); + dist->lpi_list_count--; + spin_unlock(&dist->lpi_list_lock); + + xfree(irq); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h new file mode 100644 index 0000000000..a3befd386b --- /dev/null +++ b/xen/arch/arm/vgic/vgic.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2015, 2016 ARM Ltd. + * Imported from Linux ("new" KVM VGIC) and heavily adapted to Xen. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __XEN_ARM_VGIC_VGIC_H__ +#define __XEN_ARM_VGIC_VGIC_H__ + +struct vgic_irq *vgic_get_irq(struct domain *d, struct vcpu *vcpu, + u32 intid); +void vgic_put_irq(struct domain *d, struct vgic_irq *irq); + +static inline void vgic_get_irq_kref(struct vgic_irq *irq) +{ + if ( irq->intid < VGIC_MIN_LPI ) + return; + + atomic_inc(&irq->refcount); +} + +#endif + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Wed Mar 21 16:32:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132220 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356109ljb; Wed, 21 Mar 2018 09:35:03 -0700 (PDT) X-Google-Smtp-Source: AG47ELsrSgAORdBy+mo8mrZ1/BCJGADflLA70/DyYfreV5pmvk+Ta1aziuLUHsJ1f8aVrAFCvF4j X-Received: by 10.107.53.146 with SMTP id k18mr23143258ioo.292.1521650102866; Wed, 21 Mar 2018 09:35:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650102; cv=none; d=google.com; s=arc-20160816; b=S9jPCEp7FEq/1pTaIs77srBqzzKabBSSUTVbZ/Rh6nBdF1Di3RkYhefFTJHObieGLy W+0RizRo3GkvXBt2LJDearjr10gUS7tsqkrHqe4XK4TGnoxwv8OEdbffRZMfUH4OLxzl B0izvCehDAWn3RR6AI32C4KwWoSHvHQPUusVCkkQiLCojztUHJk5SaHecu4w9umuyDcr DVzCRJqv1BD2nPk0sKBESVz2MKKJ5aSdzUDmDKgFMqcR7aw3LOvIELyiyrExsAwAPYeK pQBIHDYf09EajHPgTs/7/2kgQyQZvlXpUSPctWwzqlauOpRVKZUjpZTKQ957ABZMBly1 NvNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=tP9Oso9E/8hncupFh1386+uwFdr5F/O1AYi/rz3zW6c=; b=de23Z7QZiivdQg8sF8JmDarzRyFsbqpnV97apNqlFhT1l74jqwWMiBLTtmG751amDX VO985wjL89o25RWla96LPzmbht1TCtBKbFiFhroz7ie93ylxyStQqDgko9t6DFH36BsY 1mXQAaoy65sP64bMQNfevqBkxGrtoi90K40J7GpV8FLdvLpKswA6hWD1WsGP7keCICJT Hh85BaHtSks6QeAmxmVTqCVGCl39GQ4d5XpF1XGiQPz8kSpcfO7qSDcmE8FnAWsjXJUX YsNWi76vbLZl5lb2/i1AmpRqe97/7nXGowgmF4fgLuzu1k5Jl3e+1379aqsjKoReK9vM 7yDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=anJAsP9Y; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.32.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:32:58 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:06 +0000 Message-Id: <20180321163235.12529-11-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 10/39] ARM: new VGIC: Implement virtual IRQ injection X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Provide a vgic_queue_irq_unlock() function which decides whether a given IRQ needs to be queued to a VCPU's ap_list. This should be called whenever an IRQ becomes pending or enabled, either as a result of a hardware IRQ injection, from devices emulated by Xen (like the architected timer) or from MMIO accesses to the distributor emulation. Also provides the necessary functions to allow to inject an IRQ to a guest. Since this is the first code that starts using our locking mechanism, we add some (hopefully) clear documentation of our locking strategy and requirements along with this patch. This is based on Linux commit 81eeb95ddbab, written by Christoffer Dall. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/arch/arm/vgic/vgic.c | 226 +++++++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic.h | 10 +++ 2 files changed, 236 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index a818e382b1..f7dfd01c1d 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -17,10 +17,36 @@ #include #include +#include #include #include "vgic.h" +/* + * Locking order is always: + * vgic->lock + * vgic_cpu->ap_list_lock + * vgic->lpi_list_lock + * desc->lock + * vgic_irq->irq_lock + * + * If you need to take multiple locks, always take the upper lock first, + * then the lower ones, e.g. first take the ap_list_lock, then the irq_lock. + * If you are already holding a lock and need to take a higher one, you + * have to drop the lower ranking lock first and re-acquire it after having + * taken the upper one. + * + * When taking more than one ap_list_lock at the same time, always take the + * lowest numbered VCPU's ap_list_lock first, so: + * vcpuX->vcpu_id < vcpuY->vcpu_id: + * spin_lock(vcpuX->arch.vgic.ap_list_lock); + * spin_lock(vcpuY->arch.vgic.ap_list_lock); + * + * Since the VGIC must support injecting virtual interrupts from ISRs, we have + * to use the spin_lock_irqsave/spin_unlock_irqrestore versions of outer + * spinlocks for any lock that may be taken while injecting an interrupt. + */ + /* * Iterate over the VM's list of mapped LPIs to find the one with a * matching interrupt ID and return a reference to the IRQ structure. @@ -124,6 +150,206 @@ void vgic_put_irq(struct domain *d, struct vgic_irq *irq) xfree(irq); } +/** + * vgic_target_oracle() - compute the target vcpu for an irq + * @irq: The irq to route. Must be already locked. + * + * Based on the current state of the interrupt (enabled, pending, + * active, vcpu and target_vcpu), compute the next vcpu this should be + * given to. Return NULL if this shouldn't be injected at all. + * + * Requires the IRQ lock to be held. + * + * Returns: The pointer to the virtual CPU this interrupt should be injected + * to. Will be NULL if this IRQ does not need to be injected. + */ +static struct vcpu *vgic_target_oracle(struct vgic_irq *irq) +{ + ASSERT(spin_is_locked(&irq->irq_lock)); + + /* If the interrupt is active, it must stay on the current vcpu */ + if ( irq->active ) + return irq->vcpu ? : irq->target_vcpu; + + /* + * If the IRQ is not active but enabled and pending, we should direct + * it to its configured target VCPU. + * If the distributor is disabled, pending interrupts shouldn't be + * forwarded. + */ + if ( irq->enabled && irq_is_pending(irq) ) + { + if ( unlikely(irq->target_vcpu && + !irq->target_vcpu->domain->arch.vgic.enabled) ) + return NULL; + + return irq->target_vcpu; + } + + /* + * If neither active nor pending and enabled, then this IRQ should not + * be queued to any VCPU. + */ + return NULL; +} + +/* + * Only valid injection if changing level for level-triggered IRQs or for a + * rising edge. + */ +static bool vgic_validate_injection(struct vgic_irq *irq, bool level) +{ + /* For edge interrupts we only care about a rising edge. */ + if ( irq->config == VGIC_CONFIG_EDGE ) + return level; + + /* For level interrupts we have to act when the line level changes. */ + return irq->line_level != level; +} + +/** + * vgic_queue_irq_unlock() - Queue an IRQ to a VCPU, to be injected to a guest. + * @d: The domain the virtual IRQ belongs to. + * @irq: A pointer to the vgic_irq of the virtual IRQ, with the lock held. + * @flags: The flags used when having grabbed the IRQ lock. + * + * Check whether an IRQ needs to (and can) be queued to a VCPU's ap list. + * Do the queuing if necessary, taking the right locks in the right order. + * + * Needs to be entered with the IRQ lock already held, but will return + * with all locks dropped. + */ +void vgic_queue_irq_unlock(struct domain *d, struct vgic_irq *irq, + unsigned long flags) +{ + struct vcpu *vcpu; + + ASSERT(spin_is_locked(&irq->irq_lock)); + +retry: + vcpu = vgic_target_oracle(irq); + if ( irq->vcpu || !vcpu ) + { + /* + * If this IRQ is already on a VCPU's ap_list, then it + * cannot be moved or modified and there is no more work for + * us to do. + * + * Otherwise, if the irq is not pending and enabled, it does + * not need to be inserted into an ap_list and there is also + * no more work for us to do. + */ + spin_unlock_irqrestore(&irq->irq_lock, flags); + + /* + * We have to kick the VCPU here, because we could be + * queueing an edge-triggered interrupt for which we + * get no EOI maintenance interrupt. In that case, + * while the IRQ is already on the VCPU's AP list, the + * VCPU could have EOI'ed the original interrupt and + * won't see this one until it exits for some other + * reason. + */ + if ( vcpu ) + vcpu_kick(vcpu); + + return; + } + + /* + * We must unlock the irq lock to take the ap_list_lock where + * we are going to insert this new pending interrupt. + */ + spin_unlock_irqrestore(&irq->irq_lock, flags); + + /* someone can do stuff here, which we re-check below */ + + spin_lock_irqsave(&vcpu->arch.vgic.ap_list_lock, flags); + spin_lock(&irq->irq_lock); + + /* + * Did something change behind our backs? + * + * There are two cases: + * 1) The irq lost its pending state or was disabled behind our + * backs and/or it was queued to another VCPU's ap_list. + * 2) Someone changed the affinity on this irq behind our + * backs and we are now holding the wrong ap_list_lock. + * + * In both cases, drop the locks and retry. + */ + + if ( unlikely(irq->vcpu || vcpu != vgic_target_oracle(irq)) ) + { + spin_unlock(&irq->irq_lock); + spin_unlock_irqrestore(&vcpu->arch.vgic.ap_list_lock, flags); + + spin_lock_irqsave(&irq->irq_lock, flags); + goto retry; + } + + /* + * Grab a reference to the irq to reflect the fact that it is + * now in the ap_list. + */ + vgic_get_irq_kref(irq); + list_add_tail(&irq->ap_list, &vcpu->arch.vgic.ap_list_head); + irq->vcpu = vcpu; + + spin_unlock(&irq->irq_lock); + spin_unlock_irqrestore(&vcpu->arch.vgic.ap_list_lock, flags); + + vcpu_kick(vcpu); + + return; +} + +/** + * vgic_inject_irq() - Inject an IRQ from a device to the vgic + * @d: The domain pointer + * @vcpu: The vCPU for private IRQs (PPIs, SGIs). Ignored for SPIs and LPIs. + * @intid: The INTID to inject a new state to. + * @level: Edge-triggered: true: to trigger the interrupt + * false: to ignore the call + * Level-sensitive true: raise the input signal + * false: lower the input signal + * + * Injects an instance of the given virtual IRQ into a domain. + * The VGIC is not concerned with devices being active-LOW or active-HIGH for + * level-sensitive interrupts. You can think of the level parameter as 1 + * being HIGH and 0 being LOW and all devices being active-HIGH. + */ +void vgic_inject_irq(struct domain *d, struct vcpu *vcpu, unsigned int intid, + bool level) +{ + struct vgic_irq *irq; + unsigned long flags; + + irq = vgic_get_irq(d, vcpu, intid); + if ( !irq ) + return; + + spin_lock_irqsave(&irq->irq_lock, flags); + + if ( !vgic_validate_injection(irq, level) ) + { + /* Nothing to see here, move along... */ + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(d, irq); + return; + } + + if ( irq->config == VGIC_CONFIG_LEVEL ) + irq->line_level = level; + else + irq->pending_latch = true; + + vgic_queue_irq_unlock(d, irq, flags); + vgic_put_irq(d, irq); + + return; +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index a3befd386b..f9e2eeb2d6 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -17,9 +17,19 @@ #ifndef __XEN_ARM_VGIC_VGIC_H__ #define __XEN_ARM_VGIC_VGIC_H__ +static inline bool irq_is_pending(struct vgic_irq *irq) +{ + if ( irq->config == VGIC_CONFIG_EDGE ) + return irq->pending_latch; + else + return irq->pending_latch || irq->line_level; +} + struct vgic_irq *vgic_get_irq(struct domain *d, struct vcpu *vcpu, u32 intid); void vgic_put_irq(struct domain *d, struct vgic_irq *irq); +void vgic_queue_irq_unlock(struct domain *d, struct vgic_irq *irq, + unsigned long flags); static inline void vgic_get_irq_kref(struct vgic_irq *irq) { From patchwork Wed Mar 21 16:32:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132230 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356290ljb; Wed, 21 Mar 2018 09:35:11 -0700 (PDT) X-Google-Smtp-Source: AIpwx489zO5UHmCrcWFnoKrIjxuWP+uv4izHXdIK7YfTvD9/kHnSd0p8+9uZpgGyGIr6Kvz6bZPs X-Received: by 2002:a24:8908:: with SMTP id s8-v6mr4925110itd.24.1521650111320; Wed, 21 Mar 2018 09:35:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650111; cv=none; d=google.com; s=arc-20160816; b=D1DldH1Him1yUxkMvMxN2uRHPkPxBUV430ptL+RVa96DVZnn0IGkWbK0kpcXjQSuw1 K3yIxPzWCZWzXCv2E91XVztjwlBQUxkNmeV9dFxG3+qCzqy1LwqpEmI5VK3lcdQ2JmSE th/+/RMrMow7H7JUUTKgwJya888lqIfESwf2gGyRnB+mimksjTuswDhJLHCIpmzN3fqx 8aR6j62FnuDnhqy4O3jbmOfMh/N5k6USsXcXIz6M8QlzDQEaAU7au1PIUiKYixlMLtWT Qh8Y+3KF81vCXyddSjoT2El0h0ZTAA87MrI1zp99caeztwwap0ynwNGxxRYRBNTCmY+f jqCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=87WEp0XViUHTWQS4BCe8uBtAdHbzYm4uYZXyb+2gMgI=; b=hXNMAgYh+bCxCWMjAXSkl1sXEj2eDKz36ajhOYyypr1MD17GW9EPwdAvSdnd04XEf/ 1iOyfrK/XZYAukZKDAjEnW0oETQ25KYXAb7yPXTC3d45rlC+Req9SsPwStfBSTagquwN Io9KOOgahbU7x+IeLdkvdFJdKVAIo4YEF3xqHJmvXshuoKyIbkS300BvmR0Vd6WMOz+e 4BEgdFc75TtLhDjGud9yC2pCPOH5LL6emkQI08TmIBUER2C2LKUppfP+IJETY9STLWDh kpA1qAqdkRPwpHoRTJjlC2Ixffk9DcWhd59wPxCwugrIAAYHo0Esb4xA0xudalcX4Ahj r9zg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=IsQxe4tp; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.32.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:32:59 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:07 +0000 Message-Id: <20180321163235.12529-12-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 11/39] Add list_sort() routine from Linux X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Wei Liu , George Dunlap , Andrew Cooper , Ian Jackson , Andre Przywara , Tim Deegan , Jan Beulich , xen-devel@lists.xenproject.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" This pulls in Linux' list_sort.c, which is a merge sort implementation for linked lists. Apart from adding a full featured license header and adjusting the #include file, nothing has been changed in this code. Define a promptless Kconfig which configurations can select when they need this code and add it to the Makefile. This is from Linux' lib/list_sort.c, as of commit e327fd7c8667 ("lib: add module support to linked list sorting tests"). Signed-off-by: Andre Przywara Acked-by: Julien Grall --- Changelog v2 ... v3: - introduce promptless Kconfig - add Makefile line - note Linux commit ID xen/common/Kconfig | 3 + xen/common/Makefile | 1 + xen/common/list_sort.c | 157 ++++++++++++++++++++++++++++++++++++++++++++ xen/include/xen/list_sort.h | 11 ++++ 4 files changed, 172 insertions(+) create mode 100644 xen/common/list_sort.c create mode 100644 xen/include/xen/list_sort.h diff --git a/xen/common/Kconfig b/xen/common/Kconfig index 68abf7a5e5..986f6c4149 100644 --- a/xen/common/Kconfig +++ b/xen/common/Kconfig @@ -44,6 +44,9 @@ config HAS_GDBSX config HAS_IOPORTS bool +config NEEDS_LIST_SORT + bool + config HAS_BUILD_ID string option env="XEN_HAS_BUILD_ID" diff --git a/xen/common/Makefile b/xen/common/Makefile index 3a349f478b..24d4752ccc 100644 --- a/xen/common/Makefile +++ b/xen/common/Makefile @@ -19,6 +19,7 @@ obj-y += keyhandler.o obj-$(CONFIG_KEXEC) += kexec.o obj-$(CONFIG_KEXEC) += kimage.o obj-y += lib.o +obj-$(CONFIG_NEEDS_LIST_SORT) += list_sort.o obj-$(CONFIG_LIVEPATCH) += livepatch.o livepatch_elf.o obj-y += lzo.o obj-$(CONFIG_HAS_MEM_ACCESS) += mem_access.o diff --git a/xen/common/list_sort.c b/xen/common/list_sort.c new file mode 100644 index 0000000000..af2b2f6519 --- /dev/null +++ b/xen/common/list_sort.c @@ -0,0 +1,157 @@ +/* + * list_sort.c: merge sort implementation for linked lists + * Copied from the Linux kernel (lib/list_sort.c) + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; If not, see . + */ + +#include +#include + +#define MAX_LIST_LENGTH_BITS 20 + +/* + * Returns a list organized in an intermediate format suited + * to chaining of merge() calls: null-terminated, no reserved or + * sentinel head node, "prev" links not maintained. + */ +static struct list_head *merge(void *priv, + int (*cmp)(void *priv, struct list_head *a, + struct list_head *b), + struct list_head *a, struct list_head *b) +{ + struct list_head head, *tail = &head; + + while (a && b) { + /* if equal, take 'a' -- important for sort stability */ + if ((*cmp)(priv, a, b) <= 0) { + tail->next = a; + a = a->next; + } else { + tail->next = b; + b = b->next; + } + tail = tail->next; + } + tail->next = a?:b; + return head.next; +} + +/* + * Combine final list merge with restoration of standard doubly-linked + * list structure. This approach duplicates code from merge(), but + * runs faster than the tidier alternatives of either a separate final + * prev-link restoration pass, or maintaining the prev links + * throughout. + */ +static void merge_and_restore_back_links(void *priv, + int (*cmp)(void *priv, struct list_head *a, + struct list_head *b), + struct list_head *head, + struct list_head *a, struct list_head *b) +{ + struct list_head *tail = head; + u8 count = 0; + + while (a && b) { + /* if equal, take 'a' -- important for sort stability */ + if ((*cmp)(priv, a, b) <= 0) { + tail->next = a; + a->prev = tail; + a = a->next; + } else { + tail->next = b; + b->prev = tail; + b = b->next; + } + tail = tail->next; + } + tail->next = a ? : b; + + do { + /* + * In worst cases this loop may run many iterations. + * Continue callbacks to the client even though no + * element comparison is needed, so the client's cmp() + * routine can invoke cond_resched() periodically. + */ + if (unlikely(!(++count))) + (*cmp)(priv, tail->next, tail->next); + + tail->next->prev = tail; + tail = tail->next; + } while (tail->next); + + tail->next = head; + head->prev = tail; +} + +/** + * list_sort - sort a list + * @priv: private data, opaque to list_sort(), passed to @cmp + * @head: the list to sort + * @cmp: the elements comparison function + * + * This function implements "merge sort", which has O(nlog(n)) + * complexity. + * + * The comparison function @cmp must return a negative value if @a + * should sort before @b, and a positive value if @a should sort after + * @b. If @a and @b are equivalent, and their original relative + * ordering is to be preserved, @cmp must return 0. + */ +void list_sort(void *priv, struct list_head *head, + int (*cmp)(void *priv, struct list_head *a, + struct list_head *b)) +{ + struct list_head *part[MAX_LIST_LENGTH_BITS+1]; /* sorted partial lists + -- last slot is a sentinel */ + int lev; /* index into part[] */ + int max_lev = 0; + struct list_head *list; + + if (list_empty(head)) + return; + + memset(part, 0, sizeof(part)); + + head->prev->next = NULL; + list = head->next; + + while (list) { + struct list_head *cur = list; + list = list->next; + cur->next = NULL; + + for (lev = 0; part[lev]; lev++) { + cur = merge(priv, cmp, part[lev], cur); + part[lev] = NULL; + } + if (lev > max_lev) { + if (unlikely(lev >= ARRAY_SIZE(part)-1)) { + dprintk(XENLOG_DEBUG, + "list too long for efficiency\n"); + lev--; + } + max_lev = lev; + } + part[lev] = cur; + } + + for (lev = 0; lev < max_lev; lev++) + if (part[lev]) + list = merge(priv, cmp, part[lev], list); + + merge_and_restore_back_links(priv, cmp, head, part[max_lev], list); +} +EXPORT_SYMBOL(list_sort); diff --git a/xen/include/xen/list_sort.h b/xen/include/xen/list_sort.h new file mode 100644 index 0000000000..13ce0a55ec --- /dev/null +++ b/xen/include/xen/list_sort.h @@ -0,0 +1,11 @@ +#ifndef _LINUX_LIST_SORT_H +#define _LINUX_LIST_SORT_H + +#include + +struct list_head; + +void list_sort(void *priv, struct list_head *head, + int (*cmp)(void *priv, struct list_head *a, + struct list_head *b)); +#endif From patchwork Wed Mar 21 16:32:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132241 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356708ljb; Wed, 21 Mar 2018 09:35:35 -0700 (PDT) X-Google-Smtp-Source: AG47ELvQZhCbZLmd8it8yLoiSp5wHCDX/gBRt3dqKT9pdibVPQJVAjxbeW/NRemRJjjqtwLTRI5D X-Received: by 10.107.164.199 with SMTP id d68mr21769211ioj.34.1521650135539; Wed, 21 Mar 2018 09:35:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650135; cv=none; d=google.com; s=arc-20160816; b=WR9EoEonuveNAVFB0Ehf8SapYkz2aIQuuKe5zU7uIRgNywmIxrGoX+mDBsAE0V7ra7 WhoYeTdsPPc9D/0mfSbigy7WSvL3WGqE9ZHe1X/EEXz75h1coiqxMtusUjaCrjyAmfbd DBusXkRdrQP1416aVTTnWGKu7waWzHbkj5IV9aJE5HK86SWqkV2KNJpFvRY7mKlCYdp8 NLr8DwSx4qJXjH5W5NVgtKzzR/uqjLn5vLwC0W0bsnK/dDkVJHKxgHVyuKEwcW9DNBgO bBtNHTkGaztVC7JHdbujqWbDG1xLZJfgNCLmIj6EhYDN6n90ZMDnQ1Yxw+yKyBvfiPmO l0Pg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=hoLXJgob8O97M4ORhHMoVQ04SvCT0I49xgG6ocN28Ic=; b=EveBrbNJ5IPD94Zub4rPCKBuhueFMNlKn1WglstSwF+ckoCJyTrzvi86I8A/l5O1q6 sa+ANQ3ZT0gIHHtLSFX8is1eZ/LC4/abBN/1+wQYB+LFM0dPSE1nPeFPEC/FlNOm8NYZ wIkEYzkFhaOx5LubxuD77M0Q74MIFzuuR9oZIODOosfViETlBSvHA8I2lbNANbh4HK/J LLLHwwCKSCAgVIimszxpV2u1cpqTlkytHA+/CLWR7Zwhq9YBNgCaLQMKqIM7ydeWmRsF kT3+GBqbw33qfkuEmRUijyy1GgGqq3WAcSMazNUwRsNSnp5eU8Myid73Itefoe26oh52 +mKQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Di9FiPp/; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:00 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:08 +0000 Message-Id: <20180321163235.12529-13-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 12/39] ARM: new VGIC: Add IRQ sorting X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Adds the sorting function to cover the case where you have more IRQs to consider than you have LRs. We consider their priorities. This uses the new sort_list() implementation imported from Linux. This is based on Linux commit 8e4447457965, written by Christoffer Dall. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall Acked-by: Stefano Stabellini --- xen/arch/arm/vgic/vgic.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index f7dfd01c1d..ee0de8d2e0 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -15,6 +15,7 @@ * along with this program. If not, see . */ +#include #include #include #include @@ -193,6 +194,64 @@ static struct vcpu *vgic_target_oracle(struct vgic_irq *irq) return NULL; } +/* + * The order of items in the ap_lists defines how we'll pack things in LRs as + * well, the first items in the list being the first things populated in the + * LRs. + * + * A hard rule is that active interrupts can never be pushed out of the LRs + * (and therefore take priority) since we cannot reliably trap on deactivation + * of IRQs and therefore they have to be present in the LRs. + * + * Otherwise things should be sorted by the priority field and the GIC + * hardware support will take care of preemption of priority groups etc. + * + * Return negative if "a" sorts before "b", 0 to preserve order, and positive + * to sort "b" before "a". + */ +static int vgic_irq_cmp(void *priv, struct list_head *a, struct list_head *b) +{ + struct vgic_irq *irqa = container_of(a, struct vgic_irq, ap_list); + struct vgic_irq *irqb = container_of(b, struct vgic_irq, ap_list); + bool penda, pendb; + int ret; + + spin_lock(&irqa->irq_lock); + spin_lock(&irqb->irq_lock); + + if ( irqa->active || irqb->active ) + { + ret = (int)irqb->active - (int)irqa->active; + goto out; + } + + penda = irqa->enabled && irq_is_pending(irqa); + pendb = irqb->enabled && irq_is_pending(irqb); + + if ( !penda || !pendb ) + { + ret = (int)pendb - (int)penda; + goto out; + } + + /* Both pending and enabled, sort by priority */ + ret = irqa->priority - irqb->priority; +out: + spin_unlock(&irqb->irq_lock); + spin_unlock(&irqa->irq_lock); + return ret; +} + +/* Must be called with the ap_list_lock held */ +static void vgic_sort_ap_list(struct vcpu *vcpu) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic; + + ASSERT(spin_is_locked(&vgic_cpu->ap_list_lock)); + + list_sort(NULL, &vgic_cpu->ap_list_head, vgic_irq_cmp); +} + /* * Only valid injection if changing level for level-triggered IRQs or for a * rising edge. From patchwork Wed Mar 21 16:32:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132234 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356349ljb; Wed, 21 Mar 2018 09:35:13 -0700 (PDT) X-Google-Smtp-Source: AG47ELvDToo9W93Bt3Cna6vQk8aGRE84MyPXJAIdLhRMWjmuGTgKAJnoh1BXakhv848VzWaX2YP4 X-Received: by 10.107.55.133 with SMTP id e127mr20505697ioa.138.1521650113787; Wed, 21 Mar 2018 09:35:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650113; cv=none; d=google.com; s=arc-20160816; b=sFjua2CvqK1xoG9CDTV7Xgho3YWg7anyMvcmHUI/wqgO6xqSSCBIL+oqSr6yGQWdqy 4BbS3wlGB5pSbqfPUwBLVhk674t6bVnUOr43C2EQAp01ZfDat7Msux4Ysd8zJCUBTCs+ y+XibWJCEGcoLhdVpn3jI7oz/zhqZUtCMtlGebVr+NVizPoMLLMYubcbjAe8bkKUTH7H AQTYR/OlI4WeXVtfD4YJFfal5wEtbKFel3ZZlrWFH99Bp0asEo35orE69uKLMI7to5dX tSKnFw1cYSJyP7duE0AdDms0kbkeRjHyU73ZFy8EzRvbH2y9eTzz5Xr1tg/BeGmNv5vw k4Qg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=v2abx+GpMxRy3B8kBaYIUzH+XOmp5dJR5hUjpXf17ms=; b=lCIdtgW45t08pwR+6Xgl1vmvZzP/JVxtwOX/mlKEgNdWluSYK2MXb6nk9uRKnSHFbW mqKCeh6WUrFOj4nbRe/x9N2pOgH9BYMPUGp/P9dpymhgWC5DazEXwNSDz3LcRtkSnrrQ CepfYG1KNov6mvwL9Q6CUrzqc1v00GNmpoRP6e8QNVK6LDh6CYRCYqgSi/ZVzqHxBH90 EgYVs0G1WO+ctgsxEpJCYpaFSwM+iH77bUn/Rit0F1zNr5O9B+H1N5mUX5vSNGq+LYma 20gCYkdP3CIOvOyeFcZg0qOiPHr20/oYVXeoSb1KN/5YHPJfSmzyDVYLxwU5T/N8+9l2 CzKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=LKo/Aydk; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:01 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:09 +0000 Message-Id: <20180321163235.12529-14-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 13/39] ARM: new VGIC: Add IRQ sync/flush framework X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Implement the framework for syncing IRQs between our emulation and the list registers, which represent the guest's view of IRQs. This is done in vgic_sync_from_lrs() and vgic_sync_to_lrs(), which get called on guest entry and exit, respectively. The code talking to the actual GICv2/v3 hardware is added in the following patches. This is based on Linux commit 0919e84c0fc1, written by Marc Zyngier. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall Acked-by: Stefano Stabellini --- Changelog v2 ... v3: - replace "true" instead of "1" for the boolean parameter Changelog v1 ... v2: - make functions void - do underflow setting directly (no v2/v3 indirection) - fix multiple SGIs injections (as the late Linux bugfix) xen/arch/arm/vgic/vgic.c | 232 +++++++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic.h | 2 + 2 files changed, 234 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index ee0de8d2e0..52e1669888 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -409,6 +409,238 @@ void vgic_inject_irq(struct domain *d, struct vcpu *vcpu, unsigned int intid, return; } +/** + * vgic_prune_ap_list() - Remove non-relevant interrupts from the ap_list + * + * @vcpu: The VCPU of which the ap_list should be pruned. + * + * Go over the list of interrupts on a VCPU's ap_list, and prune those that + * we won't have to consider in the near future. + * This removes interrupts that have been successfully handled by the guest, + * or that have otherwise became obsolete (not pending anymore). + * Also this moves interrupts between VCPUs, if their affinity has changed. + */ +static void vgic_prune_ap_list(struct vcpu *vcpu) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic; + struct vgic_irq *irq, *tmp; + unsigned long flags; + +retry: + spin_lock_irqsave(&vgic_cpu->ap_list_lock, flags); + + list_for_each_entry_safe( irq, tmp, &vgic_cpu->ap_list_head, ap_list ) + { + struct vcpu *target_vcpu, *vcpuA, *vcpuB; + + spin_lock(&irq->irq_lock); + + BUG_ON(vcpu != irq->vcpu); + + target_vcpu = vgic_target_oracle(irq); + + if ( !target_vcpu ) + { + /* + * We don't need to process this interrupt any + * further, move it off the list. + */ + list_del(&irq->ap_list); + irq->vcpu = NULL; + spin_unlock(&irq->irq_lock); + + /* + * This vgic_put_irq call matches the + * vgic_get_irq_kref in vgic_queue_irq_unlock, + * where we added the LPI to the ap_list. As + * we remove the irq from the list, we drop + * also drop the refcount. + */ + vgic_put_irq(vcpu->domain, irq); + continue; + } + + if ( target_vcpu == vcpu ) + { + /* We're on the right CPU */ + spin_unlock(&irq->irq_lock); + continue; + } + + /* This interrupt looks like it has to be migrated. */ + + spin_unlock(&irq->irq_lock); + spin_unlock_irqrestore(&vgic_cpu->ap_list_lock, flags); + + /* + * Ensure locking order by always locking the smallest + * ID first. + */ + if ( vcpu->vcpu_id < target_vcpu->vcpu_id ) + { + vcpuA = vcpu; + vcpuB = target_vcpu; + } + else + { + vcpuA = target_vcpu; + vcpuB = vcpu; + } + + spin_lock_irqsave(&vcpuA->arch.vgic.ap_list_lock, flags); + spin_lock(&vcpuB->arch.vgic.ap_list_lock); + spin_lock(&irq->irq_lock); + + /* + * If the affinity has been preserved, move the + * interrupt around. Otherwise, it means things have + * changed while the interrupt was unlocked, and we + * need to replay this. + * + * In all cases, we cannot trust the list not to have + * changed, so we restart from the beginning. + */ + if ( target_vcpu == vgic_target_oracle(irq) ) + { + struct vgic_cpu *new_cpu = &target_vcpu->arch.vgic; + + list_del(&irq->ap_list); + irq->vcpu = target_vcpu; + list_add_tail(&irq->ap_list, &new_cpu->ap_list_head); + } + + spin_unlock(&irq->irq_lock); + spin_unlock(&vcpuB->arch.vgic.ap_list_lock); + spin_unlock_irqrestore(&vcpuA->arch.vgic.ap_list_lock, flags); + goto retry; + } + + spin_unlock_irqrestore(&vgic_cpu->ap_list_lock, flags); +} + +static void vgic_fold_lr_state(struct vcpu *vcpu) +{ +} + +/* Requires the irq_lock to be held. */ +static void vgic_populate_lr(struct vcpu *vcpu, + struct vgic_irq *irq, int lr) +{ + ASSERT(spin_is_locked(&irq->irq_lock)); +} + +static void vgic_set_underflow(struct vcpu *vcpu) +{ + ASSERT(vcpu == current); + + gic_hw_ops->update_hcr_status(GICH_HCR_UIE, true); +} + +/* Requires the ap_list_lock to be held. */ +static int compute_ap_list_depth(struct vcpu *vcpu) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic; + struct vgic_irq *irq; + int count = 0; + + ASSERT(spin_is_locked(&vgic_cpu->ap_list_lock)); + + list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) + { + spin_lock(&irq->irq_lock); + /* GICv2 SGIs can count for more than one... */ + if ( vgic_irq_is_sgi(irq->intid) && irq->source ) + count += hweight8(irq->source); + else + count++; + spin_unlock(&irq->irq_lock); + } + return count; +} + +/* Requires the VCPU's ap_list_lock to be held. */ +static void vgic_flush_lr_state(struct vcpu *vcpu) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic; + struct vgic_irq *irq; + int count = 0; + + ASSERT(spin_is_locked(&vgic_cpu->ap_list_lock)); + + if ( compute_ap_list_depth(vcpu) > gic_get_nr_lrs() ) + vgic_sort_ap_list(vcpu); + + list_for_each_entry( irq, &vgic_cpu->ap_list_head, ap_list ) + { + spin_lock(&irq->irq_lock); + + if ( likely(vgic_target_oracle(irq) == vcpu) ) + vgic_populate_lr(vcpu, irq, count++); + + spin_unlock(&irq->irq_lock); + + if ( count == gic_get_nr_lrs() ) + { + if ( !list_is_last(&irq->ap_list, &vgic_cpu->ap_list_head) ) + vgic_set_underflow(vcpu); + break; + } + } + + vcpu->arch.vgic.used_lrs = count; +} + +/** + * vgic_sync_from_lrs() - Update VGIC state from hardware after a guest's run. + * @vcpu: the VCPU for which to transfer from the LRs to the IRQ list. + * + * Sync back the hardware VGIC state after the guest has run, into our + * VGIC emulation structures, It reads the LRs and updates the respective + * struct vgic_irq, taking level/edge into account. + * This is the high level function which takes care of the conditions, + * also bails out early if there were no interrupts queued. + * Was: kvm_vgic_sync_hwstate() + */ +void vgic_sync_from_lrs(struct vcpu *vcpu) +{ + /* An empty ap_list_head implies used_lrs == 0 */ + if ( list_empty(&vcpu->arch.vgic.ap_list_head) ) + return; + + vgic_fold_lr_state(vcpu); + + vgic_prune_ap_list(vcpu); +} + +/** + * vgic_sync_to_lrs() - flush emulation state into the hardware on guest entry + * + * Before we enter a guest, we have to translate the virtual GIC state of a + * VCPU into the GIC virtualization hardware registers, namely the LRs. + * This is the high level function which takes care about the conditions + * and the locking, also bails out early if there are no interrupts queued. + * Was: kvm_vgic_flush_hwstate() + */ +void vgic_sync_to_lrs(void) +{ + /* + * If there are no virtual interrupts active or pending for this + * VCPU, then there is no work to do and we can bail out without + * taking any lock. There is a potential race with someone injecting + * interrupts to the VCPU, but it is a benign race as the VCPU will + * either observe the new interrupt before or after doing this check, + * and introducing additional synchronization mechanism doesn't change + * this. + */ + if ( list_empty(¤t->arch.vgic.ap_list_head) ) + return; + + ASSERT(!local_irq_is_enabled()); + + spin_lock(¤t->arch.vgic.ap_list_lock); + vgic_flush_lr_state(current); + spin_unlock(¤t->arch.vgic.ap_list_lock); +} /* * Local variables: * mode: C diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index f9e2eeb2d6..f530cfa078 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -17,6 +17,8 @@ #ifndef __XEN_ARM_VGIC_VGIC_H__ #define __XEN_ARM_VGIC_VGIC_H__ +#define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS) + static inline bool irq_is_pending(struct vgic_irq *irq) { if ( irq->config == VGIC_CONFIG_EDGE ) From patchwork Wed Mar 21 16:32:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132236 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356434ljb; Wed, 21 Mar 2018 09:35:18 -0700 (PDT) X-Google-Smtp-Source: AG47ELuvkh2RCv6Ep435+4nJNUgeTiMZVrDuHWdz548OgbA0Xk2D+kcEqCw2XKowKU6tIN3Y56Ea X-Received: by 10.107.78.22 with SMTP id c22mr21330211iob.79.1521650118621; Wed, 21 Mar 2018 09:35:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650118; cv=none; d=google.com; s=arc-20160816; b=JddekEd7MNHeaBb8/hioNJ78Sc0j2VIh81umFW9GSbO6WCiiexsVq3d9XtxBiUeMlW dvAfzBw6FdjB2NXN9Ul6tBr4RemlLSqp1/QIz7mPHEbEaH2R3wOpr+sS57TyRTWY5kr5 3NV5q34WyxWcwFLIl2V6gVPjEvgCKMYUcIpBdOR/utKl8R6TG6X3MjkifEQP7qa/YY1S U+Vf79mv6WFSZ57/FzVCPZ+eboFzKsFdckNRRbcp0dfBjtdrRzRsdcY1YKmFSYHSBkgW efblgWNiQ+EqwzesU3IZYHUilKid3xEcAeHvxTei9ZVQsoWAiJXbS3em2L3GqxuJO52s Uc0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=trH8ETrH1e3aD63QW82lqcGi5hWIUB+ew//Onht2ukk=; b=ZafIuDkAB3ZJfBx5VhrbHOG2jMXg+E78u3ee3Nd1E3MpnJSDmGB1McarMfOjcBuqQD mORpqm/KTnFHljajHX9FOtoSUkGIGvJ5nySmk/dlea4v2ezsjg2Dn5ZraZSHvb+EV5Ql JfEVcfzNWu2suvxiyqwhQ7uBuEbOD2z+iFtQYtsogsZjfHoOHRvGY1lfKdpmJJB0aRl7 WaOqsH73fX/8EC3HYqI1PlKQ0BjWcLQCrWiW310CZqmgR2/csv7nCaHFyQ8ArdoKd9DB ikUuBJdKhv1v9VwGE4ArrJjVYNS3zN+SyyHHHoRaELTfb357tyD/KnnIfhwDUR7znNBi 1bKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=AlYPMcWW; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:02 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:10 +0000 Message-Id: <20180321163235.12529-15-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 14/39] ARM: new VGIC: Add GICv2 world switch backend X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Processing maintenance interrupts and accessing the list registers are dependent on the host's GIC version. Introduce vgic-v2.c to contain GICv2 specific functions. Implement the GICv2 specific code for syncing the emulation state into the VGIC registers. This also adds the hook to let Xen setup the host GIC addresses. This is based on Linux commit 140b086dd197, written by Marc Zyngier. Signed-off-by: Andre Przywara Signed-off-by: Andre Przywara --- Changelog v2 ... v3: - remove no longer needed asm/io.h header - replace 0/1 with false/true for bool's - clear _IRQ_INPROGRESS bit when retiring hardware mapped IRQ - fix indentation and w/s issues Changelog v1 ... v2: - remove v2 specific underflow function (now generic) - re-add Linux code to properly handle acked level IRQs xen/arch/arm/vgic/vgic-v2.c | 239 ++++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic.c | 6 ++ xen/arch/arm/vgic/vgic.h | 9 ++ 3 files changed, 254 insertions(+) create mode 100644 xen/arch/arm/vgic/vgic-v2.c diff --git a/xen/arch/arm/vgic/vgic-v2.c b/xen/arch/arm/vgic/vgic-v2.c new file mode 100644 index 0000000000..8ab0cfe81d --- /dev/null +++ b/xen/arch/arm/vgic/vgic-v2.c @@ -0,0 +1,239 @@ +/* + * Copyright (C) 2015, 2016 ARM Ltd. + * Imported from Linux ("new" KVM VGIC) and heavily adapted to Xen. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include + +#include "vgic.h" + +static struct { + bool enabled; + paddr_t dbase; /* Distributor interface address */ + paddr_t cbase; /* CPU interface address & size */ + paddr_t csize; + paddr_t vbase; /* Virtual CPU interface address */ + + /* Offset to add to get an 8kB contiguous region if GIC is aliased */ + uint32_t aliased_offset; +} gic_v2_hw_data; + +void vgic_v2_setup_hw(paddr_t dbase, paddr_t cbase, paddr_t csize, + paddr_t vbase, uint32_t aliased_offset) +{ + gic_v2_hw_data.enabled = true; + gic_v2_hw_data.dbase = dbase; + gic_v2_hw_data.cbase = cbase; + gic_v2_hw_data.csize = csize; + gic_v2_hw_data.vbase = vbase; + gic_v2_hw_data.aliased_offset = aliased_offset; +} + +/* + * transfer the content of the LRs back into the corresponding ap_list: + * - active bit is transferred as is + * - pending bit is + * - transferred as is in case of edge sensitive IRQs + * - set to the line-level (resample time) for level sensitive IRQs + */ +void vgic_v2_fold_lr_state(struct vcpu *vcpu) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic; + unsigned int used_lrs = vcpu->arch.vgic.used_lrs; + unsigned long flags; + unsigned int lr; + + if ( !used_lrs ) /* No LRs used, so nothing to sync back here. */ + return; + + gic_hw_ops->update_hcr_status(GICH_HCR_UIE, false); + + for ( lr = 0; lr < used_lrs; lr++ ) + { + struct gic_lr lr_val; + uint32_t intid; + struct vgic_irq *irq; + + gic_hw_ops->read_lr(lr, &lr_val); + + /* + * TODO: Possible optimization to avoid reading LRs: + * Read the ELRSR to find out which of our LRs have been cleared + * by the guest. We just need to know the IRQ number for those, which + * we could save in an array when populating the LRs. + * This trades one MMIO access (ELRSR) for possibly more than one (LRs), + * but requires some more code to save the IRQ number and to handle + * those finished IRQs according to the algorithm below. + * We need some numbers to justify this: chances are that we don't + * have many LRs in use most of the time, so we might not save much. + */ + gic_hw_ops->clear_lr(lr); + + intid = lr_val.virq; + irq = vgic_get_irq(vcpu->domain, vcpu, intid); + + spin_lock_irqsave(&irq->irq_lock, flags); + + /* + * If a hardware mapped IRQ has been handled for good, we need to + * clear the _IRQ_INPROGRESS bit to allow handling of new IRQs. + */ + if ( irq->hw && !lr_val.active && !lr_val.pending ) + { + struct irq_desc *irqd = irq_to_desc(irq->hwintid); + + clear_bit(_IRQ_INPROGRESS, &irqd->status); + } + + /* Always preserve the active bit */ + irq->active = lr_val.active; + + /* Edge is the only case where we preserve the pending bit */ + if ( irq->config == VGIC_CONFIG_EDGE && lr_val.pending ) + { + irq->pending_latch = true; + + if ( vgic_irq_is_sgi(intid) ) + irq->source |= (1U << lr_val.virt.source); + } + + /* Clear soft pending state when level irqs have been acked. */ + if ( irq->config == VGIC_CONFIG_LEVEL && !lr_val.pending ) + irq->pending_latch = false; + + /* + * Level-triggered mapped IRQs are special because we only + * observe rising edges as input to the VGIC. + * + * If the guest never acked the interrupt we have to sample + * the physical line and set the line level, because the + * device state could have changed or we simply need to + * process the still pending interrupt later. + * + * If this causes us to lower the level, we have to also clear + * the physical active state, since we will otherwise never be + * told when the interrupt becomes asserted again. + */ + if ( vgic_irq_is_mapped_level(irq) && lr_val.pending ) + { + struct irq_desc *irqd; + + ASSERT(irq->hwintid >= VGIC_NR_PRIVATE_IRQS); + + irqd = irq_to_desc(irq->hwintid); + irq->line_level = gic_read_pending_state(irqd); + + if ( !irq->line_level ) + gic_set_active_state(irqd, false); + } + + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(vcpu->domain, irq); + } + + gic_hw_ops->update_hcr_status(GICH_HCR_EN, false); + vgic_cpu->used_lrs = 0; +} + +/** + * vgic_v2_populate_lr() - Populates an LR with the state of a given IRQ. + * @vcpu: The VCPU which the given @irq belongs to. + * @irq: The IRQ to convert into an LR. The irq_lock must be held already. + * @lr: The LR number to transfer the state into. + * + * This moves a virtual IRQ, represented by its vgic_irq, into a list register. + * Apart from translating the logical state into the LR bitfields, it also + * changes some state in the vgic_irq. + * For an edge sensitive IRQ the pending state is cleared in struct vgic_irq, + * for a level sensitive IRQ the pending state value is unchanged, as it is + * dictated directly by the input line level. + * + * If @irq describes an SGI with multiple sources, we choose the + * lowest-numbered source VCPU and clear that bit in the source bitmap. + * + * The irq_lock must be held by the caller. + */ +void vgic_v2_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr) +{ + struct gic_lr lr_val = {0}; + + lr_val.virq = irq->intid; + + if ( irq_is_pending(irq) ) + { + lr_val.pending = true; + + if ( irq->config == VGIC_CONFIG_EDGE ) + irq->pending_latch = false; + + if ( vgic_irq_is_sgi(irq->intid) ) + { + u32 src = ffs(irq->source); + + BUG_ON(!src); + lr_val.virt.source = (src - 1); + irq->source &= ~(1 << (src - 1)); + if ( irq->source ) + irq->pending_latch = true; + } + } + + lr_val.active = irq->active; + + if ( irq->hw ) + { + lr_val.hw_status = true; + lr_val.hw.pirq = irq->hwintid; + /* + * Never set pending+active on a HW interrupt, as the + * pending state is kept at the physical distributor + * level. + */ + if ( irq->active && irq_is_pending(irq) ) + lr_val.pending = false; + } + else + { + if ( irq->config == VGIC_CONFIG_LEVEL ) + lr_val.virt.eoi = true; + } + + /* + * Level-triggered mapped IRQs are special because we only observe + * rising edges as input to the VGIC. We therefore lower the line + * level here, so that we can take new virtual IRQs. See + * vgic_v2_fold_lr_state for more info. + */ + if ( vgic_irq_is_mapped_level(irq) && lr_val.pending ) + irq->line_level = false; + + /* The GICv2 LR only holds five bits of priority. */ + lr_val.priority = irq->priority >> 3; + + gic_hw_ops->write_lr(lr, &lr_val); +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 52e1669888..2fa595f4f7 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -520,6 +520,7 @@ retry: static void vgic_fold_lr_state(struct vcpu *vcpu) { + vgic_v2_fold_lr_state(vcpu); } /* Requires the irq_lock to be held. */ @@ -527,6 +528,8 @@ static void vgic_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr) { ASSERT(spin_is_locked(&irq->irq_lock)); + + vgic_v2_populate_lr(vcpu, irq, lr); } static void vgic_set_underflow(struct vcpu *vcpu) @@ -640,7 +643,10 @@ void vgic_sync_to_lrs(void) spin_lock(¤t->arch.vgic.ap_list_lock); vgic_flush_lr_state(current); spin_unlock(¤t->arch.vgic.ap_list_lock); + + gic_hw_ops->update_hcr_status(GICH_HCR_EN, 1); } + /* * Local variables: * mode: C diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index f530cfa078..41cc0c5b54 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -27,6 +27,11 @@ static inline bool irq_is_pending(struct vgic_irq *irq) return irq->pending_latch || irq->line_level; } +static inline bool vgic_irq_is_mapped_level(struct vgic_irq *irq) +{ + return irq->config == VGIC_CONFIG_LEVEL && irq->hw; +} + struct vgic_irq *vgic_get_irq(struct domain *d, struct vcpu *vcpu, u32 intid); void vgic_put_irq(struct domain *d, struct vgic_irq *irq); @@ -41,6 +46,10 @@ static inline void vgic_get_irq_kref(struct vgic_irq *irq) atomic_inc(&irq->refcount); } +void vgic_v2_fold_lr_state(struct vcpu *vcpu); +void vgic_v2_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr); +void vgic_v2_set_underflow(struct vcpu *vcpu); + #endif /* From patchwork Wed Mar 21 16:32:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132205 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2355763ljb; Wed, 21 Mar 2018 09:34:43 -0700 (PDT) X-Google-Smtp-Source: AG47ELsIZKM3vP4T3knARNNEQHssU1M7olpR4D1clPMOTTp0ERnVL2/6LPA9GUjgFkFdi5rECSF3 X-Received: by 10.107.43.7 with SMTP id r7mr20976131ior.302.1521650082900; Wed, 21 Mar 2018 09:34:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650082; cv=none; d=google.com; s=arc-20160816; b=yY5E+qB8mMXtdHNjooH0/WfAIbUIiRZI4WWCGcMyXUxXd0YTe9dRHfE+1E3SWOPwPj O2pya9C56vXFIpRNGKn/7rzUA2hHzZYA0X5YB9gp9rB4r6Qip6crhAtQoerGjZe7ltd4 cuwClw1roGFTChNPw42t/SnGnUUJNUPCN9jA94yixcRJCTM0YygRY9VXNoHT+2lsU38F HaujKzgdaQ92rqNgIp2W9LwlBtVJS4cNaYTen+3pdc4d6K4vLcqAVZtTPXHFLeCRhk8A 8xN1F96eoD7jMWaupoSJF8559As7yoKPg4K2UjFKwrvIl6EOg+iqCpPppfC+J9ChgvYR iUxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=+hIUNOWsBgDSsxwZblG4ZG/tzFohb77DwAAA48xboeI=; b=phmEw+rZPbw4nTsrn7tn6EWKJdCTBchhCZqRr4Uwxrdoxkyj4z2bwLDpNXq+m9kwIa I4kIQ9YGI/SVtZ5ofQTykom7TQE4ilTCcDEuC3UWxJcDK06rNWSTcVoXy3l+l9erLX7I VPkTP3UroMA12Q8Ggr3IteVVNniP/qw29UPS8O2gtp2cFOIi+DGTxRnUzmkHOAgnbT29 4NvacTjJ0doPsFp2LoQ2oZHK7QgwrbIGQ1LElhiThAm9230W3SPwsdYyAYgcVPXAnFF7 4rjwXpxAZkrdcFm4lqy+xt4NaV3h8RqKiVCaLLY60wy7y8BKfv2bIIZsL4CRrbyNwxWE 3UUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=GqjxOL+C; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:03 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:11 +0000 Message-Id: <20180321163235.12529-16-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 15/39] ARM: new VGIC: Implement vgic_vcpu_pending_irq X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Tell Xen whether a particular VCPU has an IRQ that needs handling in the guest. This is used to decide whether a VCPU is runnable or if a hypercall should be preempted to let the guest handle the IRQ. This is based on Linux commit 90eee56c5f90, written by Eric Auger. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall Acked-by: Stefano Stabellini --- Changelog v2 ... v3: - adjust vgic_vcpu_pending_irq() to return integers, not false/true Changelog v1 ... v2: - adjust to new vgic_vcpu_pending_irq() prototype, drop wrapper xen/arch/arm/vgic/vgic.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 2fa595f4f7..925cda4580 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -647,6 +647,43 @@ void vgic_sync_to_lrs(void) gic_hw_ops->update_hcr_status(GICH_HCR_EN, 1); } +/** + * vgic_vcpu_pending_irq() - determine if interrupts need to be injected + * @vcpu: The vCPU on which to check for interrupts. + * + * Checks whether there is an interrupt on the given VCPU which needs + * handling in the guest. This requires at least one IRQ to be pending + * and enabled. + * + * Returns: 1 if the guest should run to handle interrupts, 0 otherwise. + */ +int vgic_vcpu_pending_irq(struct vcpu *vcpu) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic; + struct vgic_irq *irq; + unsigned long flags; + int ret = 0; + + if ( !vcpu->domain->arch.vgic.enabled ) + return 0; + + spin_lock_irqsave(&vgic_cpu->ap_list_lock, flags); + + list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) + { + spin_lock(&irq->irq_lock); + ret = irq_is_pending(irq) && irq->enabled; + spin_unlock(&irq->irq_lock); + + if ( ret ) + break; + } + + spin_unlock_irqrestore(&vgic_cpu->ap_list_lock, flags); + + return ret; +} + /* * Local variables: * mode: C From patchwork Wed Mar 21 16:32:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132222 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356144ljb; Wed, 21 Mar 2018 09:35:04 -0700 (PDT) X-Google-Smtp-Source: AG47ELvLVTKTMeh5MVYxC4t+Tgj93+e2IyHr3rg927iBwjtKa0wIdtNtdaJge8SUIFUW1Ro7yj+T X-Received: by 10.107.159.76 with SMTP id i73mr22861437ioe.0.1521650104455; Wed, 21 Mar 2018 09:35:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650104; cv=none; d=google.com; s=arc-20160816; b=qHVTRus69Jc9Csr7vhbRqB9CxasmNZQY+tZfb+lZVPUgvXfk5ZmfaOxzzgYsuQNoPw C3vBASB5FIr0MBlGBkf8wMJgshPHZFXLVfXM3liCr+5gVrtQ+3HaeCvbzxDqgO+ZbGT7 5SJ9RAhOo4kilTjmBK3nQLnSGE+6Ks5wJm1P5pjp/lBKmTpOhYCDLGmNHcVfDQh1yzc6 HoX9AwASX126gKeqv84ytKZA230Is/IDZe97UAC6Kk12nezI8470i28Jc1cMwgY1THAW aSd3OzdfamOWx62GoDDPf0s5gM2Q2sDf59cxo2ax7Rw1L85vWfj5IqKwTgyjXcyK0aIk lDuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=9bGb8lTV7QJp8T5vWNeH9ho7x7hZs28j8p6cz+c7hpg=; b=z7DaViKxe0YLEoF3NHZ6dPHr6RfnlYJTPyKPs9hgIhg4/e+xhXtm3u68RbhgfSeHu3 2EomuU4SwEOKTiDVRq9QJpi6zyodBgPZplPVEBjL74CUT1ucEbGOowP6leIn29U1aLW5 yFI3Msm7466NAquzwSdv6l4iuDlTT8F+BJJgKlJEgF1shUTmZKys6O6VHeMwT8siOaj0 aPwHTtUZyC7Nw56/YA5AjIFcEeNaTI9xRQFIMq9T0qHkKteIB0EdG0D1K3GOX1eBSjWo /kgsitgeOCN16lliYC8nvqZIgtjvyQ5c1szg7P8RNGYgvWYmFIvV5/abd5BNOvCb9S+/ oEYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Mbgx6hu7; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id c80-v6si3555836itd.55.2018.03.21.09.35.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 21 Mar 2018 09:35:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Mbgx6hu7; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1eygfl-0002MF-Ra; Wed, 21 Mar 2018 16:33:09 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1eygfk-0002Ih-A2 for xen-devel@lists.xenproject.org; Wed, 21 Mar 2018 16:33:08 +0000 X-Inumbo-ID: 7fd92fc9-2d25-11e8-9728-bc764e045a96 Received: from mail-wr0-x243.google.com (unknown [2a00:1450:400c:c0c::243]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 7fd92fc9-2d25-11e8-9728-bc764e045a96; Wed, 21 Mar 2018 17:32:52 +0100 (CET) Received: by mail-wr0-x243.google.com with SMTP id d10so5834773wrf.3 for ; Wed, 21 Mar 2018 09:33:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4bBsU7hxWtOWxbq/M51jQfYX/obQ4QUxXVUUerzQEE0=; b=Mbgx6hu7EZj2cWapcq1tikpDInnwJPhoUG7UHXffCCdvHIw/U4B1QsBK5Tl9aLu/s4 Y/9sNd+ULQdzGdQFt1WFFObYYe7lNkiPOTENr8LJuKwa4QeVdv+0BUsC0mK5v1/kxm5+ a6jFDewkh6gxecVCLUo50UQMvz1r45K5HD7dc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4bBsU7hxWtOWxbq/M51jQfYX/obQ4QUxXVUUerzQEE0=; b=XH89ZJa25PnvYY87y20nTsXeElsIb6qMJOJsbLNJ9UAmVoCxLQgLR0cZOuKKFOQicx lVB8o3n1wHUbDlupWSvxszXqvz+D+z01ZFWpQUmBQvOmgRQ0OXMgs9Zagyp9vnrTvsSA WCw//BOCYMGsqUsgBnp6G8pfDJE5TK6+kTafGdzwP2nYuHaFBaq2Ch4On0esfUhUQKfS GNTVVo+NzdEjVAAuAzZyP0FK4H0oaBvRJeMHBhOcJ9gy98dbwpzTh8X9YC4BZ2K8UxPi lGcs2Wkp7xM3PUAanAerWaJ2OshATv/ALdjBE8MUlAgaLWe6vU3uipdsnNi56/kI4Du5 Njgg== X-Gm-Message-State: AElRT7FYLmAeSKQnVAv/zOW9sOe42F7B6RfEbO2dXP2soY7HU8FDFujL E/WqCH+2l40RCU/Hw4e8lS041w== X-Received: by 10.223.134.4 with SMTP id 4mr9802118wrv.230.1521649985752; Wed, 21 Mar 2018 09:33:05 -0700 (PDT) Received: from e104803-lin.lan (mail.andrep.de. [217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:05 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:12 +0000 Message-Id: <20180321163235.12529-17-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 16/39] ARM: new VGIC: Add MMIO handling framework X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Add an MMIO handling framework to the VGIC emulation: Each register is described by its offset, size (or number of bits per IRQ, if applicable) and the read/write handler functions. We provide initialization macros to describe each GIC register later easily. Separate dispatch functions for read and write accesses are connected to Xen's MMIO handling framework and binary-search for the responsible register handler based on the offset address within the region. The register handler prototype are courtesy of Christoffer Dall. This is based on Linux commit 4493b1c4866a, written by Marc Zyngier. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall Acked-by: Stefano Stabellini --- xen/arch/arm/vgic/vgic-mmio.c | 180 ++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic-mmio.h | 89 +++++++++++++++++++++ 2 files changed, 269 insertions(+) create mode 100644 xen/arch/arm/vgic/vgic-mmio.c create mode 100644 xen/arch/arm/vgic/vgic-mmio.h diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c new file mode 100644 index 0000000000..866023a84d --- /dev/null +++ b/xen/arch/arm/vgic/vgic-mmio.c @@ -0,0 +1,180 @@ +/* + * VGIC MMIO handling functions + * Imported from Linux ("new" KVM VGIC) and heavily adapted to Xen. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#include "vgic.h" +#include "vgic-mmio.h" + +unsigned long vgic_mmio_read_raz(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + return 0; +} + +unsigned long vgic_mmio_read_rao(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + return -1UL; +} + +void vgic_mmio_write_wi(struct vcpu *vcpu, paddr_t addr, + unsigned int len, unsigned long val) +{ + /* Ignore */ +} + +static int match_region(const void *key, const void *elt) +{ + const unsigned int offset = (unsigned long)key; + const struct vgic_register_region *region = elt; + + if ( offset < region->reg_offset ) + return -1; + + if ( offset >= region->reg_offset + region->len ) + return 1; + + return 0; +} + +static const struct vgic_register_region * +vgic_find_mmio_region(const struct vgic_register_region *regions, + int nr_regions, unsigned int offset) +{ + return bsearch((void *)(uintptr_t)offset, regions, nr_regions, + sizeof(regions[0]), match_region); +} + +static bool check_region(const struct domain *d, + const struct vgic_register_region *region, + paddr_t addr, int len) +{ + unsigned int flags, nr_irqs = d->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS; + + switch ( len ) + { + case sizeof(uint8_t): + flags = VGIC_ACCESS_8bit; + break; + case sizeof(uint32_t): + flags = VGIC_ACCESS_32bit; + break; + case sizeof(uint64_t): + flags = VGIC_ACCESS_64bit; + break; + default: + return false; + } + + if ( (region->access_flags & flags) && IS_ALIGNED(addr, len) ) + { + if ( !region->bits_per_irq ) + return true; + + /* Do we access a non-allocated IRQ? */ + return VGIC_ADDR_TO_INTID(addr, region->bits_per_irq) < nr_irqs; + } + + return false; +} + +static const struct vgic_register_region * +vgic_get_mmio_region(struct vcpu *vcpu, struct vgic_io_device *iodev, + paddr_t addr, unsigned int len) +{ + const struct vgic_register_region *region; + + region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions, + addr - gfn_to_gaddr(iodev->base_fn)); + if ( !region || !check_region(vcpu->domain, region, addr, len) ) + return NULL; + + return region; +} + +static int dispatch_mmio_read(struct vcpu *vcpu, mmio_info_t *info, + register_t *r, void *priv) +{ + struct vgic_io_device *iodev = priv; + const struct vgic_register_region *region; + unsigned long data = 0; + paddr_t addr = info->gpa; + int len = 1U << info->dabt.size; + + region = vgic_get_mmio_region(vcpu, iodev, addr, len); + if ( !region ) + { + memset(r, 0, len); + return 0; + } + + switch (iodev->iodev_type) + { + case IODEV_DIST: + data = region->read(vcpu, addr, len); + break; + case IODEV_REDIST: + data = region->read(iodev->redist_vcpu, addr, len); + break; + } + + memcpy(r, &data, len); + + return 1; +} + +static int dispatch_mmio_write(struct vcpu *vcpu, mmio_info_t *info, + register_t r, void *priv) +{ + struct vgic_io_device *iodev = priv; + const struct vgic_register_region *region; + unsigned long data = r; + paddr_t addr = info->gpa; + int len = 1U << info->dabt.size; + + region = vgic_get_mmio_region(vcpu, iodev, addr, len); + if ( !region ) + return 0; + + switch (iodev->iodev_type) + { + case IODEV_DIST: + region->write(vcpu, addr, len, data); + break; + case IODEV_REDIST: + region->write(iodev->redist_vcpu, addr, len, data); + break; + } + + return 1; +} + +struct mmio_handler_ops vgic_io_ops = { + .read = dispatch_mmio_read, + .write = dispatch_mmio_write, +}; + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h new file mode 100644 index 0000000000..bf062a27ca --- /dev/null +++ b/xen/arch/arm/vgic/vgic-mmio.h @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2015, 2016 ARM Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __XEN_ARM_VGIC_VGIC_MMIO_H__ +#define __XEN_ARM_VGIC_VGIC_MMIO_H__ + +struct vgic_register_region { + unsigned int reg_offset; + unsigned int len; + unsigned int bits_per_irq; + unsigned int access_flags; + unsigned long (*read)(struct vcpu *vcpu, paddr_t addr, + unsigned int len); + void (*write)(struct vcpu *vcpu, paddr_t addr, + unsigned int len, unsigned long val); +}; + +extern struct mmio_handler_ops vgic_io_ops; + +#define VGIC_ACCESS_8bit 1 +#define VGIC_ACCESS_32bit 2 +#define VGIC_ACCESS_64bit 4 + +/* + * Generate a mask that covers the number of bytes required to address + * up to 1024 interrupts, each represented by bits. This assumes + * that is a power of two. + */ +#define VGIC_ADDR_IRQ_MASK(bits) (((bits) * 1024 / 8) - 1) + +/* + * (addr & mask) gives us the _byte_ offset for the INT ID. + * We multiply this by 8 the get the _bit_ offset, then divide this by + * the number of bits to learn the actual INT ID. + * But instead of a division (which requires a "long long div" implementation), + * we shift by the binary logarithm of . + * This assumes that is a power of two. + */ +#define VGIC_ADDR_TO_INTID(addr, bits) (((addr) & VGIC_ADDR_IRQ_MASK(bits)) * \ + 8 >> ilog2(bits)) + +/* + * Some VGIC registers store per-IRQ information, with a different number + * of bits per IRQ. For those registers this macro is used. + * The _WITH_LENGTH version instantiates registers with a fixed length + * and is mutually exclusive with the _PER_IRQ version. + */ +#define REGISTER_DESC_WITH_BITS_PER_IRQ(off, rd, wr, bpi, acc) \ + { \ + .reg_offset = off, \ + .bits_per_irq = bpi, \ + .len = bpi * 1024 / 8, \ + .access_flags = acc, \ + .read = rd, \ + .write = wr, \ + } + +#define REGISTER_DESC_WITH_LENGTH(off, rd, wr, length, acc) \ + { \ + .reg_offset = off, \ + .bits_per_irq = 0, \ + .len = length, \ + .access_flags = acc, \ + .read = rd, \ + .write = wr, \ + } + +unsigned long vgic_mmio_read_raz(struct vcpu *vcpu, + paddr_t addr, unsigned int len); + +unsigned long vgic_mmio_read_rao(struct vcpu *vcpu, + paddr_t addr, unsigned int len); + +void vgic_mmio_write_wi(struct vcpu *vcpu, paddr_t addr, + unsigned int len, unsigned long val); + +#endif From patchwork Wed Mar 21 16:32:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132206 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2355860ljb; Wed, 21 Mar 2018 09:34:47 -0700 (PDT) X-Google-Smtp-Source: AG47ELtZyOO9MyLSGgT6h7UMlK5ikcRzKhGXOqVmyvzEVRqom00xghMwKFuE8z3aPaZOSzt9p0OL X-Received: by 10.107.160.74 with SMTP id j71mr21144823ioe.10.1521650087753; Wed, 21 Mar 2018 09:34:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650087; cv=none; d=google.com; s=arc-20160816; b=w3kiHRqpH+GSeYUAnjFS5GvtEwLB6hiu5dJwgMzvsssi5DpDXi189DRzU/SdV8WUHL iwkl5bweRz26DpwNP/elp72Ynf29ZBKb2R069Z3e97InTOG/ocjGJa809MLN4m4MaQ8V l/ZLHEbrQfTkJe8eFtxunZ/kLENFWpmqPIvC0cYWN4x85rz78QBP8pHgL1QWNHwaHsfI NL+1U2W83a1phcjRe54XSvlWWooLLN5PNE+WdygvcVN8xXwJfh64u+LiwCD33Y9J5iAT vku7nEluUtaLtpdAXUH4joaM01labeZx3BYYtOdS9AAEuZr1h8JWoJ083SRNCBIKsdcB mYYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=T6/YYM4jQeISqJM98hm+0ReywUb2+EyKBvNl2F2JoCA=; b=cgpbHQW3oEH7YTl+JLyx+Lx8aLAHQ2oBmOjbIU/g8Lop+Wa1ibPih3IEoRL16+NtTB jQRyoS8NZ6CoIL8MU2bvSWEeM6mxHvyYBNcx/orPnrfj/JpQVj4Rf3SHa3S7JrxKGg0D f6B4Ckvj1hstk5SYKUlU6qoCENRplp3wqGBTH2Lj2JytxhHJ0gpsV23S5aGmqcZH0hPP WDAtGJriYLZ4TSYdOSNnUqR7bbzf0K/wRzg14zrvkZvgWJlX/WoSYL5H1DhcjPcuwE04 dSCL5kpQBMJD6LFuBQfyzPNcTFA6S0Gt+RzcE6i4RSAb1MtYGgYD31FvBNNKNrXU2kki VPcw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=RgYvuTnB; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:06 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:13 +0000 Message-Id: <20180321163235.12529-18-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 17/39] ARM: new VGIC: Add GICv2 MMIO handling framework X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Create vgic-mmio-v2.c to describe GICv2 emulation specific handlers using the initializer macros provided by the VGIC MMIO framework. Provide a function to register the GICv2 distributor registers to the Xen MMIO framework. The actual handler functions are still stubs in this patch. This is based on Linux commit fb848db39661, written by Andre Przywara. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall Acked-by: Stefano Stabellini --- xen/arch/arm/vgic/vgic-mmio-v2.c | 83 ++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic-mmio.c | 25 ++++++++++++ xen/arch/arm/vgic/vgic-mmio.h | 2 + xen/arch/arm/vgic/vgic.h | 2 + 4 files changed, 112 insertions(+) create mode 100644 xen/arch/arm/vgic/vgic-mmio-v2.c diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c new file mode 100644 index 0000000000..6f10cf16ca --- /dev/null +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -0,0 +1,83 @@ +/* + * VGICv2 MMIO handling functions + * Imported from Linux ("new" KVM VGIC) and heavily adapted to Xen. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#include "vgic.h" +#include "vgic-mmio.h" + +static const struct vgic_register_region vgic_v2_dist_registers[] = { + REGISTER_DESC_WITH_LENGTH(GICD_CTLR, + vgic_mmio_read_raz, vgic_mmio_write_wi, 12, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_IGROUPR, + vgic_mmio_read_rao, vgic_mmio_write_wi, 1, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISENABLER, + vgic_mmio_read_raz, vgic_mmio_write_wi, 1, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICENABLER, + vgic_mmio_read_raz, vgic_mmio_write_wi, 1, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISPENDR, + vgic_mmio_read_raz, vgic_mmio_write_wi, 1, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICPENDR, + vgic_mmio_read_raz, vgic_mmio_write_wi, 1, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISACTIVER, + vgic_mmio_read_raz, vgic_mmio_write_wi, 1, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICACTIVER, + vgic_mmio_read_raz, vgic_mmio_write_wi, 1, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_IPRIORITYR, + vgic_mmio_read_raz, vgic_mmio_write_wi, 8, + VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ITARGETSR, + vgic_mmio_read_raz, vgic_mmio_write_wi, 8, + VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), + REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICFGR, + vgic_mmio_read_raz, vgic_mmio_write_wi, 2, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_LENGTH(GICD_SGIR, + vgic_mmio_read_raz, vgic_mmio_write_wi, 4, + VGIC_ACCESS_32bit), + REGISTER_DESC_WITH_LENGTH(GICD_CPENDSGIR, + vgic_mmio_read_raz, vgic_mmio_write_wi, 16, + VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), + REGISTER_DESC_WITH_LENGTH(GICD_SPENDSGIR, + vgic_mmio_read_raz, vgic_mmio_write_wi, 16, + VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), +}; + +unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev) +{ + dev->regions = vgic_v2_dist_registers; + dev->nr_regions = ARRAY_SIZE(vgic_v2_dist_registers); + + return SZ_4K; +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c index 866023a84d..a03e8d88b9 100644 --- a/xen/arch/arm/vgic/vgic-mmio.c +++ b/xen/arch/arm/vgic/vgic-mmio.c @@ -170,6 +170,31 @@ struct mmio_handler_ops vgic_io_ops = { .write = dispatch_mmio_write, }; +int vgic_register_dist_iodev(struct domain *d, gfn_t dist_base_fn, + enum vgic_type type) +{ + struct vgic_io_device *io_device = &d->arch.vgic.dist_iodev; + unsigned int len; + + switch ( type ) + { + case VGIC_V2: + len = vgic_v2_init_dist_iodev(io_device); + break; + default: + BUG(); + } + + io_device->base_fn = dist_base_fn; + io_device->iodev_type = IODEV_DIST; + io_device->redist_vcpu = NULL; + + register_mmio_handler(d, &vgic_io_ops, gfn_to_gaddr(dist_base_fn), len, + io_device); + + return 0; +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h index bf062a27ca..c280668694 100644 --- a/xen/arch/arm/vgic/vgic-mmio.h +++ b/xen/arch/arm/vgic/vgic-mmio.h @@ -86,4 +86,6 @@ unsigned long vgic_mmio_read_rao(struct vcpu *vcpu, void vgic_mmio_write_wi(struct vcpu *vcpu, paddr_t addr, unsigned int len, unsigned long val); +unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev); + #endif diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index 41cc0c5b54..7f221fd195 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -49,6 +49,8 @@ static inline void vgic_get_irq_kref(struct vgic_irq *irq) void vgic_v2_fold_lr_state(struct vcpu *vcpu); void vgic_v2_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr); void vgic_v2_set_underflow(struct vcpu *vcpu); +int vgic_register_dist_iodev(struct domain *d, gfn_t dist_base_fn, + enum vgic_type); #endif From patchwork Wed Mar 21 16:32:14 2018 Content-Type: text/plain; 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:07 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:14 +0000 Message-Id: <20180321163235.12529-19-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 18/39] ARM: new VGIC: Add CTLR, TYPER and IIDR handlers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Those three registers are v2 emulation specific, so their implementation lives entirely in vgic-mmio-v2.c. Also they are handled in one function, as their implementation is pretty simple. We choose to piggy-back on the existing KVM identification registers, but use a different variant (major revision). When the guest enables the distributor, we kick all VCPUs to get potentially pending interrupts serviced. This is based on Linux commit 2b0cda878965, written by Marc Zyngier. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall Acked-by: Stefano Stabellini --- Changelog v2 ... v3: - fix misleading comment about PRODUCT_ID letter - clarify on meaning of VARIANT_ID_XEN Changelog v1 ... v2: use new IIDR values (KVM product ID, Xen revision) - add comment on handling GICD enablement - use new vcpu_kick() function xen/arch/arm/vgic/vgic-mmio-v2.c | 63 +++++++++++++++++++++++++++++++++++++++- xen/arch/arm/vgic/vgic.c | 15 ++++++++++ xen/arch/arm/vgic/vgic.h | 9 ++++++ 3 files changed, 86 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index 6f10cf16ca..43c1ab5906 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -20,9 +20,70 @@ #include "vgic.h" #include "vgic-mmio.h" +static unsigned long vgic_mmio_read_v2_misc(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + uint32_t value; + + switch ( addr & 0x0c ) /* filter for the 4 registers handled here */ + { + case GICD_CTLR: + value = vcpu->domain->arch.vgic.enabled ? GICD_CTL_ENABLE : 0; + break; + case GICD_TYPER: + value = vcpu->domain->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS; + value = (value >> 5) - 1; + value |= (vcpu->domain->max_vcpus - 1) << 5; + break; + case GICD_IIDR: + value = (PRODUCT_ID_KVM << 24) | + (VARIANT_ID_XEN << 16) | + (IMPLEMENTER_ARM << 0); + break; + default: + return 0; + } + + return value; +} + +static void vgic_mmio_write_v2_misc(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + struct vgic_dist *dist = &vcpu->domain->arch.vgic; + bool enabled; + + switch ( addr & 0x0c ) /* filter for the 4 registers handled here */ + { + case GICD_CTLR: + domain_lock(vcpu->domain); + + /* + * Store the new enabled state in our distributor structure. + * Work out whether it was disabled before and now got enabled, + * so that we signal all VCPUs to check for interrupts to be injected. + */ + enabled = dist->enabled; + dist->enabled = val & GICD_CTL_ENABLE; + enabled = !enabled && dist->enabled; + + domain_unlock(vcpu->domain); + + if ( enabled ) + vgic_kick_vcpus(vcpu->domain); + + break; + case GICD_TYPER: + case GICD_IIDR: + /* read-only, writes ignored */ + return; + } +} + static const struct vgic_register_region vgic_v2_dist_registers[] = { REGISTER_DESC_WITH_LENGTH(GICD_CTLR, - vgic_mmio_read_raz, vgic_mmio_write_wi, 12, + vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc, 12, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_IGROUPR, vgic_mmio_read_rao, vgic_mmio_write_wi, 1, diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 925cda4580..37b425a16c 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -684,6 +684,21 @@ int vgic_vcpu_pending_irq(struct vcpu *vcpu) return ret; } +void vgic_kick_vcpus(struct domain *d) +{ + struct vcpu *vcpu; + + /* + * We've injected an interrupt, time to find out who deserves + * a good kick... + */ + for_each_vcpu( d, vcpu ) + { + if ( vgic_vcpu_pending_irq(vcpu) ) + vcpu_kick(vcpu); + } +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index 7f221fd195..aed7e4179a 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -17,6 +17,14 @@ #ifndef __XEN_ARM_VGIC_VGIC_H__ #define __XEN_ARM_VGIC_VGIC_H__ +/* + * We piggy-back on the already used KVM product ID, but use a different + * variant (major revision) for Xen. + */ +#define PRODUCT_ID_KVM 0x4b /* ASCII code K */ +#define VARIANT_ID_XEN 0x01 +#define IMPLEMENTER_ARM 0x43b + #define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS) static inline bool irq_is_pending(struct vgic_irq *irq) @@ -37,6 +45,7 @@ struct vgic_irq *vgic_get_irq(struct domain *d, struct vcpu *vcpu, void vgic_put_irq(struct domain *d, struct vgic_irq *irq); void vgic_queue_irq_unlock(struct domain *d, struct vgic_irq *irq, unsigned long flags); +void vgic_kick_vcpus(struct domain *d); static inline void vgic_get_irq_kref(struct vgic_irq *irq) { From patchwork Wed Mar 21 16:32:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132210 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2355931ljb; Wed, 21 Mar 2018 09:34:52 -0700 (PDT) X-Google-Smtp-Source: AG47ELt7O0f5lqRRNQdYwBukj/s8nfJ8mgV0wr5R4473PCNjTC3tKEUsGUZNFQ47feksIYDTBWqc X-Received: by 10.107.169.81 with SMTP id s78mr20869060ioe.83.1521650092429; Wed, 21 Mar 2018 09:34:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650092; cv=none; d=google.com; s=arc-20160816; b=phAHZ0aUAGm5OHG5yN7nxbm4LALFr73huVkwCNu2aLR4IPS/1TDmZ23dRMZzRygPVg VVJIHBn+A5dtrdbnIwLUQyIC/uIGT5oljgZFNUOTHuD6tlL3F6XPBuOEqOmjUxhv/AZW ERzPSVKdk0Fc/VRptMqqygfXQE/lfpiikHxFsqRQWWj2Oo5+tTHxSYOSBvzb6PvqNWvJ TfAWS57MFHxzSAsS9TcW45DuiEyiGG8otFbJEhE+LspHTn27y8vo/vm2HSsVFrSi4HuQ cV8FFgVYhydQ4/Oe34mhcjqxBRVf9LeynAoBijB5pMrP6JsEOQwDvy8o3rJJVXiBqRTR 8uMg== ARC-Message-Signature: i=1; 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:08 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:15 +0000 Message-Id: <20180321163235.12529-20-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 19/39] ARM: new VGIC: Add ENABLE registers handlers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" As the enable register handlers are shared between the v2 and v3 emulation, their implementation goes into vgic-mmio.c, to be easily referenced from the v3 emulation as well later. This introduces a vgic_sync_hardware_irq() function, which updates the physical side of a hardware mapped virtual IRQ. Because the existing locking order between vgic_irq->irq_lock and irq_desc->lock dictates so, we drop the irq_lock and retake them in the proper order. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall Acked-by: Stefano Stabellini --- Changelog v2 ... v3: - fix indentation - fix wording in comment - add Reviewed-by: Changelog v1 ... v2: - ASSERT on h/w IRQ and vIRQ staying in sync xen/arch/arm/vgic/vgic-mmio-v2.c | 4 +- xen/arch/arm/vgic/vgic-mmio.c | 117 +++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic-mmio.h | 11 ++++ xen/arch/arm/vgic/vgic.c | 40 +++++++++++++ xen/arch/arm/vgic/vgic.h | 3 + 5 files changed, 173 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index 43c1ab5906..7efd1c4eb4 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -89,10 +89,10 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { vgic_mmio_read_rao, vgic_mmio_write_wi, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISENABLER, - vgic_mmio_read_raz, vgic_mmio_write_wi, 1, + vgic_mmio_read_enable, vgic_mmio_write_senable, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICENABLER, - vgic_mmio_read_raz, vgic_mmio_write_wi, 1, + vgic_mmio_read_enable, vgic_mmio_write_cenable, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISPENDR, vgic_mmio_read_raz, vgic_mmio_write_wi, 1, diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c index a03e8d88b9..f219b7c509 100644 --- a/xen/arch/arm/vgic/vgic-mmio.c +++ b/xen/arch/arm/vgic/vgic-mmio.c @@ -39,6 +39,123 @@ void vgic_mmio_write_wi(struct vcpu *vcpu, paddr_t addr, /* Ignore */ } +/* + * Read accesses to both GICD_ICENABLER and GICD_ISENABLER return the value + * of the enabled bit, so there is only one function for both here. + */ +unsigned long vgic_mmio_read_enable(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 1); + uint32_t value = 0; + unsigned int i; + + /* Loop over all IRQs affected by this read */ + for ( i = 0; i < len * 8; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + if ( irq->enabled ) + value |= (1U << i); + + vgic_put_irq(vcpu->domain, irq); + } + + return value; +} + +void vgic_mmio_write_senable(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 1); + unsigned int i; + + for_each_set_bit( i, &val, len * 8 ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + unsigned long flags; + irq_desc_t *desc; + + spin_lock_irqsave(&irq->irq_lock, flags); + + if ( irq->enabled ) /* skip already enabled IRQs */ + { + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(vcpu->domain, irq); + continue; + } + + irq->enabled = true; + if ( irq->hw ) + { + /* + * The irq cannot be a PPI, we only support delivery + * of SPIs to guests. + */ + ASSERT(irq->hwintid >= VGIC_NR_PRIVATE_IRQS); + + desc = irq_to_desc(irq->hwintid); + } + else + desc = NULL; + + vgic_queue_irq_unlock(vcpu->domain, irq, flags); + + if ( desc ) + vgic_sync_hardware_irq(vcpu->domain, desc, irq); + + vgic_put_irq(vcpu->domain, irq); + } +} + +void vgic_mmio_write_cenable(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 1); + unsigned int i; + + for_each_set_bit( i, &val, len * 8 ) + { + struct vgic_irq *irq; + unsigned long flags; + irq_desc_t *desc; + + irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + spin_lock_irqsave(&irq->irq_lock, flags); + + if ( !irq->enabled ) /* skip already disabled IRQs */ + { + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(vcpu->domain, irq); + continue; + } + + irq->enabled = false; + + if ( irq->hw ) + { + /* + * The irq cannot be a PPI, we only support delivery + * of SPIs to guests. + */ + ASSERT(irq->hwintid >= VGIC_NR_PRIVATE_IRQS); + + desc = irq_to_desc(irq->hwintid); + } + else + desc = NULL; + + spin_unlock_irqrestore(&irq->irq_lock, flags); + + if ( desc ) + vgic_sync_hardware_irq(vcpu->domain, desc, irq); + + vgic_put_irq(vcpu->domain, irq); + } +} + static int match_region(const void *key, const void *elt) { const unsigned int offset = (unsigned long)key; diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h index c280668694..a2cebd77f4 100644 --- a/xen/arch/arm/vgic/vgic-mmio.h +++ b/xen/arch/arm/vgic/vgic-mmio.h @@ -86,6 +86,17 @@ unsigned long vgic_mmio_read_rao(struct vcpu *vcpu, void vgic_mmio_write_wi(struct vcpu *vcpu, paddr_t addr, unsigned int len, unsigned long val); +unsigned long vgic_mmio_read_enable(struct vcpu *vcpu, + paddr_t addr, unsigned int len); + +void vgic_mmio_write_senable(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val); + +void vgic_mmio_write_cenable(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val); + unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev); #endif diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 37b425a16c..90041eb071 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -699,6 +699,46 @@ void vgic_kick_vcpus(struct domain *d) } } +static unsigned int translate_irq_type(bool is_level) +{ + return is_level ? IRQ_TYPE_LEVEL_HIGH : IRQ_TYPE_EDGE_RISING; +} + +void vgic_sync_hardware_irq(struct domain *d, + irq_desc_t *desc, struct vgic_irq *irq) +{ + unsigned long flags; + + spin_lock_irqsave(&desc->lock, flags); + spin_lock(&irq->irq_lock); + + /* + * We forbid tinkering with the hardware IRQ association during + * a domain's lifetime. + */ + ASSERT(irq->hw && desc->irq == irq->hwintid); + + if ( irq->enabled ) + { + /* + * We might end up from various callers, so check that the + * interrrupt is disabled before trying to change the config. + */ + if ( irq_type_set_by_domain(d) && + test_bit(_IRQ_DISABLED, &desc->status) ) + gic_set_irq_type(desc, translate_irq_type(irq->config)); + + if ( irq->target_vcpu ) + irq_set_affinity(desc, cpumask_of(irq->target_vcpu->processor)); + desc->handler->enable(desc); + } + else + desc->handler->disable(desc); + + spin_unlock(&irq->irq_lock); + spin_unlock_irqrestore(&desc->lock, flags); +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index aed7e4179a..071e061066 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -55,6 +55,9 @@ static inline void vgic_get_irq_kref(struct vgic_irq *irq) atomic_inc(&irq->refcount); } +void vgic_sync_hardware_irq(struct domain *d, + irq_desc_t *desc, struct vgic_irq *irq); + void vgic_v2_fold_lr_state(struct vcpu *vcpu); void vgic_v2_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr); void vgic_v2_set_underflow(struct vcpu *vcpu); From patchwork Wed Mar 21 16:32:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132215 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356034ljb; Wed, 21 Mar 2018 09:34:58 -0700 (PDT) X-Google-Smtp-Source: AG47ELuoc1qkll/RhrdZN4tJuSMgVzvpAE07eBiC3mV14yiFUgL7INSWP3xP5+s3IKWNsr/HYKol X-Received: by 2002:a24:d786:: with SMTP id y128-v6mr4693220itg.98.1521650098654; Wed, 21 Mar 2018 09:34:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650098; cv=none; d=google.com; s=arc-20160816; b=oUfCNT3STQIh/6tuSTsLqmT89WISvixWdONoHqi/tzpKgO5FImd8gaKUlU1Ge3qzqJ vAm9uxVT13hDewf73/X9XacuGNG9tfBmofnYIIK8s6BKMrsHQ6YUyF9Lfx3XBZn8sDff 9xcEjVFLUCTIF99OIJ+Gt7bh4XPG5sLdN+vHEW94RxTUxAQWdZ5NFm0heRxayZPO48zR h9iJvXuE70xK3tjBmuJCYCyQnAXkFtKrpox+dq3kaGxIEW+FEp2P/piOJZFznZ0W9W8D Rtu9JPplM86/bJ5UcIRyzLsr4emLfHb6HOZ0wIru9tnGmbnZLcUj5/GvZF3yFb9C2T3v K59g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=QyLn5v3ao0FAV6F716dZ4qrzOC59Y35/WDxNLClzrbk=; b=Pjppx8lyGCKpAm7bJPHuyZWfVAALM1gBpMufvtrXsJdLTUkYJ+u1iwzh674IhoQzyp ErAf8aQZfnHPWZk0PRNzi4gaa/mOLYihX3wTELuvVrIzIPToFa7ZVFnB3AYMT8EDLA9Z PM4NBTLCKHfU6r8WHGU36VkQhC5b3XWsSb0x3lBGi6+1XLJq/V2uoa/8m/jPwBdCR93O PAsSaD1yQDjfteyukkY2pc4IAVzJe1Ju6Zk2ae0MtFimANgychYi91yVEWh0+91fhcBX K48gSGEMpW9YLJs9C6/PMuSPl9e48mnxlREcB3w+W2VZDK/mynePrZx1d1aNm6ohFAig KUvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=PsAPLYjb; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:09 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:16 +0000 Message-Id: <20180321163235.12529-21-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 20/39] ARM: new VGIC: Add PENDING registers handlers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The pending register handlers are shared between the v2 and v3 emulation, so their implementation goes into vgic-mmio.c, to be easily referenced from the v3 emulation as well later. For level triggered interrupts the real line level is unaffected by this write, so we keep this state separate and combine it with the device's level to get the actual pending state. Hardware mapped IRQs need some special handling, as their hardware state has to be coordinated with the virtual pending bit to avoid hanging or masked interrupts. This is based on Linux commit 96b298000db4, written by Andre Przywara. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall --- xen/arch/arm/vgic/vgic-mmio-v2.c | 4 +- xen/arch/arm/vgic/vgic-mmio.c | 125 +++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic-mmio.h | 11 ++++ 3 files changed, 138 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index 7efd1c4eb4..a48c554040 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -95,10 +95,10 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { vgic_mmio_read_enable, vgic_mmio_write_cenable, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISPENDR, - vgic_mmio_read_raz, vgic_mmio_write_wi, 1, + vgic_mmio_read_pending, vgic_mmio_write_spending, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICPENDR, - vgic_mmio_read_raz, vgic_mmio_write_wi, 1, + vgic_mmio_read_pending, vgic_mmio_write_cpending, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISACTIVER, vgic_mmio_read_raz, vgic_mmio_write_wi, 1, diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c index f219b7c509..53b8978c02 100644 --- a/xen/arch/arm/vgic/vgic-mmio.c +++ b/xen/arch/arm/vgic/vgic-mmio.c @@ -156,6 +156,131 @@ void vgic_mmio_write_cenable(struct vcpu *vcpu, } } +unsigned long vgic_mmio_read_pending(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 1); + uint32_t value = 0; + unsigned int i; + + /* Loop over all IRQs affected by this read */ + for ( i = 0; i < len * 8; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + if ( irq_is_pending(irq) ) + value |= (1U << i); + + vgic_put_irq(vcpu->domain, irq); + } + + return value; +} + +void vgic_mmio_write_spending(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 1); + unsigned int i; + unsigned long flags; + irq_desc_t *desc; + + for_each_set_bit( i, &val, len * 8 ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + spin_lock_irqsave(&irq->irq_lock, flags); + irq->pending_latch = true; + + /* To observe the locking order, just take the irq_desc pointer here. */ + if ( irq->hw ) + desc = irq_to_desc(irq->hwintid); + else + desc = NULL; + + vgic_queue_irq_unlock(vcpu->domain, irq, flags); + + /* + * When the VM sets the pending state for a HW interrupt on the virtual + * distributor we set the active state on the physical distributor, + * because the virtual interrupt can become active and then the guest + * can deactivate it. + */ + if ( desc ) + { + spin_lock_irqsave(&desc->lock, flags); + spin_lock(&irq->irq_lock); + + /* This h/w IRQ should still be assigned to the virtual IRQ. */ + ASSERT(irq->hw && desc->irq == irq->hwintid); + + gic_set_active_state(desc, true); + + spin_unlock(&irq->irq_lock); + spin_unlock_irqrestore(&desc->lock, flags); + } + + vgic_put_irq(vcpu->domain, irq); + } +} + +void vgic_mmio_write_cpending(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 1); + unsigned int i; + unsigned long flags; + irq_desc_t *desc; + + for_each_set_bit( i, &val, len * 8 ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + spin_lock_irqsave(&irq->irq_lock, flags); + irq->pending_latch = false; + + /* To observe the locking order, just take the irq_desc pointer here. */ + if ( irq->hw ) + desc = irq_to_desc(irq->hwintid); + else + desc = NULL; + + spin_unlock_irqrestore(&irq->irq_lock, flags); + + /* + * We don't want the guest to effectively mask the physical + * interrupt by doing a write to SPENDR followed by a write to + * CPENDR for HW interrupts, so we clear the active state on + * the physical side if the virtual interrupt is not active. + * This may lead to taking an additional interrupt on the + * host, but that should not be a problem as the worst that + * can happen is an additional vgic injection. We also clear + * the pending state to maintain proper semantics for edge HW + * interrupts. + */ + if ( desc ) + { + spin_lock_irqsave(&desc->lock, flags); + spin_lock(&irq->irq_lock); + + /* This h/w IRQ should still be assigned to the virtual IRQ. */ + ASSERT(irq->hw && desc->irq == irq->hwintid); + + gic_set_pending_state(desc, false); + if (!irq->active) + gic_set_active_state(desc, false); + + spin_unlock(&irq->irq_lock); + spin_unlock_irqrestore(&desc->lock, flags); + } + + + vgic_put_irq(vcpu->domain, irq); + } +} + static int match_region(const void *key, const void *elt) { const unsigned int offset = (unsigned long)key; diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h index a2cebd77f4..5c927f28b0 100644 --- a/xen/arch/arm/vgic/vgic-mmio.h +++ b/xen/arch/arm/vgic/vgic-mmio.h @@ -97,6 +97,17 @@ void vgic_mmio_write_cenable(struct vcpu *vcpu, paddr_t addr, unsigned int len, unsigned long val); +unsigned long vgic_mmio_read_pending(struct vcpu *vcpu, + paddr_t addr, unsigned int len); + +void vgic_mmio_write_spending(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val); + +void vgic_mmio_write_cpending(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val); + unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev); #endif From patchwork Wed Mar 21 16:32:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132208 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2355927ljb; Wed, 21 Mar 2018 09:34:52 -0700 (PDT) X-Google-Smtp-Source: AIpwx48two3iadqwycyLpbPMDgVzVPraC2RaiRW0qsA2fI/Wz9RGSE+Oh8NPiqeopF37OgsksVGc X-Received: by 2002:a24:2289:: with SMTP id o131-v6mr4749211ito.95.1521650092207; Wed, 21 Mar 2018 09:34:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650092; cv=none; d=google.com; s=arc-20160816; b=LUNH6Rx5RzjI3koIUWnLwn4Lpl9VtbmPMGHU57MA0+11JlLnCyEx9qD7wPUdVqhNj3 7yl6OYmuxGnsQ/kLqRjM0Y/NhhvAKi7MA9QiWa5DP+93UU76TFUzGoSXtRRroPl0xn39 7XjoAPNlYq6Ih1v5Mu5+Ckx+/+bFm9suP7defISD6Gt9ROyCWGoddcKrMbsbSLNX2QOL kU0HIYcxhu055Ih/N+EoH3gINQQAhpKLtM9W5+cM/avQVn7aLlYehiyGhQn5QJkqOkoj j/Hi6dt34xxSb73aH4EYDeN83RM8MTVRyRoGk/KPS7Abb2eu5Ja0YBr4FbcST2KNXWrT i8wQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=egc670A50FwE4L/YwnYg3jRWo7/gVzGQp7BfMoP+8wc=; b=VYEs3i4aPBjR3Pf3hJ8xf7eSLK18n/VOSjIPwQWjmeUTO2UjPlNy7pUz4TE3bolNtO 2eGWjZCbnmbAl7a+iHRc1PBnfD7zjSnRvt8N9djQ/oS3qb7pTp+thZ2g/U/kXNR3Vkry O6+LwHuSVpSMA9AWDZWhfMtnP66hNkmfWSLy0XmWY+88AmMCFSv+P4eyVWksqHBWS5W+ hXlICBZsh98v9qY2w+vy7i5GVbIrsPgLpwy9/g6ZO2tN+exM7AstzI9/Ti99omYJA3hi L8RK9ufkeqWORK00dBF9kjKT4ClpnpYAZApmhYeVA9k86O5jWYCQwx+vIYVR+O150lR0 4R7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=RlS51ftO; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:10 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:17 +0000 Message-Id: <20180321163235.12529-22-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 21/39] ARM: new VGIC: Add ACTIVE registers handlers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The active register handlers are shared between the v2 and v3 emulation, so their implementation goes into vgic-mmio.c, to be easily referenced from the v3 emulation as well later. Since activation/deactivation of an interrupt may happen entirely in the guest without it ever exiting, we need some extra logic to properly track the active state. For clearing the active state, we would basically have to halt the guest to make sure this is properly propagated into the respective VCPUs. This is not yet implemented in Xen. Fortunately this feature is mostly used to reset a just in initialised GIC, so chances are we are tasked to clear bits that are already zero. Add a simple check to avoid pointless warnings in this case. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall --- xen/arch/arm/vgic/vgic-mmio-v2.c | 4 +- xen/arch/arm/vgic/vgic-mmio.c | 91 ++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic-mmio.h | 11 +++++ 3 files changed, 104 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index a48c554040..724681e0f8 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -101,10 +101,10 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { vgic_mmio_read_pending, vgic_mmio_write_cpending, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ISACTIVER, - vgic_mmio_read_raz, vgic_mmio_write_wi, 1, + vgic_mmio_read_active, vgic_mmio_write_sactive, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICACTIVER, - vgic_mmio_read_raz, vgic_mmio_write_wi, 1, + vgic_mmio_read_active, vgic_mmio_write_cactive, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_IPRIORITYR, vgic_mmio_read_raz, vgic_mmio_write_wi, 8, diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c index 53b8978c02..b79e431f50 100644 --- a/xen/arch/arm/vgic/vgic-mmio.c +++ b/xen/arch/arm/vgic/vgic-mmio.c @@ -281,6 +281,97 @@ void vgic_mmio_write_cpending(struct vcpu *vcpu, } } +/* + * The actual active bit for a virtual IRQ is held in the LR. Our shadow + * copy in struct vgic_irq is only synced when needed and may not be + * up-to-date all of the time. + * Returning the actual active state is quite costly (stopping all + * VCPUs processing any affected vIRQs), so we use a simple implementation + * to get the best possible answer. + */ +unsigned long vgic_mmio_read_active(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 1); + uint32_t value = 0; + unsigned int i; + + /* Loop over all IRQs affected by this read */ + for ( i = 0; i < len * 8; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + if ( irq->active ) + value |= (1U << i); + + vgic_put_irq(vcpu->domain, irq); + } + + return value; +} + +/* + * We don't actually support clearing the active state of an IRQ (yet). + * However there is a chance that most guests use this for initialization. + * We check whether this MMIO access would actually affect any active IRQ, + * and only print our warning in this case. So clearing already non-active + * IRQs would not be moaned about in the logs. + */ +void vgic_mmio_write_cactive(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 1); + unsigned int i; + + for_each_set_bit( i, &val, len * 8 ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + /* + * If we know that the IRQ is active or we can't be sure about + * it (because it is currently in a CPU), log the not properly + * emulated MMIO access. + */ + if ( irq->active || irq->vcpu ) + printk(XENLOG_G_ERR + "%pv: vGICD: IRQ%u: clearing active state not supported\n", + vcpu, irq->intid); + + vgic_put_irq(vcpu->domain, irq); + } +} + +/* + * We don't actually support setting the active state of an IRQ (yet). + * We check whether this MMIO access would actually affect any non-active IRQ, + * and only print our warning in this case. + */ +void vgic_mmio_write_sactive(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 1); + unsigned int i; + + for_each_set_bit( i, &val, len * 8 ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + /* + * If we know that the IRQ is not active or we can't be sure about + * it (because it is currently in a CPU), log the not properly + * emulated MMIO access. + */ + if ( !irq->active || irq->vcpu ) + printk(XENLOG_G_ERR + "%pv: vGICD: IRQ%u: setting active state not supported\n", + vcpu, irq->intid); + + vgic_put_irq(vcpu->domain, irq); + } +} + static int match_region(const void *key, const void *elt) { const unsigned int offset = (unsigned long)key; diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h index 5c927f28b0..832e2eb3d8 100644 --- a/xen/arch/arm/vgic/vgic-mmio.h +++ b/xen/arch/arm/vgic/vgic-mmio.h @@ -108,6 +108,17 @@ void vgic_mmio_write_cpending(struct vcpu *vcpu, paddr_t addr, unsigned int len, unsigned long val); +unsigned long vgic_mmio_read_active(struct vcpu *vcpu, + paddr_t addr, unsigned int len); + +void vgic_mmio_write_cactive(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val); + +void vgic_mmio_write_sactive(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val); + unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev); #endif From patchwork Wed Mar 21 16:32:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132240 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356679ljb; Wed, 21 Mar 2018 09:35:34 -0700 (PDT) X-Google-Smtp-Source: AG47ELtaUim86mJvVmGStaFPljHdlu1Ff5IJJlkwiQoQSuTuIJrtWJqQWPmKp2Dj4YD7WLlbcGkZ X-Received: by 10.107.44.199 with SMTP id s190mr22664830ios.123.1521650133867; Wed, 21 Mar 2018 09:35:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650133; cv=none; d=google.com; s=arc-20160816; b=hEwbnRFa2MHiioZM+Io6TKtQL14BaZpalibXbrf/jRsBv1KUuBnADlPEfAwQ+MaYvX hU12H//FJQ83hDYU/O+4edUEIE8ky1i78qhTrl/d0ymKWAMKOiuzkHwzdgt5FTNBk4Ja 80Ns2K5NxULeaBk8eeDUCHaX6uCm/QYfEH6SlwB4YBPm4nJiXO8J5UxrAvkz/cXVODBd Mfa6ABJr09PvIocBZXF+/RQtw/6siFlwZB5GzWp6bmKBf5XBxdwpMA10zjQNaCuvnQLm OJJC7JeTfF2Y+9kvKNMRQsfQsskjPqk9xuYNYHvKJTwX1lOJYHuM3EkjW7LtA8AvZrAY O6Xw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=9eY7AV0EjuPArUOCTwGq22XueTTUvVxOjlWdm2Y2r3I=; b=ilkQDb712u4dgFM4EMB4zG5kI5fn7cNNLoyO0ZqLOM6AIfl6HHswOZi1oeQtP613ce tBIT0geGvRBAkIWtYH8hB+UcMIT/VJbJ77o3L0b5xlj3u5taQ4u+PuZWfndB30qq1JFn 7BLFsVDW9U5C3acpYJSIpN5VGi2qABnRUJ6ZJ+u0eeNM/mj4cZsudKLZIsGmVjJtiXCo wBrwVB8egaCvWYjOgsx3dX2PznmGCROlhRc29+TxXprmt65XtzG4b5xDhbLiETVCUIUW 4y1smgww8ZXfj+SxvE7WL3kM0kRKy5MMRHUg1DmuH+uXN+NoHIO+fxEk6pYUO+Y/82RI wv4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=fXlzMhUS; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:11 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:18 +0000 Message-Id: <20180321163235.12529-23-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 22/39] ARM: new VGIC: Add PRIORITY registers handlers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The priority register handlers are shared between the v2 and v3 emulation, so their implementation goes into vgic-mmio.c, to be easily referenced from the v3 emulation as well later. This is based on Linux commit 055658bf48fc, written by Andre Przywara. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall --- xen/arch/arm/vgic/vgic-mmio-v2.c | 2 +- xen/arch/arm/vgic/vgic-mmio.c | 47 ++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic-mmio.h | 7 ++++++ xen/arch/arm/vgic/vgic.h | 2 ++ 4 files changed, 57 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index 724681e0f8..d2d6a07e1b 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -107,7 +107,7 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { vgic_mmio_read_active, vgic_mmio_write_cactive, 1, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_IPRIORITYR, - vgic_mmio_read_raz, vgic_mmio_write_wi, 8, + vgic_mmio_read_priority, vgic_mmio_write_priority, 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ITARGETSR, vgic_mmio_read_raz, vgic_mmio_write_wi, 8, diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c index b79e431f50..14b69d80d4 100644 --- a/xen/arch/arm/vgic/vgic-mmio.c +++ b/xen/arch/arm/vgic/vgic-mmio.c @@ -372,6 +372,53 @@ void vgic_mmio_write_sactive(struct vcpu *vcpu, } } +unsigned long vgic_mmio_read_priority(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 8); + unsigned int i; + uint32_t val = 0; + + for ( i = 0; i < len; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + val |= (uint32_t)irq->priority << (i * 8); + + vgic_put_irq(vcpu->domain, irq); + } + + return val; +} + +/* + * We currently don't handle changing the priority of an interrupt that + * is already pending on a VCPU. If there is a need for this, we would + * need to make this VCPU exit and re-evaluate the priorities, potentially + * leading to this interrupt getting presented now to the guest (if it has + * been masked by the priority mask before). + */ +void vgic_mmio_write_priority(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 8); + unsigned int i; + unsigned long flags; + + for ( i = 0; i < len; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + spin_lock_irqsave(&irq->irq_lock, flags); + /* Narrow the priority range to what we actually support */ + irq->priority = (val >> (i * 8)) & GENMASK(7, 8 - VGIC_PRI_BITS); + spin_unlock_irqrestore(&irq->irq_lock, flags); + + vgic_put_irq(vcpu->domain, irq); + } +} + static int match_region(const void *key, const void *elt) { const unsigned int offset = (unsigned long)key; diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h index 832e2eb3d8..b2d572d562 100644 --- a/xen/arch/arm/vgic/vgic-mmio.h +++ b/xen/arch/arm/vgic/vgic-mmio.h @@ -119,6 +119,13 @@ void vgic_mmio_write_sactive(struct vcpu *vcpu, paddr_t addr, unsigned int len, unsigned long val); +unsigned long vgic_mmio_read_priority(struct vcpu *vcpu, + paddr_t addr, unsigned int len); + +void vgic_mmio_write_priority(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val); + unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev); #endif diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index 071e061066..c7eeaf7a38 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -25,6 +25,8 @@ #define VARIANT_ID_XEN 0x01 #define IMPLEMENTER_ARM 0x43b +#define VGIC_PRI_BITS 5 + #define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS) static inline bool irq_is_pending(struct vgic_irq *irq) From patchwork Wed Mar 21 16:32:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132214 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356004ljb; Wed, 21 Mar 2018 09:34:57 -0700 (PDT) X-Google-Smtp-Source: AG47ELtF9d07FXZCWhObpA6c8qx9Ekj3lqAWZ3xBh/YODrqSkHgSeL+Kwy1XHLkj0BTmRdTmwELR X-Received: by 10.107.47.198 with SMTP id v67mr12043978iov.281.1521650097051; Wed, 21 Mar 2018 09:34:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650097; cv=none; d=google.com; s=arc-20160816; b=u3Pi73WpBayb6ixD5LYhVFnIpPV2GOEyXQJcjQCX558Pwg10NCDlPVoirBGp4MX9Kv j/RGTxuUMdz4FBG5sdxUxq3cvZY/lH9JGtpSRqyOEXNwbCz43vGREVTo+7Gsa4znt8eO yKx+M6jJ6N/WTomzioYBK5AtshPjmS9DxunpafA3xMxDxKiFO3EqVe5V4Vq0JVIIK1Pj 8TvBOd78gK/R/m8s+FYp5AmzJC7hdEWheYLN5UfaleKUjcdoPrb3rs2rXFYttxTVQd5z PJAIamimPa6GyPn/CnjNhz/49ykxwSmTIvzBWy04+mnsXXMr23JeSzRTmsoIQiW0fKK5 iq6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=vobgIKvXBl2LlyBQRWGwoWv3tVpqqGHjrvD/+ZWP6UI=; b=aeHb0SyCrexNfj9nJC7HL2Y+jwQ6GOBtzoulF4r4sDMZrSuZ3MfQ0jrc0f7a1fddO3 7OhJ6tri2abdlNomKEfwhz9bhz36gVcX/RXNNCu7xG4h9l+BabjIHXJz/zH83a65b6bX C6qjbjH8me8lXvQ1J1yb4l91UmuB4Makuk++sR9CsspffZ72bbUNY2QxdiKqHkwaGsfU Guwo2ii+EJTc/dJZmw28sPxlK46+JL3Y1TJwl4wYfpkElpGhPwgATfjh1FS/vzO5cG9Z RHNpVj4Wb9K+aX0EY023U6S/evoXwV2owO4wB7bikmnwWF6f1dmiCj4uKiSHpyHiGAFI 6KCg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=HTH840Zu; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:12 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:19 +0000 Message-Id: <20180321163235.12529-24-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 23/39] ARM: new VGIC: Add CONFIG registers handlers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The config register handlers are shared between the v2 and v3 emulation, so their implementation goes into vgic-mmio.c, to be easily referenced from the v3 emulation as well later. This is based on Linux commit 79717e4ac09c, written by Andre Przywara. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall --- xen/arch/arm/vgic/vgic-mmio-v2.c | 2 +- xen/arch/arm/vgic/vgic-mmio.c | 54 ++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic-mmio.h | 7 ++++++ 3 files changed, 62 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index d2d6a07e1b..a28d0e459b 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -113,7 +113,7 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { vgic_mmio_read_raz, vgic_mmio_write_wi, 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICFGR, - vgic_mmio_read_raz, vgic_mmio_write_wi, 2, + vgic_mmio_read_config, vgic_mmio_write_config, 2, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_LENGTH(GICD_SGIR, vgic_mmio_read_raz, vgic_mmio_write_wi, 4, diff --git a/xen/arch/arm/vgic/vgic-mmio.c b/xen/arch/arm/vgic/vgic-mmio.c index 14b69d80d4..5bcb02e8c6 100644 --- a/xen/arch/arm/vgic/vgic-mmio.c +++ b/xen/arch/arm/vgic/vgic-mmio.c @@ -419,6 +419,60 @@ void vgic_mmio_write_priority(struct vcpu *vcpu, } } +unsigned long vgic_mmio_read_config(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 2); + uint32_t value = 0; + int i; + + for ( i = 0; i < len * 4; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + if ( irq->config == VGIC_CONFIG_EDGE ) + value |= (2U << (i * 2)); + + vgic_put_irq(vcpu->domain, irq); + } + + return value; +} + +void vgic_mmio_write_config(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 2); + int i; + unsigned long flags; + + for ( i = 0; i < len * 4; i++ ) + { + struct vgic_irq *irq; + + /* + * The configuration cannot be changed for SGIs in general, + * for PPIs this is IMPLEMENTATION DEFINED. The arch timer + * code relies on PPIs being level triggered, so we also + * make them read-only here. + */ + if ( intid + i < VGIC_NR_PRIVATE_IRQS ) + continue; + + irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + spin_lock_irqsave(&irq->irq_lock, flags); + + if ( test_bit(i * 2 + 1, &val) ) + irq->config = VGIC_CONFIG_EDGE; + else + irq->config = VGIC_CONFIG_LEVEL; + + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(vcpu->domain, irq); + } +} + static int match_region(const void *key, const void *elt) { const unsigned int offset = (unsigned long)key; diff --git a/xen/arch/arm/vgic/vgic-mmio.h b/xen/arch/arm/vgic/vgic-mmio.h index b2d572d562..3566cf237c 100644 --- a/xen/arch/arm/vgic/vgic-mmio.h +++ b/xen/arch/arm/vgic/vgic-mmio.h @@ -126,6 +126,13 @@ void vgic_mmio_write_priority(struct vcpu *vcpu, paddr_t addr, unsigned int len, unsigned long val); +unsigned long vgic_mmio_read_config(struct vcpu *vcpu, + paddr_t addr, unsigned int len); + +void vgic_mmio_write_config(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val); + unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev); #endif From patchwork Wed Mar 21 16:32:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132207 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2355892ljb; Wed, 21 Mar 2018 09:34:49 -0700 (PDT) X-Google-Smtp-Source: AG47ELuIBeBhffM+xMN/4LiO2yZ/dO4XBV7grdnzwJP41RTnSV3thYOkqQ2DTu3xZc64H5QmCLsu X-Received: by 2002:a24:cac7:: with SMTP id k190-v6mr3413960itg.0.1521650089510; Wed, 21 Mar 2018 09:34:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650089; cv=none; d=google.com; s=arc-20160816; b=G8Ke8pug5HpLhh+I2idl7oDa6GjlgN9gb+c57+RWc4RhB7TC8ki/Hky1F3pjQwJzJ3 WiIABjISizBSnh4/Z8thl+9f4ZSjVPb4UxxaX0ONr15xsJtL7vU0vkADjV8i3kJb874e PR7CcW2bBpn5To4JnVF6bzD5B+t/O+TPt/f4vOs3StMkx+LQo6JOMORIyuxpNSd9Y26k OxzZEeMVJt5latdw84uySia2HRpVu62+fCYmaZf4ZgeHxM8Ge8XfOm8sDqxdBqOMelOF bBpXnremhz+H+DE4YGvXlwlxUcZROQANNqAmdxKOfKfFzq9oqT9nyPbm6/5vKIwg6Exf nDIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=IMlig+SnerEi7W+yurnMZNCo1F74onNZ7EvzMXdF/ts=; b=FyQ8Wa7VvhNm326ZtFKzR6Jq5ZfXNVsx6v9++V+JVOrNU/M1201LX3yjWJj16b/Px+ piTm/kjHoTtPFE3HqcVvDeynFMNfTS15/E4wsHU3LlYxCqysXpHhBlXWcgpAZFv0Dz91 CU6LDFovVsFqp05q5fv4mXrXren2Yr7yGX0Tkaca4Q62CYJx+OhKh0wWajBZ0HN92Rqg yBznMqT6rJsBbqa85444WMUjVFbebzpWmOs2S4bYsN1XyY+7gkVM5IVycdXDwRMdBA8a YEpQhNLnTaYShTbAlRjbvbLUJmnloL5jrc+GeGKjVgYmf/YPGHvp6yEjpOlqWu9Jd9DS I02g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=cs4dxG5p; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:13 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:20 +0000 Message-Id: <20180321163235.12529-25-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 24/39] ARM: new VGIC: Add TARGET registers handlers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The target register handlers are v2 emulation specific, so their implementation lives entirely in vgic-mmio-v2.c. We copy the old VGIC behaviour of assigning an IRQ to the first VCPU set in the target mask instead of making it possibly pending on multiple VCPUs. We update the physical affinity of a hardware mapped vIRQ on the way. This is based on Linux commit 2c234d6f1826, written by Andre Przywara. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall Acked-by: Stefano Stabellini --- xen/arch/arm/vgic/vgic-mmio-v2.c | 59 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 58 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index a28d0e459b..b333de9ed7 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -81,6 +81,63 @@ static void vgic_mmio_write_v2_misc(struct vcpu *vcpu, } } +static unsigned long vgic_mmio_read_target(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 8); + uint32_t val = 0; + unsigned int i; + + for ( i = 0; i < len; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + val |= (uint32_t)irq->targets << (i * 8); + + vgic_put_irq(vcpu->domain, irq); + } + + return val; +} + +static void vgic_mmio_write_target(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 8); + uint8_t cpu_mask = GENMASK(vcpu->domain->max_vcpus - 1, 0); + unsigned int i; + unsigned long flags; + + /* GICD_ITARGETSR[0-7] are read-only */ + if ( intid < VGIC_NR_PRIVATE_IRQS ) + return; + + for ( i = 0; i < len; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, NULL, intid + i); + + spin_lock_irqsave(&irq->irq_lock, flags); + + irq->targets = (val >> (i * 8)) & cpu_mask; + if ( irq->targets ) + { + irq->target_vcpu = vcpu->domain->vcpu[ffs(irq->targets) - 1]; + if ( irq->hw ) + { + struct irq_desc *desc = irq_to_desc(irq->hwintid); + + irq_set_affinity(desc, cpumask_of(irq->target_vcpu->processor)); + } + } + else + irq->target_vcpu = NULL; + + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(vcpu->domain, irq); + } +} + static const struct vgic_register_region vgic_v2_dist_registers[] = { REGISTER_DESC_WITH_LENGTH(GICD_CTLR, vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc, 12, @@ -110,7 +167,7 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { vgic_mmio_read_priority, vgic_mmio_write_priority, 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ITARGETSR, - vgic_mmio_read_raz, vgic_mmio_write_wi, 8, + vgic_mmio_read_target, vgic_mmio_write_target, 8, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), REGISTER_DESC_WITH_BITS_PER_IRQ(GICD_ICFGR, vgic_mmio_read_config, vgic_mmio_write_config, 2, From patchwork Wed Mar 21 16:32:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132219 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356038ljb; Wed, 21 Mar 2018 09:34:58 -0700 (PDT) X-Google-Smtp-Source: AG47ELvC+hoIm9F8c82EKcxqw1gUOFj6V4koyaJKLthOt/HLrLI4E+SnWi1En6MBVbgt6FPFXC6H X-Received: by 2002:a24:f685:: with SMTP id u127-v6mr4767732ith.131.1521650098834; Wed, 21 Mar 2018 09:34:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650098; cv=none; d=google.com; s=arc-20160816; b=xYjdRaAIA28RYAulb1op/anvfHMfXFSkxIbG5ShT5tT80lvz1pJXFR3rVT1A4eZ1hC nXrsN55X4g2ZGw1QGXoLuxTvnjeFiD4KZtCbEFxjoPoO7BCo3yNAYNZ97c0+NSN/mPZk YiLfdjvVADOAx4X2E3RQYZKjNXsAOIzaPTcYJElJO2i8bHwankb7y0ptIoqZhXQCUnr6 fpufpBPBZEWjd0Y5c52OBjV1kGMeZSbJeyIqhnLXgUj3we0bMXJY2m9QntpgEdcvRYmz n2bQ9uJgIVgabIWH9eMYXafrCxp8uV+sUgp0W52WVxAy49PVqw6kNTex3vFDFbKS2GMx m5Xg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=ZDgFhZMHeq9MXY1M1DBGLD+pcGRNC0Vy60Hh3YB+8ZU=; b=QqJK2k+GEFC+entoLGXGDH8y//Nyxk2NQPl5kETX1DreLv6YmHfQuoxP6CTHmqtrgT fpjb6c5IWDt8Xhkj48A8aJYM2Lou7TxMxxGMAju6opd3vpfyNai88Dga+uu0B78FKDt5 NuSy/dfVA9AUSO23v4q+JSMot/IKSqtGQOGoJ2p1H4bED+VIyX/+c10vBc7+0qheBdby IM3Fm71ZQ6gkhP3r4aAFOWSbjAG+4kvB1Tt+yERb66lK4U4u+JhsvN27zm2kR7JkvcEJ XPj/Hq54SNKqdqwXIxotZnXveegs5bNB+/BcM59iwa4957BzwxyPHCk40KIvjjcZmAOn xmBw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=DVXNkMj+; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:14 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:21 +0000 Message-Id: <20180321163235.12529-26-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 25/39] ARM: new VGIC: Add SGIR register handler X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Triggering an IPI via this register is v2 specific, so the implementation lives entirely in vgic-mmio-v2.c. This is based on Linux commit 55cc01fb9004, written by Andre Przywara. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall Acked-by: Stefano Stabellini --- Changelog v2 ... v3: - fix target mask calculation Changelog v1 ... v2: - remove stray rebase artefact xen/arch/arm/vgic/vgic-mmio-v2.c | 45 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index b333de9ed7..9ef80608c1 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -81,6 +81,49 @@ static void vgic_mmio_write_v2_misc(struct vcpu *vcpu, } } +static void vgic_mmio_write_sgir(struct vcpu *source_vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + struct domain *d = source_vcpu->domain; + unsigned int nr_vcpus = d->max_vcpus; + unsigned int intid = val & GICD_SGI_INTID_MASK; + unsigned long targets = (val & GICD_SGI_TARGET_MASK) >> + GICD_SGI_TARGET_SHIFT; + unsigned int vcpu_id; + + switch ( val & GICD_SGI_TARGET_LIST_MASK ) + { + case GICD_SGI_TARGET_LIST: /* as specified by targets */ + targets &= GENMASK(nr_vcpus - 1, 0); /* limit to existing VCPUs */ + break; + case GICD_SGI_TARGET_OTHERS: + targets = GENMASK(nr_vcpus - 1, 0); /* all, ... */ + targets &= ~(1U << source_vcpu->vcpu_id); /* but self */ + break; + case GICD_SGI_TARGET_SELF: /* this very vCPU only */ + targets = (1U << source_vcpu->vcpu_id); + break; + case 0x3: /* reserved */ + return; + } + + for_each_set_bit( vcpu_id, &targets, 8 ) + { + struct vcpu *vcpu = d->vcpu[vcpu_id]; + struct vgic_irq *irq = vgic_get_irq(d, vcpu, intid); + unsigned long flags; + + spin_lock_irqsave(&irq->irq_lock, flags); + + irq->pending_latch = true; + irq->source |= 1U << source_vcpu->vcpu_id; + + vgic_queue_irq_unlock(d, irq, flags); + vgic_put_irq(d, irq); + } +} + static unsigned long vgic_mmio_read_target(struct vcpu *vcpu, paddr_t addr, unsigned int len) { @@ -173,7 +216,7 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { vgic_mmio_read_config, vgic_mmio_write_config, 2, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_LENGTH(GICD_SGIR, - vgic_mmio_read_raz, vgic_mmio_write_wi, 4, + vgic_mmio_read_raz, vgic_mmio_write_sgir, 4, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_LENGTH(GICD_CPENDSGIR, vgic_mmio_read_raz, vgic_mmio_write_wi, 16, From patchwork Wed Mar 21 16:32:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132209 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2355930ljb; Wed, 21 Mar 2018 09:34:52 -0700 (PDT) X-Google-Smtp-Source: AG47ELvcM3+dibU04KQm8DR+q9ZH796JzrroCxAQSj/SMSJjT8OAzgkuidNKXTATO1WjWF21RfVd X-Received: by 10.107.131.207 with SMTP id n76mr19190342ioi.158.1521650092379; Wed, 21 Mar 2018 09:34:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650092; cv=none; d=google.com; s=arc-20160816; b=WuCXYsgOffT1fNgFt8JK6evS2bp8be9dVUVUlbTLi+5jhYAMG5I7AfouoXcWkj1STA 6Yw68FVcJUsodZQSHERZSU2rACX6d/IkAHg9ci4SKdJIdlj5IbiYFFbQJz399aDkx8Ho woZGoJc6TWjPqrRr6ulhbx2OdYmCGBVwPk4rkPEr7jKLjBOCEcecQQVb7f2Oewsez7lL QPL8lNbW3rdNt1p+aptwShd6xKqmsrtAlRo1ZTDdqnJ5bxUBOO3iM8XOwpq04fpJU7L+ niHY3VyuizQBrg1MFO7d99FatCmbKzhtd5hEeTlEhVSAAr+yiyUrgUwSvudI0vpdHMrF GuUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=ELkdz314nVkIXAgdgBA7Lnwfoz14Mg/qw2Kz/0JAUlk=; b=XYHyiDGWJ2BjoT4KIiwVLGHHlwH4uyRyzPvga57q6db8AE1DyMvWQwx1Lzfv7Z8pQC YeswOlyTo5/VhN8QSloODYahzwdPUF8Veyq+YM8nQxTzSOMwZYfeJKKZPYNZiULXQwxo +ZB82UYwftqMwrfT6xfTAsyxE73kNIRv9QQ185JuRwvZ9v65WXmQF0mq9Brpf+hLpSRS dR8zSHyl+D4DEUkUY6NqoH/eCC8Om0CJbPi8LQc2WzAXj2VOavkkvmkDPxYYKN2PDEcK akVwIlQVWELv4x/MQXQLgJ/58Rld6nZCAhDEzqwatofX2KbAUm0jhfPj5U/AGxgyU9sZ EJ/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=DcMtie7e; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:15 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:22 +0000 Message-Id: <20180321163235.12529-27-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 26/39] ARM: new VGIC: Add SGIPENDR register handlers X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" As this register is v2 specific, its implementation lives entirely in vgic-mmio-v2.c. This register allows setting the source mask of an IPI. This is based on Linux commit ed40213ef9b0, written by Andre Przywara. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall --- xen/arch/arm/vgic/vgic-mmio-v2.c | 81 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/vgic/vgic-mmio-v2.c b/xen/arch/arm/vgic/vgic-mmio-v2.c index 9ef80608c1..32e0f6fc33 100644 --- a/xen/arch/arm/vgic/vgic-mmio-v2.c +++ b/xen/arch/arm/vgic/vgic-mmio-v2.c @@ -181,6 +181,83 @@ static void vgic_mmio_write_target(struct vcpu *vcpu, } } +static unsigned long vgic_mmio_read_sgipend(struct vcpu *vcpu, + paddr_t addr, unsigned int len) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 8); + uint32_t val = 0; + unsigned int i; + + ASSERT(intid < VGIC_NR_SGIS); + + for ( i = 0; i < len; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + val |= (uint32_t)irq->source << (i * 8); + + vgic_put_irq(vcpu->domain, irq); + } + + return val; +} + +static void vgic_mmio_write_sgipendc(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 8); + unsigned int i; + unsigned long flags; + + ASSERT(intid < VGIC_NR_SGIS); + + for ( i = 0; i < len; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + spin_lock_irqsave(&irq->irq_lock, flags); + + irq->source &= ~((val >> (i * 8)) & 0xff); + if ( !irq->source ) + irq->pending_latch = false; + + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(vcpu->domain, irq); + } +} + +static void vgic_mmio_write_sgipends(struct vcpu *vcpu, + paddr_t addr, unsigned int len, + unsigned long val) +{ + uint32_t intid = VGIC_ADDR_TO_INTID(addr, 8); + unsigned int i; + unsigned long flags; + + ASSERT(intid < VGIC_NR_SGIS); + + for ( i = 0; i < len; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(vcpu->domain, vcpu, intid + i); + + spin_lock_irqsave(&irq->irq_lock, flags); + + irq->source |= (val >> (i * 8)) & 0xff; + + if ( irq->source ) + { + irq->pending_latch = true; + vgic_queue_irq_unlock(vcpu->domain, irq, flags); + } + else + { + spin_unlock_irqrestore(&irq->irq_lock, flags); + } + vgic_put_irq(vcpu->domain, irq); + } +} + static const struct vgic_register_region vgic_v2_dist_registers[] = { REGISTER_DESC_WITH_LENGTH(GICD_CTLR, vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc, 12, @@ -219,10 +296,10 @@ static const struct vgic_register_region vgic_v2_dist_registers[] = { vgic_mmio_read_raz, vgic_mmio_write_sgir, 4, VGIC_ACCESS_32bit), REGISTER_DESC_WITH_LENGTH(GICD_CPENDSGIR, - vgic_mmio_read_raz, vgic_mmio_write_wi, 16, + vgic_mmio_read_sgipend, vgic_mmio_write_sgipendc, 16, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), REGISTER_DESC_WITH_LENGTH(GICD_SPENDSGIR, - vgic_mmio_read_raz, vgic_mmio_write_wi, 16, + vgic_mmio_read_sgipend, vgic_mmio_write_sgipends, 16, VGIC_ACCESS_32bit | VGIC_ACCESS_8bit), }; From patchwork Wed Mar 21 16:32:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132221 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356131ljb; Wed, 21 Mar 2018 09:35:04 -0700 (PDT) X-Google-Smtp-Source: AG47ELt6vE1YQHnscSJXnaMMoS148HlJlfJfKW1dwZv7GFcjd3c15PdReGX2SaOZS122w5fDEnSX X-Received: by 10.107.130.203 with SMTP id m72mr22409468ioi.250.1521650103927; Wed, 21 Mar 2018 09:35:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650103; cv=none; d=google.com; s=arc-20160816; b=suop5Q1bmnJsFbeNcaVEBbRHWOX4b5MkbVa5Hy5oNyU6V7XrxfnDIgywcMFJjII92r OQjCRrm2hQlvRkPGd+GTMTBIAYrV1ykqh9InjzIg/34BMdUBMPOcjZeqFmWjPaqGBq8R N6VfI4II0w2Ri3CDbpxKXOms4NiS/7OkpocQSS7hESDZ5vMDsYBqf2qEi3FgCjhcD2Sf /lzEfxc97LcmWTnOwCFiZhYT/k9Tgif8b4cHCc8wPoArECysCJIp2+fDHxa2L04tuosb xGaxSiQmnFcrxXma0QC6DAUTIziw/4phlT+gTEF8HhHGqim5QbPW9Unx9sioUnc/CC/N /I9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=s/PazONAQuNTOteSv1E6VVxFvHNIWnAzQutc2dzTo10=; b=IoP9DquOdRDR5b8oG7uEJ4TURwXNMrIcTL2LzpVnPNw9Mnz5OgqHGzuQyqVruzqb+m GtyxuPjSulHqgo18jGLQuf45HIbFM0Pd71RgaVufmgyXzXec1ra2zjjatIN4lOeTYiK1 9xxM6eUcJLXQQL1sgUKlN5LaHWvwGDbO5hT2hxQKfb4j5t6AGo/5ui/ixFOIpI0o4ph0 D7qAnpj6S1re8RYfdibn9y6dKTmGxIUUnOEtwj6yf6RqCeoB+zOup9TYuySOr7NdZ9A4 alJxXmh5wYvmBDUPHeNBH/NhDhTL1DRkIzuuMOj2P2iL4ab0sDgnsHAeyHJGzbJ6Ssid 1n5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=OuTYLMor; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:16 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:23 +0000 Message-Id: <20180321163235.12529-28-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 27/39] ARM: new VGIC: Handle hardware mapped IRQs X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The VGIC supports virtual IRQs to be connected to a hardware IRQ, so when a guest EOIs the virtual interrupt, it affects the state of that corresponding interrupt on the hardware side at the same time. Implement the interface that the Xen arch/core code expects to connect the virtual and the physical world. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall Acked-by: Stefano Stabellini --- xen/arch/arm/vgic/vgic.c | 71 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 90041eb071..07866d7243 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -699,6 +699,77 @@ void vgic_kick_vcpus(struct domain *d) } } +struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, + unsigned int virq) +{ + struct irq_desc *desc = NULL; + struct vgic_irq *irq = vgic_get_irq(d, v, virq); + unsigned long flags; + + if ( !irq ) + return NULL; + + spin_lock_irqsave(&irq->irq_lock, flags); + if ( irq->hw ) + { + ASSERT(irq->hwintid >= VGIC_NR_PRIVATE_IRQS); + desc = irq_to_desc(irq->hwintid); + } + spin_unlock_irqrestore(&irq->irq_lock, flags); + + vgic_put_irq(d, irq); + + return desc; +} + +/* + * was: + * int kvm_vgic_map_phys_irq(struct vcpu *vcpu, u32 virt_irq, u32 phys_irq) + * int kvm_vgic_unmap_phys_irq(struct vcpu *vcpu, unsigned int virt_irq) + */ +int vgic_connect_hw_irq(struct domain *d, struct vcpu *vcpu, + unsigned int virt_irq, struct irq_desc *desc, + bool connect) +{ + struct vgic_irq *irq = vgic_get_irq(d, vcpu, virt_irq); + unsigned long flags; + int ret = 0; + + if ( !irq ) + return -EINVAL; + + spin_lock_irqsave(&irq->irq_lock, flags); + + if ( connect ) /* assign a mapped IRQ */ + { + /* The VIRQ should not be already enabled by the guest */ + if ( !irq->hw && !irq->enabled ) + { + irq->hw = true; + irq->hwintid = desc->irq; + } + else + ret = -EBUSY; + } + else /* remove a mapped IRQ */ + { + if ( desc && irq->hwintid != desc->irq ) + { + ret = -EINVAL; + } + else + { + irq->hw = false; + irq->hwintid = 0; + } + } + + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(d, irq); + + return ret; +} + static unsigned int translate_irq_type(bool is_level) { return is_level ? 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:17 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:24 +0000 Message-Id: <20180321163235.12529-29-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 28/39] ARM: new VGIC: Add event channel IRQ handling X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The Xen core/arch code relies on two abstracted functions to inject an event channel IRQ and to query its pending state. Implement those to query the state of the new VGIC implementation. Signed-off-by: Andre Przywara Acked-by: Julien Grall Acked-by: Stefano Stabellini --- xen/arch/arm/vgic/vgic.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 07866d7243..3d818a98ad 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -699,6 +699,29 @@ void vgic_kick_vcpus(struct domain *d) } } +void arch_evtchn_inject(struct vcpu *v) +{ + vgic_inject_irq(v->domain, v, v->domain->arch.evtchn_irq, true); +} + +bool vgic_evtchn_irq_pending(struct vcpu *v) +{ + struct vgic_irq *irq; + unsigned long flags; + bool pending; + + /* Does not work for LPIs. */ + ASSERT(!is_lpi(v->domain->arch.evtchn_irq)); + + irq = vgic_get_irq(v->domain, v, v->domain->arch.evtchn_irq); + spin_lock_irqsave(&irq->irq_lock, flags); + pending = irq_is_pending(irq); + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(v->domain, irq); + + return pending; +} + struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, unsigned int virq) { From patchwork Wed Mar 21 16:32:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132216 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356047ljb; Wed, 21 Mar 2018 09:34:59 -0700 (PDT) X-Google-Smtp-Source: AG47ELsXAFDcDYyOrDG8Sb651pTN1+Ka4dXMIfwe2O53Cpx+rsJQYApSRCGE5rHXaKV7JO/ZLa0x X-Received: by 10.107.55.133 with SMTP id e127mr20504618ioa.138.1521650099087; Wed, 21 Mar 2018 09:34:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650099; cv=none; d=google.com; s=arc-20160816; b=cuOFQjqQb23jkorlhFBe9djorZQHfR7r33h+2HniMyikNxt/5kE7pyRF4gtWkxDOGf 5gdmUnmex0ZJb7N7I1YgKdjfehIPJxF747LWC0OuLIdV2k2AWidEMIonNHpBb+qdn6ZN AxIirfko9js+LHySJK5D7ScfJ31Caop0TBNLKmP0SbkeqqO7vvk8gYdWzvXRYgZypVT2 6HQCXYweKdRR6BxxRour0VttVXOo+Qy/S8x+fyLNSi/+cvJrc9+7/x7xYSOCxFlBXNIB 7JE8nSUhWMBAdQsIF7WQsxAnG0PYqUJVrkSDO2+AESOy+D41TOrcQMaja3AroH/ccBi4 wiZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=BZ3MWym13TGJpSokA0vMAWmr4yER79IKZ0c9N5ceyYY=; b=ts0vPGK56ChDCPd8VXiWAi3i3GbBQAOPnQ7cQbO6wBz0FNAeio5Ly/ziRJf1yRA1bC oAu2R0F5PINweZOft71WMgUFoFaDzB6b2ptLfSa2P9SRMSi6qNQBIM1bPjx/YoJU9w4Y rC+PFX1dRdzt0F7NYq2nJa+kaYmw8HIsSm6ZyL1gc723zdaOxNxyY3lI15ZY1PLLmDbf itBMQxkXqiRb7aeLd3q6eP4CMvEBez0kqg+DUPKZpEyTYbJpFbQRiv7y+gTRjjgcICuj UUecmmxtgR6fnBTe/mQ5K8zEs873T7gMzB9y2kXYz4mJMJKV3jDwrVRgyeAZytuNPhlY sdpA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=ia0MCwvZ; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:18 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:25 +0000 Message-Id: <20180321163235.12529-30-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 29/39] ARM: new VGIC: Handle virtual IRQ allocation/reservation X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" To find an unused virtual IRQ number Xen uses a scheme to track used virtual IRQs. Implement this interface in the new VGIC to make the Xen core/arch code happy. This is actually somewhat VGIC agnostic, so is mostly a copy of the code from the old VGIC. But it has to live in the VGIC files, so we can't easily reuse the existing implementation. Signed-off-by: Andre Przywara Acked-by: Julien Grall Acked-by: Stefano Stabellini --- xen/arch/arm/vgic/vgic.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 3d818a98ad..8aaad4bffa 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -722,6 +722,50 @@ bool vgic_evtchn_irq_pending(struct vcpu *v) return pending; } +bool vgic_reserve_virq(struct domain *d, unsigned int virq) +{ + if ( virq >= vgic_num_irqs(d) ) + return false; + + return !test_and_set_bit(virq, d->arch.vgic.allocated_irqs); +} + +int vgic_allocate_virq(struct domain *d, bool spi) +{ + int first, end; + unsigned int virq; + + if ( !spi ) + { + /* We only allocate PPIs. SGIs are all reserved */ + first = 16; + end = 32; + } + else + { + first = 32; + end = vgic_num_irqs(d); + } + + /* + * There is no spinlock to protect allocated_irqs, therefore + * test_and_set_bit may fail. If so retry it. + */ + do + { + virq = find_next_zero_bit(d->arch.vgic.allocated_irqs, end, first); + if ( virq >= end ) + return -1; + } while ( test_and_set_bit(virq, d->arch.vgic.allocated_irqs) ); + + return virq; +} + +void vgic_free_virq(struct domain *d, unsigned int virq) +{ + clear_bit(virq, d->arch.vgic.allocated_irqs); +} + struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, unsigned int virq) { From patchwork Wed Mar 21 16:32:26 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132224 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356170ljb; Wed, 21 Mar 2018 09:35:05 -0700 (PDT) X-Google-Smtp-Source: AG47ELuaisJqVZ/MZD6tcxD5rp9VvkUQqaJ+qKjoqcPaqZVFslyPIjx+WP3985g3Ovf2XLMHsHva X-Received: by 2002:a24:7a15:: with SMTP id a21-v6mr4962166itc.65.1521650105808; Wed, 21 Mar 2018 09:35:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650105; cv=none; d=google.com; s=arc-20160816; b=tDII7cG6k3te1qj6WaGM9H1mDf+zO8v0POUWEd1b8sU28RyaN1o4mqglafI3aUTIPa QcYiWP3Vit44Z/MwD3PG/9P023Ayg7yEArnuM0WR513WlLoYFM7Rm8cFtCHamuWu8yMi GKgZ19q1DSt4VTBs7UyUY+pMANDQWMNVLpigeViLl1byvDyvsAbJJRglTxZz6K+kiAQf in8sYppeuCZ2bnt689cK+BLAB5DgLdlHFnHgFblFLV4nnIBh/K1JHtb8PF6i3C1ty3l1 PwrcFqKAbM0Lu+5BkqLz+zFkjlLylgv87g8RDei4xqY+3SpgF+Ghy7uvbav8YzW5xc4X ST6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=S8i4dVo1+rB39YLx8kbPvt+oCcmiVbav1e+jmJz0sjM=; b=oAIwYcov6/kUDdNLgRv1XWq78S1axMPYmhfr89i40J1kYvOQ+JBCgXQDu0c3kND/YD OMFlMsxdbqeXOfJeYMRjFuflMVaICyKk9CGm0x4rcXqoD7pqhPzqYx7ouzRHEm4REqY4 Uf/Usv3uENA1dwe0+P66x5qVDfDetN8U6gMuizyX9dRlngo1BGjoc80C1I4mvUucmHBR /pQlDXLPiXBlNWUkqcxP2bzFGEE3xXcp3hwYVLfKTSH13cB0XfRAUXFfDzP4WcqWhASA 1+sZsPLia5SAwUq3PBMClYxNjZAggiDYWU4EKHGyRnLiWuOQjl5mU1li81mdMT88seUY nrOg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Bbr3plKV; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:19 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:26 +0000 Message-Id: <20180321163235.12529-31-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 30/39] ARM: new VGIC: Dump virtual IRQ info X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" When we dump guest state on the Xen console, we also print the state of IRQs that are on a VCPU. Add the code to dump the state of an IRQ handled by the new VGIC. Signed-off-by: Andre Przywara Acked-by: Julien Grall Acked-by: Stefano Stabellini --- xen/arch/arm/vgic/vgic.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 8aaad4bffa..79c6a5553d 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -766,6 +766,31 @@ void vgic_free_virq(struct domain *d, unsigned int virq) clear_bit(virq, d->arch.vgic.allocated_irqs); } +void gic_dump_vgic_info(struct vcpu *v) +{ + struct vgic_cpu *vgic_cpu = &v->arch.vgic; + struct vgic_irq *irq; + unsigned long flags; + + spin_lock_irqsave(&v->arch.vgic.ap_list_lock, flags); + + if ( !list_empty(&vgic_cpu->ap_list_head) ) + printk(" active or pending interrupts queued:\n"); + + list_for_each_entry ( irq, &vgic_cpu->ap_list_head, ap_list ) + { + spin_lock(&irq->irq_lock); + printk(" %s %s irq %u: %spending, %sactive, %senabled\n", + irq->hw ? "hardware" : "virtual", + irq->config == VGIC_CONFIG_LEVEL ? "level" : "edge", + irq->intid, irq_is_pending(irq) ? "" : "not ", + irq->active ? "" : "not ", irq->enabled ? "" : "not "); + spin_unlock(&irq->irq_lock); + } + + spin_unlock_irqrestore(&v->arch.vgic.ap_list_lock, flags); +} + struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, unsigned int virq) { From patchwork Wed Mar 21 16:32:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132231 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356305ljb; Wed, 21 Mar 2018 09:35:12 -0700 (PDT) X-Google-Smtp-Source: AG47ELv0n6ABlTRYHz3orNvQxH/Ethr4KXyvMnJ+RgxRpsp4QZ1vsgO8/3GFkEvF7FKBgan/CYKq X-Received: by 2002:a24:5a05:: with SMTP id v5-v6mr4959691ita.138.1521650112258; Wed, 21 Mar 2018 09:35:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650112; cv=none; d=google.com; s=arc-20160816; b=isrUJ0NA9rRxD715yaZyOwy0va1aIN5jj1wuKqnw+vDb/xDE9+W02ZEX2X4Bj+8LvA fH0rX695BbwyVQ1ctwdAOMiMl9CpXd9CtpfT85QhqYPKkoyedbc7EU6zh8CNKwT01Fby bMIPmoQRdWxaFXoZct9qsR0jGWm6NcPW0XiXgpcbAisDQJPRdDWB02LpcLFZuXq5zS2Z 7ukshP4YncoCNoEmFsVKS/2Co0AanZPsnRCurfvGpoL+qiuadCCPkthgDm0GTdN6YvxX n6+mfoJvg454zP+Dj+og6I14LJtCTc7FJSEy+US5ofZWhfuXgRA8n/T6FGJfSwhCL0DK OXEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=In4OGqJIN2XeKnct5FeIvbjPvaycaWel+xI5jwQOfrg=; b=O39QaDJtxLUqxPt+YqiuA+nAIjl6fv6wnjDX84iLFluQomel0XTtrLbKhiwLr2vfWq 64OocQlNSrWH+OHxrTyqnD1cCkq3m35lZRYWjO9G762aW4IvFomTj/U17dqwtJ2PvdmN rFFolX2qmQxeeisIS8hsnDHVb3FNj6Lx90Dt7aqYrjwSi0a8k3sHEY8LwgmRqcWCAPIG xGxwZxSoPCRt92VQqrPnlBDPUQWMQJT19E80lSna7zxOVwisS8yjtrzyQzJWs1WWjLi/ wiz9EoKtYw76JrBGy4RjolRH5dDT6tBT1ckYIgLrSS1uRZEVO/clBmxZianPeZ5yiVQ0 R4Pw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=h5mYZjxN; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:20 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:27 +0000 Message-Id: <20180321163235.12529-32-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 31/39] ARM: new VGIC: Provide system register emulation stub X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The Xen arch code traps system registers writes from the guest and will relay anything GIC related to the VGIC. Since this affects only GICv3 (which we don't yet emulate), provide a stub implementation of vgic_emulate() for now. Signed-off-by: Andre Przywara Acked-by: Julien Grall Acked-by: Stefano Stabellini --- xen/arch/arm/vgic/vgic.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 79c6a5553d..ffab0b2635 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -814,6 +814,13 @@ struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, return desc; } +bool vgic_emulate(struct cpu_user_regs *regs, union hsr hsr) +{ + ASSERT(current->domain->arch.vgic.version == GIC_V3); + + return false; +} + /* * was: * int kvm_vgic_map_phys_irq(struct vcpu *vcpu, u32 virt_irq, u32 phys_irq) From patchwork Wed Mar 21 16:32:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132233 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356318ljb; Wed, 21 Mar 2018 09:35:13 -0700 (PDT) X-Google-Smtp-Source: AG47ELtT3cfymvekL2j3Su0lO44zB9n8w24aGzp1CZ4ZM7eMYQPow9Nk1fJhr48alFUPhZwT8z2V X-Received: by 2002:a24:f685:: with SMTP id u127-v6mr4768738ith.131.1521650112873; Wed, 21 Mar 2018 09:35:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650112; cv=none; d=google.com; s=arc-20160816; b=vMt1buOT7PxilZM/oRE5IwiKZLyW6NaEoyDKnLR3yC4/n1n6cr/3zK2P7Aw+viq3W0 p99Kn1DuQbwjtxYDejGjp0nXzwmu3e1UvTWbQJ7Cxb5Jcbp1rPgD4cWX0uiTX5Kl5HPo aYHpww2z/BE24B4DSgIXfVPiJwfrzfauTkXKLuS6Rowka05Pk7naJCmZkYXJjhi/gCl5 NMX3IRU4VZwWqb8kCxQmOHEl+Flf/75OI8vgqbdbTeyCfWqcFAeMudeFW02rrQEkG33N HSEvjwOnGVZBznWii3lZirJ9igOCJ0u/ycMH/mzo8hlGG0b+FPSh+hLop2F1KSIfPoun ie3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=b990bRi//Dksbgx5VAJO3Go1zC9L/m/9BFvsZDDxCQI=; b=t6kxRX7i6LNM4Tb6pBMpgHM5uqCVETavnTUC6Rab81i+vmoOyzNNFGGzAJszZvVrg/ 2KppPHTL5b4nphNSXl51/9yNgtUYXty2Qjdr3MV6pGB+FvCOIgSsovq7M3dDBKAOX950 +1z8S58dqU/AGCjlKUi09q+swISz+OrjtaLCKda1l1+n8VlJxqXflpuR8yvP9762xaO0 +7ZAsVlIgkznIq/Dn4ojdrCSm46J0sVfSEHHb4TSpGuefKXjlFd6wPos3TNILk9NDxEJ iGFjPDxTBd4n3bj8Ysi3U/jJE0mZEa9cd2Uv6qlEhStvXPwPp18tG9EUmCv5ivsExPIV +qxw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=OU9KtMR3; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id v186-v6si3517338itf.66.2018.03.21.09.35.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 21 Mar 2018 09:35:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=OU9KtMR3; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1eygg5-00035y-Mt; Wed, 21 Mar 2018 16:33:29 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1eygg0-0002u5-WB for xen-devel@lists.xenproject.org; Wed, 21 Mar 2018 16:33:25 +0000 X-Inumbo-ID: 89b07d06-2d25-11e8-9728-bc764e045a96 Received: from mail-wr0-x241.google.com (unknown [2a00:1450:400c:c0c::241]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTPS id 89b07d06-2d25-11e8-9728-bc764e045a96; Wed, 21 Mar 2018 17:33:08 +0100 (CET) Received: by mail-wr0-x241.google.com with SMTP id s10so5825167wra.13 for ; Wed, 21 Mar 2018 09:33:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZpcWBgjhGo5s0B50sbO2oQv3At8FYHfyo+zJke4XiJM=; b=OU9KtMR3RAd234elh8928p9wq7U3ekbkw/MGVt935OAIw4k1BFCzRXpnMMdIXZrrJm WHL6U9pA3J3i1j0MIR6WRN2xtgBbrVSI8hnbnJKyrtgt0hpAtT0uVyvNyp93UWPuVvLj WcnqbRvB0Swgm8UzdR8erTK9NfixXbqVrgqyw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZpcWBgjhGo5s0B50sbO2oQv3At8FYHfyo+zJke4XiJM=; b=QfHei0JFgkvUyKomB3OPOUnoy2q8gBgsRi/IEz/OcDLqatU1Ph/5GmvYS54CacpR8G AOkGjiBo70HitLVMs9A2wNTPs7/y22cLWzvfhasovWo4fniPqHICewVPDQjCpLoJHo24 oQ94yQ2J9VQVYjUm42j2BqwtktI08xJrDmrMdWfWs6F9cYDfNs+OnSb5aF90hGRjWHqU WSVtUbGeBhfpyCzG+Cp8ElMg6tyacOa6wPUjOILDpQu+dDilpr3rhgm/G+pIs9xsjA0Z cXxSdZBp69aR9Bfvc8AismMBr+/1Q2w/KUJ+5DrEJ9z18pl8rjxHNXztBK3SkAA25DzC Hptw== X-Gm-Message-State: AElRT7Gqvw1A0nZ+wESk3vTzD87WTIhoFfDCPG0Ai6EQkAcz9+Be5Z+M gXX402kU73XM1dHfi4NueslDN0/rhQU= X-Received: by 10.223.186.75 with SMTP id t11mr9072806wrg.155.1521650002447; Wed, 21 Mar 2018 09:33:22 -0700 (PDT) Received: from e104803-lin.lan (mail.andrep.de. [217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:22 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:28 +0000 Message-Id: <20180321163235.12529-33-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 32/39] ARM: new VGIC: Implement arch_move_irqs() X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" When a VCPU moves to another CPU, we need to adjust the target affinity of any hardware mapped vIRQs, to observe our "physical-follows-virtual" policy. Implement arch_move_irqs() to adjust the physical affinity of all hardware mapped vIRQs targetting this VCPU. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall Acked-by: Stefano Stabellini --- xen/arch/arm/vgic/vgic.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index ffab0b2635..23b8abfc5e 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -791,6 +791,45 @@ void gic_dump_vgic_info(struct vcpu *v) spin_unlock_irqrestore(&v->arch.vgic.ap_list_lock, flags); } +/** + * arch_move_irqs() - migrate the physical affinity of hardware mapped vIRQs + * @v: the vCPU, already assigned to the new pCPU + * + * arch_move_irqs() updates the physical affinity of all virtual IRQs + * targetting this given vCPU. This only affects hardware mapped IRQs. The + * new pCPU to target is already set in v->processor. + * This is called by the core code after a vCPU has been migrated to a new + * physical CPU. + */ +void arch_move_irqs(struct vcpu *v) +{ + struct domain *d = v->domain; + unsigned int i; + + /* We only target SPIs with this function */ + for ( i = 0; i < d->arch.vgic.nr_spis; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(d, NULL, i + VGIC_NR_PRIVATE_IRQS); + unsigned long flags; + + if ( !irq ) + continue; + + spin_lock_irqsave(&irq->irq_lock, flags); + + /* only vIRQs that are not on a vCPU yet , but targetting this vCPU */ + if ( irq->hw && !irq->vcpu && irq->target_vcpu == v) + { + irq_desc_t *desc = irq_to_desc(irq->hwintid); + + irq_set_affinity(desc, cpumask_of(v->processor)); + } + + spin_unlock_irqrestore(&irq->irq_lock, flags); + vgic_put_irq(d, irq); + } +} + struct irq_desc *vgic_get_hw_irq_desc(struct domain *d, struct vcpu *v, unsigned int virq) { From patchwork Wed Mar 21 16:32:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132227 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356273ljb; Wed, 21 Mar 2018 09:35:10 -0700 (PDT) X-Google-Smtp-Source: AIpwx48Vqn9b11+CfQysrHJjldIQboJPjZGnHEAOs0V8k4npTTkQd3tYFStCvJOUInjCcewHTiJK X-Received: by 10.107.185.138 with SMTP id j132mr7154023iof.261.1521650110438; Wed, 21 Mar 2018 09:35:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650110; cv=none; d=google.com; s=arc-20160816; b=Z34SReCzCAGy6BmmJPJTC3SxOlWcsj3fvj5+QZeKev3zdiNYiRz05j9n3KAVIYDXoc L5V5+c9P15p+M4DqCIVw2Ip22nSOw6msE/WRRsXyux6u6DZ36FBe6O42vqd6gjohBrIR qrjDN1xuohuynpuK7aXIOh5qA2yl6BvgCFNecgfDpp5zkxQwqWMMb4ioKyl2r+B6FNLa mfPxlVFLEmXQvYxoAfo6rEuSXX3TKRfKxVVXnRMm/HOoKb4uZ05eqciqoMjBFPwYUXi9 ql8uSLZeV6zGUKxLtSq7HmO1GrMvqHZ4GllqhbA7Kwzy7jreehf6IPAm981k+DituPJ8 nTog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=qJpT2lP3Y5+rob0U5qeuGy0behUwigocz9gKFfEp9t0=; b=r/sT1wJ27kB0KaT+cBlk45vZ5G/aVB7CO/MRaq1dBxGjiZgGKDc1/HE6TMNpBPrWfH LXAT9/JG7g9o2V3lsw4pxmQr/YiccKCQ6aNP6cCNyukeu3aYb4IA32u54ns4LJ+NvZl1 AwhaxPN65jxSbU/nHTrGWs6IfyZxXAo/zMe3oHezsl8j3bXyDtokITZohaBjvrTrqCXn 9O8C9p69UgQR+fZpmc4eOMBDFUhaAjVWIjde5w/xpxbfdYdxTl0DjLxtTcvChm4GWLtF yXhAffzcbL7IFeLRUOCPLO9j4JutPYRxtwVEtchP/XNUVSeXJjCbKYYAVow5A/27wqkw aYDQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=KrmZG6Oc; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:22 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:29 +0000 Message-Id: <20180321163235.12529-34-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 33/39] ARM: new VGIC: Add preliminary stub implementation X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" The ARM arch code requires an interrupt controller emulation to implement vgic_clear_pending_irqs(), although it is suspected that it is actually not necessary. Go with a stub for now to make the linker happy. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall --- xen/arch/arm/vgic/vgic.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 23b8abfc5e..b70fdaaecb 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -791,6 +791,14 @@ void gic_dump_vgic_info(struct vcpu *v) spin_unlock_irqrestore(&v->arch.vgic.ap_list_lock, flags); } +void vgic_clear_pending_irqs(struct vcpu *v) +{ + /* + * TODO: It is unclear whether we really need this, so we might instead + * remove it on the caller site. + */ +} + /** * arch_move_irqs() - migrate the physical affinity of hardware mapped vIRQs * @v: the vCPU, already assigned to the new pCPU From patchwork Wed Mar 21 16:32:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132235 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356384ljb; Wed, 21 Mar 2018 09:35:15 -0700 (PDT) X-Google-Smtp-Source: AG47ELtZK/WV5TN87NTvnLf+kGn/PRBxpy+YDNjNjrYsIFlK4CdQOhF5ZIjwTayIeVBxubObL80k X-Received: by 10.107.142.2 with SMTP id q2mr21506571iod.21.1521650115202; Wed, 21 Mar 2018 09:35:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650115; cv=none; d=google.com; s=arc-20160816; b=E9tfIOVtmbyEJ9nVQfXVthFh3V25wY5BYpWZZjappbaxLQQKLs9C6SrLDr2ODkV4Gz qOwT/WeRqjamhM0Iaa4HKaDrRJVbkAej2wGvNAO8HZHthx5vYx6IB7UiQf/1Zh8enkjV FEPONP2Htp8wrlDOdrhQkSlcW4VqSKgJvcXWdTYSuZoIfXyitye/q6J0VxeavCKEy84W FwMGE1t9W9oX7uGKHVcUwwxlKhzkOLPh4prgUWTrqfq/+DJMnddC+IqDQ+jASRUk+I7x GN9/klxM8gPJsblj72bV0YfwGDjHF0Y9KldG32JLMZ0LpVsDH2oL7reONWDrAZQI+Gy8 vMiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=TWHiiMK0Z/QSaiNUP215EIU4CenmR+ngD82EuZT1Was=; b=x+KUtsQdUmKVNOyGv0tVL3mXkhkgKZRAc/EXgpIAoZ2iijFqSjKEuexBteSV8uMMoh GSpahYwxqBaojjNXU9YMaclKpM2oE9cHpLBdteV4vqe8AWMIHo6CiqvM1G8UdEThhJCp OlD0vpOgVLe8ClEb6JtTWcVUrzk33IBmgoLhNVQV5BqPEQw+dVfiD9EZ+qEsypk2A83e u4HzT7xn/5h14neU9XlqQiiiJcG6uvU8NX5XBY9mOnlkjpRm/No4p5ePAPktWf+uJti4 DQJN4huBX6hIEYCqHzMvp4HrKRjoVSv7iZia++FKkwDZCJl9jvwNhDFGTJCo49sPhEsG v6EQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=E3shqwqp; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:24 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:30 +0000 Message-Id: <20180321163235.12529-35-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 34/39] ARM: new VGIC: vgic-init: register VGIC X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" This patch implements the function which is called by Xen when it wants to register the virtual GIC. This also implements vgic_max_vcpus() for the new VGIC, which reports back the maximum number of VCPUs a certain GIC model supports. Similar to the counterpart in the "old" VGIC, we return some maximum value if the VGIC has not been initialised yet. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall Acked-by: Stefano Stabellini --- Changelog v2 ... v3: - drop premature #ifdef CONFIG_HAS_GICV3 - use new GIC_INVALID to detect uninitialised VGIC xen/arch/arm/vgic/vgic-init.c | 60 +++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic.c | 25 ++++++++++++++++++ xen/arch/arm/vgic/vgic.h | 3 +++ 3 files changed, 88 insertions(+) create mode 100644 xen/arch/arm/vgic/vgic-init.c diff --git a/xen/arch/arm/vgic/vgic-init.c b/xen/arch/arm/vgic/vgic-init.c new file mode 100644 index 0000000000..d091c92ed0 --- /dev/null +++ b/xen/arch/arm/vgic/vgic-init.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2015, 2016 ARM Ltd. + * Imported from Linux ("new" KVM VGIC) and heavily adapted to Xen. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include + +#include "vgic.h" + +/* CREATION */ + +/** + * domain_vgic_register: create a virtual GIC + * @d: domain pointer + * @mmio_count: pointer to add number of required MMIO regions + * + * was: kvm_vgic_create + */ +int domain_vgic_register(struct domain *d, int *mmio_count) +{ + switch ( d->arch.vgic.version ) + { + case GIC_V2: + *mmio_count = 1; + break; + default: + BUG(); + } + + if ( d->max_vcpus > domain_max_vcpus(d) ) + return -E2BIG; + + d->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF; + d->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF; + d->arch.vgic.vgic_redist_base = VGIC_ADDR_UNDEF; + + return 0; +} + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index b70fdaaecb..131358a5a1 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -956,6 +956,31 @@ void vgic_sync_hardware_irq(struct domain *d, spin_unlock_irqrestore(&desc->lock, flags); } +unsigned int vgic_max_vcpus(const struct domain *d) +{ + unsigned int vgic_vcpu_limit; + + switch ( d->arch.vgic.version ) + { + case GIC_INVALID: + /* + * Since evtchn_init would call domain_max_vcpus for poll_mask + * allocation before the VGIC has been initialised, we need to + * return some safe value in this case. As this is for allocation + * purposes, go with the maximum value. + */ + vgic_vcpu_limit = MAX_VIRT_CPUS; + break; + case GIC_V2: + vgic_vcpu_limit = VGIC_V2_MAX_CPUS; + break; + default: + BUG(); + } + + return min_t(unsigned int, MAX_VIRT_CPUS, vgic_vcpu_limit); +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index c7eeaf7a38..a3fcd4d965 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -25,6 +25,9 @@ #define VARIANT_ID_XEN 0x01 #define IMPLEMENTER_ARM 0x43b +#define VGIC_ADDR_UNDEF INVALID_PADDR +#define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF) + #define VGIC_PRI_BITS 5 #define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS) From patchwork Wed Mar 21 16:32:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132237 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356159ljb; Wed, 21 Mar 2018 09:35:05 -0700 (PDT) X-Google-Smtp-Source: AG47ELsNxRgzb7BZ3HC84WCCES12Y7pJlDa7tCWyWZiKGs7AkLbUkvcRAbamWYzpKI/6EjPYT+hA X-Received: by 10.107.131.207 with SMTP id n76mr19191288ioi.158.1521650105340; Wed, 21 Mar 2018 09:35:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650105; cv=none; d=google.com; s=arc-20160816; b=jHQHRBEinGoPJObIt2Uaz7AhTnzX5aBc7nUavRKmqToNKXvIjiGixH8qsWSubSqYAx kn5/kKuixjQtcn3dlb0lYILgBvOFcth6inGIPNDUoEy8zEbBg4fc6Ftro9vGKbFsy3GH yfGkWKTRZIoG3CEhEYtutNkXdHWtBoiz2MFI+5lbwHSJfazr65Nh5BbSx6qHPmhStlmh VFQKbti6U/nYV5DNuQwZJraT4JWWSP6mTti/RSd5JIpg/KFkRRGYQhP3lxsdlEyWN+TQ 6C3f9Mtej/pmNi05s1kxCQFh3E6JWQfCRp4ntwdt/yZnT/4MadTfJvYCywNrvkG68g// jTcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=SCbVCH2vy6ViLDJwNoC9jFLKDVBusaefQ6KHvS5Xo7U=; b=cMG6GpTY+HBPFC5qcFNCfjCCDBmSkZe70eDRdGfwwJQFhB4pAxR7of4/hNIAu7C/ln OKN3/c0BwYwq843tAAdk1oUhrJ3cF3tk+ZIWmXIN8DJt1QKM3AaoUnsP38gU2psU0pj7 H3ebKEMJgkSVI3pl/adw6GdUu7TYJAUpdNIbbaF19TLeIPeXii8qDDPwkpie59CJbqxd ihLLDE453mUgRXJB2Hs9EYgOa6S4EGNxlHz1lVpzguDvST3FlaZBHh9PzMNdk0TnWjbW 6uNyEb7m7TGVDTXzm1S84s15nss+O2Hc6p0KgNVAUhfsa/b9icWddtIjk43vIvR6cXeW fihQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=SSMkeC1o; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:25 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:31 +0000 Message-Id: <20180321163235.12529-36-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 35/39] ARM: new VGIC: Add vgic_v2_enable X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Enable the VGIC operation by properly initialising the registers in the hypervisor GIC interface. This is based on Linux commit f7b6985cc3d0, written by Eric Auger. Signed-off-by: Andre Przywara Acked-by: Julien Grall Acked-by: Stefano Stabellini --- Changelog v2 ... v3: - replace "1" with "true" in boolean parameter Changelog v1 ... v2: - move patch from later part in the series xen/arch/arm/vgic/vgic-v2.c | 6 ++++++ xen/arch/arm/vgic/vgic.h | 1 + 2 files changed, 7 insertions(+) diff --git a/xen/arch/arm/vgic/vgic-v2.c b/xen/arch/arm/vgic/vgic-v2.c index 8ab0cfe81d..ce77e58857 100644 --- a/xen/arch/arm/vgic/vgic-v2.c +++ b/xen/arch/arm/vgic/vgic-v2.c @@ -229,6 +229,12 @@ void vgic_v2_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr) gic_hw_ops->write_lr(lr, &lr_val); } +void vgic_v2_enable(struct vcpu *vcpu) +{ + /* Get the show on the road... */ + gic_hw_ops->update_hcr_status(GICH_HCR_EN, true); +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index a3fcd4d965..112952fbf9 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -66,6 +66,7 @@ void vgic_sync_hardware_irq(struct domain *d, void vgic_v2_fold_lr_state(struct vcpu *vcpu); void vgic_v2_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr); void vgic_v2_set_underflow(struct vcpu *vcpu); +void vgic_v2_enable(struct vcpu *vcpu); int vgic_register_dist_iodev(struct domain *d, gfn_t dist_base_fn, enum vgic_type); From patchwork Wed Mar 21 16:32:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132239 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356522ljb; Wed, 21 Mar 2018 09:35:23 -0700 (PDT) X-Google-Smtp-Source: AG47ELvoKo/bUQbgBifctxHsjzRq7CqIMjIamgjPiw2UYzC9JX5Of9QUO4MHUo2ea9X+Mo0n73NZ X-Received: by 10.107.130.203 with SMTP id m72mr22410990ioi.250.1521650123536; Wed, 21 Mar 2018 09:35:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650123; cv=none; d=google.com; s=arc-20160816; b=Hlazc78NjFUYqVIQBMKwkBbUdowrFQYAS5kMx6S1NRfLwo4lRZ98e+kK5NodiQ6/3k Tlm3VrfaUCrSmTzkXPsYxYcRCBwvtU1KkBRSUDlzMwjkjUHlxZEUtqOZi+saWRnhyimi jAjGJ/mH1VQEjmNtTJce4I0EHFVBUvpY5YlaUy/2SzZ9T8ohPO5+OD1HHxv+CB2YaiGj a7qoE7nZl4O8BMGKYgtQEI3D3U5nj5lUYvdesdSkwZsBubTbGcaXhit6g7Iv1hfWV5JW bWKHS6DgMx2fbVpA/egOmvdNwjqEsgKkFuJFb2/5hCGfL4J6+eXRKQCui051KR3TpeVl 2hHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=RFeWwYHnQZObvyrYbxCaUVohyyRN4449yreGlE5dSPA=; b=qO7EHHytP0AcbqwkZ1NLpHUf0Gw6RQpLSZpcm2t6agHeY6nUk0HKoK5CNncGbU0Ktj jyOK3xM/WOXgUatDAHT9JiILZpYAI7h4nMfP9feJ0EmCe+rQXC/KSXOyUP7VFFDmNkGb lRrlIg6rQo5L8hFzFigygudmy1UZNJU/yV5msRb2lQvQ9vlnuqeX6SGGu+BI6ucNES0V T/SytFbtAZKO6hY0qGiDGHhqL/j1OlsigPzcL16PX+4iVkMX+3zsE2iWy1IOGOq0FCqI zGy1jrklpRjWoUQXOPaLzivTRTNjrN7B57nKlYr37GEBWZvJL2INlM1D5TWNpATdB2+F Pl7Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Dvya1XSS; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:26 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:32 +0000 Message-Id: <20180321163235.12529-37-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 36/39] ARM: new VGIC: vgic-init: implement vgic_init X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" This patch allocates and initializes the data structures used to model the vgic distributor and virtual cpu interfaces. At that stage the number of IRQs and number of virtual CPUs is frozen. Implement the various functions that the Xen arch code is expecting to call during domain and VCPU setup to initialize the VGIC. Their prototypes are already in existing header files. This is based on Linux commit ad275b8bb1e6, written by Eric Auger. Signed-off-by: Andre Przywara Reviewed-by: Julien Grall Acked-by: Stefano Stabellini --- Changelog v2 ... v3: - move ROUNDUP(nr_spis) call before boundary check Changelog v1 ... v2: - remove stray kvm_ prefix in comment - use unsigned int - ROUNDUP number of SPIs - fix indentation xen/arch/arm/vgic/vgic-init.c | 201 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 201 insertions(+) diff --git a/xen/arch/arm/vgic/vgic-init.c b/xen/arch/arm/vgic/vgic-init.c index d091c92ed0..bfd3d09edb 100644 --- a/xen/arch/arm/vgic/vgic-init.c +++ b/xen/arch/arm/vgic/vgic-init.c @@ -15,11 +15,83 @@ * along with this program. If not, see . */ +#include #include #include #include "vgic.h" +/* + * Initialization rules: there are multiple stages to the vgic + * initialization, both for the distributor and the CPU interfaces. The basic + * idea is that even though the VGIC is not functional or not requested from + * user space, the critical path of the run loop can still call VGIC functions + * that just won't do anything, without them having to check additional + * initialization flags to ensure they don't look at uninitialized data + * structures. + * + * Distributor: + * + * - vgic_early_init(): initialization of static data that doesn't + * depend on any sizing information or emulation type. No allocation + * is allowed there. + * + * - vgic_init(): allocation and initialization of the generic data + * structures that depend on sizing information (number of CPUs, + * number of interrupts). Also initializes the vcpu specific data + * structures. Can be executed lazily for GICv2. + * + * CPU Interface: + * + * - vgic_vcpu_early_init(): initialization of static data that + * doesn't depend on any sizing information or emulation type. No + * allocation is allowed there. + */ + +/** + * vgic_vcpu_early_init() - Initialize static VGIC VCPU data structures + * @vcpu: The VCPU whose VGIC data structures whould be initialized + * + * Only do initialization, but do not actually enable the VGIC CPU interface + * yet. + */ +static void vgic_vcpu_early_init(struct vcpu *vcpu) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic; + unsigned int i; + + INIT_LIST_HEAD(&vgic_cpu->ap_list_head); + spin_lock_init(&vgic_cpu->ap_list_lock); + + /* + * Enable and configure all SGIs to be edge-triggered and + * configure all PPIs as level-triggered. + */ + for ( i = 0; i < VGIC_NR_PRIVATE_IRQS; i++ ) + { + struct vgic_irq *irq = &vgic_cpu->private_irqs[i]; + + INIT_LIST_HEAD(&irq->ap_list); + spin_lock_init(&irq->irq_lock); + irq->intid = i; + irq->vcpu = NULL; + irq->target_vcpu = vcpu; + irq->targets = 1U << vcpu->vcpu_id; + atomic_set(&irq->refcount, 0); + if ( vgic_irq_is_sgi(i) ) + { + /* SGIs */ + irq->enabled = 1; + irq->config = VGIC_CONFIG_EDGE; + } + else + { + /* PPIs */ + irq->config = VGIC_CONFIG_LEVEL; + } + } +} + /* CREATION */ /** @@ -50,6 +122,135 @@ int domain_vgic_register(struct domain *d, int *mmio_count) return 0; } +/* INIT/DESTROY */ + +/** + * domain_vgic_init: initialize the dist data structures + * @d: domain pointer + * @nr_spis: number of SPIs + */ +int domain_vgic_init(struct domain *d, unsigned int nr_spis) +{ + struct vgic_dist *dist = &d->arch.vgic; + unsigned int i; + int ret; + + /* The number of SPIs must be a multiple of 32 per the GIC spec. */ + nr_spis = ROUNDUP(nr_spis, 32); + + /* Limit the number of virtual SPIs supported to (1020 - 32) = 988 */ + if ( nr_spis > (1020 - NR_LOCAL_IRQS) ) + return -EINVAL; + + dist->nr_spis = nr_spis; + dist->spis = xzalloc_array(struct vgic_irq, nr_spis); + if ( !dist->spis ) + return -ENOMEM; + + /* + * In the following code we do not take the irq struct lock since + * no other action on irq structs can happen while the VGIC is + * not initialized yet: + * If someone wants to inject an interrupt or does a MMIO access, we + * require prior initialization in case of a virtual GICv3 or trigger + * initialization when using a virtual GICv2. + */ + for ( i = 0; i < nr_spis; i++ ) + { + struct vgic_irq *irq = &dist->spis[i]; + + irq->intid = i + VGIC_NR_PRIVATE_IRQS; + INIT_LIST_HEAD(&irq->ap_list); + spin_lock_init(&irq->irq_lock); + irq->vcpu = NULL; + irq->target_vcpu = NULL; + atomic_set(&irq->refcount, 0); + if ( dist->version == GIC_V2 ) + irq->targets = 0; + else + irq->mpidr = 0; + } + + INIT_LIST_HEAD(&dist->lpi_list_head); + spin_lock_init(&dist->lpi_list_lock); + + if ( dist->version == GIC_V2 ) + ret = vgic_v2_map_resources(d); + else + ret = -ENXIO; + + if ( ret ) + return ret; + + /* allocated_irqs() is used by Xen to find available vIRQs */ + d->arch.vgic.allocated_irqs = + xzalloc_array(unsigned long, BITS_TO_LONGS(vgic_num_irqs(d))); + if ( !d->arch.vgic.allocated_irqs ) + return -ENOMEM; + + /* vIRQ0-15 (SGIs) are reserved */ + for ( i = 0; i < NR_GIC_SGI; i++ ) + set_bit(i, d->arch.vgic.allocated_irqs); + + return 0; +} + +/** + * vcpu_vgic_init() - Register VCPU-specific KVM iodevs + * was: kvm_vgic_vcpu_init() + * Xen: adding vgic_vx_enable() call + * @vcpu: pointer to the VCPU being created and initialized + */ +int vcpu_vgic_init(struct vcpu *vcpu) +{ + int ret = 0; + + vgic_vcpu_early_init(vcpu); + + if ( gic_hw_version() == GIC_V2 ) + vgic_v2_enable(vcpu); + else + ret = -ENXIO; + + return ret; +} + +void domain_vgic_free(struct domain *d) +{ + struct vgic_dist *dist = &d->arch.vgic; + int i, ret; + + for ( i = 0; i < dist->nr_spis; i++ ) + { + struct vgic_irq *irq = vgic_get_irq(d, NULL, 32 + i); + + if ( !irq->hw ) + continue; + + ret = release_guest_irq(d, irq->hwintid); + if ( ret ) + dprintk(XENLOG_G_WARNING, + "d%u: Failed to release virq %u ret = %d\n", + d->domain_id, 32 + i, ret); + } + + dist->ready = false; + dist->initialized = false; + + xfree(dist->spis); + xfree(dist->allocated_irqs); + dist->nr_spis = 0; +} + +int vcpu_vgic_free(struct vcpu *vcpu) +{ + struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic; + + INIT_LIST_HEAD(&vgic_cpu->ap_list_head); + + return 0; +} + /* * Local variables: * mode: C From patchwork Wed Mar 21 16:32:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132232 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356309ljb; 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:27 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:33 +0000 Message-Id: <20180321163235.12529-38-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 37/39] ARM: new VGIC: vgic-init: implement map_resources X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" map_resources is the last initialization step needed before the first VCPU is run. At that stage the code stores the MMIO base addresses used. Also it registers the respective register frames with the MMIO framework. This is based on Linux commit cbae53e663ea, written by Eric Auger. Signed-off-by: Andre Przywara Acked-by: Julien Grall Acked-by: Stefano Stabellini --- xen/arch/arm/vgic/vgic-v2.c | 66 +++++++++++++++++++++++++++++++++++++++++++++ xen/arch/arm/vgic/vgic.h | 1 + 2 files changed, 67 insertions(+) diff --git a/xen/arch/arm/vgic/vgic-v2.c b/xen/arch/arm/vgic/vgic-v2.c index ce77e58857..5516a8534f 100644 --- a/xen/arch/arm/vgic/vgic-v2.c +++ b/xen/arch/arm/vgic/vgic-v2.c @@ -235,6 +235,72 @@ void vgic_v2_enable(struct vcpu *vcpu) gic_hw_ops->update_hcr_status(GICH_HCR_EN, true); } +int vgic_v2_map_resources(struct domain *d) +{ + struct vgic_dist *dist = &d->arch.vgic; + paddr_t cbase, csize; + paddr_t vbase; + int ret; + + /* + * The hardware domain gets the hardware address. + * Guests get the virtual platform layout. + */ + if ( is_hardware_domain(d) ) + { + d->arch.vgic.vgic_dist_base = gic_v2_hw_data.dbase; + /* + * For the hardware domain, we always map the whole HW CPU + * interface region in order to match the device tree (the "reg" + * properties is copied as it is). + * Note that we assume the size of the CPU interface is always + * aligned to PAGE_SIZE. + */ + cbase = gic_v2_hw_data.cbase; /* was: dist->vgic_cpu_base */ + csize = gic_v2_hw_data.csize; + vbase = gic_v2_hw_data.vbase; /* was: kvm_vgic_global_state.vcpu_base */ + } + else + { + d->arch.vgic.vgic_dist_base = GUEST_GICD_BASE; + /* + * The CPU interface exposed to the guest is always 8kB. We may + * need to add an offset to the virtual CPU interface base + * address when in the GIC is aliased to get a 8kB contiguous + * region. + */ + BUILD_BUG_ON(GUEST_GICC_SIZE != SZ_8K); + cbase = GUEST_GICC_BASE; + csize = GUEST_GICC_SIZE; + vbase = gic_v2_hw_data.vbase + gic_v2_hw_data.aliased_offset; + } + + + ret = vgic_register_dist_iodev(d, gaddr_to_gfn(dist->vgic_dist_base), + VGIC_V2); + if ( ret ) + { + gdprintk(XENLOG_ERR, "Unable to register VGIC MMIO regions\n"); + return ret; + } + + /* + * Map the gic virtual cpu interface in the gic cpu interface + * region of the guest. + */ + ret = map_mmio_regions(d, gaddr_to_gfn(cbase), csize / PAGE_SIZE, + maddr_to_mfn(vbase)); + if ( ret ) + { + gdprintk(XENLOG_ERR, "Unable to remap VGIC CPU to VCPU\n"); + return ret; + } + + dist->ready = true; + + return 0; +} + /* * Local variables: * mode: C diff --git a/xen/arch/arm/vgic/vgic.h b/xen/arch/arm/vgic/vgic.h index 112952fbf9..e8e407adbe 100644 --- a/xen/arch/arm/vgic/vgic.h +++ b/xen/arch/arm/vgic/vgic.h @@ -67,6 +67,7 @@ void vgic_v2_fold_lr_state(struct vcpu *vcpu); void vgic_v2_populate_lr(struct vcpu *vcpu, struct vgic_irq *irq, int lr); void vgic_v2_set_underflow(struct vcpu *vcpu); void vgic_v2_enable(struct vcpu *vcpu); +int vgic_v2_map_resources(struct domain *d); int vgic_register_dist_iodev(struct domain *d, gfn_t dist_base_fn, enum vgic_type); From patchwork Wed Mar 21 16:32:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132242 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356815ljb; Wed, 21 Mar 2018 09:35:42 -0700 (PDT) X-Google-Smtp-Source: AG47ELsRXx483iB66qPsLm341hzfgcfTr8mFalqJF7JRYQ6XxHJ5gBmjnFsZqSNq3QAuCkHIAisC X-Received: by 10.107.39.138 with SMTP id n132mr22056199ion.91.1521650142540; Wed, 21 Mar 2018 09:35:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650142; cv=none; d=google.com; s=arc-20160816; b=Lr0V1AQ+rf1WM9gtTkyqHShpCCfDWvPkcV2lc7QOn3PnY3/J8sBbp+f8bFdP0IWmYC YZve3ZV/O9CVb+7c8kpcs22zc2Khn5TctdcfcLIfINn46EwbKKQhULuoFCWSxCU2ZpK2 f18O0bqwmilRYqW2Jbnz/uka4NVwt2BGfVELfbhqdmzcVDrzF2blj8lDQuUq8yUnjQxi 28C2+qpUUzr/pvUJroqEfC71SSnBUViJntbx72Z+c/r0cPS3sytsbrPAe+YbnoyZT1LE ztqPZH55n5h/MJIfXH12RkRr5zwnMIpTdboqsb3TXQvYjLKbuqC1WacEI8W72VOSArP3 neVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=hWo9gwfqNsLrg6UarDMQ2ofFvno/gyB8sahrtnb2nKI=; b=rlDTQH2CoDXtvOee9j635ZmRc54+LoHFuz97akiIRsIyqeE6efzniF69NK3P9qHq7Y KH0j3iGqmtwhKtMHgJxvKOvSWwDovvalzYufM/vaAheCJ/GYHN91b7ZnUknj+PTsS8KJ b5EcIXA61xda4w38CV09BYHcoL9VEQ02GhYqYzCDsQD3AwV7+4S6ezhalS7La6GsCTEd E32uzWVTb6d/CiHLP3uklCKOE0TXMvzplTPYIv5+KBprp9z3Z47Etbns3ocZo3kEi3tU qIyVsHzLpcqwGVXwY6cYkHMdvHfkITp2+ZcnX78EPrZIs2i0rxGKsKwCl970sVLtQaGF UgSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=E45f2pVu; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:28 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:34 +0000 Message-Id: <20180321163235.12529-39-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 38/39] ARM: new VGIC: Allocate two pages for struct vcpu X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: xen-devel@lists.xenproject.org, Andre Przywara MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" At the moment we allocate exactly one page for struct vcpu on ARM, also have a check in place to prevent it growing beyond 4KB. As the struct includes the state of all 32 private (per-VCPU) interrupts, we are at 3840 bytes on arm64 at the moment already. Growing the per-IRQ VGIC structure even slightly makes the VCPU quickly exceed the 4K limit. The new VGIC will need more space per virtual IRQ. I spent a few hours trying to trim this down, but couldn't get it below 4KB, even with the nasty hacks piling up to save some bytes here and there. It turns out that beyond efficiency, maybe, there is no real technical reason this struct has to fit in one page, so lifting the limit to two pages seems like the most pragmatic solution. Restrict this to compiling with the new VGIC and for ARM64 only. Signed-off-by: Andre Przywara Acked-by: Julien Grall Acked-by: Stefano Stabellini --- Changelog v2 ... v3: - rework alloc_vcpu_struct() to avoid nasty #ifdef Changelog v1 ... v2: - confine change to new VGIC and ARM64 only xen/arch/arm/domain.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 9688e62f78..23bda3f7db 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -505,19 +505,36 @@ void dump_pageframe_info(struct domain *d) } +/* + * The new VGIC has a bigger per-IRQ structure, so we need more than one + * page on ARM64. Cowardly increase the limit in this case. + */ +#if defined(CONFIG_NEW_VGIC) && defined(CONFIG_ARM_64) +#define PAGES_PER_VCPU 2 +#else +#define PAGES_PER_VCPU 1 +#endif + struct vcpu *alloc_vcpu_struct(void) { struct vcpu *v; - BUILD_BUG_ON(sizeof(*v) > PAGE_SIZE); - v = alloc_xenheap_pages(0, 0); + + BUILD_BUG_ON(sizeof(*v) > PAGES_PER_VCPU * PAGE_SIZE); + v = alloc_xenheap_pages(get_order_from_pages(PAGES_PER_VCPU), 0); if ( v != NULL ) - clear_page(v); + { + unsigned int i; + + for ( i = 0; i < PAGES_PER_VCPU; i++ ) + clear_page((void *)v + i * PAGE_SIZE); + } + return v; } void free_vcpu_struct(struct vcpu *v) { - free_xenheap_page(v); + free_xenheap_pages(v, get_order_from_pages(PAGES_PER_VCPU)); } int vcpu_initialise(struct vcpu *v) From patchwork Wed Mar 21 16:32:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andre Przywara X-Patchwork-Id: 132229 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2356295ljb; Wed, 21 Mar 2018 09:35:11 -0700 (PDT) X-Google-Smtp-Source: AG47ELtpBS+g0yFpEz2zZLUbsNR3q7Nd1bhFKu7XCF9mcscXr1zhGG3ik5ALpnM1MqT8uc89FKU8 X-Received: by 2002:a24:441:: with SMTP id 62-v6mr4852906itb.57.1521650111620; Wed, 21 Mar 2018 09:35:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1521650111; cv=none; d=google.com; s=arc-20160816; b=rjMU6YnNHbICgLV+LLkxNmokkYsmBG8VkVOANkzBpX4Fj3Wn48idALzkU6agDpN6E9 uyOYcxJdJYiFOcGaeN+Hvwbtb7xQjWayrKzdIJ38s7C1QL9H7VZCJIo8xSmLjTYcKmDC 9nYvvHTT2xkqTC4mpMElr279ZYTTGbAwMRtTxcBmyn9IvDSvgFYQmwW0B6wcCCToiAEK VdDKL6+9CHcxe9OhOaECYTHEbcv6rjL+kPMPYsNSBqyC1uEb3IrRM6OYz7jwykQAzVLN oHcMvXK//zXZ/DzVLjNV8i3+15rmvPju0apWUPDUSSeFd+htsUc77lXlMIt5CKg90ttT aVKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=NS/uRFAfMk+JwNP4lEw3+YThTEm3N5Ht2r53QEkl/Lw=; b=tQ5IH0Bo19IC6XKUz0jyCLaR3EGAMxBTxzxPEwQeRwzK3qe8FDAdVrE1mFYrX7QVmS a2KR+XtOG9RcXf3sDLGvz5hPrzN7+3J0NXgHxi6NShgcxRDeR+oWyRAwJzZz/EgLxfwb NgOnBcBnVgwtqLPU+MRCcd9RGBTsZ6Sp5HZfJfQUCPgSBtWi34YaexEccn21Gu9XSA8F xVlbE66UqBhg6f4poMy4FVHTnA2GIB3/D9KXH+i/tifrjXdl51ym/PKbQBubdwEtZuTa jZTDtHs2MCzGROYLw1nQ9Vm99R05gTQhNrsZ3mKWQBhvRy0Nbap8dNwYA92U4paDOhMa zBRw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=fhq2FCP2; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. 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[217.160.17.100]) by smtp.gmail.com with ESMTPSA id n64sm4423724wmd.11.2018.03.21.09.33.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 21 Mar 2018 09:33:29 -0700 (PDT) From: Andre Przywara To: Julien Grall , Stefano Stabellini Date: Wed, 21 Mar 2018 16:32:35 +0000 Message-Id: <20180321163235.12529-40-andre.przywara@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180321163235.12529-1-andre.przywara@linaro.org> References: <20180321163235.12529-1-andre.przywara@linaro.org> Subject: [Xen-devel] [PATCH v3 39/39] ARM: VGIC: wire new VGIC(-v2) files into Xen build system X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Wei Liu , George Dunlap , Andrew Cooper , Ian Jackson , Andre Przywara , Tim Deegan , Jan Beulich , xen-devel@lists.xenproject.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Now that we have both the old VGIC prepared to cope with a sibling and the code for the new VGIC in place, lets add a Kconfig option to enable the new code and wire it into the Xen build system. This will add a compile time option to use either the "old" or the "new" VGIC. In the moment this is restricted to a vGIC-v2. To make the build system happy, we provide a temporary dummy implementation of vgic_v3_setup_hw() to allow building for now. Signed-off-by: Andre Przywara --- Changelog v2 ... v3: - fix indentation of Kconfig entry - select NEEDS_LIST_SORT - drop unconditional list_sort.o inclusion Changelog v1 ... v2: - add Kconfig help text - use separate Makefile in vgic/ directory - protect compilation without GICV3 support - always include list_sort() in build xen/arch/arm/Kconfig | 18 +++++++++++++++++- xen/arch/arm/Makefile | 5 ++++- xen/arch/arm/vgic/Makefile | 5 +++++ xen/arch/arm/vgic/vgic.c | 10 ++++++++++ 4 files changed, 36 insertions(+), 2 deletions(-) create mode 100644 xen/arch/arm/vgic/Makefile diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 2782ee6589..8174c0c635 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -48,7 +48,23 @@ config HAS_GICV3 config HAS_ITS bool prompt "GICv3 ITS MSI controller support" if EXPERT = "y" - depends on HAS_GICV3 + depends on HAS_GICV3 && !NEW_VGIC + +config NEW_VGIC + bool + prompt "Use new VGIC implementation" + select NEEDS_LIST_SORT + ---help--- + + This is an alternative implementation of the ARM GIC interrupt + controller emulation, based on the Linux/KVM VGIC. It has a better + design and fixes many shortcomings of the existing GIC emulation in + Xen. It will eventually replace the existing/old VGIC. + However at the moment it lacks support for Dom0 using the ITS for + using MSIs. + Say Y if you want to help testing this new code or if you experience + problems with the standard emulation. + At the moment this implementation is not security supported. config SBSA_VUART_CONSOLE bool "Emulated SBSA UART console support" diff --git a/xen/arch/arm/Makefile b/xen/arch/arm/Makefile index 41d7366527..a9533b107e 100644 --- a/xen/arch/arm/Makefile +++ b/xen/arch/arm/Makefile @@ -16,7 +16,6 @@ obj-y += domain_build.o obj-y += domctl.o obj-$(EARLY_PRINTK) += early_printk.o obj-y += gic.o -obj-y += gic-vgic.o obj-y += gic-v2.o obj-$(CONFIG_HAS_GICV3) += gic-v3.o obj-$(CONFIG_HAS_ITS) += gic-v3-its.o @@ -47,10 +46,14 @@ obj-y += sysctl.o obj-y += time.o obj-y += traps.o obj-y += vcpreg.o +subdir-$(CONFIG_NEW_VGIC) += vgic +ifneq ($(CONFIG_NEW_VGIC),y) +obj-y += gic-vgic.o obj-y += vgic.o obj-y += vgic-v2.o obj-$(CONFIG_HAS_GICV3) += vgic-v3.o obj-$(CONFIG_HAS_ITS) += vgic-v3-its.o +endif obj-y += vm_event.o obj-y += vtimer.o obj-$(CONFIG_SBSA_VUART_CONSOLE) += vpl011.o diff --git a/xen/arch/arm/vgic/Makefile b/xen/arch/arm/vgic/Makefile new file mode 100644 index 0000000000..806826948e --- /dev/null +++ b/xen/arch/arm/vgic/Makefile @@ -0,0 +1,5 @@ +obj-y += vgic.o +obj-y += vgic-v2.o +obj-y += vgic-mmio.o +obj-y += vgic-mmio-v2.o +obj-y += vgic-init.o diff --git a/xen/arch/arm/vgic/vgic.c b/xen/arch/arm/vgic/vgic.c index 131358a5a1..22c70ff7cd 100644 --- a/xen/arch/arm/vgic/vgic.c +++ b/xen/arch/arm/vgic/vgic.c @@ -981,6 +981,16 @@ unsigned int vgic_max_vcpus(const struct domain *d) return min_t(unsigned int, MAX_VIRT_CPUS, vgic_vcpu_limit); } +#ifdef CONFIG_HAS_GICV3 +void vgic_v3_setup_hw(paddr_t dbase, + unsigned int nr_rdist_regions, + const struct rdist_region *regions, + unsigned int intid_bits) +{ + /* Dummy implementation to allow building without actual vGICv3 support. */ +} +#endif + /* * Local variables: * mode: C