From patchwork Fri Mar 30 09:44:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 132595 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2828246ljb; Fri, 30 Mar 2018 02:44:53 -0700 (PDT) X-Google-Smtp-Source: AIpwx4+9Gb1qgIjOWdJvpm6eg6ZOJI6y6Mlq6NClWp+xfgIsx7OjSfKvPMrgUeFkCeMgwNeQJiNy X-Received: by 2002:a17:902:6085:: with SMTP id s5-v6mr12257212plj.307.1522403093519; Fri, 30 Mar 2018 02:44:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1522403093; cv=none; d=google.com; s=arc-20160816; b=aAJ27zX6UeIYcIoXtypu6w99+XXEPYarPXdoYM/ZPq5ZQp7PhlEI5sDtOObSSILt1F CwEMQjCD5LzcWCXgL51aSV4QOTkIJHMozq9+ZsdOBNYs5SplUEj4lT94idgYZWfJYJQn GNgIIEF+c2ScvbzdBa/Z7cEr5N8Ua+q47ykujGXfCSst9JNJEkmjc/hPstvynU6ekBCf UdyWsGSu6Pz55+n29AtsCNDtLU9LHF+uIuBXVrXo1R6dE+dD9rOUVRDjDa+ULS9v2wH9 VeGjgSRN+PZZXPq2zl+sQiFOHNeXEWX4c8SlDGszYPB/OcGc7S04XEAXvKdc5srTag8D lT0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=QIOLl0pwfIQhXZckPfesdVtxD6j9cZ3UXEcW1WxHKTQ=; b=JJ23+O28fKxgPuSGg8iKfDcCjLrGyyMe63ZTrQRZvTuJlMXVDdIWthnlFbMceFRT4x la72J+p0jhS5nKviactITCPoPnNRu0eoRVNEkYq3tGdOvB/5+cvoyOAOOFEwlTaW50Wk 7OM5+pb9snlGYZznJJtvwrDdFm5AFmlH3RmjRaBpCgpWFOTCzDIY7t1wp55/ujqdfW9w rg5Tg9M41AzaTNdI2EJB2erry3qW/+NweOxsEDyq1uMjck4WmFqocEdE5lNGVP8Kujy4 wp3yuLK97fUt+8lA/1aus54YheVzoYBNhwrFg9oBSxYn6Ia9U1dgiIUTmrWgCMATFFJm zB2w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x13si5882329pfm.281.2018.03.30.02.44.53; Fri, 30 Mar 2018 02:44:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752006AbeC3Jov (ORCPT + 29 others); Fri, 30 Mar 2018 05:44:51 -0400 Received: from mx.socionext.com ([202.248.49.38]:52277 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751868AbeC3Jot (ORCPT ); Fri, 30 Mar 2018 05:44:49 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 30 Mar 2018 18:44:48 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id CE6C8180CA5; Fri, 30 Mar 2018 18:44:48 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 30 Mar 2018 18:44:48 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 29ED21A0DEC; Fri, 30 Mar 2018 18:44:48 +0900 (JST) From: Kunihiko Hayashi To: Philipp Zabel , Masahiro Yamada Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Kunihiko Hayashi Subject: [PATCH 1/2] reset: uniphier: add PCIe reset control support Date: Fri, 30 Mar 2018 18:44:43 +0900 Message-Id: <1522403084-18780-2-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1522403084-18780-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1522403084-18780-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add reset lines for PCIe controller on UniPhier SoCs. This adds support for Pro5, LD20 and PXs3. Signed-off-by: Kunihiko Hayashi --- drivers/reset/reset-uniphier.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.7.4 Acked-by: Masahiro Yamada diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c index 360e06b..55ae0f1 100644 --- a/drivers/reset/reset-uniphier.c +++ b/drivers/reset/reset-uniphier.c @@ -73,6 +73,7 @@ static const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = { UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (PCIe, USB3) */ UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */ UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */ + UNIPHIER_RESETX(24, 0x2008, 2), /* PCIe */ UNIPHIER_RESETX(40, 0x2000, 13), /* AIO */ UNIPHIER_RESET_END, }; @@ -115,6 +116,7 @@ static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = { UNIPHIER_RESETX(17, 0x200c, 13), /* USB30-PHY1 */ UNIPHIER_RESETX(18, 0x200c, 14), /* USB30-PHY2 */ UNIPHIER_RESETX(19, 0x200c, 15), /* USB30-PHY3 */ + UNIPHIER_RESETX(24, 0x200c, 4), /* PCIe */ UNIPHIER_RESETX(40, 0x2008, 0), /* AIO */ UNIPHIER_RESETX(41, 0x2008, 1), /* EVEA */ UNIPHIER_RESETX(42, 0x2010, 2), /* EXIV */ @@ -134,6 +136,7 @@ static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = { UNIPHIER_RESETX(18, 0x200c, 20), /* USB30-PHY2 */ UNIPHIER_RESETX(20, 0x200c, 17), /* USB31-PHY0 */ UNIPHIER_RESETX(21, 0x200c, 19), /* USB31-PHY1 */ + UNIPHIER_RESETX(24, 0x200c, 3), /* PCIe */ UNIPHIER_RESET_END, }; From patchwork Fri Mar 30 09:44:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 132597 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2828516ljb; Fri, 30 Mar 2018 02:45:13 -0700 (PDT) X-Google-Smtp-Source: AIpwx48jTIft72lE+Q+d+9CAWTjQARxYnIoxSvbwpRKsDWxI6sz2HPUoT6O3+CQRhxs0vi5Wh4A0 X-Received: by 2002:a17:902:7042:: with SMTP id h2-v6mr6308058plt.370.1522403113241; Fri, 30 Mar 2018 02:45:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1522403113; cv=none; d=google.com; s=arc-20160816; b=LjqCUWvtcs1ka63/JmeaXBdJh89gQduh6Vf65jyi/muJHi6DZ1OBHGdKtTweB3hILb O82rgOq9kUCnjYSLQFSIbj/rmXCwUaOxGF1rxuzlsiTi8UZVPsieNftHYeF4HgXsckfW ODAMDhVrW3ZiDHyhBHbijaRx3WwVy4PfoJWz+1QSJ4lJeRo56eDKp6/hbmCPU++gLvZo sVDi93G0Gj2R0gx5WWNaMlHQ3dd4Gq5lKgWchS0p/JodXJSbbINC8ojJx2fI0HNmYiox pognF2Y45Ha2SJjmXiSZrk0008Na9z/ii0NUpn2vSLr5vJHm0xfV35p6RjhTe5Sjy69z +9PQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=Qu6bFeiPMwYUa0D4C46puV0UWmS4tUaqKNDE39p8LzM=; b=VU0LLOzyJRuxWo7+upO/ikGKGi1fmZaum8vJy/j1H5I1FEmQFklDw3yWs/T8CTPCbY qlM6hTEg+uOTnf32f+VORNKM8hvL444xAXYFIAI4w/M2q/OcQOEW+DG4u0CGd9WazAPN x35lo39fz62iwWHOKmMTryKbv5FN0S2jEnT3HRso8b+S0XHnkile3hiuYvrL28f14HR4 3ra+BOa4VtDtxCWj6tZAeK90PYv3XjuA6bn1qeoZepbzZNCqji+ZOFJSy8+DX/shBS4+ lN1JqCE9P7AW7CiIVqVrwmQMKV3AeuucX1MT+M3zFpT95MSvuH3w0wlfdHmRnxNZ9nft 8fbA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i21si6198240pfk.34.2018.03.30.02.45.12; Fri, 30 Mar 2018 02:45:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752189AbeC3JpK (ORCPT + 29 others); Fri, 30 Mar 2018 05:45:10 -0400 Received: from mx.socionext.com ([202.248.49.38]:52281 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751878AbeC3Jov (ORCPT ); Fri, 30 Mar 2018 05:44:51 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 30 Mar 2018 18:44:49 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id D9F44180CA5; Fri, 30 Mar 2018 18:44:49 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 30 Mar 2018 18:44:49 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 8D9751A0DEC; Fri, 30 Mar 2018 18:44:49 +0900 (JST) From: Kunihiko Hayashi To: Philipp Zabel , Masahiro Yamada Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Kunihiko Hayashi Subject: [PATCH 2/2] reset: uniphier: add SATA reset control support and change SATA-PHY ID Date: Fri, 30 Mar 2018 18:44:44 +0900 Message-Id: <1522403084-18780-3-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1522403084-18780-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1522403084-18780-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add reset lines for SATA controller on UniPhier SoCs. This adds support for Pro4 and PXs3 in addition to PXs2. And this changes the ID of the reset line for SATA-PHY on PXs2. Since some SoCs have two controller instances with a common PHY, this moves the ID of SATA-PHY for consistency. Signed-off-by: Kunihiko Hayashi --- drivers/reset/reset-uniphier.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -- 2.7.4 Acked-by: Masahiro Yamada diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c index 55ae0f1..90e6caf 100644 --- a/drivers/reset/reset-uniphier.c +++ b/drivers/reset/reset-uniphier.c @@ -63,6 +63,9 @@ static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = { UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (Ether, SATA, USB3) */ UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */ UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */ + UNIPHIER_RESETX(28, 0x2000, 18), /* SATA0 */ + UNIPHIER_RESETX(29, 0x2004, 18), /* SATA1 */ + UNIPHIER_RESETX(30, 0x2000, 19), /* SATA-PHY */ UNIPHIER_RESETX(40, 0x2000, 13), /* AIO */ UNIPHIER_RESET_END, }; @@ -90,7 +93,7 @@ static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = { UNIPHIER_RESETX(20, 0x2014, 5), /* USB31-PHY0 */ UNIPHIER_RESETX(21, 0x2014, 1), /* USB31-PHY1 */ UNIPHIER_RESETX(28, 0x2014, 12), /* SATA */ - UNIPHIER_RESET(29, 0x2014, 8), /* SATA-PHY (active high) */ + UNIPHIER_RESET(30, 0x2014, 8), /* SATA-PHY (active high) */ UNIPHIER_RESETX(40, 0x2000, 13), /* AIO */ UNIPHIER_RESET_END, }; @@ -137,6 +140,9 @@ static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = { UNIPHIER_RESETX(20, 0x200c, 17), /* USB31-PHY0 */ UNIPHIER_RESETX(21, 0x200c, 19), /* USB31-PHY1 */ UNIPHIER_RESETX(24, 0x200c, 3), /* PCIe */ + UNIPHIER_RESETX(28, 0x200c, 7), /* SATA0 */ + UNIPHIER_RESETX(29, 0x200c, 8), /* SATA1 */ + UNIPHIER_RESETX(30, 0x200c, 21), /* SATA-PHY */ UNIPHIER_RESET_END, };