From patchwork Thu Apr 6 12:48:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Pundir X-Patchwork-Id: 96951 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp714309qgd; Thu, 6 Apr 2017 05:49:45 -0700 (PDT) X-Received: by 10.84.140.235 with SMTP id 98mr43427118plt.161.1491482985294; Thu, 06 Apr 2017 05:49:45 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s4si1781387pgc.281.2017.04.06.05.49.45; Thu, 06 Apr 2017 05:49:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757194AbdDFMth (ORCPT + 13 others); Thu, 6 Apr 2017 08:49:37 -0400 Received: from mail-pg0-f44.google.com ([74.125.83.44]:32911 "EHLO mail-pg0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756947AbdDFMtT (ORCPT ); Thu, 6 Apr 2017 08:49:19 -0400 Received: by mail-pg0-f44.google.com with SMTP id x125so35560484pgb.0 for ; Thu, 06 Apr 2017 05:49:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TOxjxf4ip6bCk7os3b/Ok2YkmVYrOcbigSyMEjr1ACw=; b=ImLgf/wYDD9ThzTRX2hH9Yht4DfKUBvrOZ1p7bH6LgXp1t4mD54ZmZzQH52tmd5XSs 2ECaYayZdnUJxDUyN38RANKbd6aUKfyI7ii1DZFyncKzVC2cAAv7geHvpYd+I2DR3lhq jWNCd1Q8uK7WCOJ24HDAO9UHzR69qiGmkZ8kg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=TOxjxf4ip6bCk7os3b/Ok2YkmVYrOcbigSyMEjr1ACw=; b=a//dRxe6KIbbvqvG3iHyo2GLGbvVU4GBUcpzsA6kATDTVAgdAJ3USPCK8lCMkVcF9k w/CTG6AexN86+SNsFmeTk2KOkZhT6+EIIv923YdFIDYb69wEIX9je8Y37cQC4i6qCOsm XSUJ46NT4bJdyS2agMyXePp8AICmekZLjxxR51a6gVGxjgX6mamDUUpr83cKEx7sYRX5 btYqc7r5/ppZ6KeYsfCeRQA8K4W3QBkuvuLQkRZWyimqfewj/bEow+gcyuHd4Ud/cJiJ oJUC0855l0HC4rIREbZwoIjJC91K2XsWoopNbGZbEZ8i+4bJO4nnsl1eAVIHa6Q1AR5z 4oTA== X-Gm-Message-State: AFeK/H3BBEciWpufbESK4TG3u4LZS11+n7hjzkw9bZtb/ColUZN6x1atqD/+SUibnTl15EVc X-Received: by 10.99.164.26 with SMTP id c26mr36625230pgf.89.1491482958036; Thu, 06 Apr 2017 05:49:18 -0700 (PDT) Received: from localhost.localdomain ([106.51.240.246]) by smtp.gmail.com with ESMTPSA id n7sm3892564pfn.0.2017.04.06.05.49.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 06 Apr 2017 05:49:17 -0700 (PDT) From: Amit Pundir To: gregkh@linuxfoundation.org Cc: stable@vger.kernel.org, james.hogan@imgtec.com, Matt Redfearn , Thomas Gleixner , Paul Burton , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Ralf Baechle Subject: [PATCH for-4.4 3/7] MIPS: Only change $28 to thread_info if coming from user mode Date: Thu, 6 Apr 2017 18:18:56 +0530 Message-Id: <1491482940-1163-4-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491482940-1163-1-git-send-email-amit.pundir@linaro.org> References: <1491482940-1163-1-git-send-email-amit.pundir@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Matt Redfearn The SAVE_SOME macro is used to save the execution context on all exceptions. If an exception occurs while executing user code, the stack is switched to the kernel's stack for the current task, and register $28 is switched to point to the current_thread_info, which is at the bottom of the stack region. If the exception occurs while executing kernel code, the stack is left, and this change ensures that register $28 is not updated. This is the correct behaviour when the kernel can be executing on the separate irq stack, because the thread_info will not be at the base of it. With this change, register $28 is only switched to it's kernel conventional usage of the currrent thread info pointer at the point at which execution enters kernel space. Doing it on every exception was redundant, but OK without an IRQ stack, but will be erroneous once that is introduced. Signed-off-by: Matt Redfearn Acked-by: Jason A. Donenfeld Cc: Thomas Gleixner Cc: James Hogan Cc: Paul Burton Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14742/ Signed-off-by: Ralf Baechle (cherry picked from commit 510d86362a27577f5ee23f46cfb354ad49731e61) Signed-off-by: Amit Pundir --- arch/mips/include/asm/stackframe.h | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.7.4 diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index a71da57..5347f13 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h @@ -216,12 +216,19 @@ LONG_S $25, PT_R25(sp) LONG_S $28, PT_R28(sp) LONG_S $31, PT_R31(sp) + + /* Set thread_info if we're coming from user mode */ + mfc0 k0, CP0_STATUS + sll k0, 3 /* extract cu0 bit */ + bltz k0, 9f + ori $28, sp, _THREAD_MASK xori $28, _THREAD_MASK #ifdef CONFIG_CPU_CAVIUM_OCTEON .set mips64 pref 0, 0($28) /* Prefetch the current pointer */ #endif +9: .set pop .endm From patchwork Thu Apr 6 12:48:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Pundir X-Patchwork-Id: 96955 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp714503qgd; Thu, 6 Apr 2017 05:50:15 -0700 (PDT) X-Received: by 10.98.135.1 with SMTP id i1mr3978070pfe.106.1491483015012; Thu, 06 Apr 2017 05:50:15 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s84si1803360pgs.70.2017.04.06.05.50.14; Thu, 06 Apr 2017 05:50:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757342AbdDFMuK (ORCPT + 13 others); Thu, 6 Apr 2017 08:50:10 -0400 Received: from mail-pg0-f51.google.com ([74.125.83.51]:35023 "EHLO mail-pg0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754909AbdDFMtW (ORCPT ); Thu, 6 Apr 2017 08:49:22 -0400 Received: by mail-pg0-f51.google.com with SMTP id 81so35570834pgh.2 for ; Thu, 06 Apr 2017 05:49:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3bjVxBZE1ORVcmMPBuz4nCvoQM/Fj96OKFA9zbFKFic=; b=VaDEdbuiVKM2tyXk8xXfW8BsFaAkJFb/eEiIHXH7qDFQ8OMMlWm/LGd/7dgxyHPSRi vsEM7vBj2eC+/gQkYxrVS/XCBGZt4gqyTt7JgiHvV2USh97HUcriIzNDW35P+VE0CxOw /dA32NO38Cj9gH1Dc8GHcDznfFkwzpw0UGTvY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3bjVxBZE1ORVcmMPBuz4nCvoQM/Fj96OKFA9zbFKFic=; b=Su5gScGEqaU8OsufvmbULjjxohtUhmx5pRIh90RYWo1f1IVBMU0VkcSVP7iOSMnUap Pft/lG8IN0H9X8JoHpLTmjX8tk5NkliW7dFaRrJ+L0P1vcMllc0dJVpECNabjUtbWMTI bU0HnpfGDEUAa91a1ydFVXSmJNbRax7tgmUMijThi4hLhkdRRhZ77CdLnuaFGgidafkm LCJcT5nwJZaJSuDVq4xnUnoGltH+bPW1FoXSnqI0o6a/pYYayb5q2lLc2BNb/IRH5Dn4 4zdq5wNm+jPnFEtuHvJXLjvmVzsMuCF4mjE7AavwkuQHnodKXWw8OZPInZS+1qmK5/fd hTDA== X-Gm-Message-State: AFeK/H2iDjA5q4fxqNNbbGS5oma28WNwkEDn+wXlRrbA8KF5D+CgjAEbJxAsyh8vB+v3Wrw8 X-Received: by 10.99.116.18 with SMTP id p18mr36678390pgc.74.1491482961355; Thu, 06 Apr 2017 05:49:21 -0700 (PDT) Received: from localhost.localdomain ([106.51.240.246]) by smtp.gmail.com with ESMTPSA id n7sm3892564pfn.0.2017.04.06.05.49.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 06 Apr 2017 05:49:20 -0700 (PDT) From: Amit Pundir To: gregkh@linuxfoundation.org Cc: stable@vger.kernel.org, james.hogan@imgtec.com, Matt Redfearn , Thomas Gleixner , Paul Burton , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Ralf Baechle Subject: [PATCH for-4.4 4/7] MIPS: Switch to the irq_stack in interrupts Date: Thu, 6 Apr 2017 18:18:57 +0530 Message-Id: <1491482940-1163-5-git-send-email-amit.pundir@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1491482940-1163-1-git-send-email-amit.pundir@linaro.org> References: <1491482940-1163-1-git-send-email-amit.pundir@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Matt Redfearn When enterring interrupt context via handle_int or except_vec_vi, switch to the irq_stack of the current CPU if it is not already in use. The current stack pointer is masked with the thread size and compared to the base or the irq stack. If it does not match then the stack pointer is set to the top of that stack, otherwise this is a nested irq being handled on the irq stack so the stack pointer should be left as it was. The in-use stack pointer is placed in the callee saved register s1. It will be saved to the stack when plat_irq_dispatch is invoked and can be restored once control returns here. Signed-off-by: Matt Redfearn Acked-by: Jason A. Donenfeld Cc: Thomas Gleixner Cc: James Hogan Cc: Paul Burton Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14743/ Signed-off-by: Ralf Baechle (cherry picked from commit dda45f701c9d7ad4ac0bb446e3a96f6df9a468d9) Signed-off-by: Amit Pundir --- arch/mips/kernel/genex.S | 81 +++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 76 insertions(+), 5 deletions(-) -- 2.7.4 diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index baa7b6f..2c7cd62 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -188,9 +188,44 @@ NESTED(handle_int, PT_SIZE, sp) LONG_L s0, TI_REGS($28) LONG_S sp, TI_REGS($28) - PTR_LA ra, ret_from_irq - PTR_LA v0, plat_irq_dispatch - jr v0 + + /* + * SAVE_ALL ensures we are using a valid kernel stack for the thread. + * Check if we are already using the IRQ stack. + */ + move s1, sp # Preserve the sp + + /* Get IRQ stack for this CPU */ + ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG +#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) + lui k1, %hi(irq_stack) +#else + lui k1, %highest(irq_stack) + daddiu k1, %higher(irq_stack) + dsll k1, 16 + daddiu k1, %hi(irq_stack) + dsll k1, 16 +#endif + LONG_SRL k0, SMP_CPUID_PTRSHIFT + LONG_ADDU k1, k0 + LONG_L t0, %lo(irq_stack)(k1) + + # Check if already on IRQ stack + PTR_LI t1, ~(_THREAD_SIZE-1) + and t1, t1, sp + beq t0, t1, 2f + + /* Switch to IRQ stack */ + li t1, _IRQ_STACK_SIZE + PTR_ADD sp, t0, t1 + +2: + jal plat_irq_dispatch + + /* Restore sp */ + move sp, s1 + + j ret_from_irq #ifdef CONFIG_CPU_MICROMIPS nop #endif @@ -263,8 +298,44 @@ NESTED(except_vec_vi_handler, 0, sp) LONG_L s0, TI_REGS($28) LONG_S sp, TI_REGS($28) - PTR_LA ra, ret_from_irq - jr v0 + + /* + * SAVE_ALL ensures we are using a valid kernel stack for the thread. + * Check if we are already using the IRQ stack. + */ + move s1, sp # Preserve the sp + + /* Get IRQ stack for this CPU */ + ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG +#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) + lui k1, %hi(irq_stack) +#else + lui k1, %highest(irq_stack) + daddiu k1, %higher(irq_stack) + dsll k1, 16 + daddiu k1, %hi(irq_stack) + dsll k1, 16 +#endif + LONG_SRL k0, SMP_CPUID_PTRSHIFT + LONG_ADDU k1, k0 + LONG_L t0, %lo(irq_stack)(k1) + + # Check if already on IRQ stack + PTR_LI t1, ~(_THREAD_SIZE-1) + and t1, t1, sp + beq t0, t1, 2f + + /* Switch to IRQ stack */ + li t1, _IRQ_STACK_SIZE + PTR_ADD sp, t0, t1 + +2: + jal plat_irq_dispatch + + /* Restore sp */ + move sp, s1 + + j ret_from_irq END(except_vec_vi_handler) /*