From patchwork Mon Apr 9 06:38:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 132999 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp883183ljb; Sun, 8 Apr 2018 23:39:10 -0700 (PDT) X-Google-Smtp-Source: AIpwx48yCqQW+149/x06udXncE3B5wBW5UwLQaaJknY2djx0qo1pQbi3Jkj298yPzN81M9qaP5E5 X-Received: by 2002:a17:902:1e2:: with SMTP id b89-v6mr36770092plb.389.1523255950506; Sun, 08 Apr 2018 23:39:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1523255950; cv=none; d=google.com; s=arc-20160816; b=Vpi8rhNVrrlz5E5b34pnTkOjsEcyqGVIKzmb8zdYiw2BfAVPZDk2LQJ5ekrhINt4bA uREovT5dgZNAAXc9MFXxkewYdQH0EysSSJQPo37JSfDVjTNSNCzmsV2d1I6OPWld6BBi vqvEn6u3KvQXOVP7bPGBA/fIikCtn3/58ji1ShOxi7BBDqdjf8sUcc50FEEB3RFHak2D s+dNX9DIOHTBZuqhkkCrrm50N4edhZZwtCBXv+6pEymA07iRlTrdktkbTzxo47+91mfF 86qrC/wQmxjsTbtjE8aIc6sBeQR/c7d76PGpT7jX7Q841z770twlMuhqx0B8JRqfygkC sQIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=D6CwCUVxIH5j16T/iq3eGRn+Ro0j/g3pIdGryiVmdwE=; b=x8+uzq7vOCER29/mpceYHZ8AULHTk87qkPNoa3OWnRNL4kgxahieX16K6lo1wgeW8U kA3jK2m2X2oiTkszjnXsZJP0OxfEglPLxYJbTeB9rOSXGtlUpOYGmiZ7MaKAIhAOpaJy yw0HdZ0uhzCqtetkRKqjiNLFQBmmJcAZ6HFPgKRz/9JuEbn7XNDm42TK038ls0a6bIjd ilvjGwMirNgZFvWnEAN0kG5yFurwDwhKuTRWc3vzjGViB2zjCUhsNbN8D3NGWmAPF/yl vSjA12Q5KEQjxTLBLXrSxkrJKSwZt46X3wnQdMb95p0g66IlP9g4xl0cADWEnXpV8hYC +WoQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o61-v6si13589111pld.646.2018.04.08.23.39.10; Sun, 08 Apr 2018 23:39:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752068AbeDIGjH (ORCPT + 29 others); Mon, 9 Apr 2018 02:39:07 -0400 Received: from mx.socionext.com ([202.248.49.38]:3254 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751799AbeDIGjE (ORCPT ); Mon, 9 Apr 2018 02:39:04 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 09 Apr 2018 15:39:02 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 52BBE180237; Mon, 9 Apr 2018 15:39:02 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Mon, 9 Apr 2018 15:39:02 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 9E1B31A0DEC; Mon, 9 Apr 2018 15:39:01 +0900 (JST) From: Kunihiko Hayashi To: David Miller , netdev@vger.kernel.org Cc: Andrew Lunn , Florian Fainelli , Rob Herring , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Masahiro Yamada , Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH net-next 1/3] net: ethernet: ave: add multiple clocks and resets support as required property Date: Mon, 9 Apr 2018 15:38:43 +0900 Message-Id: <1523255925-6469-2-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1523255925-6469-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1523255925-6469-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When the link is becoming up for Pro4 SoC, the kernel is stalled due to some missing clocks and resets. The AVE block for Pro4 is connected to the GIO bus in the SoC. Without its clock/reset, the access to the AVE register makes the system stall. In the same way, another MAC clock for Giga-bit Connection and the PHY clock are also required for Pro4 to activate the Giga-bit feature and to recognize the PHY. To satisfy these requirements, this patch adds support for multiple clocks and resets, and adds the clock-names and reset-names to the binding because we need to distinguish clock/reset for the AVE main block and the others. Also, make the resets a required property. Currently, "reset is optional" relies on that the bootloader or firmware has deasserted the reset before booting the kernel. Drivers should work without such expectation. Fixes: 4c270b55a5af ("net: ethernet: socionext: add AVE ethernet driver") Suggested-by: Masahiro Yamada Signed-off-by: Kunihiko Hayashi --- .../bindings/net/socionext,uniphier-ave4.txt | 13 ++- drivers/net/ethernet/socionext/sni_ave.c | 108 ++++++++++++++++----- 2 files changed, 96 insertions(+), 25 deletions(-) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt b/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt index 96398cc..85e0c49 100644 --- a/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt +++ b/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt @@ -17,9 +17,18 @@ Required properties: - phy-handle: Should point to the external phy device. See ethernet.txt file in the same directory. - clocks: A phandle to the clock for the MAC. + For Pro4 SoC, that is "socionext,uniphier-pro4-ave4", + another MAC clock, GIO bus clock and PHY clock are also required. + - clock-names: Should contain + - "ether", "ether-gb", "gio", "ether-phy" for Pro4 SoC + - "ether" for others + - resets: A phandle to the reset control for the MAC. For Pro4 SoC, + GIO bus reset is also required. + - reset-names: Should contain + - "ether", "gio" for Pro4 SoC + - "ether" for others Optional properties: - - resets: A phandle to the reset control for the MAC. - local-mac-address: See ethernet.txt in the same directory. Required subnode: @@ -34,7 +43,9 @@ Example: interrupts = <0 66 4>; phy-mode = "rgmii"; phy-handle = <ðphy>; + clock-names = "ether"; clocks = <&sys_clk 6>; + reset-names = "ether"; resets = <&sys_rst 6>; local-mac-address = [00 00 00 00 00 00]; diff --git a/drivers/net/ethernet/socionext/sni_ave.c b/drivers/net/ethernet/socionext/sni_ave.c index 0b3b7a4..52940bd 100644 --- a/drivers/net/ethernet/socionext/sni_ave.c +++ b/drivers/net/ethernet/socionext/sni_ave.c @@ -199,6 +199,9 @@ #define IS_DESC_64BIT(p) ((p)->data->is_desc_64bit) +#define AVE_MAX_CLKS 4 +#define AVE_MAX_RSTS 2 + enum desc_id { AVE_DESCID_RX, AVE_DESCID_TX, @@ -227,6 +230,8 @@ struct ave_desc_info { struct ave_soc_data { bool is_desc_64bit; + const char *clock_names[AVE_MAX_CLKS]; + const char *reset_names[AVE_MAX_RSTS]; }; struct ave_stats { @@ -245,8 +250,10 @@ struct ave_private { int phy_id; unsigned int desc_size; u32 msg_enable; - struct clk *clk; - struct reset_control *rst; + int nclks; + struct clk *clk[AVE_MAX_CLKS]; + int nrsts; + struct reset_control *rst[AVE_MAX_RSTS]; phy_interface_t phy_mode; struct phy_device *phydev; struct mii_bus *mdio; @@ -1153,18 +1160,23 @@ static int ave_init(struct net_device *ndev) struct device_node *np = dev->of_node; struct device_node *mdio_np; struct phy_device *phydev; - int ret; + int nc, nr, ret; /* enable clk because of hw access until ndo_open */ - ret = clk_prepare_enable(priv->clk); - if (ret) { - dev_err(dev, "can't enable clock\n"); - return ret; + for (nc = 0; nc < priv->nclks; nc++) { + ret = clk_prepare_enable(priv->clk[nc]); + if (ret) { + dev_err(dev, "can't enable clock\n"); + goto out_clk_disable; + } } - ret = reset_control_deassert(priv->rst); - if (ret) { - dev_err(dev, "can't deassert reset\n"); - goto out_clk_disable; + + for (nr = 0; nr < priv->nrsts; nr++) { + ret = reset_control_deassert(priv->rst[nr]); + if (ret) { + dev_err(dev, "can't deassert reset\n"); + goto out_reset_assert; + } } ave_global_reset(ndev); @@ -1207,9 +1219,11 @@ static int ave_init(struct net_device *ndev) out_mdio_unregister: mdiobus_unregister(priv->mdio); out_reset_assert: - reset_control_assert(priv->rst); + while (--nr >= 0) + reset_control_assert(priv->rst[nr]); out_clk_disable: - clk_disable_unprepare(priv->clk); + while (--nc >= 0) + clk_disable_unprepare(priv->clk[nc]); return ret; } @@ -1217,13 +1231,16 @@ static int ave_init(struct net_device *ndev) static void ave_uninit(struct net_device *ndev) { struct ave_private *priv = netdev_priv(ndev); + int i; phy_disconnect(priv->phydev); mdiobus_unregister(priv->mdio); /* disable clk because of hw access after ndo_stop */ - reset_control_assert(priv->rst); - clk_disable_unprepare(priv->clk); + for (i = 0; i < priv->nrsts; i++) + reset_control_assert(priv->rst[i]); + for (i = 0; i < priv->nclks; i++) + clk_disable_unprepare(priv->clk[i]); } static int ave_open(struct net_device *ndev) @@ -1527,8 +1544,9 @@ static int ave_probe(struct platform_device *pdev) struct resource *res; const void *mac_addr; void __iomem *base; + const char *name; + int i, irq, ret; u64 dma_mask; - int irq, ret; u32 ave_id; data = of_device_get_match_data(dev); @@ -1614,16 +1632,28 @@ static int ave_probe(struct platform_device *pdev) u64_stats_init(&priv->stats_tx.syncp); u64_stats_init(&priv->stats_rx.syncp); - priv->clk = devm_clk_get(dev, NULL); - if (IS_ERR(priv->clk)) { - ret = PTR_ERR(priv->clk); - goto out_free_netdev; + for (i = 0; i < AVE_MAX_CLKS; i++) { + name = priv->data->clock_names[i]; + if (!name) + break; + priv->clk[i] = devm_clk_get(dev, name); + if (IS_ERR(priv->clk[i])) { + ret = PTR_ERR(priv->clk[i]); + goto out_free_netdev; + } + priv->nclks++; } - priv->rst = devm_reset_control_get_optional_shared(dev, NULL); - if (IS_ERR(priv->rst)) { - ret = PTR_ERR(priv->rst); - goto out_free_netdev; + for (i = 0; i < AVE_MAX_RSTS; i++) { + name = priv->data->reset_names[i]; + if (!name) + break; + priv->rst[i] = devm_reset_control_get_shared(dev, name); + if (IS_ERR(priv->rst[i])) { + ret = PTR_ERR(priv->rst[i]); + goto out_free_netdev; + } + priv->nrsts++; } priv->mdio = devm_mdiobus_alloc(dev); @@ -1687,22 +1717,52 @@ static int ave_remove(struct platform_device *pdev) static const struct ave_soc_data ave_pro4_data = { .is_desc_64bit = false, + .clock_names = { + "gio", "ether", "ether-gb", "ether-phy", + }, + .reset_names = { + "gio", "ether", + }, }; static const struct ave_soc_data ave_pxs2_data = { .is_desc_64bit = false, + .clock_names = { + "ether", + }, + .reset_names = { + "ether", + }, }; static const struct ave_soc_data ave_ld11_data = { .is_desc_64bit = false, + .clock_names = { + "ether", + }, + .reset_names = { + "ether", + }, }; static const struct ave_soc_data ave_ld20_data = { .is_desc_64bit = true, + .clock_names = { + "ether", + }, + .reset_names = { + "ether", + }, }; static const struct ave_soc_data ave_pxs3_data = { .is_desc_64bit = false, + .clock_names = { + "ether", + }, + .reset_names = { + "ether", + }, }; static const struct of_device_id of_ave_match[] = { From patchwork Mon Apr 9 06:38:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 133001 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp883707ljb; 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[209.132.180.67]) by mx.google.com with ESMTP id r8-v6si16274180pli.12.2018.04.08.23.40.01; Sun, 08 Apr 2018 23:40:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752296AbeDIGj5 (ORCPT + 29 others); Mon, 9 Apr 2018 02:39:57 -0400 Received: from mx.socionext.com ([202.248.49.38]:3259 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750877AbeDIGjF (ORCPT ); Mon, 9 Apr 2018 02:39:05 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 09 Apr 2018 15:39:03 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id DC98B180237; Mon, 9 Apr 2018 15:39:03 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Mon, 9 Apr 2018 15:39:03 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 2CD641A0DEC; Mon, 9 Apr 2018 15:39:03 +0900 (JST) From: Kunihiko Hayashi To: David Miller , netdev@vger.kernel.org Cc: Andrew Lunn , Florian Fainelli , Rob Herring , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Masahiro Yamada , Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH net-next 2/3] dt-bindings: net: ave: add syscon-phy-mode property to configure phy-mode setting Date: Mon, 9 Apr 2018 15:38:44 +0900 Message-Id: <1523255925-6469-3-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1523255925-6469-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1523255925-6469-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add "socionext,syscon-phy-mode" property to specify system controller that configures the settings about phy-mode. Signed-off-by: Kunihiko Hayashi --- Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- 2.7.4 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt b/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt index 85e0c49..fc8f017 100644 --- a/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt +++ b/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt @@ -13,7 +13,8 @@ Required properties: - reg: Address where registers are mapped and size of region. - interrupts: Should contain the MAC interrupt. - phy-mode: See ethernet.txt in the same directory. Allow to choose - "rgmii", "rmii", or "mii" according to the PHY. + "rgmii", "rmii", "mii", or "internal" according to the PHY. + The acceptable mode is SoC-dependent. - phy-handle: Should point to the external phy device. See ethernet.txt file in the same directory. - clocks: A phandle to the clock for the MAC. @@ -27,6 +28,8 @@ Required properties: - reset-names: Should contain - "ether", "gio" for Pro4 SoC - "ether" for others + - socionext,syscon-phy-mode: A phandle to syscon with one argument + that configures phy mode. The argument is the ID of MAC instance. Optional properties: - local-mac-address: See ethernet.txt in the same directory. @@ -47,6 +50,7 @@ Example: clocks = <&sys_clk 6>; reset-names = "ether"; resets = <&sys_rst 6>; + socionext,syscon-phy-mode = <&soc_glue 0>; local-mac-address = [00 00 00 00 00 00]; mdio { From patchwork Mon Apr 9 06:38:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 133000 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp883348ljb; Sun, 8 Apr 2018 23:39:27 -0700 (PDT) X-Google-Smtp-Source: AIpwx4/Ja9SvMc4Cq/wVN8Wn31q+nL1o0nXT/3rPH/DIckvQrW8Gz8l7aT+PuZRJ8vDVFkxl0vqF X-Received: by 2002:a17:902:aa98:: with SMTP id d24-v6mr37779096plr.220.1523255967335; Sun, 08 Apr 2018 23:39:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1523255967; cv=none; d=google.com; s=arc-20160816; b=07fsX7vb46d8PtV0EQEE4JlOCWxt1w+un/Wl4v4mXBHiP1GxlGozD8ku2b91J0E7Fg rQ9cXgIUHAsERRGg2QmD9JinT5gYlMJjmmxVs6wPgse1hBGPKpmOZeUrB91Unjz2Ljlu ThTOAXhhlkEBRTpb9FfA0x7/sOmlyIaqeowteck+PV0+t36B0CQx/pzxduwSBGMt3pv2 aJHOAfdL2jG5srFGhkiYYgeD7b3M2ZOUqwMEyavZ+GqmY+RNJgoFeqxHoJkp/UZMNERR fKzRNvnqYi07hMf7kaJ4e2DGcNT7uN/FvkDdv/Y3waZjKaq3m5rWAjYMg/00G059IiEz c3Ow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=zp4+3x2nL2c1tYuy7GSNgjIg2fIcl3VirGqS5hnEo7o=; b=olUUOussLgLYeFBiyCWf40A+MfWwfgA2Cso1uirTxPcijiU0tChFhRGaIgf3c/RMUs 8jUBblk6QszPKvhQaptrDZByYtjaUQ3v/7SRn+yCOZCPcfvQwQVscMzd3svvvtvhPc8N oTiWvVnB7Qq/t+5ZacEPlEVVlZ+4K7/uYgUbHRIXHuZBWN+Q2hpReTIiUYuOiGyQmbvh SJrLxgL1hvyYFrK1YCdLAOM06vQvrX9POGL9KICEsugBlX8yeP2S9/Lnj9y7uCneTa6K hcRF4gFgpaQPjrONmtNsFa6yYgPzX8xEBgYffhC0XHBEqBO34ANwoq2eZcfFdPTA018W Hsvw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i63si12266195pfk.159.2018.04.08.23.39.27; Sun, 08 Apr 2018 23:39:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752137AbeDIGjX (ORCPT + 29 others); Mon, 9 Apr 2018 02:39:23 -0400 Received: from mx.socionext.com ([202.248.49.38]:3243 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750925AbeDIGjG (ORCPT ); Mon, 9 Apr 2018 02:39:06 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 09 Apr 2018 15:39:04 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id F2D6A180237; Mon, 9 Apr 2018 15:39:04 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Mon, 9 Apr 2018 15:39:04 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 65F0D1A0DEC; Mon, 9 Apr 2018 15:39:04 +0900 (JST) From: Kunihiko Hayashi To: David Miller , netdev@vger.kernel.org Cc: Andrew Lunn , Florian Fainelli , Rob Herring , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Masahiro Yamada , Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH net-next 3/3] net: ethernet: ave: add support for phy-mode setting of system controller Date: Mon, 9 Apr 2018 15:38:45 +0900 Message-Id: <1523255925-6469-4-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1523255925-6469-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1523255925-6469-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds support for specifying system controller that configures phy-mode setting. According to the DT property "phy-mode", it's necessary to configure the controller, which is used to choose the settings of the MAC suitable, for example, mdio pin connections, internal clocks, and so on. Supported phy-modes are SoC-dependent. The driver allows phy-mode to set "internal" if the SoC has a built-in PHY, and {"mii", "rmii", "rgmii"} if the SoC supports each mode. So we have to check whether the phy-mode is valid or not. This adds the following features for each SoC: - check whether the SoC supports the specified phy-mode - configure the controller accroding to phy-mode The DT property accepts one argument to distinguish them for multiple MAC instances. ethernet@65000000 { ... socionext,syscon-phy-mode = <&soc_glue 0>; }; ethernet@65200000 { ... socionext,syscon-phy-mode = <&soc_glue 1>; }; Signed-off-by: Kunihiko Hayashi Signed-off-by: Masahiro Yamada --- drivers/net/ethernet/socionext/Kconfig | 2 + drivers/net/ethernet/socionext/sni_ave.c | 150 ++++++++++++++++++++++++++++--- 2 files changed, 140 insertions(+), 12 deletions(-) -- 2.7.4 diff --git a/drivers/net/ethernet/socionext/Kconfig b/drivers/net/ethernet/socionext/Kconfig index 6bcfe27..b80048c 100644 --- a/drivers/net/ethernet/socionext/Kconfig +++ b/drivers/net/ethernet/socionext/Kconfig @@ -14,6 +14,8 @@ if NET_VENDOR_SOCIONEXT config SNI_AVE tristate "Socionext AVE ethernet support" depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF + depends on HAS_IOMEM + select MFD_SYSCON select PHYLIB ---help--- Driver for gigabit ethernet MACs, called AVE, in the diff --git a/drivers/net/ethernet/socionext/sni_ave.c b/drivers/net/ethernet/socionext/sni_ave.c index 52940bd..f7eccee 100644 --- a/drivers/net/ethernet/socionext/sni_ave.c +++ b/drivers/net/ethernet/socionext/sni_ave.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -18,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -197,6 +199,11 @@ #define AVE_INTM_COUNT 20 #define AVE_FORCE_TXINTCNT 1 +/* SG */ +#define SG_ETPINMODE 0x540 +#define SG_ETPINMODE_EXTPHY BIT(1) /* for LD11 */ +#define SG_ETPINMODE_RMII(ins) BIT(ins) + #define IS_DESC_64BIT(p) ((p)->data->is_desc_64bit) #define AVE_MAX_CLKS 4 @@ -228,12 +235,6 @@ struct ave_desc_info { struct ave_desc *desc; /* skb info related descriptor */ }; -struct ave_soc_data { - bool is_desc_64bit; - const char *clock_names[AVE_MAX_CLKS]; - const char *reset_names[AVE_MAX_RSTS]; -}; - struct ave_stats { struct u64_stats_sync syncp; u64 packets; @@ -257,6 +258,9 @@ struct ave_private { phy_interface_t phy_mode; struct phy_device *phydev; struct mii_bus *mdio; + struct regmap *regmap; + unsigned int pinmode_mask; + unsigned int pinmode_val; /* stats */ struct ave_stats stats_rx; @@ -279,6 +283,14 @@ struct ave_private { const struct ave_soc_data *data; }; +struct ave_soc_data { + bool is_desc_64bit; + const char *clock_names[AVE_MAX_CLKS]; + const char *reset_names[AVE_MAX_RSTS]; + int (*get_pinmode)(struct ave_private *priv, + phy_interface_t phy_mode, u32 arg); +}; + static u32 ave_desc_read(struct net_device *ndev, enum desc_id id, int entry, int offset) { @@ -1179,6 +1191,11 @@ static int ave_init(struct net_device *ndev) } } + ret = regmap_update_bits(priv->regmap, SG_ETPINMODE, + priv->pinmode_mask, priv->pinmode_val); + if (ret) + return ret; + ave_global_reset(ndev); mdio_np = of_get_child_by_name(np, "mdio"); @@ -1537,6 +1554,7 @@ static int ave_probe(struct platform_device *pdev) const struct ave_soc_data *data; struct device *dev = &pdev->dev; char buf[ETHTOOL_FWVERS_LEN]; + struct of_phandle_args args; phy_interface_t phy_mode; struct ave_private *priv; struct net_device *ndev; @@ -1559,12 +1577,6 @@ static int ave_probe(struct platform_device *pdev) dev_err(dev, "phy-mode not found\n"); return -EINVAL; } - if ((!phy_interface_mode_is_rgmii(phy_mode)) && - phy_mode != PHY_INTERFACE_MODE_RMII && - phy_mode != PHY_INTERFACE_MODE_MII) { - dev_err(dev, "phy-mode is invalid\n"); - return -EINVAL; - } irq = platform_get_irq(pdev, 0); if (irq < 0) { @@ -1656,6 +1668,26 @@ static int ave_probe(struct platform_device *pdev) priv->nrsts++; } + ret = of_parse_phandle_with_fixed_args(np, + "socionext,syscon-phy-mode", + 1, 0, &args); + if (ret) { + netdev_err(ndev, "can't get syscon-phy-mode property\n"); + goto out_free_netdev; + } + priv->regmap = syscon_node_to_regmap(args.np); + of_node_put(args.np); + if (IS_ERR(priv->regmap)) { + netdev_err(ndev, "can't map syscon-phy-mode\n"); + ret = PTR_ERR(priv->regmap); + goto out_free_netdev; + } + ret = priv->data->get_pinmode(priv, phy_mode, args.args[0]); + if (ret) { + netdev_err(ndev, "invalid phy-mode setting\n"); + goto out_free_netdev; + } + priv->mdio = devm_mdiobus_alloc(dev); if (!priv->mdio) { ret = -ENOMEM; @@ -1715,6 +1747,95 @@ static int ave_remove(struct platform_device *pdev) return 0; } +static int ave_pro4_get_pinmode(struct ave_private *priv, + phy_interface_t phy_mode, u32 arg) +{ + if (arg > 0) + return -EINVAL; + + priv->pinmode_mask = SG_ETPINMODE_RMII(0); + + switch (phy_mode) { + case PHY_INTERFACE_MODE_RMII: + priv->pinmode_val = SG_ETPINMODE_RMII(0); + break; + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_RGMII: + priv->pinmode_val = 0; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int ave_ld11_get_pinmode(struct ave_private *priv, + phy_interface_t phy_mode, u32 arg) +{ + if (arg > 0) + return -EINVAL; + + priv->pinmode_mask = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0); + + switch (phy_mode) { + case PHY_INTERFACE_MODE_INTERNAL: + priv->pinmode_val = 0; + break; + case PHY_INTERFACE_MODE_RMII: + priv->pinmode_val = SG_ETPINMODE_EXTPHY | SG_ETPINMODE_RMII(0); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int ave_ld20_get_pinmode(struct ave_private *priv, + phy_interface_t phy_mode, u32 arg) +{ + if (arg > 0) + return -EINVAL; + + priv->pinmode_mask = SG_ETPINMODE_RMII(0); + + switch (phy_mode) { + case PHY_INTERFACE_MODE_RMII: + priv->pinmode_val = SG_ETPINMODE_RMII(0); + break; + case PHY_INTERFACE_MODE_RGMII: + priv->pinmode_val = 0; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int ave_pxs3_get_pinmode(struct ave_private *priv, + phy_interface_t phy_mode, u32 arg) +{ + if (arg > 1) + return -EINVAL; + + priv->pinmode_mask = SG_ETPINMODE_RMII(arg); + + switch (phy_mode) { + case PHY_INTERFACE_MODE_RMII: + priv->pinmode_val = SG_ETPINMODE_RMII(arg); + break; + case PHY_INTERFACE_MODE_RGMII: + priv->pinmode_val = 0; + break; + default: + return -EINVAL; + } + + return 0; +} + static const struct ave_soc_data ave_pro4_data = { .is_desc_64bit = false, .clock_names = { @@ -1723,6 +1844,7 @@ static const struct ave_soc_data ave_pro4_data = { .reset_names = { "gio", "ether", }, + .get_pinmode = ave_pro4_get_pinmode, }; static const struct ave_soc_data ave_pxs2_data = { @@ -1733,6 +1855,7 @@ static const struct ave_soc_data ave_pxs2_data = { .reset_names = { "ether", }, + .get_pinmode = ave_pro4_get_pinmode, }; static const struct ave_soc_data ave_ld11_data = { @@ -1743,6 +1866,7 @@ static const struct ave_soc_data ave_ld11_data = { .reset_names = { "ether", }, + .get_pinmode = ave_ld11_get_pinmode, }; static const struct ave_soc_data ave_ld20_data = { @@ -1753,6 +1877,7 @@ static const struct ave_soc_data ave_ld20_data = { .reset_names = { "ether", }, + .get_pinmode = ave_ld20_get_pinmode, }; static const struct ave_soc_data ave_pxs3_data = { @@ -1763,6 +1888,7 @@ static const struct ave_soc_data ave_pxs3_data = { .reset_names = { "ether", }, + .get_pinmode = ave_pxs3_get_pinmode, }; static const struct of_device_id of_ave_match[] = {