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X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH for-2.12] fpu: Fix rounding mode for floatN_to_uintM_round_to_zero X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We incorrectly passed in the current rounding mode instead of float_round_to_zero. Signed-off-by: Richard Henderson --- Found while runnning SVE RISU tests; it should be visible with the right set of inputs to AdvSIMD RISU tests. r~ --- fpu/softfloat.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.14.3 Reviewed-by: Alex Bennée diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 6e16284e66..b46dccc63e 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -1486,8 +1486,8 @@ uint ## isz ## _t float ## fsz ## _to_uint ## isz ## _round_to_zero \ (float ## fsz a, float_status *s) \ { \ FloatParts p = float ## fsz ## _unpack_canonical(a, s); \ - return round_to_uint_and_pack(p, s->float_rounding_mode, \ - UINT ## isz ## _MAX, s); \ + return round_to_uint_and_pack(p, float_round_to_zero, \ + UINT ## isz ## _MAX, s); \ } FLOAT_TO_UINT(16, 16)