From patchwork Sat Mar 6 21:35:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 394550 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp548966jai; Sat, 6 Mar 2021 13:36:54 -0800 (PST) X-Google-Smtp-Source: ABdhPJy1WwgVntDS4/UWoUuJdlul/wdenzKP32cJSSXd9CbBOgPiP6lEb67sPQdzpYIGVql83/6/ X-Received: by 2002:a92:d7ce:: with SMTP id g14mr13489295ilq.255.1615066614456; Sat, 06 Mar 2021 13:36:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615066614; cv=none; d=google.com; s=arc-20160816; b=rbqzzSzJQ9nqjrKh6pilBWAlHjjU5UXD4ku9h92d8w1emHmKxIcHCb5GNNlBl0r4o3 v9SQg9fnmxW+IOOMWeqkEoWDCw+6RACg3m6J5uCHgxXbKv+9vjh9uETSoX9zIZOpFhDg oUmUCNxbua370rFK1yvwWujjZSLQuZh7SpFOU0/GfpPWhKznPGjiUjLpfslTmDA0sF5o ozg9oKZq/JdcPWx7groMcWvS5TinXe7szLAUPYZ6GS6I3Z3Qb/SSYUeIBa4T9/sij5K/ 4TtgzuBu4pJjfJdaZap1nxp1ruGwkrXNSTmS0/wDGCto9h00ZhKr8a+VlHpzXb7HUBMJ eYyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=CuWrYyiZWdulIwmEpBK4yxV1iSuukhkkcBuC0p9tN6M=; b=VHSa0xcJSlt1ugW0LpyEXu9QUegn1L8kMIGzX6XM6v2ZnZ8m/pqkSpISnoFVmA98J6 j/3X4Nv77SbO6bg7ApgaSL48byEXn4QAazAdOFzXWIFkgUF09fsaKKPkk5Ki9rIQRmXv nXR1C4VaO6PP2pO9QKaxBVc6NNBSnUtQHh86CMVlrg4OaqqIr4wzv147uJbRYfJf0zDV 6lnoSWtW8BI7XnVKWfOX/TTK6AtBOR4k42eUkdZ2QPJdlhWj3IkvjFgHCrWUqcz6pvvo UYuu5kCb7iCeqYKho0zYPjMRRX5aTwmO1dYovedTD8JvZf6PgLu4QLM0i8ppy0teDCAL wtug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UsuD6lFo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v24si6280396ioh.28.2021.03.06.13.36.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 06 Mar 2021 13:36:54 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UsuD6lFo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46708 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIebV-0006vy-Mi for patch@linaro.org; Sat, 06 Mar 2021 16:36:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56664) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIeay-0006vU-Bf for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:21 -0500 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:39921) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lIeav-0002wM-QL for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:20 -0500 Received: by mail-pl1-x62e.google.com with SMTP id j6so3104843plx.6 for ; Sat, 06 Mar 2021 13:36:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CuWrYyiZWdulIwmEpBK4yxV1iSuukhkkcBuC0p9tN6M=; b=UsuD6lFoeaAQyHElTQwPGm8OycHr/LFtX6U6I1OlQzj1Ib2yUVo6gPvafAjfy8sjOh rWa//ngTygk9c4OzgsBRmASsLJhqkhwOHKhZGIPCDRyk07ScjJ+AXG6XIHGWfO/Yb7Ck i9Z9OlTDQEvauzh9vrF/X/oC5mfJHimsUygF+7M9AW9HYGXkLPCMB17l6EUGP2TcLG/t 8JLXsUJi2JvI1naptR9HvVaXL7kwKB7DhyWpeDqGyKPn5/hs7UUERlamyj8C1iFoqcDg j3qybroDhpHMB5IO9jkIQ1M+VSTM3rmDbDc1szYISJVXbTBCD4YwDJcnFqM7R0nrt1to Guiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CuWrYyiZWdulIwmEpBK4yxV1iSuukhkkcBuC0p9tN6M=; b=P55SY7QUhFbSFkfbd7ty5chQf1s5aNuHY2x0vQREZLnARDUiJhLO5zRfccHM3PoxOQ 6JG8c4ve8eRSYwimbM8aOsXLCpRxDzQUhQsRMJfqz7tUAtdOsYbYM5HWBiE3UJpxOiQf b9O3COiJEaI/D1kU/oA/5KMEcWlYm/cZeKT9DcP9US8jQHZlQ2gyT4qV8OifjjNuBwM8 hjKMnwQI8yzosm2kyRbj90B86ldnxNHh7zEb/CasokvAKuGCNrVcoxrvtBKHz3v6FhsM PyLZsQyTcRXEeeLjbX4A7sy03tfYAQJ+djonQBxeePqA3hQ1TVe3xMTQdA/FfOy/6GcU TAxQ== X-Gm-Message-State: AOAM5313MMa5zINYft/sfANNoj+rsfYmMe3SP4axkUGmFWpZxloQdmn0 FXJZ09Fo3GAOhWt8lbuLNN3whQKdp+WJQw== X-Received: by 2002:a17:90a:840a:: with SMTP id j10mr1492484pjn.97.1615066576526; Sat, 06 Mar 2021 13:36:16 -0800 (PST) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id r30sm6365616pgu.86.2021.03.06.13.36.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Mar 2021 13:36:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 01/27] tcg/aarch64: Fix constant subtraction in tcg_out_addsub2 Date: Sat, 6 Mar 2021 13:35:47 -0800 Message-Id: <20210306213613.85168-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210306213613.85168-1-richard.henderson@linaro.org> References: <20210306213613.85168-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" An hppa guest executing 0x000000000000e05c: ldil L%10000,r4 0x000000000000e060: ldo 0(r4),r4 0x000000000000e064: sub r3,r4,sp produces ---- 000000000000e064 000000000000e068 sub2_i32 tmp0,tmp4,r3,$0x1,$0x10000,$0x0 after folding and constant propagation. Then we hit tcg-target.c.inc:640: tcg_out_insn_3401: Assertion `aimm <= 0xfff' failed. because aimm is in fact -16, but unsigned. The ((bl < 0) ^ sub) condition which negates bl is incorrect and will always lead to this abort. If the constant is positive, sub will make it negative; if the constant is negative, sub will keep it negative. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) -- 2.25.1 diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 1376cdc404..ec0a86d9d8 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1410,10 +1410,10 @@ static void tcg_out_addsubi(TCGContext *s, int ext, TCGReg rd, } } -static inline void tcg_out_addsub2(TCGContext *s, TCGType ext, TCGReg rl, - TCGReg rh, TCGReg al, TCGReg ah, - tcg_target_long bl, tcg_target_long bh, - bool const_bl, bool const_bh, bool sub) +static void tcg_out_addsub2(TCGContext *s, TCGType ext, TCGReg rl, + TCGReg rh, TCGReg al, TCGReg ah, + tcg_target_long bl, tcg_target_long bh, + bool const_bl, bool const_bh, bool sub) { TCGReg orig_rl = rl; AArch64Insn insn; @@ -1423,11 +1423,13 @@ static inline void tcg_out_addsub2(TCGContext *s, TCGType ext, TCGReg rl, } if (const_bl) { - insn = I3401_ADDSI; - if ((bl < 0) ^ sub) { - insn = I3401_SUBSI; + if (bl < 0) { bl = -bl; + insn = sub ? I3401_ADDSI : I3401_SUBSI; + } else { + insn = sub ? I3401_SUBSI : I3401_ADDSI; } + if (unlikely(al == TCG_REG_XZR)) { /* ??? We want to allow al to be zero for the benefit of negation via subtraction. However, that leaves open the From patchwork Sat Mar 6 21:35:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 394551 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp548967jai; Sat, 6 Mar 2021 13:36:54 -0800 (PST) X-Google-Smtp-Source: ABdhPJyDGfIbmFKdRujsqKeVxcHdzqv3q6h/0t2TT3KMOHVsnYWp45KmicIqofgx4i572RAeuaiy X-Received: by 2002:a5e:9612:: with SMTP id a18mr13216551ioq.13.1615066614458; Sat, 06 Mar 2021 13:36:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615066614; cv=none; d=google.com; s=arc-20160816; b=WJndu+jeYb25qhFSoTGhpEGzDutrivxZTrpUT2YzAI2ZjwltRD8qG2h9ZBWa034Ogl ytUALefS0v8ywi53pqu66ckth0JtNZj/rfDnxGAvpxZb/6UALTmhggyZMA7rr/j/Zwuf ZgfvoamtPhSz2V22Am63QeeUbavszAweHUtP8YTnhBCSsi+kH8w8761BXZV/zBg1w0OA jkBUbVfDcC4gum44lseJX10Y3TgTVjkmbcWXcL6OWAe7WPU/Nx1DF/d9ejciTjR4SP8H u7SE65PldtozYRM9yRFp0UtAOvcz2pFubi8nj1RHpAi6O01rk35z1utaNZ3QmELCr0Un Pe7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=f+XOqZ5nVIKFE5Wvq06250YDVlIY9I1NmppdkJVW9Dc=; b=DGqQfnYPDSdo+LYUSCzTUYSoi/JqCqguzT/zivqibV00l0olgWefHhYjrGcj8Q7iO6 ggJTIJq75WdSYJC2TeDkc6IO2iNYsKP6Jj9ZxqC38Q8sRFgtImjLsFk49EHnjD5cYw8I sN1jekaw9Co9mf4L+2gHZutWEE6lXWbrbnZcg5ELQlpPmyxphjeswzji7ZWcpCDUYaZQ VWankL0Hwfu28xELvNj28phlLkEMc3a8XsQcJ7GBRCz/AV3tpZNVxicvpbvY06HNTunN AVCjTlC2B0oxlCP2NO5xm9E+67QWi6m+6HbZD6OdXoEKl7n6CDzPjgR7eqTDm8ZoiUuM Bj/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Sz/Mmaci"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x18si7234142jas.18.2021.03.06.13.36.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 06 Mar 2021 13:36:54 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Sz/Mmaci"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:46722 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIebV-0006wK-MV for patch@linaro.org; Sat, 06 Mar 2021 16:36:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56698) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIeaz-0006vY-U9 for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:22 -0500 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]:35731) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lIeay-0002wS-3D for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:21 -0500 Received: by mail-pl1-x632.google.com with SMTP id g20so3116263plo.2 for ; Sat, 06 Mar 2021 13:36:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=f+XOqZ5nVIKFE5Wvq06250YDVlIY9I1NmppdkJVW9Dc=; b=Sz/MmaciIMkFOxgJbgWOV1MZan9hflilUjfGq9gB4vrU1xEFXDN2Aa0mTGsCxxFizU DkoJKrBgPoRbJ4c4UreJYSt6klVXJfgut3LUbyZjsWKFnAE9gyfiCzsqzg6e1uh+1lAr EGjZdRhuScB9Qxyw7zmecdVn7pRmqpCChlR4Nwk0eCozebnuI+bvpRBmzsNxdtkzOryT rsGPR9LUB6F9WLgkHeN39iahMN7JdYnagwKU7isen2qX45qHAjz/PBBAG/Qud6ikkIJG az5+IxfUgu3uQ1a9M4ck//d/MCJLznXemOoJ/QFS0+VvndAj5JGzPJgTCZLoI8usrQXq iLyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=f+XOqZ5nVIKFE5Wvq06250YDVlIY9I1NmppdkJVW9Dc=; b=YsmdO5/qUc8RrCFJGOXV2MtymQJSwe9vkHgxDNwKTNamM+XhZ09qwWs0M+peYPeT+H QHdYCspeFzBir5wi9AtzHau4LUTam8PyCJCicr+xA90lH6t6g7LjMzKe/3RMiJ0Bi+fd bo/S6NPfthLxtBTXqhau372BZW/K5RFaV3olTQv8WDAKbXYGyowCJ0eIjXJDuwQYE5lo iRm8v0MQ7XdRBnrLHSFKcMH9OxKOYyGUqqZgZVcP3vHzzzFnj9fTgW6ZCUnNol+LsobH 9B9ursz0x2/58Ni1LKXGU5mgvRj6pmtYGVG8SdphAWVaEGnr+7Zqir7SJvLjgizrKBhz E3EA== X-Gm-Message-State: AOAM531PBhxEoMjipn7u79ef7DyFY+iiXmA1GNmn1MQ7w7pQhFfYfJUM D86thS1CGwgHV9Tu1pnlPy4tH4pXxvPVCw== X-Received: by 2002:a17:902:c40a:b029:e5:b98e:a4a with SMTP id k10-20020a170902c40ab02900e5b98e0a4amr14217031plk.67.1615066577530; Sat, 06 Mar 2021 13:36:17 -0800 (PST) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id r30sm6365616pgu.86.2021.03.06.13.36.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Mar 2021 13:36:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 02/27] tcg/aarch64: Fix I3617_CMLE0 Date: Sat, 6 Mar 2021 13:35:48 -0800 Message-Id: <20210306213613.85168-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210306213613.85168-1-richard.henderson@linaro.org> References: <20210306213613.85168-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Fix a typo in the encodeing of the cmle (zero) instruction. Fixes: 14e4c1e2355 ("tcg/aarch64: Add vector operations") Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.25.1 diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index ec0a86d9d8..c8e41dd638 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -561,7 +561,7 @@ typedef enum { I3617_CMEQ0 = 0x0e209800, I3617_CMLT0 = 0x0e20a800, I3617_CMGE0 = 0x2e208800, - I3617_CMLE0 = 0x2e20a800, + I3617_CMLE0 = 0x2e209800, I3617_NOT = 0x2e205800, I3617_ABS = 0x0e20b800, I3617_NEG = 0x2e20b800, From patchwork Sat Mar 6 21:35:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 394555 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp549716jai; Sat, 6 Mar 2021 13:38:42 -0800 (PST) X-Google-Smtp-Source: ABdhPJzt9A/poCgmgrhSvZpdWZQfnnkMR8tOGATAxyumFGIpBDzYZQIxolxmmVbYAUBt3/Cx4Kjx X-Received: by 2002:a92:1a51:: with SMTP id z17mr14829078ill.295.1615066722898; Sat, 06 Mar 2021 13:38:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615066722; cv=none; d=google.com; s=arc-20160816; b=Ik3hw2m+Kbeq5/wfNPp6jKIcGdQT5V8UluKroDL7wx8jJMpOUCGCo4jTI1sqATNlpX qZjXQmtIwd53Rphb2AkYym/lk5+bvlxziAETDQf22iOSAHZLfLRFKEdqJtyVUwLxNmUP EyqJjnkFwXp+6yM3FHdwClMTSS/P+uxBwYdLD7P4xPO7f97qZZKqR9Tl0P6icIuOHGej H7zXpYgkLlRbQGgsEt4HMugEe71zoaBvWLqnXqshWuxbQmzTM6k0N4HFgZfYS/y5zVrd ouRenCrzU+MwpUKKwKO5mPe1Hb4xuqs+jdGGnfomBTZq9RAgYUmJkEz0rpABYdL9lJEk +GhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=FqzYpQQUR12rN4BKMEYAAfl4rSAyL7gT/RoypMfN2sE=; b=FrcWh5CBLHQQtY3kn/GCyWGVQEnTwe3G9PGTAlG2S1fBfdRFAzb04ZXFE7vaiUIHUv 1IgqzpAeaRPUcPSb6j9X7OTmPdQbI/SDhx+Ym/VhAXgLqY41Q+jxeJ3SVoUY0Hgmt6ZT Xi6CmjpUy04pXqxmvsAiwBEOLAKnbOQoWEHPRhIDKXSYtYkJklezpASMUqPBb3wqX1Kr wOv+wxJ2h2Xycqo45eddYtazEywR7oLVnZrQN6VoLKMcyJcbaSQMpf6YsfmSFRCSRklo yUeAMe3OnIwf+coJZvA+1YAYw8dr+w5eQCbjHc8yFxdc63S4erYFOcoSvGIVst2VnAXB +1qg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=T5rRbvXU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tested-by: Stefan Weil Buglink: https://bugs.launchpad.net/qemu/+bug/1916112 Fixes: 14e4c1e2355 ("tcg/aarch64: Add vector operations") Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 211 ++++++++++++++++++++++++++++++----- 1 file changed, 181 insertions(+), 30 deletions(-) -- 2.25.1 diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index c8e41dd638..fcaa5aface 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -519,6 +519,39 @@ typedef enum { I3606_BIC = 0x2f001400, I3606_ORR = 0x0f001400, + /* AdvSIMD scalar shift by immediate */ + I3609_SSHR = 0x5f000400, + I3609_SSRA = 0x5f001400, + I3609_SHL = 0x5f005400, + I3609_USHR = 0x7f000400, + I3609_USRA = 0x7f001400, + I3609_SLI = 0x7f005400, + + /* AdvSIMD scalar three same */ + I3611_SQADD = 0x5e200c00, + I3611_SQSUB = 0x5e202c00, + I3611_CMGT = 0x5e203400, + I3611_CMGE = 0x5e203c00, + I3611_SSHL = 0x5e204400, + I3611_ADD = 0x5e208400, + I3611_CMTST = 0x5e208c00, + I3611_UQADD = 0x7e200c00, + I3611_UQSUB = 0x7e202c00, + I3611_CMHI = 0x7e203400, + I3611_CMHS = 0x7e203c00, + I3611_USHL = 0x7e204400, + I3611_SUB = 0x7e208400, + I3611_CMEQ = 0x7e208c00, + + /* AdvSIMD scalar two-reg misc */ + I3612_CMGT0 = 0x5e208800, + I3612_CMEQ0 = 0x5e209800, + I3612_CMLT0 = 0x5e20a800, + I3612_ABS = 0x5e20b800, + I3612_CMGE0 = 0x7e208800, + I3612_CMLE0 = 0x7e209800, + I3612_NEG = 0x7e20b800, + /* AdvSIMD shift by immediate */ I3614_SSHR = 0x0f000400, I3614_SSRA = 0x0f001400, @@ -735,6 +768,25 @@ static void tcg_out_insn_3606(TCGContext *s, AArch64Insn insn, bool q, | (imm8 & 0xe0) << (16 - 5) | (imm8 & 0x1f) << 5); } +static void tcg_out_insn_3609(TCGContext *s, AArch64Insn insn, + TCGReg rd, TCGReg rn, unsigned immhb) +{ + tcg_out32(s, insn | immhb << 16 | (rn & 0x1f) << 5 | (rd & 0x1f)); +} + +static void tcg_out_insn_3611(TCGContext *s, AArch64Insn insn, + unsigned size, TCGReg rd, TCGReg rn, TCGReg rm) +{ + tcg_out32(s, insn | (size << 22) | (rm & 0x1f) << 16 + | (rn & 0x1f) << 5 | (rd & 0x1f)); +} + +static void tcg_out_insn_3612(TCGContext *s, AArch64Insn insn, + unsigned size, TCGReg rd, TCGReg rn) +{ + tcg_out32(s, insn | (size << 22) | (rn & 0x1f) << 5 | (rd & 0x1f)); +} + static void tcg_out_insn_3614(TCGContext *s, AArch64Insn insn, bool q, TCGReg rd, TCGReg rn, unsigned immhb) { @@ -2236,23 +2288,38 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl, unsigned vece, const TCGArg *args, const int *const_args) { - static const AArch64Insn cmp_insn[16] = { + static const AArch64Insn cmp_vec_insn[16] = { [TCG_COND_EQ] = I3616_CMEQ, [TCG_COND_GT] = I3616_CMGT, [TCG_COND_GE] = I3616_CMGE, [TCG_COND_GTU] = I3616_CMHI, [TCG_COND_GEU] = I3616_CMHS, }; - static const AArch64Insn cmp0_insn[16] = { + static const AArch64Insn cmp_scalar_insn[16] = { + [TCG_COND_EQ] = I3611_CMEQ, + [TCG_COND_GT] = I3611_CMGT, + [TCG_COND_GE] = I3611_CMGE, + [TCG_COND_GTU] = I3611_CMHI, + [TCG_COND_GEU] = I3611_CMHS, + }; + static const AArch64Insn cmp0_vec_insn[16] = { [TCG_COND_EQ] = I3617_CMEQ0, [TCG_COND_GT] = I3617_CMGT0, [TCG_COND_GE] = I3617_CMGE0, [TCG_COND_LT] = I3617_CMLT0, [TCG_COND_LE] = I3617_CMLE0, }; + static const AArch64Insn cmp0_scalar_insn[16] = { + [TCG_COND_EQ] = I3612_CMEQ0, + [TCG_COND_GT] = I3612_CMGT0, + [TCG_COND_GE] = I3612_CMGE0, + [TCG_COND_LT] = I3612_CMLT0, + [TCG_COND_LE] = I3612_CMLE0, + }; TCGType type = vecl + TCG_TYPE_V64; unsigned is_q = vecl; + bool is_scalar = !is_q && vece == MO_64; TCGArg a0, a1, a2, a3; int cmode, imm8; @@ -2271,19 +2338,35 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, tcg_out_dupm_vec(s, type, vece, a0, a1, a2); break; case INDEX_op_add_vec: - tcg_out_insn(s, 3616, ADD, is_q, vece, a0, a1, a2); + if (is_scalar) { + tcg_out_insn(s, 3611, ADD, vece, a0, a1, a2); + } else { + tcg_out_insn(s, 3616, ADD, is_q, vece, a0, a1, a2); + } break; case INDEX_op_sub_vec: - tcg_out_insn(s, 3616, SUB, is_q, vece, a0, a1, a2); + if (is_scalar) { + tcg_out_insn(s, 3611, SUB, vece, a0, a1, a2); + } else { + tcg_out_insn(s, 3616, SUB, is_q, vece, a0, a1, a2); + } break; case INDEX_op_mul_vec: tcg_out_insn(s, 3616, MUL, is_q, vece, a0, a1, a2); break; case INDEX_op_neg_vec: - tcg_out_insn(s, 3617, NEG, is_q, vece, a0, a1); + if (is_scalar) { + tcg_out_insn(s, 3612, NEG, vece, a0, a1); + } else { + tcg_out_insn(s, 3617, NEG, is_q, vece, a0, a1); + } break; case INDEX_op_abs_vec: - tcg_out_insn(s, 3617, ABS, is_q, vece, a0, a1); + if (is_scalar) { + tcg_out_insn(s, 3612, ABS, vece, a0, a1); + } else { + tcg_out_insn(s, 3617, ABS, is_q, vece, a0, a1); + } break; case INDEX_op_and_vec: if (const_args[2]) { @@ -2337,16 +2420,32 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, tcg_out_insn(s, 3616, EOR, is_q, 0, a0, a1, a2); break; case INDEX_op_ssadd_vec: - tcg_out_insn(s, 3616, SQADD, is_q, vece, a0, a1, a2); + if (is_scalar) { + tcg_out_insn(s, 3611, SQADD, vece, a0, a1, a2); + } else { + tcg_out_insn(s, 3616, SQADD, is_q, vece, a0, a1, a2); + } break; case INDEX_op_sssub_vec: - tcg_out_insn(s, 3616, SQSUB, is_q, vece, a0, a1, a2); + if (is_scalar) { + tcg_out_insn(s, 3611, SQSUB, vece, a0, a1, a2); + } else { + tcg_out_insn(s, 3616, SQSUB, is_q, vece, a0, a1, a2); + } break; case INDEX_op_usadd_vec: - tcg_out_insn(s, 3616, UQADD, is_q, vece, a0, a1, a2); + if (is_scalar) { + tcg_out_insn(s, 3611, UQADD, vece, a0, a1, a2); + } else { + tcg_out_insn(s, 3616, UQADD, is_q, vece, a0, a1, a2); + } break; case INDEX_op_ussub_vec: - tcg_out_insn(s, 3616, UQSUB, is_q, vece, a0, a1, a2); + if (is_scalar) { + tcg_out_insn(s, 3611, UQSUB, vece, a0, a1, a2); + } else { + tcg_out_insn(s, 3616, UQSUB, is_q, vece, a0, a1, a2); + } break; case INDEX_op_smax_vec: tcg_out_insn(s, 3616, SMAX, is_q, vece, a0, a1, a2); @@ -2364,22 +2463,46 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1); break; case INDEX_op_shli_vec: - tcg_out_insn(s, 3614, SHL, is_q, a0, a1, a2 + (8 << vece)); + if (is_scalar) { + tcg_out_insn(s, 3609, SHL, a0, a1, a2 + (8 << vece)); + } else { + tcg_out_insn(s, 3614, SHL, is_q, a0, a1, a2 + (8 << vece)); + } break; case INDEX_op_shri_vec: - tcg_out_insn(s, 3614, USHR, is_q, a0, a1, (16 << vece) - a2); + if (is_scalar) { + tcg_out_insn(s, 3609, USHR, a0, a1, (16 << vece) - a2); + } else { + tcg_out_insn(s, 3614, USHR, is_q, a0, a1, (16 << vece) - a2); + } break; case INDEX_op_sari_vec: - tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2); + if (is_scalar) { + tcg_out_insn(s, 3609, SSHR, a0, a1, (16 << vece) - a2); + } else { + tcg_out_insn(s, 3614, SSHR, is_q, a0, a1, (16 << vece) - a2); + } break; case INDEX_op_aa64_sli_vec: - tcg_out_insn(s, 3614, SLI, is_q, a0, a2, args[3] + (8 << vece)); + if (is_scalar) { + tcg_out_insn(s, 3609, SLI, a0, a2, args[3] + (8 << vece)); + } else { + tcg_out_insn(s, 3614, SLI, is_q, a0, a2, args[3] + (8 << vece)); + } break; case INDEX_op_shlv_vec: - tcg_out_insn(s, 3616, USHL, is_q, vece, a0, a1, a2); + if (is_scalar) { + tcg_out_insn(s, 3611, USHL, vece, a0, a1, a2); + } else { + tcg_out_insn(s, 3616, USHL, is_q, vece, a0, a1, a2); + } break; case INDEX_op_aa64_sshl_vec: - tcg_out_insn(s, 3616, SSHL, is_q, vece, a0, a1, a2); + if (is_scalar) { + tcg_out_insn(s, 3611, SSHL, vece, a0, a1, a2); + } else { + tcg_out_insn(s, 3616, SSHL, is_q, vece, a0, a1, a2); + } break; case INDEX_op_cmp_vec: { @@ -2388,30 +2511,58 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, if (cond == TCG_COND_NE) { if (const_args[2]) { - tcg_out_insn(s, 3616, CMTST, is_q, vece, a0, a1, a1); + if (is_scalar) { + tcg_out_insn(s, 3611, CMTST, vece, a0, a1, a1); + } else { + tcg_out_insn(s, 3616, CMTST, is_q, vece, a0, a1, a1); + } } else { - tcg_out_insn(s, 3616, CMEQ, is_q, vece, a0, a1, a2); + if (is_scalar) { + tcg_out_insn(s, 3611, CMEQ, vece, a0, a1, a2); + } else { + tcg_out_insn(s, 3616, CMEQ, is_q, vece, a0, a1, a2); + } tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a0); } } else { if (const_args[2]) { - insn = cmp0_insn[cond]; - if (insn) { - tcg_out_insn_3617(s, insn, is_q, vece, a0, a1); - break; + if (is_scalar) { + insn = cmp0_scalar_insn[cond]; + if (insn) { + tcg_out_insn_3612(s, insn, vece, a0, a1); + break; + } + } else { + insn = cmp0_vec_insn[cond]; + if (insn) { + tcg_out_insn_3617(s, insn, is_q, vece, a0, a1); + break; + } } tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0); a2 = TCG_VEC_TMP; } - insn = cmp_insn[cond]; - if (insn == 0) { - TCGArg t; - t = a1, a1 = a2, a2 = t; - cond = tcg_swap_cond(cond); - insn = cmp_insn[cond]; - tcg_debug_assert(insn != 0); + if (is_scalar) { + insn = cmp_scalar_insn[cond]; + if (insn == 0) { + TCGArg t; + t = a1, a1 = a2, a2 = t; + cond = tcg_swap_cond(cond); + insn = cmp_scalar_insn[cond]; + tcg_debug_assert(insn != 0); + } + tcg_out_insn_3611(s, insn, vece, a0, a1, a2); + } else { + insn = cmp_vec_insn[cond]; + if (insn == 0) { + TCGArg t; + t = a1, a1 = a2, a2 = t; + cond = tcg_swap_cond(cond); + insn = cmp_vec_insn[cond]; + tcg_debug_assert(insn != 0); + } + tcg_out_insn_3616(s, insn, is_q, vece, a0, a1, a2); } - tcg_out_insn_3616(s, insn, is_q, vece, a0, a1, a2); } } break; From patchwork Sat Mar 6 21:35:50 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 394560 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp550601jai; Sat, 6 Mar 2021 13:40:35 -0800 (PST) X-Google-Smtp-Source: ABdhPJzlnV9thnqO7vE6F+UinIybGKf7iM3FPhcabrje72c2oZXjt8Hw0X1Knw0S60cKE+uL/CCJ X-Received: by 2002:a02:a691:: with SMTP id j17mr16762941jam.14.1615066835490; Sat, 06 Mar 2021 13:40:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615066835; cv=none; d=google.com; s=arc-20160816; b=iC+7rf+gvNpaq6UPUWXGLIYbNQPcdVBjokpyFTemkSeG+0k6K71UYKsPNhzu+iApGn fbyvx8NuB0zEZfuO+IP4zW5n5ueKuvnMR2ocQZ3jTtf3RoCzpd7hBLwmIUsXHd6RmxUD 9FYVAULPJwokOKdjsAkJsMQFPjyVFYpSf8NYPUER9qd9Rd3xSc5ETkDl5omBr5Q3VKkP /PLnlM/FYwhhs3ehKd/M+HKr+Qp1S4TRZB57BC9wsnrny4C2a8vFyCLSiiuE9JGq2Axj 4Qui34/VFEOf+4Or+VWXvQDM7sX3IXC1zdUEFKw3JJgntu2QPM97wgIBxuH0htz3IkwH 6rsA== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id t26si6044915jan.106.2021.03.06.13.40.35 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 06 Mar 2021 13:40:35 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Deo7r2jK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35692 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIef4-0005QP-TO for patch@linaro.org; Sat, 06 Mar 2021 16:40:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56762) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIeb5-0006w5-1Q for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:27 -0500 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:34301) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lIeaz-0002wh-65 for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:26 -0500 Received: by mail-pg1-x52d.google.com with SMTP id l2so3801219pgb.1 for ; Sat, 06 Mar 2021 13:36:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qXvTR6xq0CezXE1eROwLDPe0hk6sXQteYv5BD9wz3/8=; b=Deo7r2jKBt95/Hkqus9IbqI/M9yoj0kjLiLb3zPCJzM5cdpYlbJG+m2rGfZl2osm13 sCvLmkffNEKLeZXVdpDDd20YQfYYmj0YOj1nwKf9quk6g5bvIpAVwlXWLCwJM14EFoqR s/sNWE6i8i9y7TRZ5M3LXykHD7cypFTl6+eaHC1hdFdcPqqShJJ/8o64RNrWBkEQCe1w Z/OLLKDiBdmMB7DnOD8bmeEo/COp716zhQI6MyrYyVwL9Nw68l19Y94E1mxcDVGFJ4Nz pJhxGFvimL0H5TiBu8p876Pi6a0GWQ7C7PzHapJm2t99qrd2UFyBNzQ+w2crHKwjmF1R PlCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qXvTR6xq0CezXE1eROwLDPe0hk6sXQteYv5BD9wz3/8=; b=Bqw9F4H1vx3h9r2ANr87Wt9b1BUgxeuTEtGUgRjE5v15R5QWSY9Fw6nMtaKLEoSNux reGfanvR1x0h5liXIIKXZrKCVc8btBs64TCQHGpHMLdHUk2lex0NLxuKKG90T79TgAU+ kTk9mu7fzGdHP0gKyem/1JZZebKbAZ353Ls+oOycjLhIMZwynkcM61xsUr45HQSxvO3c wq1+T6oNHn+qVOryAr0bPL0xMtk6uVLYxZdckgxZxh2yj+YBn4Nk7urdEzpJtnXbBebM qb55xAnSiFWJquRKt9EMN68YrBZzMlmDHjjwGte+3m0TCG98i6UZeAT6fRKSrNicJwUt vJcg== X-Gm-Message-State: AOAM530+6KJxiKtpXLf3o94dV5mFpkNcH8MOc64qohA22vG5RKlQo/vO ZatFYYQY85p78oAZFC2HBUEXO/R58Z/j+w== X-Received: by 2002:a63:7a4b:: with SMTP id j11mr14175097pgn.369.1615066579868; Sat, 06 Mar 2021 13:36:19 -0800 (PST) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id r30sm6365616pgu.86.2021.03.06.13.36.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Mar 2021 13:36:19 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 04/27] tcg/tci: Use exec/cpu_ldst.h interfaces Date: Sat, 6 Mar 2021 13:35:50 -0800 Message-Id: <20210306213613.85168-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210306213613.85168-1-richard.henderson@linaro.org> References: <20210306213613.85168-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use the provided cpu_ldst.h interfaces. This fixes the build vs the unconverted uses of g2h(), adds missed memory trace events, and correctly recognizes when a SIGSEGV belongs to the guest via set_helper_retaddr(). Fixes: 3e8f1628e864 Tested-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci.c | 73 +++++++++++++++++++++---------------------------------- 1 file changed, 28 insertions(+), 45 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index fb3c97aaf1..1c667537fe 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -346,51 +346,34 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition) return result; } -#ifdef CONFIG_SOFTMMU -# define qemu_ld_ub \ - helper_ret_ldub_mmu(env, taddr, oi, (uintptr_t)tb_ptr) -# define qemu_ld_leuw \ - helper_le_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr) -# define qemu_ld_leul \ - helper_le_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr) -# define qemu_ld_leq \ - helper_le_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr) -# define qemu_ld_beuw \ - helper_be_lduw_mmu(env, taddr, oi, (uintptr_t)tb_ptr) -# define qemu_ld_beul \ - helper_be_ldul_mmu(env, taddr, oi, (uintptr_t)tb_ptr) -# define qemu_ld_beq \ - helper_be_ldq_mmu(env, taddr, oi, (uintptr_t)tb_ptr) -# define qemu_st_b(X) \ - helper_ret_stb_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) -# define qemu_st_lew(X) \ - helper_le_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) -# define qemu_st_lel(X) \ - helper_le_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) -# define qemu_st_leq(X) \ - helper_le_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) -# define qemu_st_bew(X) \ - helper_be_stw_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) -# define qemu_st_bel(X) \ - helper_be_stl_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) -# define qemu_st_beq(X) \ - helper_be_stq_mmu(env, taddr, X, oi, (uintptr_t)tb_ptr) -#else -# define qemu_ld_ub ldub_p(g2h(taddr)) -# define qemu_ld_leuw lduw_le_p(g2h(taddr)) -# define qemu_ld_leul (uint32_t)ldl_le_p(g2h(taddr)) -# define qemu_ld_leq ldq_le_p(g2h(taddr)) -# define qemu_ld_beuw lduw_be_p(g2h(taddr)) -# define qemu_ld_beul (uint32_t)ldl_be_p(g2h(taddr)) -# define qemu_ld_beq ldq_be_p(g2h(taddr)) -# define qemu_st_b(X) stb_p(g2h(taddr), X) -# define qemu_st_lew(X) stw_le_p(g2h(taddr), X) -# define qemu_st_lel(X) stl_le_p(g2h(taddr), X) -# define qemu_st_leq(X) stq_le_p(g2h(taddr), X) -# define qemu_st_bew(X) stw_be_p(g2h(taddr), X) -# define qemu_st_bel(X) stl_be_p(g2h(taddr), X) -# define qemu_st_beq(X) stq_be_p(g2h(taddr), X) -#endif +#define qemu_ld_ub \ + cpu_ldub_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_ld_leuw \ + cpu_lduw_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_ld_leul \ + cpu_ldl_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_ld_leq \ + cpu_ldq_le_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_ld_beuw \ + cpu_lduw_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_ld_beul \ + cpu_ldl_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_ld_beq \ + cpu_ldq_be_mmuidx_ra(env, taddr, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_st_b(X) \ + cpu_stb_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_st_lew(X) \ + cpu_stw_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_st_lel(X) \ + cpu_stl_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_st_leq(X) \ + cpu_stq_le_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_st_bew(X) \ + cpu_stw_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_st_bel(X) \ + cpu_stl_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) +#define qemu_st_beq(X) \ + cpu_stq_be_mmuidx_ra(env, taddr, X, get_mmuidx(oi), (uintptr_t)tb_ptr) #if TCG_TARGET_REG_BITS == 64 # define CASE_32_64(x) \ From patchwork Sat Mar 6 21:35:51 2021 Content-Type: text/plain; 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[209.51.188.17]) by mx.google.com with ESMTPS id y1si7081338ybq.124.2021.03.06.13.39.06 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 06 Mar 2021 13:39:06 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=m1Ai1dw9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55330 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIedd-00021j-Ne for patch@linaro.org; Sat, 06 Mar 2021 16:39:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56728) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIeb1-0006vk-TR for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:25 -0500 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]:39097) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lIeaz-0002wq-UD for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:23 -0500 Received: by mail-pf1-x42e.google.com with SMTP id 18so4646694pfo.6 for ; Sat, 06 Mar 2021 13:36:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=myPurBGQOJ9HRp/gWQglk2sYpbZ88UPxyO7dwBmpmMU=; b=m1Ai1dw9Za2kqbDvuaKHBLrY1mMGZR+HzdzI5hAX+4V0K0PRn1V3NrF1bEPOZqodSM UWiZ/7MEFLXbu8wjKqbJSw0W3NN/X7H7qFWnqzVuX1ElhFIRGOKNXxVhkwgGTx3JrKf+ N4ZCq+P9b8tvYoPzB1B1MeYiNkpp2e6kJgwW3/AfTJBRU3TpZDlqxWvokHAqDTVp7NY7 h6XdbTPf0LZxSrLiosV+DiukBsdvBdbQm1MqeAfco+A0Jbz/7okO74zqYtq4ueA/Dm9S 9dV4g9DNauy+FGsTWIDyWkoStzDdP6VLngPuRqKT+3o/jhn/2J0QeeFXPl42BMpOwutb oLcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=myPurBGQOJ9HRp/gWQglk2sYpbZ88UPxyO7dwBmpmMU=; b=qdK9zZ4j4kTUxOPkratyn2mDNurdSJAkE4ZFe1juAQmSLGEfzyWe/1Be9Q/yMhUO2R 5GnME5VtonwsAAx6Y7NXoUgeIvWlrSRq9Czno9F8l2pwHpkbaHoOpNEwNTgxNCw///DR V54AlQcy9aTh2AHggHswoG7Iv6nYKxYKTmNZoOF5IGOR2SccHUIrvTFMLEz/DL+Qr/Ve xtjzkXHze1+rMFhwW8rih3VDksh+DI06A7KswQo1kAIpcrpZsbFXWhJKrH56evnWcLbl /90fRo9tWNHUZ9iAHq5RBID4L8Smv0aqlVz9lchvURnjyw02S0aSgmECSKIFxprd7UBg iIFQ== X-Gm-Message-State: AOAM532pghlo4i/q1H3DRqR0HCaR02bE7IArXYyp1QD9A8/l9Tc7rZaj u7dRXhnwEM6vCtUowokzSPZOc45g9MH1kg== X-Received: by 2002:a63:1958:: with SMTP id 24mr14477563pgz.320.1615066580592; Sat, 06 Mar 2021 13:36:20 -0800 (PST) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id r30sm6365616pgu.86.2021.03.06.13.36.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Mar 2021 13:36:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 05/27] tcg: Split out tcg_raise_tb_overflow Date: Sat, 6 Mar 2021 13:35:51 -0800 Message-Id: <20210306213613.85168-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210306213613.85168-1-richard.henderson@linaro.org> References: <20210306213613.85168-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Allow other places in tcg to restart with a smaller tb. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/tcg/tcg.c b/tcg/tcg.c index 63a12b197b..bbe3dcee03 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -346,6 +346,12 @@ static void set_jmp_reset_offset(TCGContext *s, int which) s->tb_jmp_reset_offset[which] = tcg_current_code_size(s); } +/* Signal overflow, starting over with fewer guest insns. */ +static void QEMU_NORETURN tcg_raise_tb_overflow(TCGContext *s) +{ + siglongjmp(s->jmp_trans, -2); +} + #define C_PFX1(P, A) P##A #define C_PFX2(P, A, B) P##A##_##B #define C_PFX3(P, A, B, C) P##A##_##B##_##C @@ -1310,8 +1316,7 @@ static TCGTemp *tcg_temp_alloc(TCGContext *s) int n = s->nb_temps++; if (n >= TCG_MAX_TEMPS) { - /* Signal overflow, starting over with fewer guest insns. */ - siglongjmp(s->jmp_trans, -2); + tcg_raise_tb_overflow(s); } return memset(&s->temps[n], 0, sizeof(TCGTemp)); } From patchwork Sat Mar 6 21:35:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 394557 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp549934jai; Sat, 6 Mar 2021 13:39:06 -0800 (PST) X-Google-Smtp-Source: ABdhPJxFM1KAZT6Tx/G10F4HotYw2wzDWnbQ4enpUgrHzYQ7msiAG+P3OL4XaS9O5d94A7rcLDWk X-Received: by 2002:a25:d14d:: with SMTP id i74mr22604662ybg.38.1615066746500; Sat, 06 Mar 2021 13:39:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615066746; cv=none; d=google.com; s=arc-20160816; b=ON7yf9ugvmyZGuVenHl9HaWIINKE1ZD+koiaKkABUzlzWH2eVHu4PXKCQaqD/HbqQ4 oiBSdkC467aQbMKNKgk75eJmlc897/0XDoqtkoJJs/qOTPiXQA6nolTQnKvY3i70XxDX 6HOJdttYfe56kRvQihP1z9ama28BYG3V+NhT77iCuOSJIt1JIL4rx/vJfnEL+HsN44Zh JeI5apb/J6zwZY+Yf+SZU60EFxc/RMVtn5Xahdzij7ZxRTsB2noL/IvDLLPsPYSZzbah L17uRT5Vg0DSaJhZzlf7ZyZlDDKTZASH/onQn2589uVwUWzWL+WOPv7+E1gXDP9Y2fm1 mUyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vXWtOAbqO0IiL4x1PJ+ry/MmusWHvhWYDh4bY00za1s=; b=Mj3aScAiRUKaD/hWnWvFlxoJnLRgUaYoqGf/VAP7OjdROmHZRcIj7aaqzxKfY5j/6W YKOOcOz3BJ/iJe7F3a0ykhtuPap+FfKDNv3u5duKnzovfMSKhEBT7yHnsBYDhERXP2pc h2nVkPf6dFZZ/MRJr4XgUX7lX06Y7FeLw2vJBgRyUOsfvlI0d9OnvM05rNLt6JoeOY3h VovF2h/VBoTgcF6kLjnBSY1+cDKXmjJ7wg04dGm8UAC5JCBkQhqkSjlH2YelH9J1Q5tI TxhnwXNivbJWiwS2I+d3g8R5+D47prh4kesanaYN+vqBfI5Ys5W7J50IfltLQHi4/cdz 4odA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kpd50Ibp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 130si6483646ybu.189.2021.03.06.13.39.06 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 06 Mar 2021 13:39:06 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kpd50Ibp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:55392 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIedd-00023E-UK for patch@linaro.org; Sat, 06 Mar 2021 16:39:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56832) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIeb9-0006y7-AP for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:32 -0500 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:36968) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lIeb1-0002x1-0l for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:31 -0500 Received: by mail-pg1-x533.google.com with SMTP id o10so3810024pgg.4 for ; Sat, 06 Mar 2021 13:36:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vXWtOAbqO0IiL4x1PJ+ry/MmusWHvhWYDh4bY00za1s=; b=kpd50IbpVc4XoNRRhBIyqS/ZxPYamEXvdvmIBrR7iaiaguawXE8gkB9DbAyDD452Pe SkZeMyfrUG/WsMrjrbqIXkP4X++oG+YpBDQQwSU4WZeztZ3TN3c/EcX0ADCulcRXVoBJ fpYL7yzbnUhzjunklXCNcTkaJCESSZNvqH7OayK8EQ/4kkWvS9NV/1EANyAdtHbqNck5 Jtf6xfouVN4flotOUlGj89sCpTDpeaHs1HMSs9mypgLelSGU7od9AIMa8fFr3jAxohke jm7Z0zsvMbLCm+4GRZGJSf7azKQm/UMY6Xz44Fhea4QLNn/xW+KvjnFmnf9lbDvcu6jC K5OQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vXWtOAbqO0IiL4x1PJ+ry/MmusWHvhWYDh4bY00za1s=; b=nnvCb0eL3SyZ3LcChGu9hK+yjoqPDQu5Ylt05tN9vPgcNZtFAv0d6RQRL56UCrWWu/ cQb+Ll1OjjhgSPohSU7pSzN47y49RHHjOjE8KMf8aYgga6HeHB5r9Qkf8UdMxMNTMH2f 8LmtkiNKv7r0BtuBdCia1s4ebB+TYU6+75Umjx1T6gpyS2Hnv4AWbjCZxD8Xgj9MjVGD WVfUGZo2S3CnVogcWSS7c73nY53BlVDD8lfCeJ4OnDjZaAfVKE0sS6d9mC12fx9325X9 wN8kdmb5CKe/WfOidQGfdPEOI7nqqgLdMxNKHPAlbXi68yP9HFe7DEc6WBjnkVtt5/fW vxMw== X-Gm-Message-State: AOAM5335jP97+a51cT+tUr040IRvH0uCE6ak6k3TC86xIDlXAn+YxwwK nmhRgLS0bAyTulM0Htp4ffhQxvaiAAyLdA== X-Received: by 2002:a63:4e26:: with SMTP id c38mr14266789pgb.81.1615066581606; Sat, 06 Mar 2021 13:36:21 -0800 (PST) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id r30sm6365616pgu.86.2021.03.06.13.36.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Mar 2021 13:36:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 06/27] tcg: Manage splitwx in tc_ptr_to_region_tree by hand Date: Sat, 6 Mar 2021 13:35:52 -0800 Message-Id: <20210306213613.85168-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210306213613.85168-1-richard.henderson@linaro.org> References: <20210306213613.85168-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The use in tcg_tb_lookup is given a random pc that comes from the pc of a signal handler. Do not assert that the pointer is already within the code gen buffer at all, much less the writable mirror of it. Fixes: db0c51a3803 Signed-off-by: Richard Henderson --- tcg/tcg.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) -- 2.25.1 diff --git a/tcg/tcg.c b/tcg/tcg.c index bbe3dcee03..2991112829 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -513,11 +513,21 @@ static void tcg_region_trees_init(void) } } -static struct tcg_region_tree *tc_ptr_to_region_tree(const void *cp) +static struct tcg_region_tree *tc_ptr_to_region_tree(const void *p) { - void *p = tcg_splitwx_to_rw(cp); size_t region_idx; + /* + * Like tcg_splitwx_to_rw, with no assert. The pc may come from + * a signal handler over which the caller has no control. + */ + if (!in_code_gen_buffer(p)) { + p -= tcg_splitwx_diff; + if (!in_code_gen_buffer(p)) { + return NULL; + } + } + if (p < region.start_aligned) { region_idx = 0; } else { @@ -536,6 +546,7 @@ void tcg_tb_insert(TranslationBlock *tb) { struct tcg_region_tree *rt = tc_ptr_to_region_tree(tb->tc.ptr); + g_assert(rt != NULL); qemu_mutex_lock(&rt->lock); g_tree_insert(rt->tree, &tb->tc, tb); qemu_mutex_unlock(&rt->lock); @@ -545,6 +556,7 @@ void tcg_tb_remove(TranslationBlock *tb) { struct tcg_region_tree *rt = tc_ptr_to_region_tree(tb->tc.ptr); + g_assert(rt != NULL); qemu_mutex_lock(&rt->lock); g_tree_remove(rt->tree, &tb->tc); qemu_mutex_unlock(&rt->lock); @@ -561,6 +573,10 @@ TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr) TranslationBlock *tb; struct tb_tc s = { .ptr = (void *)tc_ptr }; + if (rt == NULL) { + return NULL; + } + qemu_mutex_lock(&rt->lock); tb = g_tree_lookup(rt->tree, &s); qemu_mutex_unlock(&rt->lock); From patchwork Sat Mar 6 21:35:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 394554 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp549713jai; Sat, 6 Mar 2021 13:38:42 -0800 (PST) X-Google-Smtp-Source: ABdhPJyObX/3Kr1EEfwVnuth2nmG7lZeuCICITj6vBWDkE8oUh9fxYQEpYAO+EeStRrK0DGrI/oR X-Received: by 2002:a92:3647:: with SMTP id d7mr15211834ilf.264.1615066722635; Sat, 06 Mar 2021 13:38:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615066722; cv=none; d=google.com; s=arc-20160816; b=F2cJ1dtdKdTwS8EEcLUITBqGFHTDEFdqryL+peZNpDjKAxGZmWr6XCZ1X3gg9ewPex iYZcs8QUMdnu2fwOXf+PXC8p0GXEObmfoGUdFgk5v3TcFM1CQsWVuUXgr6k6b4TXusvG 9S7O/QzusYxtOeyPPVyKFUqzHDKDd1tkFasM97ciUgPBAy8Knf6ssHaNzc6HL/VpB8us IpkrQ5csnOWr1aFb1suLgLCvzFH8OY/AQg77kSTkTW6EREwDjB/V7MT99qsrkvZac7Dq A8tER1gq6JqYQg8OgPPg12AI3IiKtJ/2pNWYrXaAFc5XT1TFwJpI+Ac+CDDmxNUCKv1s 4oVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3oEIKQLfBmHUmZruF1WOanf+8RYMbOoh2V8q7ZF9vas=; b=HJ3fu5GBCTIo4/CbHuXel1b4cxRPeOqOpPqb0gDR8kgRr8xIpH8mbEYXmg/pj7aj1o AdIiOalG8cal0/Ncrjr3jhZrgW8FJVLMvw+Pa7r2qSja8Iej0vUMmH9lSlLpQTvX7WIp 4gCHXYLx3jkVDMqCTzfmtQfPACPgDVo2x28JSm9+vRJ6P5Hm9khuhX+hKLIQDWoUVAYM XDVjTnl7OqEb8ncrTr6WmKzqZJeva1j1PoeQvG7/FDiPORitoMUCsz8RnPNR/uh50B/u duVErCeRV54tBu1zPvmgIuSYORggKmVCrAAKU/2Bg2v9tdZRATpNI9YqV4cZWQbe6iU5 4Kzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tU9Graym; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org> [PMD: Split patch as 1/5] Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210218232840.1760806-2-f4bug@amsat.org> Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 85 +++++++++++++++++----------------------- 1 file changed, 37 insertions(+), 48 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index feac4659cc..ea42775cb0 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -380,6 +380,18 @@ static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) old_code_ptr[1] = s->code_ptr - old_code_ptr; } +#if TCG_TARGET_REG_BITS == 64 +# define CASE_32_64(x) \ + case glue(glue(INDEX_op_, x), _i64): \ + case glue(glue(INDEX_op_, x), _i32): +# define CASE_64(x) \ + case glue(glue(INDEX_op_, x), _i64): +#else +# define CASE_32_64(x) \ + case glue(glue(INDEX_op_, x), _i32): +# define CASE_64(x) +#endif + static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) { @@ -391,6 +403,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_exit_tb: tcg_out64(s, args[0]); break; + case INDEX_op_goto_tb: if (s->tb_jmp_insn_offset) { /* Direct jump method. */ @@ -456,22 +469,27 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_debug_assert(args[2] == (int32_t)args[2]); tcg_out32(s, args[2]); break; - case INDEX_op_add_i32: - case INDEX_op_sub_i32: - case INDEX_op_mul_i32: - case INDEX_op_and_i32: - case INDEX_op_andc_i32: /* Optional (TCG_TARGET_HAS_andc_i32). */ - case INDEX_op_eqv_i32: /* Optional (TCG_TARGET_HAS_eqv_i32). */ - case INDEX_op_nand_i32: /* Optional (TCG_TARGET_HAS_nand_i32). */ - case INDEX_op_nor_i32: /* Optional (TCG_TARGET_HAS_nor_i32). */ - case INDEX_op_or_i32: - case INDEX_op_orc_i32: /* Optional (TCG_TARGET_HAS_orc_i32). */ - case INDEX_op_xor_i32: - case INDEX_op_shl_i32: - case INDEX_op_shr_i32: - case INDEX_op_sar_i32: - case INDEX_op_rotl_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */ - case INDEX_op_rotr_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */ + + CASE_32_64(add) + CASE_32_64(sub) + CASE_32_64(mul) + CASE_32_64(and) + CASE_32_64(or) + CASE_32_64(xor) + CASE_32_64(andc) /* Optional (TCG_TARGET_HAS_andc_*). */ + CASE_32_64(orc) /* Optional (TCG_TARGET_HAS_orc_*). */ + CASE_32_64(eqv) /* Optional (TCG_TARGET_HAS_eqv_*). */ + CASE_32_64(nand) /* Optional (TCG_TARGET_HAS_nand_*). */ + CASE_32_64(nor) /* Optional (TCG_TARGET_HAS_nor_*). */ + CASE_32_64(shl) + CASE_32_64(shr) + CASE_32_64(sar) + CASE_32_64(rotl) /* Optional (TCG_TARGET_HAS_rot_*). */ + CASE_32_64(rotr) /* Optional (TCG_TARGET_HAS_rot_*). */ + CASE_32_64(div) /* Optional (TCG_TARGET_HAS_div_*). */ + CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */ + CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */ + CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */ tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); @@ -487,30 +505,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; #if TCG_TARGET_REG_BITS == 64 - case INDEX_op_add_i64: - case INDEX_op_sub_i64: - case INDEX_op_mul_i64: - case INDEX_op_and_i64: - case INDEX_op_andc_i64: /* Optional (TCG_TARGET_HAS_andc_i64). */ - case INDEX_op_eqv_i64: /* Optional (TCG_TARGET_HAS_eqv_i64). */ - case INDEX_op_nand_i64: /* Optional (TCG_TARGET_HAS_nand_i64). */ - case INDEX_op_nor_i64: /* Optional (TCG_TARGET_HAS_nor_i64). */ - case INDEX_op_or_i64: - case INDEX_op_orc_i64: /* Optional (TCG_TARGET_HAS_orc_i64). */ - case INDEX_op_xor_i64: - case INDEX_op_shl_i64: - case INDEX_op_shr_i64: - case INDEX_op_sar_i64: - case INDEX_op_rotl_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */ - case INDEX_op_rotr_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */ - case INDEX_op_div_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ - case INDEX_op_divu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ - case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ - case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - break; case INDEX_op_deposit_i64: /* Optional (TCG_TARGET_HAS_deposit_i64). */ tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); @@ -551,14 +545,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); break; - case INDEX_op_div_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ - case INDEX_op_divu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ - case INDEX_op_rem_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ - case INDEX_op_remu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - break; + #if TCG_TARGET_REG_BITS == 32 case INDEX_op_add2_i32: case INDEX_op_sub2_i32: @@ -628,8 +615,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, } tcg_out_i(s, *args++); break; + case INDEX_op_mb: break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_call: /* Always emitted via tcg_out_call. */ From patchwork Sat Mar 6 21:35:54 2021 Content-Type: text/plain; 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[209.51.188.17]) by mx.google.com with ESMTPS id z9si5926921ior.7.2021.03.06.13.40.31 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 06 Mar 2021 13:40:31 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QAw15lxD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35612 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIef0-0005Oc-PT for patch@linaro.org; Sat, 06 Mar 2021 16:40:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56894) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIebD-0006zS-7K for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:35 -0500 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:53305) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lIeb3-0002xJ-GF for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:34 -0500 Received: by mail-pj1-x102d.google.com with SMTP id kx1so1071894pjb.3 for ; Sat, 06 Mar 2021 13:36:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Y3W2C4gQqJ3gt54X13AfM/Luzq4svOq0hI3JMg2PfDU=; b=QAw15lxDhRBK0U0IRHVt5xlMrJn0Wigh+CbvSu9twgAwXLgBxBQZcsqbevXYhoINMx jjfSirTfO06LBCLBtHfP8k28WRE15dqFh8c2jmT3An0g3tzP9rpi7DPljHFRsT6jTX9h C5rDSLqqP0BxXCO7Rb27ee5dIZmQ3d1rDG+ZWdJBKhh+ah1ku6VYIVR5Q/6tDJFVvdQ5 BDc7s2GJHHe9MQN0a9hKwPmb72NkKlATGPacLxS9ugYs+tKQQgF0ALWOeY6qE41m4eXu UWmrqbDddx19TCVY2z+JGGneBVGyO4PaIpzzfXwFc7iRTomTfpqNrvnM+WnzDmfM6vjm uwHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y3W2C4gQqJ3gt54X13AfM/Luzq4svOq0hI3JMg2PfDU=; b=PN3I1dBEHira6/vsbbnyYxo3TvXk+17YxNKXNYnyZOd4tDftOD8G65B7oJ82wcBDR3 88DKhObZOerteXolBhOnxoyEj6keRR7FSGzLIa6CnMsou6V54m4jJGRsnBO0RA7iywOz jju8Hm5A1eOh65/rb5fTdF++eZhrMXb4Z3VanUpwm79Y1EjoThe5HDniJZvuUCq4gwbW WZ7WJrc2lDLVdDLTQo7tblipTfEhw00EvjHJIBkOTAUjDb2aaB7HV07rciPv6ut0rBVJ +c+BTokzxn4X6UOu/d7ccUP4VZtFVtNLXgSaOLXlRKzkXf3gjDM+3I9R91/6B2NoEQj8 fk+A== X-Gm-Message-State: AOAM533Srw4Y9cvR/fCyyxzXv2YU7kHhoVZROa0wwDA0Mbbpe275fyv6 F9wnC6mb3W4IOvsLsnKuEUHfdTHQ6NR3Iw== X-Received: by 2002:a17:902:6a88:b029:e3:cd8a:3a92 with SMTP id n8-20020a1709026a88b02900e3cd8a3a92mr14159870plk.22.1615066583753; Sat, 06 Mar 2021 13:36:23 -0800 (PST) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id r30sm6365616pgu.86.2021.03.06.13.36.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Mar 2021 13:36:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 08/27] tcg/tci: Merge identical cases in generation (exchange opcodes) Date: Sat, 6 Mar 2021 13:35:54 -0800 Message-Id: <20210306213613.85168-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210306213613.85168-1-richard.henderson@linaro.org> References: <20210306213613.85168-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use CASE_32_64 and CASE_64 to reduce ifdefs and merge cases that are identical between 32-bit and 64-bit hosts. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org> [PMD: Split patch as 2/5] Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210218232840.1760806-3-f4bug@amsat.org> Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 35 ++++++++++++++--------------------- 1 file changed, 14 insertions(+), 21 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index ea42775cb0..1896efd100 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -520,28 +520,21 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out8(s, args[2]); /* condition */ tci_out_label(s, arg_label(args[3])); break; - case INDEX_op_bswap16_i64: /* Optional (TCG_TARGET_HAS_bswap16_i64). */ - case INDEX_op_bswap32_i64: /* Optional (TCG_TARGET_HAS_bswap32_i64). */ - case INDEX_op_bswap64_i64: /* Optional (TCG_TARGET_HAS_bswap64_i64). */ - case INDEX_op_not_i64: /* Optional (TCG_TARGET_HAS_not_i64). */ - case INDEX_op_neg_i64: /* Optional (TCG_TARGET_HAS_neg_i64). */ - case INDEX_op_ext8s_i64: /* Optional (TCG_TARGET_HAS_ext8s_i64). */ - case INDEX_op_ext8u_i64: /* Optional (TCG_TARGET_HAS_ext8u_i64). */ - case INDEX_op_ext16s_i64: /* Optional (TCG_TARGET_HAS_ext16s_i64). */ - case INDEX_op_ext16u_i64: /* Optional (TCG_TARGET_HAS_ext16u_i64). */ - case INDEX_op_ext32s_i64: /* Optional (TCG_TARGET_HAS_ext32s_i64). */ - case INDEX_op_ext32u_i64: /* Optional (TCG_TARGET_HAS_ext32u_i64). */ - case INDEX_op_ext_i32_i64: - case INDEX_op_extu_i32_i64: #endif /* TCG_TARGET_REG_BITS == 64 */ - case INDEX_op_neg_i32: /* Optional (TCG_TARGET_HAS_neg_i32). */ - case INDEX_op_not_i32: /* Optional (TCG_TARGET_HAS_not_i32). */ - case INDEX_op_ext8s_i32: /* Optional (TCG_TARGET_HAS_ext8s_i32). */ - case INDEX_op_ext16s_i32: /* Optional (TCG_TARGET_HAS_ext16s_i32). */ - case INDEX_op_ext8u_i32: /* Optional (TCG_TARGET_HAS_ext8u_i32). */ - case INDEX_op_ext16u_i32: /* Optional (TCG_TARGET_HAS_ext16u_i32). */ - case INDEX_op_bswap16_i32: /* Optional (TCG_TARGET_HAS_bswap16_i32). */ - case INDEX_op_bswap32_i32: /* Optional (TCG_TARGET_HAS_bswap32_i32). */ + + CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ + CASE_32_64(not) /* Optional (TCG_TARGET_HAS_not_*). */ + CASE_32_64(ext8s) /* Optional (TCG_TARGET_HAS_ext8s_*). */ + CASE_32_64(ext8u) /* Optional (TCG_TARGET_HAS_ext8u_*). */ + CASE_32_64(ext16s) /* Optional (TCG_TARGET_HAS_ext16s_*). */ + CASE_32_64(ext16u) /* Optional (TCG_TARGET_HAS_ext16u_*). */ + CASE_64(ext32s) /* Optional (TCG_TARGET_HAS_ext32s_i64). */ + CASE_64(ext32u) /* Optional (TCG_TARGET_HAS_ext32u_i64). */ + CASE_64(ext_i32) + CASE_64(extu_i32) + CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */ + CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */ + CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */ tcg_out_r(s, args[0]); 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[209.51.188.17]) by mx.google.com with ESMTPS id g18si7040762ioo.24.2021.03.06.13.43.34 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 06 Mar 2021 13:43:34 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rOlUwhZv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44228 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIehy-0000YT-5Y for patch@linaro.org; Sat, 06 Mar 2021 16:43:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56812) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIeb7-0006wQ-Uv for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:30 -0500 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:42751) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lIeb4-0002xR-Dp for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:29 -0500 Received: by mail-pl1-x629.google.com with SMTP id s16so3093365plr.9 for ; Sat, 06 Mar 2021 13:36:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yoPJEjHaD9Y/eQNAtgp4CmM0ipXsKYPy7ttmPn2mZ+I=; b=rOlUwhZveo5K78xMo/r7QuADCmv/49FiRyu0Qfun+mEkkkkovN2THMZe32D2ovRvK/ /5y0HXP8frJv8VXEJLFLBhKRv6pzPq6WQNR5aFTIqqjRYdPjMTx10HDugd3xw8E386f+ MBabnETGgZJGavT+qZIjb6ms6dvd6k1migMh/DN5JA/Pp7lOFrZFoa97WkN1nVJQPqRi y6uJfskWz+m9MfZ/6Edydae106baB5caWYFfo/zWSlceryPhfpGLj2yRRkjcPRhamrA5 UlE0O/PhavRKyLoypRqO3i0VPo2aEs69FUcnpOEtzC7Z/YYYTaGv/huzx6zm4dyBfrVN NWng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yoPJEjHaD9Y/eQNAtgp4CmM0ipXsKYPy7ttmPn2mZ+I=; b=QK1Nfyt8Nbgkmbx/oxvIZSPR7SUFBFZ11UVfRS4NIKs17cagh3WkRvYLYCr5imN75G qpzFZqFHBCKdfwlx7SnqmHrkNvLB9KPUTtDCH8P/UsVkMaeRHLd4vNlpNhIT2PWtpDN0 X/dkVT43cMvhMYpHVmXkttxoY8eFfLCf5Abmg7Md7M1/hcWAj73ZCa9pHTNufxsk8IOu 2L6gRuR74HeJ19y4cy0bLOgouzNtBNPHw5pZU0IpQZHBUdGmgVFDsaOQsBNu08/0WQal DmoTD7MKjLx2vzonC5biafl3yTJJEx5Ft0m7OEORVQas+DawhewzmeIax7l6gvAA785Y IcEA== X-Gm-Message-State: AOAM531piCTqz80hE5C4fEKKKEu26FaQmtXPna9jWGQ1qG3WK5ux9Lqu z7+BL5ZFzrGZXNNkYpEUREMnnLZnM+CN7g== X-Received: by 2002:a17:90a:2a46:: with SMTP id d6mr16781290pjg.197.1615066585065; Sat, 06 Mar 2021 13:36:25 -0800 (PST) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id r30sm6365616pgu.86.2021.03.06.13.36.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Mar 2021 13:36:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 09/27] tcg/tci: Merge identical cases in generation (deposit opcode) Date: Sat, 6 Mar 2021 13:35:55 -0800 Message-Id: <20210306213613.85168-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210306213613.85168-1-richard.henderson@linaro.org> References: <20210306213613.85168-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use CASE_32_64 and CASE_64 to reduce ifdefs and merge cases that are identical between 32-bit and 64-bit hosts. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org> [PMD: Split patch as 3/5] Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210218232840.1760806-4-f4bug@amsat.org> Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 1896efd100..4a86a3bb46 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -494,7 +494,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); break; - case INDEX_op_deposit_i32: /* Optional (TCG_TARGET_HAS_deposit_i32). */ + + CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */ tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); @@ -505,15 +506,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; #if TCG_TARGET_REG_BITS == 64 - case INDEX_op_deposit_i64: /* Optional (TCG_TARGET_HAS_deposit_i64). */ - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_debug_assert(args[3] <= UINT8_MAX); - tcg_out8(s, args[3]); - tcg_debug_assert(args[4] <= UINT8_MAX); - tcg_out8(s, args[4]); - break; case INDEX_op_brcond_i64: tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); From patchwork Sat Mar 6 21:35:56 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 394558 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp550548jai; Sat, 6 Mar 2021 13:40:29 -0800 (PST) X-Google-Smtp-Source: ABdhPJzD/0tSFhS9WkXRzwF03a+snKPVhyQ5nhvRJ5z3Ocx5OPzZckiF2VwiHFFHzqqN42zDUsJQ X-Received: by 2002:a05:6e02:1be6:: with SMTP id y6mr13448711ilv.145.1615066829567; Sat, 06 Mar 2021 13:40:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615066829; cv=none; d=google.com; s=arc-20160816; b=nLDxylbYZeYIGzI62s8xUh4JbE3gSjfW2d4i/CNzJk34oQEOxHHfWi0RO5L98HhNbA w5vV/7YHzpLfuAn11xuxSgNpg9XAGe3ak8P83eZxmi/rQbDOMPbNnxHHhVRfakxDMpHs Z+Q6XdLoydH+m3EZEIIEQ9mtUghoLexRhbTAzMZxWUNa5m3E9pddELhvVGRVaNl9IACy 3qdtSqjYl5eADJZ6xCVefMEGTprovPiizFuhVLa8DVarkXiQBRWS5RJohc9n0e3FmrhI ZnS5EiN6oIU8HTavS54OpUGCxRfNPDoVJDshzpJXt+PKzwQHECOXWYdbr9d2lheNpzfR kGmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=A6vR6ziB3b9O465GIDkN5AIXP0cK+f5XI51tj6udrHk=; b=bLBG02BsiTu/Fz3ZIwcBja9KfBEz5YIcVfcvPjxkYad5yHacefLsGab4qYOoJJyXUA RyiUjVo8YCWPJAENkYfe9tUqMRsCbbEUcuhJWQsk8IX33Kh1DFVvIHbTYG/pWA0SFRzm BmcY2Zv3mb34ClLV9X6nYFldCWW89gPIH/Gdxw+Yybyf3mjlghW637TSDJyzdD3ljEUc OmWn0FA/5y1GnEeLQeLoCtOMM7g8MFOF3KRQn1RJvxJGSFBOWnrg49AVNY+ifN8TTbot VgiHdcDhmuTDueW6Z/rLFYoywfR95XPfw0qvrQY7oTEXrOFfmJRUgUCpLAyH/eQ88P40 cUFg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sHAkdhud; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org> [PMD: Split patch as 4/5] Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210218232840.1760806-5-f4bug@amsat.org> Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 23 ++++++----------------- 1 file changed, 6 insertions(+), 17 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 4a86a3bb46..f9893b9539 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -417,15 +417,18 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, } set_jmp_reset_offset(s, args[0]); break; + case INDEX_op_br: tci_out_label(s, arg_label(args[0])); break; - case INDEX_op_setcond_i32: + + CASE_32_64(setcond) tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); tcg_out8(s, args[3]); /* condition */ break; + #if TCG_TARGET_REG_BITS == 32 case INDEX_op_setcond2_i32: /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */ @@ -436,13 +439,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out_r(s, args[4]); tcg_out8(s, args[5]); /* condition */ break; -#elif TCG_TARGET_REG_BITS == 64 - case INDEX_op_setcond_i64: - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out_r(s, args[2]); - tcg_out8(s, args[3]); /* condition */ - break; #endif case INDEX_op_ld8u_i32: case INDEX_op_ld8s_i32: @@ -505,14 +501,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out8(s, args[4]); break; -#if TCG_TARGET_REG_BITS == 64 - case INDEX_op_brcond_i64: + CASE_32_64(brcond) tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out8(s, args[2]); /* condition */ tci_out_label(s, arg_label(args[3])); break; -#endif /* TCG_TARGET_REG_BITS == 64 */ CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ CASE_32_64(not) /* Optional (TCG_TARGET_HAS_not_*). */ @@ -556,12 +550,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out_r(s, args[3]); break; #endif - case INDEX_op_brcond_i32: - tcg_out_r(s, args[0]); - tcg_out_r(s, args[1]); - tcg_out8(s, args[2]); /* condition */ - tci_out_label(s, arg_label(args[3])); - break; + case INDEX_op_qemu_ld_i32: tcg_out_r(s, *args++); tcg_out_r(s, *args++); From patchwork Sat Mar 6 21:35:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 394562 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp551440jai; Sat, 6 Mar 2021 13:42:54 -0800 (PST) X-Google-Smtp-Source: ABdhPJykaLcLXqMhsWquBlVIlHVJ9bA5vFF+OtPWGOqn74bfsxhKeIZz2jrp0sb9D7e+aQCdsMdT X-Received: by 2002:a25:9c44:: with SMTP id x4mr23613294ybo.317.1615066974111; Sat, 06 Mar 2021 13:42:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615066974; cv=none; d=google.com; s=arc-20160816; b=cP+otba314WTAN2v1cAytgH7GvtgTac3V7FyAe/bHP97cbsKie3vHM/G97qqwsxG93 C5sb3qVoYxfHX5oWAwQnOcyYJCNYbQ7bEHgpvVKqd+7ox5Slv9c/4S3Eh376180Quorr 7ILjjCWeUiKFAAk+5NNf7YL55blFAD94jFBjacNee+a2FkIsz8B3I7hkaYEzAYeaxerU koP5vZ36FgnzcQDSkI5Lcbmtsbjj/nh3t9/18mFODlnZJxUflkx/ZIsbLbzwhyRLDuir Xy3boii6j9FFP50/vo1ZKGVps3E516mrq6+c1VFgnID2EY5FflXMB1kh8s0WlhEylBoy CbKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=xk1GB79AaGUkcV+qDEpBrBCVOi2EqtNfKQnf1wr+BmM=; b=EGFwJLqU/FoaoFEmAb2n20DkjbY6idNmagEKGWajV6bhAZKse+ZQrbUgJGSjp5DQOQ io+rmopx+hVyKpkjz8ZalSDj6t5m41WQMNQJlXXU7hVjlHUpN+MQ9aZOZnGeY7BkylnX b54QRet4vmhDA1iQnNV0f3GAI6bSav17gB8rht5uz1LcxhZLwQESMrTR/Wj5q2Fo0/DH QSZmqU/0W6bBUu/H3mmFUNcdzqbPpmPLsUkhFFUNAkt1fE2tS6dLaEIF+WTVRTbQ3X6/ PubfF0bo7LxmPPyaN5lxPOw3v/8bs9pbxmkQvXiLkQmMvaTDe/jYHLojYNWPJ8mC8kWW saAg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uSaziWlk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d37si8120587ybe.379.2021.03.06.13.42.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 06 Mar 2021 13:42:54 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uSaziWlk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44130 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIehJ-0000WG-GC for patch@linaro.org; Sat, 06 Mar 2021 16:42:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56852) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIebA-0006y9-7A for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:32 -0500 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:39098) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lIeb6-0002xe-Ic for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:31 -0500 Received: by mail-pf1-x42f.google.com with SMTP id 18so4646799pfo.6 for ; Sat, 06 Mar 2021 13:36:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xk1GB79AaGUkcV+qDEpBrBCVOi2EqtNfKQnf1wr+BmM=; b=uSaziWlkTsvp7WKiKbvVtCTZKB++EvLVWEhZbHsxF4MH8BRvRvTxKTVYBEnH0a+mcj W18VjnRi9kyVVcBJYxZ26Cx5rw7GBdEwyhFBadpZ/QDRtOWxqAr/hKgPQIu8rzZ33AsG gSEC5USYd61uRGvWChj4XbV9nLRoLwWjaWjzFhGqbu/j6PBrGslA/aNwqXQrL8ApIUXt fOALjUlycJ866eLrtVdAUaxv5SOCEUyw/Nv/4nd/8nKOXbCSeqk85T4EfJ5JGwG+XM+Q ITZTlC0sn74MqvhwjDH2TZR9/2gwTltV6lBMoKzUV6LCfBuzfFoCKIencfTow0dADeXB nFjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xk1GB79AaGUkcV+qDEpBrBCVOi2EqtNfKQnf1wr+BmM=; b=uidvlJj2hFhR2hsJIpNOaP1aoM8CfFY6X73/i3MAFuFe51p+TMOdf1tqLDPVyigplu /P6lZeCRhdgKGYmZfBwpXZbB6wWj56pcJ2joirptFAj9zcq4SjQYfzioeDOHfws7jddb vaW7r69heqKe+xVcO4Rb8ovKgX/IxLWxGpG8GHgPiUEfI9TEOV4zOK0rfeQ5nEGlbSQ5 bBkCQ982H4rAqcEFYvuIJ61fJ2TGxvza8q1b0LVLGF9X1pqhw4HvXfR8BPatN2wqWv1D vqhsvsg1/lpx5GwXMWQ+kLzw0i0qFC5pYIv9qSdTUfyBGBWMsMgQyk1JFdgQXzQc98BG Q7OQ== X-Gm-Message-State: AOAM532bB89r/Nvb5VLxU4JuZZvlk3j/0XHl5iOEo1OPDyKaSczMboWc yqI+mB4rU+HC/NqI3NBKJFsvPjWR+3fH6w== X-Received: by 2002:a63:1845:: with SMTP id 5mr14508118pgy.244.1615066586903; Sat, 06 Mar 2021 13:36:26 -0800 (PST) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id r30sm6365616pgu.86.2021.03.06.13.36.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Mar 2021 13:36:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 11/27] tcg/tci: Merge identical cases in generation (load/store opcodes) Date: Sat, 6 Mar 2021 13:35:57 -0800 Message-Id: <20210306213613.85168-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210306213613.85168-1-richard.henderson@linaro.org> References: <20210306213613.85168-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use CASE_32_64 and CASE_64 to reduce ifdefs and merge cases that are identical between 32-bit and 64-bit hosts. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20210217202036.1724901-5-richard.henderson@linaro.org> [PMD: Split patch as 5/5] Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210218232840.1760806-6-f4bug@amsat.org> Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 49 ++++++++++++---------------------------- 1 file changed, 14 insertions(+), 35 deletions(-) -- 2.25.1 diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index f9893b9539..c79f9c32d8 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -440,25 +440,20 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out8(s, args[5]); /* condition */ break; #endif - case INDEX_op_ld8u_i32: - case INDEX_op_ld8s_i32: - case INDEX_op_ld16u_i32: - case INDEX_op_ld16s_i32: + + CASE_32_64(ld8u) + CASE_32_64(ld8s) + CASE_32_64(ld16u) + CASE_32_64(ld16s) case INDEX_op_ld_i32: - case INDEX_op_st8_i32: - case INDEX_op_st16_i32: + CASE_64(ld32u) + CASE_64(ld32s) + CASE_64(ld) + CASE_32_64(st8) + CASE_32_64(st16) case INDEX_op_st_i32: - case INDEX_op_ld8u_i64: - case INDEX_op_ld8s_i64: - case INDEX_op_ld16u_i64: - case INDEX_op_ld16s_i64: - case INDEX_op_ld32u_i64: - case INDEX_op_ld32s_i64: - case INDEX_op_ld_i64: - case INDEX_op_st8_i64: - case INDEX_op_st16_i64: - case INDEX_op_st32_i64: - case INDEX_op_st_i64: + CASE_64(st32) + CASE_64(st) stack_bounds_check(args[1], args[2]); tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); @@ -552,24 +547,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, #endif case INDEX_op_qemu_ld_i32: - tcg_out_r(s, *args++); - tcg_out_r(s, *args++); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_r(s, *args++); - } - tcg_out_i(s, *args++); - break; - case INDEX_op_qemu_ld_i64: - tcg_out_r(s, *args++); - if (TCG_TARGET_REG_BITS == 32) { - tcg_out_r(s, *args++); - } - tcg_out_r(s, *args++); - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - tcg_out_r(s, *args++); - } - tcg_out_i(s, *args++); - break; case INDEX_op_qemu_st_i32: tcg_out_r(s, *args++); tcg_out_r(s, *args++); @@ -578,6 +555,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, } tcg_out_i(s, *args++); break; + + case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_st_i64: tcg_out_r(s, *args++); if (TCG_TARGET_REG_BITS == 32) { From patchwork Sat Mar 6 21:35:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 394569 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp552436jai; Sat, 6 Mar 2021 13:45:15 -0800 (PST) X-Google-Smtp-Source: ABdhPJy2nfUjU0/lXOspuqOkhBPGrotJ1fUE7CWgynlIdhWDn4yvw4tbiKLuCXj3Yz9/uDxXNFbQ X-Received: by 2002:a25:7802:: with SMTP id t2mr23190821ybc.100.1615067115874; Sat, 06 Mar 2021 13:45:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615067115; cv=none; d=google.com; s=arc-20160816; b=0nttr+MTh369Ah3NkQ1lQ51VNqsgaqc77QglEJ675SeJ/gcVeko0+bgkCUp2s+u9qy kHXcyi/xSO8MISNWpOwGKDLXXT0cz7gJIRsNiLHArVeiQtkdmnvIjhdbKvpGRT0GJ6hs ysuP/IGOJJAFNV5ZGrNICdAExCnb7cEp0VgDCnxDfEHbRFP9UVAynnM0bVSo5rtcLjAQ KGrbAtY6AvHfVJQXCcXGkxW5HXd5IMyGtU/h4hW0yYDasvcqUh5kjs3pt+0gT5vRzYmV 92KHSArxs52UB8tEn/qRe1yhPQxLSLT0pVKqSuDJDs+f1w/BLaT9uH0glctwPnVD+bkN 3jTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=fptILMWrA+pDg1XvV+KF1NfoqcnNqb93ja/TFgoMbqs=; b=oTz0l78MG+/1brKy/yn3BIYx3Iy7RtS5V31vpPmnHEmj1t/w/7RkxprJtV8kxHIk9N RtHd8U3dsEZqZMtbacujlcTwq7Z2d3hTPeZln48YQMtk9CcQ8v8H0DFegEgANVf8vHsw nUUeQLxssgU6oBmM7ZbxQcCm9OUX7XJgcdzp0c9wz+6fHOsFQ2u6zXCJHkl9TIM+olSR 01y9FxsROWVziGv4aMToHqKtLALmtCUIctEGYhzIldrEe85ZiQ4N4tEiqeqSHBeAyd/B QLXVajttuXI4pgN1S8qNly+iOPvf4OJDfTMSzlcWzwBct6vIiKcDvEIffSsnldKgoDgn y2SA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="d0/wzP1F"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x4si7098278ybl.56.2021.03.06.13.45.15 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 06 Mar 2021 13:45:15 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="d0/wzP1F"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:52764 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIejb-0003wJ-7E for patch@linaro.org; Sat, 06 Mar 2021 16:45:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56828) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIeb9-0006xg-5v for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:32 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:56107) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lIeb7-0002xk-1f for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:30 -0500 Received: by mail-pj1-x1031.google.com with SMTP id t9so1067667pjl.5 for ; Sat, 06 Mar 2021 13:36:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fptILMWrA+pDg1XvV+KF1NfoqcnNqb93ja/TFgoMbqs=; b=d0/wzP1F0HqjaYfQpSm7clOdRrHySiwJyvPiTemJgTk0FU6AJAWK+nLbcHhNx1JtcM KMZjR3GuxwwsYJ7O1vZzaFr+4sCumaxqks9B/x3vSNkpy1XJXqYPQxlWeBh3jvTrRCn1 hgpZBUt25MSyqlfeCVievTc2if8EjbteS1TPWuysgirIkRnvJm1bwTqx+P0pSEOfibIT UEYlAfKZ9g4ymnI5QOQXjo5bHpNFsxg6lXQWIJMQ0zOgn15/e0oXbLQDkLHrTMxtxuyy Xcze5eafAVDeF3deFTHxP/rOVHsKbXy7v5MYMaMnnR7FFvS8PC3OcXVa/BYzpsWwr2xA 1c9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fptILMWrA+pDg1XvV+KF1NfoqcnNqb93ja/TFgoMbqs=; b=XfiufUDLfYjhpGzFu/C07Y2CeoT595777qrPb7SmGvlR0Crunqg93Te11DNivYXdjG j5w26DXVfvzxBlgRexKILKJAA+CDzKbAjhN7mjUcie2I+ShQbb09UYmosSKbZAtVRy7v uovDmCkc4sbSKxj+iwffpupaslyHqcF82HVIPRDD7DuFcwmmVaJhnRkNSxVBA46ETZw6 8C3k50+NueI16TSD4UMFXaza5eefizw1tW3kF+58PqTm2Un1M9h+GrrkSVYTlyCHiEtJ tjCCyDPoMKZnSZJnRWofSUsnn8ig78ds8fMjIsIjo5kftWI8lq+9uZspgcmhx2xUaLj/ qUNg== X-Gm-Message-State: AOAM530uJvxX3sFyony1nLsP+Wk2I6u9+3VtjPhsBjArkH1+e4UnFEC3 p+7K7clZwkYlcF+H0PaFz/3eUCTsjWT/Gw== X-Received: by 2002:a17:90b:e18:: with SMTP id ge24mr17269379pjb.199.1615066587677; Sat, 06 Mar 2021 13:36:27 -0800 (PST) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id r30sm6365616pgu.86.2021.03.06.13.36.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Mar 2021 13:36:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 12/27] tcg/tci: Remove tci_read_r8 Date: Sat, 6 Mar 2021 13:35:58 -0800 Message-Id: <20210306213613.85168-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210306213613.85168-1-richard.henderson@linaro.org> References: <20210306213613.85168-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use explicit casts for ext8u opcodes, and allow truncation to happen with the store for st8 opcodes. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci.c | 23 +++++------------------ 1 file changed, 5 insertions(+), 18 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 1c667537fe..4ade0ccaf9 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -78,11 +78,6 @@ static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index) } #endif -static uint8_t tci_read_reg8(const tcg_target_ulong *regs, TCGReg index) -{ - return (uint8_t)tci_read_reg(regs, index); -} - static uint16_t tci_read_reg16(const tcg_target_ulong *regs, TCGReg index) { return (uint16_t)tci_read_reg(regs, index); @@ -169,14 +164,6 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr) return value; } -/* Read indexed register (8 bit) from bytecode. */ -static uint8_t tci_read_r8(const tcg_target_ulong *regs, const uint8_t **tb_ptr) -{ - uint8_t value = tci_read_reg8(regs, **tb_ptr); - *tb_ptr += 1; - return value; -} - #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 /* Read indexed register (8 bit signed) from bytecode. */ static int8_t tci_read_r8s(const tcg_target_ulong *regs, const uint8_t **tb_ptr) @@ -533,7 +520,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2)); break; CASE_32_64(st8) - t0 = tci_read_r8(regs, &tb_ptr); + t0 = tci_read_r(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); *(uint8_t *)(t1 + t2) = t0; @@ -722,8 +709,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_ext8u_i32 case INDEX_op_ext8u_i32: t0 = *tb_ptr++; - t1 = tci_read_r8(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16u_i32 @@ -916,8 +903,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_ext8u_i64 case INDEX_op_ext8u_i64: t0 = *tb_ptr++; - t1 = tci_read_r8(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint8_t)t1); break; #endif #if TCG_TARGET_HAS_ext8s_i64 From patchwork Sat Mar 6 21:35:59 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 394552 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp549045jai; Sat, 6 Mar 2021 13:37:06 -0800 (PST) X-Google-Smtp-Source: ABdhPJzG5Ib9ZXchH1c8TXUB3nYUv96kZLQaflp5n2jqdXUd06pWmwXf30yItd/4tUb0xEVz2G4Q X-Received: by 2002:a6b:6618:: with SMTP id a24mr13347653ioc.100.1615066626069; Sat, 06 Mar 2021 13:37:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615066626; cv=none; d=google.com; s=arc-20160816; b=tp0NHGPO1QO4DlOFBYoFJs+D5ACyVptRXLxAGPQG9YGfOelDJEDkvc/Q/U0I+itPc4 e4LwJVfu0Prv3EcyAlc+ZCg7hr/Agw889JPXhBwOusJAvf8risH+c6TSjfzMh7r0Xj0S rJgE1oihm5+fpGNm5y3dnPggqYH3uzwfwAG1hcLeR28qX4O2vwmpTVq/glI1QB8VQNgp sbYlTUj4lBxc7Pmp0uw1wltc9/J4+mkqsziSom0XnLtf9SSbEnvdxb2RARtIqhi1GEg7 enDMDmeMq8JVuEuZx0tWZAHFCl29METTZs/JxlNwM+fVR+7cHsmaGG7n6NIlkPjMjvBT s9cw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=IYlMX6zlz5iaj2ojk5WvGQj9gx5INTxGM9zOOFclYMU=; b=nau41GoBsvLMI1Ej5U/xcX6xL3OL1yRnAcMu6Wk7KmsJAqk5dh3IFBljQG5xh3+7sG J1lt8nW/Tml20dB2z0rByK7UG2Em3/G/6cFKyL2liPphofWBx+QfE2gYVl1RZiGPyU+v ycU3oXBVOaVbXKBxXNLBW3SJ53eiIMhTEsO90deD1PlSF99bnyV5ELns+ZcfufylEhr6 ymc2v3WL4TNmAtpVIote8b4FGYyvMv9Bp7gxPNHOEPM5hS9ax5wivUOCFhEHbJ/M7Gkr WTOKr3cxUtyGfvtatehUE5Adw5I7ugBiu6pCJFSBk+VE8I/4y8aaGhacKCHRf0CTCaAq hzZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TVSDQHBw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci.c | 25 ++++--------------------- 1 file changed, 4 insertions(+), 21 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 4ade0ccaf9..7325c8bfd0 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index) return regs[index]; } -#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 -static int8_t tci_read_reg8s(const tcg_target_ulong *regs, TCGReg index) -{ - return (int8_t)tci_read_reg(regs, index); -} -#endif - #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 static int16_t tci_read_reg16s(const tcg_target_ulong *regs, TCGReg index) { @@ -164,16 +157,6 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr) return value; } -#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 -/* Read indexed register (8 bit signed) from bytecode. */ -static int8_t tci_read_r8s(const tcg_target_ulong *regs, const uint8_t **tb_ptr) -{ - int8_t value = tci_read_reg8s(regs, **tb_ptr); - *tb_ptr += 1; - return value; -} -#endif - /* Read indexed register (16 bit) from bytecode. */ static uint16_t tci_read_r16(const tcg_target_ulong *regs, const uint8_t **tb_ptr) @@ -695,8 +678,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_ext8s_i32 case INDEX_op_ext8s_i32: t0 = *tb_ptr++; - t1 = tci_read_r8s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16s_i32 @@ -910,8 +893,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_ext8s_i64 case INDEX_op_ext8s_i64: t0 = *tb_ptr++; - t1 = tci_read_r8s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int8_t)t1); break; #endif #if TCG_TARGET_HAS_ext16s_i64 From patchwork Sat Mar 6 21:36:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 394561 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp550839jai; Sat, 6 Mar 2021 13:41:15 -0800 (PST) X-Google-Smtp-Source: ABdhPJxvsCurExEK/Pz3XdyeCNCDUC9e8JKe0Vd9HdTfgjekFF+fCpHrniVGE2/N0vRvNS3S51o2 X-Received: by 2002:a05:6e02:ef4:: with SMTP id j20mr12956333ilk.199.1615066875580; Sat, 06 Mar 2021 13:41:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615066875; cv=none; d=google.com; s=arc-20160816; b=qYFAesgInFd3IOSyRjdErGX7RDHlh533bJAN826rxmD+hsAomwuRNOsRnhQL8PLq+j n493Wx+iiKhvQWSmdg6EAhj4bJcLIe3H8MExTxC6twSiQSFK72ne84KlU+3JIQPU3Lwo Yh3B8fvE63cp/p1Ef1hNXROLhN0KrfLSuJwtt2Y2zdkwVsIr5xtJQ4meZXaRH+fVVhmB TDOvCwRdZfjeUk8hm9/Wd5jzFu0tIYBpebrxSesRsAZkcs5LzBZmXzFZfd+Ht8iBH4sE ft3Fd1T59BfcRAS7eRbChYO4Og70g88zvgqWs68tjduyIvVsLkhx8NAuKM1z7HiqOtBi FTPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=YPOjQOCVvXckcnkr+oLmPc3XWSAdSsFw06IiSJpsEjQ=; b=CJOmA40SuxmTBnGgkHLLSW0u5lCuY9XCpnOLI3SYYFtDq2l6acRx6Ssdq5aFbcfMus ps8lJ6mp8IQk74kv2cr0Cr2vjEnHz3HqnxegQCbayMIYPjCu9US06cVbKUP/lTgXxExI XUAxvpSUUTGP+mwVJSKXNrQizfAKz2kWBrzFf3gZ7wCeD311dTJM3hcYWstH+TjjBC9o 3QNVUtt26O6ibrQr+OJ/hPMNSjbI1k5qPzodDOn/yk8+H1qbCGxxAwdZXe8wuYAFTiF8 YoWkl/ETExVKbvpy0Clz4MKJdEj9+4R4JtimsE0O1zrQDi/inAhyswIwGBbeU83xSHYf tbPw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pcnsXWC+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci.c | 28 +++++++--------------------- 1 file changed, 7 insertions(+), 21 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 7325c8bfd0..2440da1746 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -71,11 +71,6 @@ static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index) } #endif -static uint16_t tci_read_reg16(const tcg_target_ulong *regs, TCGReg index) -{ - return (uint16_t)tci_read_reg(regs, index); -} - static uint32_t tci_read_reg32(const tcg_target_ulong *regs, TCGReg index) { return (uint32_t)tci_read_reg(regs, index); @@ -157,15 +152,6 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr) return value; } -/* Read indexed register (16 bit) from bytecode. */ -static uint16_t tci_read_r16(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - uint16_t value = tci_read_reg16(regs, **tb_ptr); - *tb_ptr += 1; - return value; -} - #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 /* Read indexed register (16 bit signed) from bytecode. */ static int16_t tci_read_r16s(const tcg_target_ulong *regs, @@ -509,7 +495,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, *(uint8_t *)(t1 + t2) = t0; break; CASE_32_64(st16) - t0 = tci_read_r16(regs, &tb_ptr); + t0 = tci_read_r(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); *(uint16_t *)(t1 + t2) = t0; @@ -699,14 +685,14 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_ext16u_i32 case INDEX_op_ext16u_i32: t0 = *tb_ptr++; - t1 = tci_read_r16(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint16_t)t1); break; #endif #if TCG_TARGET_HAS_bswap16_i32 case INDEX_op_bswap16_i32: t0 = *tb_ptr++; - t1 = tci_read_r16(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap16(t1)); break; #endif @@ -907,8 +893,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_ext16u_i64 case INDEX_op_ext16u_i64: t0 = *tb_ptr++; - t1 = tci_read_r16(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint16_t)t1); break; #endif #if TCG_TARGET_HAS_ext32s_i64 @@ -930,7 +916,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_bswap16_i64 case INDEX_op_bswap16_i64: t0 = *tb_ptr++; - t1 = tci_read_r16(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap16(t1)); break; #endif From patchwork Sat Mar 6 21:36:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 394563 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp551684jai; Sat, 6 Mar 2021 13:43:33 -0800 (PST) X-Google-Smtp-Source: ABdhPJwiOaVv9UjBZMBFpfpLTy7pM2v611up9VQhgosIr6ilrcuLS6i/kCDU7OKVz24x0UX2Y/JI X-Received: by 2002:a92:c644:: with SMTP id 4mr14403048ill.237.1615067013149; Sat, 06 Mar 2021 13:43:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615067013; cv=none; d=google.com; s=arc-20160816; b=RX3zSMdETPCscZwpoS1fNsYI3JxWn1DVIDOSwOWnsdv8+0MbpM72dKlYoH5Dzp051D eLLEyT+f2NamcORV/9/LLm7UZ6vdQG+n+dsXRZJMK4gTMV4fR750nvx5BHQDPT/6UAe0 y4rhes4wfaiIpUFK4PvaaAAC/Ml7yjcBwjNoBO+hoJdlXEWdjZ84XGvUVfImF+d37pPL OJzRitmWxS9ObhaZHc7NQaHSCHBOn/Bb8zQGJTTd4KnkG2mbwyuGEbJjzhRhIZKlpBBi OHKPzTBEERfsgfFCC0nif+68hi5+ZoiSGIVEmiVuFYTIWBIFyC+p5KjH3pFr6oOgf8Ob u7vg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=RiZhAqk94IR59YM6JHo6AIRSs7mF45dtttOIiGxjJYA=; b=Uz/pW7wIiVQP2olFRzti8B6pMIJDLp9t2SSJxzAzsEphE8olziqDYL4uTp9r6BLp3C PrXP3vObCqULNsAMq77PVbPC9OVjXCoz4esWG6O3mIZAVYurv+c3odoySlFVrUWirkiH w1MASOrlj8S9B8uLM09+48ithfWxQdz9iVZK/DbeERYWJrHXVVL5E456Hjs9ecnhZkCT iBshVvQLjDpzbHRcgxkF6xbqW3vVLK7n9FpfWuC3I8ZJlx+4THYdLykvvwUqh+gLExS8 EwPDz1PJ1IEyWuLHzjJzDqCgNxcpyx5xEVcSQAISCZaFjWrYcItz7qnq4hPS/rTY2GDo RQ/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="y/1tpW/u"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci.c | 26 ++++---------------------- 1 file changed, 4 insertions(+), 22 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 2440da1746..8b91e6efc3 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index) return regs[index]; } -#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 -static int16_t tci_read_reg16s(const tcg_target_ulong *regs, TCGReg index) -{ - return (int16_t)tci_read_reg(regs, index); -} -#endif - #if TCG_TARGET_REG_BITS == 64 static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index) { @@ -152,17 +145,6 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr) return value; } -#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 -/* Read indexed register (16 bit signed) from bytecode. */ -static int16_t tci_read_r16s(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - int16_t value = tci_read_reg16s(regs, **tb_ptr); - *tb_ptr += 1; - return value; -} -#endif - /* Read indexed register (32 bit) from bytecode. */ static uint32_t tci_read_r32(const tcg_target_ulong *regs, const uint8_t **tb_ptr) @@ -671,8 +653,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_ext16s_i32 case INDEX_op_ext16s_i32: t0 = *tb_ptr++; - t1 = tci_read_r16s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int16_t)t1); break; #endif #if TCG_TARGET_HAS_ext8u_i32 @@ -886,8 +868,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_ext16s_i64 case INDEX_op_ext16s_i64: t0 = *tb_ptr++; - t1 = tci_read_r16s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int16_t)t1); break; #endif #if TCG_TARGET_HAS_ext16u_i64 From patchwork Sat Mar 6 21:36:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 394571 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp553124jai; Sat, 6 Mar 2021 13:47:13 -0800 (PST) X-Google-Smtp-Source: ABdhPJzHutZZI8XyJj2tLP6Yg3CgH+LCSYpOGWOwECvudVDGR+9dQe8pQr8o4KhTM1I+dh10Kc++ X-Received: by 2002:a25:254a:: with SMTP id l71mr22538434ybl.125.1615067233666; Sat, 06 Mar 2021 13:47:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615067233; cv=none; d=google.com; s=arc-20160816; b=BuVWjgYOJii1+CdGEmXTYSm9tRMmG4AVWIzJoP7HW0kl384TFCUjHH5jUjcGxk5B4g iu3NId+DQztipEOLcUrmILjOn/peSC3uw8TlGzg9aPuL7rgPyvmuxtUy5Fq/GVkvweBj bxxd1+8wG+2FHBol049FWaPtomW9nUzUCpF9HBT7qYLEhdR+lnBVkRSVripg1MAAwscC g+YzhKxX+D3PZhuM0SAPFC+PrGf5zZvD//WGaz/dVL6/1dPC2g0CzDkAwH0EdtFmc48j /8rXuJAyU/i/a/S0774o9A102X7U0AaYA8LVtDijJ7uJHls8mqo5tB5xUucy6453WO0A aIvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=+dmSE8N34SoJjro0pmrBj+i1Q6RRI4T10gidnvhwlpU=; b=OjgT4ozgJHpu/nPQUVs8M5dYQOrHyTE7CL1YXeGeuw9YGL2KNNswCbD560GLDtDmge GBFCgLljYTcBMGONU4bRyStdY9mhnEqokP++0TJOqISDj6AUxsFn7MT8ZazGSj0FjLPO MgZ7SliGsWZJNAlOvifsQLwvCVpbt8IyKLEJKwnmw+b+tCUHMXkgJFMeEok+krISla9o 3Yx29X8elWxxjcUxx5uEScKud+4hWEQW12Ykif879vdkR0TOenwtq+cHvxaYw3eY9lng Ve2bOIBhGJAP9qoghIMcm84CLpbGmpFSuK1chXOavkrvuFevi9VlG0MHQInPMv82ERSB rfUg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=J12vIspq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci.c | 122 ++++++++++++++++++++++++------------------------------ 1 file changed, 54 insertions(+), 68 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 8b91e6efc3..a5aaa763f8 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -64,11 +64,6 @@ static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index) } #endif -static uint32_t tci_read_reg32(const tcg_target_ulong *regs, TCGReg index) -{ - return (uint32_t)tci_read_reg(regs, index); -} - #if TCG_TARGET_REG_BITS == 64 static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index) { @@ -145,22 +140,13 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr) return value; } -/* Read indexed register (32 bit) from bytecode. */ -static uint32_t tci_read_r32(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - uint32_t value = tci_read_reg32(regs, **tb_ptr); - *tb_ptr += 1; - return value; -} - #if TCG_TARGET_REG_BITS == 32 /* Read two indexed registers (2 * 32 bit) from bytecode. */ static uint64_t tci_read_r64(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { - uint32_t low = tci_read_r32(regs, tb_ptr); - return tci_uint64(tci_read_r32(regs, tb_ptr), low); + uint32_t low = tci_read_r(regs, tb_ptr); + return tci_uint64(tci_read_r(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS == 64 /* Read indexed register (32 bit signed) from bytecode. */ @@ -404,8 +390,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, continue; case INDEX_op_setcond_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); condition = *tb_ptr++; tci_write_reg(regs, t0, tci_compare32(t1, t2, condition)); break; @@ -428,7 +414,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #endif case INDEX_op_mov_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1); break; case INDEX_op_tci_movi_i32: @@ -484,7 +470,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, break; case INDEX_op_st_i32: CASE_64(st32) - t0 = tci_read_r32(regs, &tb_ptr); + t0 = tci_read_r(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); *(uint32_t *)(t1 + t2) = t0; @@ -494,62 +480,62 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_add_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 + t2); break; case INDEX_op_sub_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 - t2); break; case INDEX_op_mul_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; case INDEX_op_div_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2); break; case INDEX_op_divu_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 / t2); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2); break; case INDEX_op_rem_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2); break; case INDEX_op_remu_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 % t2); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2); break; case INDEX_op_and_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 & t2); break; case INDEX_op_or_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 | t2); break; case INDEX_op_xor_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 ^ t2); break; @@ -557,41 +543,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_shl_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 << (t2 & 31)); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint32_t)t1 << (t2 & 31)); break; case INDEX_op_shr_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 >> (t2 & 31)); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint32_t)t1 >> (t2 & 31)); break; case INDEX_op_sar_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, ((int32_t)t1 >> (t2 & 31))); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int32_t)t1 >> (t2 & 31)); break; #if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, rol32(t1, t2 & 31)); break; case INDEX_op_rotr_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ror32(t1, t2 & 31)); break; #endif #if TCG_TARGET_HAS_deposit_i32 case INDEX_op_deposit_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - t2 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tmp16 = *tb_ptr++; tmp8 = *tb_ptr++; tmp32 = (((1 << tmp8) - 1) << tmp16); @@ -599,8 +585,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, break; #endif case INDEX_op_brcond_i32: - t0 = tci_read_r32(regs, &tb_ptr); - t1 = tci_read_r32(regs, &tb_ptr); + t0 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); condition = *tb_ptr++; label = tci_read_label(&tb_ptr); if (tci_compare32(t0, t1, condition)) { @@ -638,9 +624,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_mulu2_i32: t0 = *tb_ptr++; t1 = *tb_ptr++; - t2 = tci_read_r32(regs, &tb_ptr); - tmp64 = tci_read_r32(regs, &tb_ptr); - tci_write_reg64(regs, t1, t0, t2 * tmp64); + t2 = tci_read_r(regs, &tb_ptr); + tmp64 = (uint32_t)tci_read_r(regs, &tb_ptr); + tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64); break; #endif /* TCG_TARGET_REG_BITS == 32 */ #if TCG_TARGET_HAS_ext8s_i32 @@ -681,21 +667,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_bswap32_i32 case INDEX_op_bswap32_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap32(t1)); break; #endif #if TCG_TARGET_HAS_not_i32 case INDEX_op_not_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i32 case INDEX_op_neg_i32: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, -t1); break; #endif @@ -892,8 +878,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #endif case INDEX_op_extu_i32_i64: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint32_t)t1); break; #if TCG_TARGET_HAS_bswap16_i64 case INDEX_op_bswap16_i64: @@ -905,7 +891,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_bswap32_i64 case INDEX_op_bswap32_i64: t0 = *tb_ptr++; - t1 = tci_read_r32(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap32(t1)); break; #endif From patchwork Sat Mar 6 21:36:03 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 394564 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp551689jai; Sat, 6 Mar 2021 13:43:33 -0800 (PST) X-Google-Smtp-Source: ABdhPJwrPqCpnGQrnMU0CCN7f7UCSvjkNxKArtrbPsZlVxm1PrmFjBHVmCdxrpsnP8ITmWoTMj38 X-Received: by 2002:a5d:9510:: with SMTP id d16mr13005973iom.81.1615067013757; Sat, 06 Mar 2021 13:43:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615067013; cv=none; d=google.com; s=arc-20160816; b=qqrdNQyr29fjDx+20pRLwbsaxOROG1+t61oU02SILwu6vSqq4apBUxxdXHg+0KpUkh ibxcjEY7dppC8NE44bl4TRD+HiwJstW+D70gne/MmgXiuEYvFsH1GSTHiHUuBoXD9j6T 013Z8DFN3Az18Omiq11+nq+X3miOYDKuJK5nYOAYW1LJZ5O0ijjnkYuTTuiPIDQSOz04 +1hAQhpeJ74iogk9FE9/2FkukfB1kMib8NjPynZ2dO4FVZzbLuumwQIBIG7pKYTc0Pid ZNLdwm2/LXpgGOg8OQ3IeDIllarRfCtuDcgxdZtVL0tPVmhJTC5yt4jPzBMxwMYKBWHc +Nuw== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id s4si6800395ilv.10.2021.03.06.13.43.33 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 06 Mar 2021 13:43:33 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wxMK1rsQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44132 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIehx-0000WM-6M for patch@linaro.org; Sat, 06 Mar 2021 16:43:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56900) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIebD-0006zg-ID for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:35 -0500 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:37667) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lIebB-0002yd-V1 for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:35 -0500 Received: by mail-pl1-x631.google.com with SMTP id p5so3112380plo.4 for ; Sat, 06 Mar 2021 13:36:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CWFm3ag7LIImv7AYnXLhQJhOkm+Ptc6YBLG0M9ot5EY=; b=wxMK1rsQwgQ2ujJT/ccnz5qdKxjNaZzpXJn5w528Vf9unN96BUll7GfvPiFK0WL56R 7TWQf/3I6C+lEHRnxOwLW1gTzinR6eHyywuxvJ/BF52pF/vg1+qxbqCthxIqY/Z7XHil WvqvHQCH2alEO4ZIArKZFgaOEufuI5Ng1SGXG5+Tt0j3dwQQ/3QaepC50As99iIJ/KdT tXJ6WqHz8cTU8OlnK7ahqnWCXuTJRbiRIG8prukuaeEPHmFdpHGVHjrzG79jup/tp84g cuiIg2Uu59ny9IY9x1xkboDg53i7DOvf04uOghAvfdEauY8SKl4+JzPB4OTNLNRHRDr0 pGDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CWFm3ag7LIImv7AYnXLhQJhOkm+Ptc6YBLG0M9ot5EY=; b=p40e684fbvj4a8kcgjXhk0SjY0Seebc6ALZbvofTssSrCWx9GKtvtze2PMcUqAkvHz 5av9kPUQUw3WBQnHKc33i+ICl8/2A+FP5fvFlhB6m45nh7vnmqppNXH04UV17CSs3Zt+ 7q1UNHVrbKXGU+FvR456Cx6JwGRDS/T5PCQ946kLlAs3U3kGuijx7/v3orYIbCD1C/UR uY+3H8i9wzpso0I+MsxIiau9+ai/l7Hy4sEwEHZMbAwBHNbK+6aL1fwD3dD8HXQLkY2X cDIXLJAk7Zx8newJ0ovXC8gNdMlkApmU8OpC7DaMYi528Yb0QjOgmteqIsooxqD8B2LN 6S4Q== X-Gm-Message-State: AOAM533qSP1lc3vCkjx6NI/b1ALTNEGPU1bp0OEJUgSeniwc5LE9OfHm bQ0id5Lx9r9xVEE03406xvU+/iRZqesNXQ== X-Received: by 2002:a17:90a:be0e:: with SMTP id a14mr185207pjs.131.1615066592624; Sat, 06 Mar 2021 13:36:32 -0800 (PST) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id r30sm6365616pgu.86.2021.03.06.13.36.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Mar 2021 13:36:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 17/27] tcg/tci: Remove tci_read_r32s Date: Sat, 6 Mar 2021 13:36:03 -0800 Message-Id: <20210306213613.85168-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210306213613.85168-1-richard.henderson@linaro.org> References: <20210306213613.85168-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use explicit casts for ext32s opcodes. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci.c | 20 ++------------------ 1 file changed, 2 insertions(+), 18 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index a5aaa763f8..cef12f263d 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index) return regs[index]; } -#if TCG_TARGET_REG_BITS == 64 -static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index) -{ - return (int32_t)tci_read_reg(regs, index); -} -#endif - #if TCG_TARGET_REG_BITS == 64 static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index) { @@ -149,15 +142,6 @@ static uint64_t tci_read_r64(const tcg_target_ulong *regs, return tci_uint64(tci_read_r(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS == 64 -/* Read indexed register (32 bit signed) from bytecode. */ -static int32_t tci_read_r32s(const tcg_target_ulong *regs, - const uint8_t **tb_ptr) -{ - int32_t value = tci_read_reg32s(regs, **tb_ptr); - *tb_ptr += 1; - return value; -} - /* Read indexed register (64 bit) from bytecode. */ static uint64_t tci_read_r64(const tcg_target_ulong *regs, const uint8_t **tb_ptr) @@ -870,8 +854,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #endif case INDEX_op_ext_i32_i64: t0 = *tb_ptr++; - t1 = tci_read_r32s(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); + t1 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, (int32_t)t1); break; #if TCG_TARGET_HAS_ext32u_i64 case INDEX_op_ext32u_i64: From patchwork Sat Mar 6 21:36:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 394568 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp552426jai; Sat, 6 Mar 2021 13:45:15 -0800 (PST) X-Google-Smtp-Source: ABdhPJyLgTosaNalplcDw52gcbDAZ5oe/2BYBsAG13jVMGvK22WYS+sCFTUsW8BqcplEFD5+P0cK X-Received: by 2002:a25:3250:: with SMTP id y77mr22407600yby.154.1615067115541; Sat, 06 Mar 2021 13:45:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615067115; cv=none; d=google.com; s=arc-20160816; b=u8QEIAr8lfhcWxOenx0T92ahVwdAeOjlr9mSse1TgFh2GYw1zv2NUgqN3/U4rqzkZw Gf4XFS5OTpjZVz0B03gflufLFyGW57XWEU74XnkL2CsHWtmXj1dl1UQXHYtdBwsZRF7/ lkSwEps6Qee59SUrYS1amLaRKsUB5YSTxH4vgWQvOUmepuY8W1p1TtszL87tEvqpIWyr vKpP6jswQMxc5p94tqpGSYuJdSqI0vYtAUP+JZk/bNsQr2ETDB6LRWns7LAxCgzlMTWF 8a5GJmArpMmawdq/IRvKmOUgc4AKHSo+LgcYBCzn0w9tQV1LpK/yFwQl/hb788EJys73 Nz9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=v2unlqfJMNyj9BFPXRcywsgxR3r17wjB0hRJKjBA1xY=; b=YFLhsQLB5yOzq6ZoB6xacWrclIUyTArxREFTspBmtvgW6Rok5uHXy1D4XZSUgWqXdW vvO9JKIANyt7/f+VvFANuQZAP3dHnMNurkCmA2KI0lTBHntnO65OO+fSlEu+5dGH2QgM gSYWPRi1vyeqhCjgV3VAyTWiUMxpDpjsfdxj5Iwp7V/Ern+LdXzdaIxxiC+0bA+SlSFb Ny/rk+9Dht5diMpO+XgR9QQmOZ7jas1AUZ2RkTEilEMohC9fbWNygr1WUuYWE+aAiFnx LUvpAAvUfzXR2dnfLVa4buTucdNs71MrirnP4yQ8+s3kxlSzuo5nNxjzb7T32VKB1czl O7Mw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="deL9pY/o"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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We retain the 64-bit symbol for the single case of INDEX_op_qemu_st_i64. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci.c | 93 +++++++++++++++++++++++++------------------------------ 1 file changed, 42 insertions(+), 51 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index cef12f263d..9efe69d05f 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -57,13 +57,6 @@ static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index) return regs[index]; } -#if TCG_TARGET_REG_BITS == 64 -static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index) -{ - return tci_read_reg(regs, index); -} -#endif - static void tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value) { @@ -146,9 +139,7 @@ static uint64_t tci_read_r64(const tcg_target_ulong *regs, static uint64_t tci_read_r64(const tcg_target_ulong *regs, const uint8_t **tb_ptr) { - uint64_t value = tci_read_reg64(regs, **tb_ptr); - *tb_ptr += 1; - return value; + return tci_read_r(regs, tb_ptr); } #endif @@ -390,8 +381,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #elif TCG_TARGET_REG_BITS == 64 case INDEX_op_setcond_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); condition = *tb_ptr++; tci_write_reg(regs, t0, tci_compare64(t1, t2, condition)); break; @@ -672,7 +663,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_REG_BITS == 64 case INDEX_op_mov_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1); break; case INDEX_op_tci_movi_i64: @@ -696,7 +687,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2)); break; case INDEX_op_st_i64: - t0 = tci_read_r64(regs, &tb_ptr); + t0 = tci_read_r(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_s32(&tb_ptr); *(uint64_t *)(t1 + t2) = t0; @@ -706,62 +697,62 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_add_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 + t2); break; case INDEX_op_sub_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 - t2); break; case INDEX_op_mul_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; case INDEX_op_div_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2); break; case INDEX_op_divu_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2); break; case INDEX_op_rem_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2); break; case INDEX_op_remu_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2); break; case INDEX_op_and_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 & t2); break; case INDEX_op_or_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 | t2); break; case INDEX_op_xor_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 ^ t2); break; @@ -769,41 +760,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, case INDEX_op_shl_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 << (t2 & 63)); break; case INDEX_op_shr_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 >> (t2 & 63)); break; case INDEX_op_sar_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63))); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, rol64(t1, t2 & 63)); break; case INDEX_op_rotr_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ror64(t1, t2 & 63)); break; #endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); - t2 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); tmp16 = *tb_ptr++; tmp8 = *tb_ptr++; tmp64 = (((1ULL << tmp8) - 1) << tmp16); @@ -811,8 +802,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, break; #endif case INDEX_op_brcond_i64: - t0 = tci_read_r64(regs, &tb_ptr); - t1 = tci_read_r64(regs, &tb_ptr); + t0 = tci_read_r(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); condition = *tb_ptr++; label = tci_read_label(&tb_ptr); if (tci_compare64(t0, t1, condition)) { @@ -882,21 +873,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap64(t1)); break; #endif #if TCG_TARGET_HAS_not_i64 case INDEX_op_not_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i64 case INDEX_op_neg_i64: t0 = *tb_ptr++; - t1 = tci_read_r64(regs, &tb_ptr); + t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, -t1); break; #endif From patchwork Sat Mar 6 21:36:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 394572 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp553126jai; Sat, 6 Mar 2021 13:47:14 -0800 (PST) X-Google-Smtp-Source: ABdhPJwg/5L6lhV0HGkgTkh7ukQPYE10nTUedl72AZhSafVGMWAP00ENtssINe4vYKItKgk5U5V1 X-Received: by 2002:a25:dd43:: with SMTP id u64mr23699019ybg.96.1615067234362; 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Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci.c | 83 +++++++++++++++++-------------------------------------- 1 file changed, 25 insertions(+), 58 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 9efe69d05f..d0bf810781 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -451,26 +451,47 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, *(uint32_t *)(t1 + t2) = t0; break; - /* Arithmetic operations (32 bit). */ + /* Arithmetic operations (mixed 32/64 bit). */ - case INDEX_op_add_i32: + CASE_32_64(add) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 + t2); break; - case INDEX_op_sub_i32: + CASE_32_64(sub) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 - t2); break; - case INDEX_op_mul_i32: + CASE_32_64(mul) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; + CASE_32_64(and) + t0 = *tb_ptr++; + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, t1 & t2); + break; + CASE_32_64(or) + t0 = *tb_ptr++; + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, t1 | t2); + break; + CASE_32_64(xor) + t0 = *tb_ptr++; + t1 = tci_read_r(regs, &tb_ptr); + t2 = tci_read_r(regs, &tb_ptr); + tci_write_reg(regs, t0, t1 ^ t2); + break; + + /* Arithmetic operations (32 bit). */ + case INDEX_op_div_i32: t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); @@ -495,24 +516,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2); break; - case INDEX_op_and_i32: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 & t2); - break; - case INDEX_op_or_i32: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 | t2); - break; - case INDEX_op_xor_i32: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 ^ t2); - break; /* Shift/rotate operations (32 bit). */ @@ -695,24 +698,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, /* Arithmetic operations (64 bit). */ - case INDEX_op_add_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 + t2); - break; - case INDEX_op_sub_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 - t2); - break; - case INDEX_op_mul_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 * t2); - break; case INDEX_op_div_i64: t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); @@ -737,24 +722,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t2 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2); break; - case INDEX_op_and_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 & t2); - break; - case INDEX_op_or_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 | t2); - break; - case INDEX_op_xor_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - t2 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1 ^ t2); - break; /* Shift/rotate operations (64 bit). */ From patchwork Sat Mar 6 21:36:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 394566 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp552169jai; Sat, 6 Mar 2021 13:44:45 -0800 (PST) X-Google-Smtp-Source: ABdhPJwp/bYTNuJ10hRJeZB1MLa09vDnEE9yUG9C9AhpZMa2Av27wuegNqAwt2rPs5WZStVKLZbT X-Received: by 2002:a25:9204:: with SMTP id b4mr22844120ybo.420.1615067085187; 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Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci.c | 44 ++++++++------------------------------------ 1 file changed, 8 insertions(+), 36 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index d0bf810781..73f639d23a 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -607,29 +607,29 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64); break; #endif /* TCG_TARGET_REG_BITS == 32 */ -#if TCG_TARGET_HAS_ext8s_i32 - case INDEX_op_ext8s_i32: +#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 + CASE_32_64(ext8s) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int8_t)t1); break; #endif -#if TCG_TARGET_HAS_ext16s_i32 - case INDEX_op_ext16s_i32: +#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 + CASE_32_64(ext16s) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (int16_t)t1); break; #endif -#if TCG_TARGET_HAS_ext8u_i32 - case INDEX_op_ext8u_i32: +#if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64 + CASE_32_64(ext8u) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint8_t)t1); break; #endif -#if TCG_TARGET_HAS_ext16u_i32 - case INDEX_op_ext16u_i32: +#if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64 + CASE_32_64(ext16u) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint16_t)t1); @@ -779,34 +779,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, continue; } break; -#if TCG_TARGET_HAS_ext8u_i64 - case INDEX_op_ext8u_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint8_t)t1); - break; -#endif -#if TCG_TARGET_HAS_ext8s_i64 - case INDEX_op_ext8s_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (int8_t)t1); - break; -#endif -#if TCG_TARGET_HAS_ext16s_i64 - case INDEX_op_ext16s_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (int16_t)t1); - break; -#endif -#if TCG_TARGET_HAS_ext16u_i64 - case INDEX_op_ext16u_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, (uint16_t)t1); - break; -#endif #if TCG_TARGET_HAS_ext32s_i64 case INDEX_op_ext32s_i64: #endif From patchwork Sat Mar 6 21:36:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 394573 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp553932jai; Sat, 6 Mar 2021 13:49:33 -0800 (PST) X-Google-Smtp-Source: ABdhPJzgnzf4aeFnM9F4HlTTvuv26lYtFO+jpPiLLOqH/m48PAqd9T4MtA/OloWVeCEtaKYpQR6M X-Received: by 2002:a05:6e02:12e9:: with SMTP id l9mr14055800iln.201.1615067373844; Sat, 06 Mar 2021 13:49:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615067373; cv=none; d=google.com; s=arc-20160816; b=q+/J+mbIdMoO7tKisG4LrRDdejjdfCtBbaziHGMxvi5y+hODOWwJVkHtFJeJEaYRSe ALoFBvq4HL/+nk5p/JqjPn2hznZFjghUjbpKwezr7aFdIVkR8qVOO2NlQQRMxKEBKb0X yt/W3Vv0RymGz/twXegf3o0tf/6aa+Zlm6yCq/dbYHwOzxNC0T8xyRDaD18pijfXb5vZ Y/6mUr+O1eG4uMjzeg9jOHsahW+5xN7If/VyuWEgxJDo1rAKGip+7j2rQOzx8mfg5DkH 4FGcLZIWpGsX+8t9BA/ODdFVgpwflTvsVKqtL9HhvQgb6tiBSd0qkNcapnGSGDyIs3S4 1l7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=uBa0mYVDt9xRDsum9kHj5ruNUWIAR4QdH8Qq5PqaSbM=; b=wAiSjHeRd1/o9QtyLvQ4buitJ0isJ1BG2WjtkXaema7Jfv3XP4nFdoYTTWLAhtdQwp jb4jYfzISwll0VnJlEMIsoBIaWT6a1uxfC2+NzjArH9ai7lqfJNUDz1jpuQ3h4bEn+47 HvGd3IgotRSSB1vAjYXycLfrn18EcvIaG7RuOfNO+BwbUFPll2HIG6PcOHD4+HW9rEsv z282kDQ2D7UAZRbdfXLQEUsOMqWhnQFG4OYgQHGIUOtb3UgVM+Qvrrke2hSHmrvYsO2P GD0BetKqiVeqbiOxSY1SA6coIk3/Iv+JoXxJuPUYu7mczDwnc6uQULF0YJmzUbDdRlO+ HMQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XgW9PmFS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci.c | 22 ++++------------------ 1 file changed, 4 insertions(+), 18 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 73f639d23a..66f2962d6e 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -635,15 +635,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_write_reg(regs, t0, (uint16_t)t1); break; #endif -#if TCG_TARGET_HAS_bswap16_i32 - case INDEX_op_bswap16_i32: +#if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64 + CASE_32_64(bswap16) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap16(t1)); break; #endif -#if TCG_TARGET_HAS_bswap32_i32 - case INDEX_op_bswap32_i32: +#if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64 + CASE_32_64(bswap32) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, bswap32(t1)); @@ -795,20 +795,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, (uint32_t)t1); break; -#if TCG_TARGET_HAS_bswap16_i64 - case INDEX_op_bswap16_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, bswap16(t1)); - break; -#endif -#if TCG_TARGET_HAS_bswap32_i64 - case INDEX_op_bswap32_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, bswap32(t1)); - break; -#endif #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: t0 = *tb_ptr++; From patchwork Sat Mar 6 21:36:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 394567 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp552417jai; Sat, 6 Mar 2021 13:45:14 -0800 (PST) X-Google-Smtp-Source: ABdhPJwUrG2/IkBuqiKTqLhmHJ3sHa4oVa3RZYpDpVCrDTZN20O3ueXGy0j0RErS7S6FqWEfWTGf X-Received: by 2002:a25:80c7:: with SMTP id c7mr22874957ybm.406.1615067114877; Sat, 06 Mar 2021 13:45:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615067114; cv=none; d=google.com; s=arc-20160816; b=n+bkCMJklNVf35lFnTIS+m6ZoSkI/Xi+QEjxn7/omAKanswq33S1wce5dfoOeHWc8x bn4guH2+l1dihxKFsUFEHpAFCme1++QM4XwpPQYMkMyvK7hN0ADb4QuIwWIrP8ZPQZWl CZ52KLpQT3/4sZRusBdZKckg4CyNH4BOiRGD89xovprPpMNK1Uv9eskOZt2lhrqtatpq piBcejdUU5IHR8xOHQuP3+us1jOunbAoTyJjFhpy5iC47Rn5qxrOP5MnpApOQGcZY8Cw 8GjqF/Jkw3jqn/rDq2+LJz82tP351aFat64YTqALTov+8EqdpULjPUno93a479DD7z2r 6z1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Fjh8f4OqF602Y2BfCtcg6Y74/rLBbqgNaPqxsRG9w20=; b=DCiwCsjgCKIQSmW5+bTcL/KL6OHs+3nCIu/OLTjL88OHEenuYWsnAdcbwybYYLu/1u tnxpwOOGQaT2VENVmEeOtA/lojUH4nDTSSIqHscCcKGAIpnPr3gKKUaDGQ1Sy0yGbYqj Tb3d2ZsEDkcmVvYiF0ekb2HsADVxDsXk82UgUG3ld3GD+sNnabw1lLZFkMWwmdSxYQqo x33KHoTebSqoNFxNvRrjoxbBQSDqTVkZ90Y3SOFKIROtt579E7bStnTsgmPKDTeaqTLx 5VeAY8Vuyoj8cThkjwIQxApqGmYr9y/hEjcLICTL21eKmAnVtWRhvKpBjDm3sM6ajxz2 faKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BNhoV6YP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Sat, 06 Mar 2021 13:36:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 22/27] tcg/tci: Merge mov, not and neg operations Date: Sat, 6 Mar 2021 13:36:08 -0800 Message-Id: <20210306213613.85168-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210306213613.85168-1-richard.henderson@linaro.org> References: <20210306213613.85168-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tci.c | 29 +++++------------------------ 1 file changed, 5 insertions(+), 24 deletions(-) -- 2.25.1 diff --git a/tcg/tci.c b/tcg/tci.c index 66f2962d6e..3ccd30c39c 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -387,7 +387,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_write_reg(regs, t0, tci_compare64(t1, t2, condition)); break; #endif - case INDEX_op_mov_i32: + CASE_32_64(mov) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, t1); @@ -649,26 +649,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_write_reg(regs, t0, bswap32(t1)); break; #endif -#if TCG_TARGET_HAS_not_i32 - case INDEX_op_not_i32: +#if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64 + CASE_32_64(not) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, ~t1); break; #endif -#if TCG_TARGET_HAS_neg_i32 - case INDEX_op_neg_i32: +#if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64 + CASE_32_64(neg) t0 = *tb_ptr++; t1 = tci_read_r(regs, &tb_ptr); tci_write_reg(regs, t0, -t1); break; #endif #if TCG_TARGET_REG_BITS == 64 - case INDEX_op_mov_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, t1); - break; case INDEX_op_tci_movi_i64: t0 = *tb_ptr++; t1 = tci_read_i64(&tb_ptr); @@ -802,20 +797,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_write_reg(regs, t0, bswap64(t1)); break; #endif -#if TCG_TARGET_HAS_not_i64 - case INDEX_op_not_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, ~t1); - break; -#endif -#if TCG_TARGET_HAS_neg_i64 - case INDEX_op_neg_i64: - t0 = *tb_ptr++; - t1 = tci_read_r(regs, &tb_ptr); - tci_write_reg(regs, t0, -t1); - break; -#endif #endif /* TCG_TARGET_REG_BITS == 64 */ /* QEMU specific operations. */ From patchwork Sat Mar 6 21:36:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 394570 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp553122jai; Sat, 6 Mar 2021 13:47:13 -0800 (PST) X-Google-Smtp-Source: ABdhPJxwh7jH275YCSpR4c09aLoH7cY+PQ8GE6WhkMJx94JyTyv26Hno5up9Q678s6LENBSZ1VdX X-Received: by 2002:a25:ab29:: with SMTP id u38mr21978885ybi.327.1615067233389; Sat, 06 Mar 2021 13:47:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615067233; cv=none; d=google.com; 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[209.51.188.17]) by mx.google.com with ESMTPS id h83si6396410ybh.453.2021.03.06.13.47.13 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 06 Mar 2021 13:47:13 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KWplDvkP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:32912 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIelU-0007Nw-Pr for patch@linaro.org; Sat, 06 Mar 2021 16:47:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56994) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIebK-0007Gx-AW for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:42 -0500 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]:43777) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lIebI-0002zY-8Q for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:42 -0500 Received: by mail-pf1-x435.google.com with SMTP id q204so4548479pfq.10 for ; Sat, 06 Mar 2021 13:36:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fLp7ahr6cCs+oy0rVj+29A4rlPQHlhrG1zIsiKOw/kc=; b=KWplDvkP5ag0K1MPMbjz7joBt+NSh3FcqhpqpZCFtFJQVAVlvdDnAViYlMuem/+DKF 4jyinHUifZ0wcs0lBlzDZCOHlD+f/eRB2VTC74gDFCk35CTrWyfLxzI2J+2rRmIEFxS1 wMZ3FzlAOyf3UKFzLO2yRT7eq629iDxdO4WOmm6mXlalYDISnAhBLKSRqBglkF/op/f2 nvZ2tvRa5Qb/hapaXsE8rt7aJKxV7vCN3tqO2OMXRVCEGSUu+O+Tbw6eS5hpFndrsWO1 vCq5hLbGwTEJlakQ03nieeE4J7aSCKm76f6HqKQiUvjRFzKW3krVU8P571nlRD+85P/w lvrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fLp7ahr6cCs+oy0rVj+29A4rlPQHlhrG1zIsiKOw/kc=; b=qnRUPGRzmCgrpttRmnyrOu3YZQmYP/3WD9CUf8YoIyF6QfnIPhVnVdeCoO67c2Cz1t 00b4gsGM27bxZWuv3ewtBis9eyCjZ64Y3DJQmVpXUa0bu4vOTDkO4MNxTfuqR9GaKO9a rHX+uuyHyvE4xx2/VWFLG2lolIawByixqlrUrazuVIrxY9pvNoKnbCAxTjBjNRQmdDsB jy3sgI6dVYz9aKE/f4cRA3qk/Nyj8znbsHWOU8hz0xN4B68Fd4HO/W50K0D9ES06iyF8 U+66LSrrmWnmsIn+aEEPg6Rne+wHX4rGfT/YczewccKOvfMX899Qt4rMGVMLj1ilv6RB QeHQ== X-Gm-Message-State: AOAM533oCNJZU4tU8ff7bV72bgarvcPhvw8Ww8f4yKFxOBD0dLE186ul bsv2H9EvYRmB8v568F9RNfr8TYNRQ7aa9w== X-Received: by 2002:a62:1ad4:0:b029:1ed:b92c:6801 with SMTP id a203-20020a621ad40000b02901edb92c6801mr14430103pfa.7.1615066598988; Sat, 06 Mar 2021 13:36:38 -0800 (PST) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id r30sm6365616pgu.86.2021.03.06.13.36.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Mar 2021 13:36:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 23/27] accel/tcg: rename tb_lookup__cpu_state and hoist state extraction Date: Sat, 6 Mar 2021 13:36:09 -0800 Message-Id: <20210306213613.85168-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210306213613.85168-1-richard.henderson@linaro.org> References: <20210306213613.85168-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée Having a function return either and valid TB and some system state seems excessive. It will make the subsequent re-factoring easier if we lookup the current state where we are. Signed-off-by: Alex Bennée Message-Id: <20210224165811.11567-2-alex.bennee@linaro.org> Signed-off-by: Richard Henderson --- include/exec/tb-lookup.h | 18 ++++++++---------- accel/tcg/cpu-exec.c | 10 ++++++++-- accel/tcg/tcg-runtime.c | 4 +++- 3 files changed, 19 insertions(+), 13 deletions(-) -- 2.25.1 diff --git a/include/exec/tb-lookup.h b/include/exec/tb-lookup.h index 9cf475bb03..c3f5d81c55 100644 --- a/include/exec/tb-lookup.h +++ b/include/exec/tb-lookup.h @@ -17,30 +17,28 @@ #include "exec/tb-hash.h" /* Might cause an exception, so have a longjmp destination ready */ -static inline TranslationBlock * -tb_lookup__cpu_state(CPUState *cpu, target_ulong *pc, target_ulong *cs_base, - uint32_t *flags, uint32_t cf_mask) +static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc, + target_ulong cs_base, + uint32_t flags, uint32_t cf_mask) { - CPUArchState *env = (CPUArchState *)cpu->env_ptr; TranslationBlock *tb; uint32_t hash; - cpu_get_tb_cpu_state(env, pc, cs_base, flags); - hash = tb_jmp_cache_hash_func(*pc); + hash = tb_jmp_cache_hash_func(pc); tb = qatomic_rcu_read(&cpu->tb_jmp_cache[hash]); cf_mask &= ~CF_CLUSTER_MASK; cf_mask |= cpu->cluster_index << CF_CLUSTER_SHIFT; if (likely(tb && - tb->pc == *pc && - tb->cs_base == *cs_base && - tb->flags == *flags && + tb->pc == pc && + tb->cs_base == cs_base && + tb->flags == flags && tb->trace_vcpu_dstate == *cpu->trace_dstate && (tb_cflags(tb) & (CF_HASH_MASK | CF_INVALID)) == cf_mask)) { return tb; } - tb = tb_htable_lookup(cpu, *pc, *cs_base, *flags, cf_mask); + tb = tb_htable_lookup(cpu, pc, cs_base, flags, cf_mask); if (tb == NULL) { return NULL; } diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 16e4fe3ccd..ef96b312a1 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -245,6 +245,7 @@ static void cpu_exec_exit(CPUState *cpu) void cpu_exec_step_atomic(CPUState *cpu) { + CPUArchState *env = (CPUArchState *)cpu->env_ptr; TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; @@ -258,7 +259,9 @@ void cpu_exec_step_atomic(CPUState *cpu) g_assert(!cpu->running); cpu->running = true; - tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask); + cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); + tb = tb_lookup(cpu, pc, cs_base, flags, cf_mask); + if (tb == NULL) { mmap_lock(); tb = tb_gen_code(cpu, pc, cs_base, flags, cflags); @@ -418,11 +421,14 @@ static inline TranslationBlock *tb_find(CPUState *cpu, TranslationBlock *last_tb, int tb_exit, uint32_t cf_mask) { + CPUArchState *env = (CPUArchState *)cpu->env_ptr; TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; - tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask); + cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); + + tb = tb_lookup(cpu, pc, cs_base, flags, cf_mask); if (tb == NULL) { mmap_lock(); tb = tb_gen_code(cpu, pc, cs_base, flags, cf_mask); diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index d736f4ff55..05e3d52c2f 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -152,7 +152,9 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) target_ulong cs_base, pc; uint32_t flags; - tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, curr_cflags()); + cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); + + tb = tb_lookup(cpu, pc, cs_base, flags, curr_cflags()); if (tb == NULL) { return tcg_code_gen_epilogue; } From patchwork Sat Mar 6 21:36:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 394576 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp554630jai; Sat, 6 Mar 2021 13:51:26 -0800 (PST) X-Google-Smtp-Source: ABdhPJwCM1OZ7/LxzL1YQnSL8Y4Sody/e8yuwazNwLmZCD2wenia5lGI8kVInOegc1ZW/gicLENQ X-Received: by 2002:a25:4e89:: with SMTP id c131mr20974170ybb.382.1615067486700; Sat, 06 Mar 2021 13:51:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615067486; cv=none; d=google.com; s=arc-20160816; b=I3kOVBcHdeO/fgroBqgjOoHOhsHXMA+80wZD7SQ9sQljZ3OyryQ/n+zNNS7GHbaAXf DmjOF7Ql7iImnremgjUNUlnvHj2vGe/cgsYh08nbXOhTStRvGyZSdYxuNBdKbpFRHn1E PI3Q8qWHRF3DwJmyzs78X78KGHngIKJCcDYZBQLsxhTmWqYoS+/DkFyHAWQcduB2Js6o KFnJ5P72MFH46BK+2fxlWwjmM50hJeNzYthZtF+rYfABvuw4FQwIrsSeVxw/2z1ZZ0E0 S/M7nAzIV5950PXHHS2cqN/uFe6CKHOfJPee0Jszu+MVNIKWrI93bLfHTkBJlEl8Rt/t hFzQ== ARC-Message-Signature: i=1; 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Signed-off-by: Alex Bennée Message-Id: <20210224165811.11567-3-alex.bennee@linaro.org> Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 8 +++++--- include/exec/tb-lookup.h | 3 --- accel/tcg/cpu-exec.c | 9 ++++----- accel/tcg/tcg-runtime.c | 2 +- accel/tcg/translate-all.c | 6 +++--- softmmu/physmem.c | 2 +- 6 files changed, 14 insertions(+), 16 deletions(-) -- 2.25.1 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index b7b3c0ef12..1a69c07add 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -519,10 +519,12 @@ static inline uint32_t tb_cflags(const TranslationBlock *tb) } /* current cflags for hashing/comparison */ -static inline uint32_t curr_cflags(void) +static inline uint32_t curr_cflags(CPUState *cpu) { - return (parallel_cpus ? CF_PARALLEL : 0) - | (icount_enabled() ? CF_USE_ICOUNT : 0); + uint32_t cflags = deposit32(0, CF_CLUSTER_SHIFT, 8, cpu->cluster_index); + cflags |= parallel_cpus ? CF_PARALLEL : 0; + cflags |= icount_enabled() ? CF_USE_ICOUNT : 0; + return cflags; } /* TranslationBlock invalidate API */ diff --git a/include/exec/tb-lookup.h b/include/exec/tb-lookup.h index c3f5d81c55..1c92fe0521 100644 --- a/include/exec/tb-lookup.h +++ b/include/exec/tb-lookup.h @@ -27,9 +27,6 @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc, hash = tb_jmp_cache_hash_func(pc); tb = qatomic_rcu_read(&cpu->tb_jmp_cache[hash]); - cf_mask &= ~CF_CLUSTER_MASK; - cf_mask |= cpu->cluster_index << CF_CLUSTER_SHIFT; - if (likely(tb && tb->pc == pc && tb->cs_base == cs_base && diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index ef96b312a1..45286dc4b3 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -249,8 +249,7 @@ void cpu_exec_step_atomic(CPUState *cpu) TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags; - uint32_t cflags = 1; - uint32_t cf_mask = cflags & CF_HASH_MASK; + uint32_t cflags = (curr_cflags(cpu) & ~CF_PARALLEL) | 1; int tb_exit; if (sigsetjmp(cpu->jmp_env, 0) == 0) { @@ -260,7 +259,7 @@ void cpu_exec_step_atomic(CPUState *cpu) cpu->running = true; cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - tb = tb_lookup(cpu, pc, cs_base, flags, cf_mask); + tb = tb_lookup(cpu, pc, cs_base, flags, cflags); if (tb == NULL) { mmap_lock(); @@ -497,7 +496,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret) if (replay_has_exception() && cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra == 0) { /* Execute just one insn to trigger exception pending in the log */ - cpu->cflags_next_tb = (curr_cflags() & ~CF_USE_ICOUNT) | 1; + cpu->cflags_next_tb = (curr_cflags(cpu) & ~CF_USE_ICOUNT) | 1; } #endif return false; @@ -794,7 +793,7 @@ int cpu_exec(CPUState *cpu) have CF_INVALID set, -1 is a convenient invalid value that does not require tcg headers for cpu_common_reset. */ if (cflags == -1) { - cflags = curr_cflags(); + cflags = curr_cflags(cpu); } else { cpu->cflags_next_tb = -1; } diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index 05e3d52c2f..99403e3eb3 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -154,7 +154,7 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - tb = tb_lookup(cpu, pc, cs_base, flags, curr_cflags()); + tb = tb_lookup(cpu, pc, cs_base, flags, curr_cflags(cpu)); if (tb == NULL) { return tcg_code_gen_epilogue; } diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index bbd919a393..f29b47f090 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -2194,7 +2194,7 @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages, if (current_tb_modified) { page_collection_unlock(pages); /* Force execution of one insn next time. */ - cpu->cflags_next_tb = 1 | curr_cflags(); + cpu->cflags_next_tb = 1 | curr_cflags(cpu); mmap_unlock(); cpu_loop_exit_noexc(cpu); } @@ -2362,7 +2362,7 @@ static bool tb_invalidate_phys_page(tb_page_addr_t addr, uintptr_t pc) #ifdef TARGET_HAS_PRECISE_SMC if (current_tb_modified) { /* Force execution of one insn next time. */ - cpu->cflags_next_tb = 1 | curr_cflags(); + cpu->cflags_next_tb = 1 | curr_cflags(cpu); return true; } #endif @@ -2438,7 +2438,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) * operations only (which execute after completion) so we don't * double instrument the instruction. */ - cpu->cflags_next_tb = curr_cflags() | CF_MEMI_ONLY | CF_LAST_IO | n; + cpu->cflags_next_tb = curr_cflags(cpu) | CF_MEMI_ONLY | CF_LAST_IO | n; qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc, "cpu_io_recompile: rewound execution of TB to " diff --git a/softmmu/physmem.c b/softmmu/physmem.c index 19e0aa9836..7e8b0fab89 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -937,7 +937,7 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, cpu_loop_exit_restore(cpu, ra); } else { /* Force execution of one insn next time. */ - cpu->cflags_next_tb = 1 | curr_cflags(); + cpu->cflags_next_tb = 1 | curr_cflags(cpu); mmap_unlock(); if (ra) { cpu_restore_state(cpu, ra, true); From patchwork Sat Mar 6 21:36:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 394577 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp555196jai; Sat, 6 Mar 2021 13:53:06 -0800 (PST) X-Google-Smtp-Source: ABdhPJwspfbnWadUyNu34C2RDRrqrt39Zh6POnwy8B3HbowIbpbEqa+lStOItpTfN/alfJlVF41A X-Received: by 2002:a6b:6f14:: with SMTP id k20mr13588004ioc.52.1615067586196; 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[209.51.188.17]) by mx.google.com with ESMTPS id o24si6346257jah.41.2021.03.06.13.53.06 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 06 Mar 2021 13:53:06 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uVSJMStO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:48722 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIerB-0005ck-LV for patch@linaro.org; Sat, 06 Mar 2021 16:53:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57026) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIebM-0007NG-9C for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:44 -0500 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:45760) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lIebK-00030v-0E for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:43 -0500 Received: by mail-pj1-x1034.google.com with SMTP id kr3-20020a17090b4903b02900c096fc01deso1060633pjb.4 for ; Sat, 06 Mar 2021 13:36:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qdJQTrZvuPYuM+1LU47WoaAqWeUYoE9iACFM/G+MpSw=; b=uVSJMStOZ6E3SXfHnGwwMhAuY3fJFpnFL+q4NhJAgzEdWoB+GEar3CCoh9RZMzYVeA 4Q+b6YBh++vtRrRpuRUm2hXXxTZCvUuXdgqQ6hsbQ4hsFfdt5zt4aidS/+8Jai0Sz7f2 ysZta3K0CExIJroPq85GoLBkL34oH3DiyYUcDX+v+d5JFi0ht0HMT51O15XX4FvGA9ro hZmF3C85aLif93tMGGBahSm0dNr2Go6O3Xhvnn4zLLO7B0RR00G82CfdItejAUrP7SDb o7iOoxl9n6D8rIgeQlj1HE7QdurZLWgNBOaLoHVXG+WayBWMLrKSQZ2kqSPsr1KOngI6 Ddug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qdJQTrZvuPYuM+1LU47WoaAqWeUYoE9iACFM/G+MpSw=; b=YUgqecCxTHpBZjjJSAp8eG2WcrLWzMsKsegQLjGH/e1JEBeV2wYtN4Ddy2/SArPbtK saB/W9XJdkEweq+tRJNCc0ux1RL88Opm5xTufgrbsFndLLLs45OtN2eMmcrswj27F5du DVCrk9nc8TpruUXqihrjoznFpxgik0lDxkwN1Hhnj5VOQUWhnz/A4UiDuh5wXpVTrFep 3i5y3ikM+0GYSmNbK+5irSV14Zmie74qOZddXV3bh0iKJ6/CvtiKYDctkioBPZ5lW7q8 sXqARz1Lzazl9mlNQJVPAtWvZxqMmcCmqrJQSvN7mwKfMIH4V9qlOgHPHsAJpaIqa+Gn kIsQ== X-Gm-Message-State: AOAM530hkx+oLDkno2wT6li9P03jTsuDP2RT1dr9x3fc7u64bTK8cnrC yqGDA5HALtV0O1EdgqekSsxM9IkOxbK7ow== X-Received: by 2002:a17:90a:8408:: with SMTP id j8mr15552596pjn.1.1615066600639; Sat, 06 Mar 2021 13:36:40 -0800 (PST) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id r30sm6365616pgu.86.2021.03.06.13.36.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Mar 2021 13:36:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 25/27] accel/tcg: drop the use of CF_HASH_MASK and rename params Date: Sat, 6 Mar 2021 13:36:11 -0800 Message-Id: <20210306213613.85168-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210306213613.85168-1-richard.henderson@linaro.org> References: <20210306213613.85168-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée We don't really deal in cf_mask most of the time. The one time it's relevant is when we want to remove an invalidated TB from the QHT lookup. Everywhere else we should be looking up things without CF_INVALID set. Signed-off-by: Alex Bennée Message-Id: <20210224165811.11567-4-alex.bennee@linaro.org> Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 4 +--- include/exec/tb-lookup.h | 9 ++++++--- accel/tcg/cpu-exec.c | 16 ++++++++-------- accel/tcg/tcg-runtime.c | 2 +- accel/tcg/translate-all.c | 8 +++++--- 5 files changed, 21 insertions(+), 18 deletions(-) -- 2.25.1 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 1a69c07add..acf66ab692 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -460,8 +460,6 @@ struct TranslationBlock { #define CF_PARALLEL 0x00080000 /* Generate code for a parallel context */ #define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */ #define CF_CLUSTER_SHIFT 24 -/* cflags' mask for hashing/comparison, basically ignore CF_INVALID */ -#define CF_HASH_MASK (~CF_INVALID) /* Per-vCPU dynamic tracing state used to generate this TB */ uint32_t trace_vcpu_dstate; @@ -538,7 +536,7 @@ void tb_flush(CPUState *cpu); void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, target_ulong cs_base, uint32_t flags, - uint32_t cf_mask); + uint32_t cflags); void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr); /* GETPC is the true target of the return instruction that we'll execute. */ diff --git a/include/exec/tb-lookup.h b/include/exec/tb-lookup.h index 1c92fe0521..29d61ceb34 100644 --- a/include/exec/tb-lookup.h +++ b/include/exec/tb-lookup.h @@ -19,11 +19,14 @@ /* Might cause an exception, so have a longjmp destination ready */ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc, target_ulong cs_base, - uint32_t flags, uint32_t cf_mask) + uint32_t flags, uint32_t cflags) { TranslationBlock *tb; uint32_t hash; + /* we should never be trying to look up an INVALID tb */ + tcg_debug_assert(!(cflags & CF_INVALID)); + hash = tb_jmp_cache_hash_func(pc); tb = qatomic_rcu_read(&cpu->tb_jmp_cache[hash]); @@ -32,10 +35,10 @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc, tb->cs_base == cs_base && tb->flags == flags && tb->trace_vcpu_dstate == *cpu->trace_dstate && - (tb_cflags(tb) & (CF_HASH_MASK | CF_INVALID)) == cf_mask)) { + tb_cflags(tb) == cflags)) { return tb; } - tb = tb_htable_lookup(cpu, pc, cs_base, flags, cf_mask); + tb = tb_htable_lookup(cpu, pc, cs_base, flags, cflags); if (tb == NULL) { return NULL; } diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 45286dc4b3..931da96c2b 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -307,7 +307,7 @@ struct tb_desc { CPUArchState *env; tb_page_addr_t phys_page1; uint32_t flags; - uint32_t cf_mask; + uint32_t cflags; uint32_t trace_vcpu_dstate; }; @@ -321,7 +321,7 @@ static bool tb_lookup_cmp(const void *p, const void *d) tb->cs_base == desc->cs_base && tb->flags == desc->flags && tb->trace_vcpu_dstate == desc->trace_vcpu_dstate && - (tb_cflags(tb) & (CF_HASH_MASK | CF_INVALID)) == desc->cf_mask) { + tb_cflags(tb) == desc->cflags) { /* check next page if needed */ if (tb->page_addr[1] == -1) { return true; @@ -341,7 +341,7 @@ static bool tb_lookup_cmp(const void *p, const void *d) TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, target_ulong cs_base, uint32_t flags, - uint32_t cf_mask) + uint32_t cflags) { tb_page_addr_t phys_pc; struct tb_desc desc; @@ -350,7 +350,7 @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, desc.env = (CPUArchState *)cpu->env_ptr; desc.cs_base = cs_base; desc.flags = flags; - desc.cf_mask = cf_mask; + desc.cflags = cflags; desc.trace_vcpu_dstate = *cpu->trace_dstate; desc.pc = pc; phys_pc = get_page_addr_code(desc.env, pc); @@ -358,7 +358,7 @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, return NULL; } desc.phys_page1 = phys_pc & TARGET_PAGE_MASK; - h = tb_hash_func(phys_pc, pc, flags, cf_mask, *cpu->trace_dstate); + h = tb_hash_func(phys_pc, pc, flags, cflags, *cpu->trace_dstate); return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp); } @@ -418,7 +418,7 @@ static inline void tb_add_jump(TranslationBlock *tb, int n, static inline TranslationBlock *tb_find(CPUState *cpu, TranslationBlock *last_tb, - int tb_exit, uint32_t cf_mask) + int tb_exit, uint32_t cflags) { CPUArchState *env = (CPUArchState *)cpu->env_ptr; TranslationBlock *tb; @@ -427,10 +427,10 @@ static inline TranslationBlock *tb_find(CPUState *cpu, cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - tb = tb_lookup(cpu, pc, cs_base, flags, cf_mask); + tb = tb_lookup(cpu, pc, cs_base, flags, cflags); if (tb == NULL) { mmap_lock(); - tb = tb_gen_code(cpu, pc, cs_base, flags, cf_mask); + tb = tb_gen_code(cpu, pc, cs_base, flags, cflags); mmap_unlock(); /* We add the TB in the virtual pc hash table for the fast lookup */ qatomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)], tb); diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index 99403e3eb3..49f5de37e8 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -27,10 +27,10 @@ #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/exec-all.h" -#include "exec/tb-lookup.h" #include "disas/disas.h" #include "exec/log.h" #include "tcg/tcg.h" +#include "exec/tb-lookup.h" /* 32-bit helpers */ diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index f29b47f090..0b0bfd35ab 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1311,7 +1311,7 @@ static bool tb_cmp(const void *ap, const void *bp) return a->pc == b->pc && a->cs_base == b->cs_base && a->flags == b->flags && - (tb_cflags(a) & CF_HASH_MASK) == (tb_cflags(b) & CF_HASH_MASK) && + (tb_cflags(a) & ~CF_INVALID) == (tb_cflags(b) & ~CF_INVALID) && a->trace_vcpu_dstate == b->trace_vcpu_dstate && a->page_addr[0] == b->page_addr[0] && a->page_addr[1] == b->page_addr[1]; @@ -1616,6 +1616,7 @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list) PageDesc *p; uint32_t h; tb_page_addr_t phys_pc; + uint32_t orig_cflags = tb_cflags(tb); assert_memory_lock(); @@ -1626,7 +1627,7 @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list) /* remove the TB from the hash list */ phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); - h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb_cflags(tb) & CF_HASH_MASK, + h = tb_hash_func(phys_pc, tb->pc, tb->flags, orig_cflags, tb->trace_vcpu_dstate); if (!qht_remove(&tb_ctx.htable, tb, h)) { return; @@ -1793,6 +1794,7 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, uint32_t h; assert_memory_lock(); + tcg_debug_assert(!(tb->cflags & CF_INVALID)); /* * Add the TB to the page list, acquiring first the pages's locks. @@ -1811,7 +1813,7 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, } /* add in the hash table */ - h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags & CF_HASH_MASK, + h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags, tb->trace_vcpu_dstate); qht_insert(&tb_ctx.htable, tb, h, &existing_tb); From patchwork Sat Mar 6 21:36:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 394575 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp554444jai; Sat, 6 Mar 2021 13:50:51 -0800 (PST) X-Google-Smtp-Source: ABdhPJwLDPw6dPxOUnEI8uHYsIa3a+K3j/utOpsUZT1lCfIzbr12dZORWcHWiHZmoGGNL0sKZuSQ X-Received: by 2002:a5d:9ec7:: with SMTP id a7mr12609900ioe.126.1615067451873; Sat, 06 Mar 2021 13:50:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615067451; cv=none; d=google.com; s=arc-20160816; b=xt6ryNrojk4oGxwkVjDT+RbErmmBUiCN3EvYtOCLXYwVhpM6/rB7GyxyIc8WY8Txjw AfjdczNzvLiAtxK8rhfHzlXrSzvK0ZbV2q9IYmA/SYTguHyNukZ4zSoVHMec9D01aYu1 yuLPOXRW9LP2z5yFnB4QUNjn3EeNiI10LeQk8Id5kiQfYMvSJ3FL2eF45IXkAR4a6XrJ a5OL5ZkXP+Tl/RsW+0YEIbCTcJ+IwVCUzzbDH4ye+ermLNwEdjkbyvuTU7ZirWIQlzS7 m5ylOq/+YwbzFm1SlRNNfMqyBV3qKxZybUevUTBU3rWllFnz2QtAaPOUhv5Jt7V0RNuE q8kA== ARC-Message-Signature: i=1; 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[209.51.188.17]) by mx.google.com with ESMTPS id a24si6626108iok.37.2021.03.06.13.50.51 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 06 Mar 2021 13:50:51 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ndos8ema; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41516 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lIep1-0002VX-8K for patch@linaro.org; Sat, 06 Mar 2021 16:50:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57036) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lIebM-0007Os-TU for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:44 -0500 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]:37542) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lIebL-000310-2o for qemu-devel@nongnu.org; Sat, 06 Mar 2021 16:36:44 -0500 Received: by mail-pj1-x1030.google.com with SMTP id x7-20020a17090a2b07b02900c0ea793940so995238pjc.2 for ; Sat, 06 Mar 2021 13:36:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=F8oLm+b5MpB59nkWYQpAlXOnlN0WpiVVfnOPsmvYmdk=; b=Ndos8emaMlLeaoogiRUa+YsIPwrZhJseoGnQL6HO8OKslWjGk0JePnohKxzAnb/NUk U0MQKw4gf7mbFj/TfDilaaWsutm+6cvj9qoal7irkWLuNPhVQKLsoJu2EPgodUk8vXtr 1eltfjhn6y96vGvzKSygiuPfX0mIGn45XKYUMb6rx/Fvo3iQPAy1dlsJNEAAJsnKQMVL u03SwA6EhqicMtCCNID26C1Co5o2/lj4VdNMZlTxBsBF/q8SVPTkcfQQJkJhyTrLyfMQ Y9KtT6jKpROKffWmBupNqNZ8Qdol1JxfUMnKdJ/8JDkw1sDj7Kt81ywJQkeT7hyIbKNQ 7UPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=F8oLm+b5MpB59nkWYQpAlXOnlN0WpiVVfnOPsmvYmdk=; b=uRr8W7I+utKq/wYrjyTAW9IVyzdWIb8zv6TGNXf9a+ZQk5oxc0S3u0zaieA7Rhlct6 KKxwcBJf9PGwPjU7h0Q0F1Ahz48oUil77JuYMeI5fw6OdFzFiWJ2ZQrsm/ldRMV3vM3u yAObpjBByWCQIEIAujTI1/6TIHoJzf0VtJtriXTC92MJ3cUsvOOViMPEo2UeSZnN1PW6 yHK5ojIfPHFHtlkqasCukBtusc+ZDM4U6j9tLngkxhUHWdzeRFrVRTu4ZJwZTje6Mc+l RfP6Et+xk7OxfQqAlLEzgeicN4ubmxLLx3U0KLY6u+PvDL/1LtDYXZYw5uRc2Vq5015o x24A== X-Gm-Message-State: AOAM532jmoM4bHby/4ORha51RKgiwFsBfs73Hg/Hq3ZJdAWSRP8bMSph WHs5fFk2liMZ/423j3vJbPQOaKi2F9MxXg== X-Received: by 2002:a17:90b:fd2:: with SMTP id gd18mr17221543pjb.115.1615066601707; Sat, 06 Mar 2021 13:36:41 -0800 (PST) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id r30sm6365616pgu.86.2021.03.06.13.36.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Mar 2021 13:36:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 26/27] include/exec: lightly re-arrange TranslationBlock Date: Sat, 6 Mar 2021 13:36:12 -0800 Message-Id: <20210306213613.85168-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210306213613.85168-1-richard.henderson@linaro.org> References: <20210306213613.85168-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Alex Bennée Lets make sure all the flags we compare when looking up blocks are together in the same place. Signed-off-by: Alex Bennée Message-Id: <20210224165811.11567-5-alex.bennee@linaro.org> Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) -- 2.25.1 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index acf66ab692..a262dd5804 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -448,9 +448,6 @@ struct TranslationBlock { target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */ target_ulong cs_base; /* CS base for this block */ uint32_t flags; /* flags defining in which context the code was generated */ - uint16_t size; /* size of target code for this block (1 <= - size <= TARGET_PAGE_SIZE) */ - uint16_t icount; uint32_t cflags; /* compile flags */ #define CF_COUNT_MASK 0x00007fff #define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */ @@ -464,6 +461,14 @@ struct TranslationBlock { /* Per-vCPU dynamic tracing state used to generate this TB */ uint32_t trace_vcpu_dstate; + /* + * Above fields used for comparing + */ + + /* size of target code for this block (1 <= size <= TARGET_PAGE_SIZE) */ + uint16_t size; + uint16_t icount; + struct tb_tc tc; /* first and second physical page containing code. The lower bit From patchwork Sat Mar 6 21:36:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 394574 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp554130jai; Sat, 6 Mar 2021 13:50:04 -0800 (PST) X-Google-Smtp-Source: ABdhPJzIPF2kXu7qS7enH8zYjW1zcRim4vl9Lyd6Tz9y0hKCeUWkAP+kGhkxLrYj/brlIUsM/ym4 X-Received: by 2002:a05:6e02:1049:: with SMTP id p9mr14388265ilj.125.1615067404032; Sat, 06 Mar 2021 13:50:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1615067404; cv=none; d=google.com; s=arc-20160816; b=c5bp3bniSchaabzL3G1vEHJ0DyoxVJXswQu+pbumTFVw5koVeKyDJqGO+ytg96lG9F yk2zXZBmSzv11B2B5lagL6Kbxn5/tpCSFZJxjU1CkquZO3dL8/Rt9/ygmSZ6RiJlgDOC 8rGwR08lLGUVAcbb0C5+B4yqmI59dSb+06pIWRS5kAql7ppPCX7Tg5O5PXln+2Y6zQnK e/Ij75IZbO8MDK2q7As9XB8h3mePpW4cRa/ZICS6srRVYdsdCoGaGJ9+d4xRHj5sqe4U TpTu+sgzHDebCQienRimflY0/4CtxH8pCfQOuDf2B9/+58/3UsNT6LpL40iRDwixSDES P89Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=GwJxG66e4p7W1I3fD4aM6XDpJ+3y7V4Z2paPMR5PGCU=; b=ZJZYYGtYU7+pBCPGyCj/opITS9/3qxedCkTPvVWSnu2LZy3VpN2Dg8RMpcsxyQhEod en3P1HVC5bJMCgspo8nSCK8s6sIYS01AbQSOnseJtosnaM26gRBf+nhvT6gB6higFvn7 vvUq5YTamOlxwuigneDjMQR2IviS+kHU/gBn/5L4IylhfN4BxVwhwlCWnpTSk9ha2Kgz 3CpjJa6f6193WVzy7x6c3yJ7CD4C7TC+391rxMO3vuU1hpMt/uA0R7XL4iV4It2/E5cj 1mOxDw09F7Ppjw/fxhouOjF84zt4jljrTnw5ukHWgaTroG7zpxbSXpJYkEwo0Gl+cR1J M7gg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qvYVtcTb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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As a byproduct, this allows us to completely remove parallel_cpus. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- accel/tcg/tcg-accel-ops.h | 1 + include/exec/exec-all.h | 7 +------ include/hw/core/cpu.h | 2 ++ accel/tcg/cpu-exec.c | 3 --- accel/tcg/tcg-accel-ops-mttcg.c | 3 +-- accel/tcg/tcg-accel-ops-rr.c | 2 +- accel/tcg/tcg-accel-ops.c | 8 ++++++++ accel/tcg/translate-all.c | 4 ---- linux-user/main.c | 1 + linux-user/sh4/signal.c | 8 +++++--- linux-user/syscall.c | 18 ++++++++++-------- 11 files changed, 30 insertions(+), 27 deletions(-) -- 2.25.1 diff --git a/accel/tcg/tcg-accel-ops.h b/accel/tcg/tcg-accel-ops.h index 48130006de..6a5fcef889 100644 --- a/accel/tcg/tcg-accel-ops.h +++ b/accel/tcg/tcg-accel-ops.h @@ -17,5 +17,6 @@ void tcg_cpus_destroy(CPUState *cpu); int tcg_cpus_exec(CPUState *cpu); void tcg_handle_interrupt(CPUState *cpu, int mask); +void tcg_cpu_init_cflags(CPUState *cpu, bool parallel); #endif /* TCG_CPUS_H */ diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index a262dd5804..6b036cae8f 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -513,8 +513,6 @@ struct TranslationBlock { uintptr_t jmp_dest[2]; }; -extern bool parallel_cpus; - /* Hide the qatomic_read to make code a little easier on the eyes */ static inline uint32_t tb_cflags(const TranslationBlock *tb) { @@ -524,10 +522,7 @@ static inline uint32_t tb_cflags(const TranslationBlock *tb) /* current cflags for hashing/comparison */ static inline uint32_t curr_cflags(CPUState *cpu) { - uint32_t cflags = deposit32(0, CF_CLUSTER_SHIFT, 8, cpu->cluster_index); - cflags |= parallel_cpus ? CF_PARALLEL : 0; - cflags |= icount_enabled() ? CF_USE_ICOUNT : 0; - return cflags; + return cpu->tcg_cflags; } /* TranslationBlock invalidate API */ diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index c005d3dc2d..c68bc3ba8a 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -282,6 +282,7 @@ struct qemu_work_item; * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will * be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER * QOM parent. + * @tcg_cflags: Pre-computed cflags for this cpu. * @nr_cores: Number of cores within this CPU package. * @nr_threads: Number of threads within this CPU. * @running: #true if CPU is currently running (lockless). @@ -412,6 +413,7 @@ struct CPUState { /* TODO Move common fields from CPUArchState here. */ int cpu_index; int cluster_index; + uint32_t tcg_cflags; uint32_t halted; uint32_t can_do_io; int32_t exception_index; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 931da96c2b..bdfa036ac8 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -267,8 +267,6 @@ void cpu_exec_step_atomic(CPUState *cpu) mmap_unlock(); } - /* Since we got here, we know that parallel_cpus must be true. */ - parallel_cpus = false; cpu_exec_enter(cpu); /* execute the generated code */ trace_exec_tb(tb, pc); @@ -296,7 +294,6 @@ void cpu_exec_step_atomic(CPUState *cpu) * the execution. */ g_assert(cpu_in_exclusive_context(cpu)); - parallel_cpus = true; cpu->running = false; end_exclusive(); } diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttcg.c index 42973fb062..847d2079d2 100644 --- a/accel/tcg/tcg-accel-ops-mttcg.c +++ b/accel/tcg/tcg-accel-ops-mttcg.c @@ -114,8 +114,7 @@ void mttcg_start_vcpu_thread(CPUState *cpu) char thread_name[VCPU_THREAD_NAME_SIZE]; g_assert(tcg_enabled()); - - parallel_cpus = (current_machine->smp.max_cpus > 1); + tcg_cpu_init_cflags(cpu, current_machine->smp.max_cpus > 1); cpu->thread = g_malloc0(sizeof(QemuThread)); cpu->halt_cond = g_malloc0(sizeof(QemuCond)); diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c index 4a66055e0d..018b54c508 100644 --- a/accel/tcg/tcg-accel-ops-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -269,7 +269,7 @@ void rr_start_vcpu_thread(CPUState *cpu) static QemuThread *single_tcg_cpu_thread; g_assert(tcg_enabled()); - parallel_cpus = false; + tcg_cpu_init_cflags(cpu, false); if (!single_tcg_cpu_thread) { cpu->thread = g_malloc0(sizeof(QemuThread)); diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 6144d9df87..6cdcaa2855 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -41,6 +41,14 @@ /* common functionality among all TCG variants */ +void tcg_cpu_init_cflags(CPUState *cpu, bool parallel) +{ + uint32_t cflags = cpu->cluster_index << CF_CLUSTER_SHIFT; + cflags |= parallel ? CF_PARALLEL : 0; + cflags |= icount_enabled() ? CF_USE_ICOUNT : 0; + cpu->tcg_cflags = cflags; +} + void tcg_cpus_destroy(CPUState *cpu) { cpu_thread_signal_destroyed(cpu); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 0b0bfd35ab..f32df8b240 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -224,7 +224,6 @@ static void *l1_map[V_L1_MAX_SIZE]; TCGContext tcg_init_ctx; __thread TCGContext *tcg_ctx; TBContext tb_ctx; -bool parallel_cpus; static void page_table_config_init(void) { @@ -1867,9 +1866,6 @@ TranslationBlock *tb_gen_code(CPUState *cpu, cflags = (cflags & ~CF_COUNT_MASK) | 1; } - cflags &= ~CF_CLUSTER_MASK; - cflags |= cpu->cluster_index << CF_CLUSTER_SHIFT; - max_insns = cflags & CF_COUNT_MASK; if (max_insns == 0) { max_insns = CF_COUNT_MASK; diff --git a/linux-user/main.c b/linux-user/main.c index 81f48ff54e..4f4746dce8 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -205,6 +205,7 @@ CPUArchState *cpu_copy(CPUArchState *env) /* Reset non arch specific state */ cpu_reset(new_cpu); + new_cpu->tcg_cflags = cpu->tcg_cflags; memcpy(new_env, env, sizeof(CPUArchState)); /* Clone all break/watchpoints. diff --git a/linux-user/sh4/signal.c b/linux-user/sh4/signal.c index cc89a48ff8..29c1ee30e6 100644 --- a/linux-user/sh4/signal.c +++ b/linux-user/sh4/signal.c @@ -82,9 +82,11 @@ static abi_ulong get_sigframe(struct target_sigaction *ka, return (sp - frame_size) & -8ul; } -/* Notice when we're in the middle of a gUSA region and reset. - Note that this will only occur for !parallel_cpus, as we will - translate such sequences differently in a parallel context. */ +/* + * Notice when we're in the middle of a gUSA region and reset. + * Note that this will only occur when #CF_PARALLEL is unset, as we + * will translate such sequences differently in a parallel context. + */ static void unwind_gusa(CPUSH4State *regs) { /* If the stack pointer is sufficiently negative, and we haven't diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 389ec09764..9522f603aa 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6481,6 +6481,16 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp, /* Grab a mutex so that thread setup appears atomic. */ pthread_mutex_lock(&clone_lock); + /* + * If this is our first additional thread, we need to ensure we + * generate code for parallel execution and flush old translations. + * Do this now so that the copy gets CF_PARALLEL too. + */ + if (!(cpu->tcg_cflags & CF_PARALLEL)) { + cpu->tcg_cflags |= CF_PARALLEL; + tb_flush(cpu); + } + /* we create a new CPU instance. */ new_env = cpu_copy(env); /* Init regs that differ from the parent. */ @@ -6521,14 +6531,6 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp, sigprocmask(SIG_BLOCK, &sigmask, &info.sigmask); cpu->random_seed = qemu_guest_random_seed_thread_part1(); - /* If this is our first additional thread, we need to ensure we - * generate code for parallel execution and flush old translations. - */ - if (!parallel_cpus) { - parallel_cpus = true; - tb_flush(cpu); - } - ret = pthread_create(&info.thread, &attr, clone_func, &info); /* TODO: Free new CPU state if thread creation failed. */