From patchwork Fri Apr 20 14:52:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 133885 Delivered-To: patches@linaro.org Received: by 10.46.66.142 with SMTP id h14csp374944ljf; Fri, 20 Apr 2018 07:52:56 -0700 (PDT) X-Google-Smtp-Source: AIpwx4/RdG9SMUTzKfKVaGz5QlX4D+uH3uxHV36a7Mm1BnzJ/tgUb4yMt7fzPoyLKcJYrPnJrYIK X-Received: by 10.99.123.17 with SMTP id w17mr8815236pgc.8.1524235976261; Fri, 20 Apr 2018 07:52:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524235976; cv=none; d=google.com; s=arc-20160816; b=kSrKcvvsbjNHLd5nRECGLOQ0egNGxr02oZ5kszwCDqxwh3hYFcY+Ul9ZxM387rnyhM dRINTmqLPeiksJnOXx2ewzy8ni8zRxxZUCPYlpbSYuL53C8FEObKGT7Hr2qxQBSKT7QH unfaBEGHrj32K64jow/496MQbAiNLrHcAFU6hRbmpi9Kme/Enl1VaggwbtkP9C+Pg9N8 X56Gdrr822IeK/uRd3qftVeEXlY4hLxqoefvO3ACA/eAUiiXVPl7Zc1gOgU83srpEO5f GBqxK043rbXex+qBa+rnXlH1xOV1TVbLVQPz03/zowVmIbHXKpfFHRGRGGSsXD7Z2nNn 0l+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=XS3ZbZ5fXJhiAxoSXAgmEV7xB2CzzELM5CAm4wwllGM=; b=OKs2BEMKte97x2LCIyF27HX5cTKwkrz514YlzdLObtOkw5dX8HFQ6uK/y0wt5vMijD UEka2hQBaalQYGcDspaxso+88duHO4NO+VOEUegQDN6YmCPgp+2ohMEwT8GicXLTr3Nh aKT3sckdWOZSzGlB2WKiIUDO/a9rVc7rVloVceenw8qQ6HYLy4dJGri8CNSYH1LigMfH X5zUbvseNo/KXFOWa0u2XG7fwhP068nKGoSvQDMRLjf/GZqfJet5VN8c0oVD//mKawa0 hbc6lJ7Y9HTWEXwJs3Y5hFd9rs/L+joXBS0weS38cr7Eklv8N9/Uwa9Otq+tlvwRV8MK zFmg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 1-v6si5677386plz.279.2018.04.20.07.52.55 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 20 Apr 2018 07:52:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1f9XP8-0006Wz-Q8; Fri, 20 Apr 2018 15:52:50 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, "Michael S . Tsirkin" , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Subject: [PATCH 01/13] hw/char/serial: Allow disconnected chardevs Date: Fri, 20 Apr 2018 15:52:37 +0100 Message-Id: <20180420145249.32435-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180420145249.32435-1-peter.maydell@linaro.org> References: <20180420145249.32435-1-peter.maydell@linaro.org> Currently the serial.c realize code has an explicit check that it is not connected to a disconnected backend (ie one with a NULL chardev). This isn't what we want -- you should be able to create a serial device even if it isn't attached to anything. Remove the check. Signed-off-by: Peter Maydell --- hw/char/serial.c | 5 ----- 1 file changed, 5 deletions(-) -- 2.17.0 Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Acked-by: Thomas Huth diff --git a/hw/char/serial.c b/hw/char/serial.c index eb72191ee7..2c080c9862 100644 --- a/hw/char/serial.c +++ b/hw/char/serial.c @@ -923,11 +923,6 @@ static int serial_be_change(void *opaque) void serial_realize_core(SerialState *s, Error **errp) { - if (!qemu_chr_fe_backend_connected(&s->chr)) { - error_setg(errp, "Can't create serial device, empty char device"); - return; - } - s->modem_status_poll = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) serial_update_msl, s); s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) fifo_timeout_int, s); From patchwork Fri Apr 20 14:52:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 133879 Delivered-To: patches@linaro.org Received: by 10.46.66.142 with SMTP id h14csp374874ljf; Fri, 20 Apr 2018 07:52:52 -0700 (PDT) X-Google-Smtp-Source: AIpwx49HLLbHZKI8QFsyZGa5qtVzFYwzSIUmHIrqrOzT+2JqLls3eodigKlls+UE53lBXuyrs3Zy X-Received: by 2002:adf:afe4:: with SMTP id y36-v6mr8547272wrd.107.1524235972354; Fri, 20 Apr 2018 07:52:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524235972; cv=none; d=google.com; s=arc-20160816; b=ecociFdmbfMtnmKm9vdhL9t2zrT7u5AnmJgQZP5GvQo0JE/XZVDTZQEfeeT91JYcqr Igzjh5/LkrS6Kji+PzU9vFFjGaW9tvpXh7gLMIYoPlN/FHRiAAMJ11/RXpfMNYf4zQPu X2J/Sznrbe0UPYZxmcGXdjH2jxB4FMVBbgWWAU95twi3e5PMuhAc7H9XHOE/yhgYyTaD wdQcqCQ0P+trNAFlXMtQADJmRvEFNIOrj/sk87xNlu22Ud30Ge5/iZAt1zGXoZj0c8is bhMbc0u/1p07X+DxcQxSYrnFH03AI7+7Cprxzl56HDoxZ8Z4gqXwyGhyPSM+c4Npb98h OaLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=vib07ld9Y/c8nmzzwNlIbDJbw1IlASvZ1uk8diO0Mmk=; b=CmlOhEzlMj5vgZmgjshXzqqQhpOFqxxULW8Us+LDJSTUGH3Z0ZyU3bXcPIcRK2EcV5 +btvUHXAyYidvW++jpSBaR1y3k/qGkMWEWbfrPLbMyJVFhSJU61CPESGHA5bdA/gs7q/ hy/R/cHMS4fJBfiAHE0/JLL/U3FGFsLayLhKrP8WjWCM/IRRCL4NzYQVkqpeYrxZ++js PW82aSs/RLKndlu5svgB87OvJy4xKOshiHK1uX3JB75QKHunS2gn3d1F7LtWfDjvrVtR pWI2Faj6Y2dcr7n9FMa0TVICtrYsR8yHw7ZhekAwYdyNyAPWWJwsiqrFJeA4yHXnnuP7 2iEg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id y63si1210197wmb.109.2018.04.20.07.52.52 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 20 Apr 2018 07:52:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1f9XP9-0006XC-HZ; Fri, 20 Apr 2018 15:52:51 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, "Michael S . Tsirkin" , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Subject: [PATCH 02/13] hw/arm/fsl-imx*: Don't create "null" chardevs for serial devices Date: Fri, 20 Apr 2018 15:52:38 +0100 Message-Id: <20180420145249.32435-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180420145249.32435-1-peter.maydell@linaro.org> References: <20180420145249.32435-1-peter.maydell@linaro.org> Following commit 12051d82f004024, UART devices should handle being passed a NULL pointer chardev, so we don't need to create "null" backends in board code. Remove the code that does this and updates serial_hds[]. (fsl-imx7.c was already written this way.) Signed-off-by: Peter Maydell --- hw/arm/fsl-imx25.c | 12 +----------- hw/arm/fsl-imx31.c | 12 +----------- hw/arm/fsl-imx6.c | 13 +------------ 3 files changed, 3 insertions(+), 34 deletions(-) -- 2.17.0 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index cb988a6c25..d7d064e5ce 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -118,17 +118,7 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp) }; if (i < MAX_SERIAL_PORTS) { - Chardev *chr; - - chr = serial_hds[i]; - - if (!chr) { - char label[20]; - snprintf(label, sizeof(label), "imx31.uart%d", i); - chr = qemu_chr_new(label, "null"); - } - - qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr); + qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hds[i]); } object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c index 3eee83d547..e6c788049d 100644 --- a/hw/arm/fsl-imx31.c +++ b/hw/arm/fsl-imx31.c @@ -107,17 +107,7 @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp) }; if (i < MAX_SERIAL_PORTS) { - Chardev *chr; - - chr = serial_hds[i]; - - if (!chr) { - char label[20]; - snprintf(label, sizeof(label), "imx31.uart%d", i); - chr = qemu_chr_new(label, "null"); - } - - qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr); + qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hds[i]); } object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index 9dfbc9a8c4..ea14de33c6 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -189,18 +189,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) }; if (i < MAX_SERIAL_PORTS) { - Chardev *chr; - - chr = serial_hds[i]; - - if (!chr) { - char *label = g_strdup_printf("imx6.uart%d", i + 1); - chr = qemu_chr_new(label, "null"); - g_free(label); - serial_hds[i] = chr; - } - - qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr); + qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hds[i]); } object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); From patchwork Fri Apr 20 14:52:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 133883 Delivered-To: patches@linaro.org Received: by 10.46.66.142 with SMTP id h14csp374919ljf; Fri, 20 Apr 2018 07:52:54 -0700 (PDT) X-Google-Smtp-Source: AIpwx49Jpv70uLgJhiH6vOoJLYWfUg3JnKUzoYgugMvMxOMf84VkBlCBePYlJTpi2byWYKY+bSup X-Received: by 2002:a17:902:2f84:: with SMTP id t4-v6mr10804997plb.24.1524235974549; Fri, 20 Apr 2018 07:52:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524235974; cv=none; d=google.com; s=arc-20160816; b=VM4xGPIaOER+ciQxLay6KFtvJwDLbllO6J9OPLXhBYW4hSX0VJysL3wF0JLHQLVXj5 xuklcEXgZHhrs+uE2aOF/9NHKql57DbshDY0IyOu4pICOQOoXij9FJKYzeZoSdJZBXE8 YZSFjLvw6DxVUgOe4rdZ9aBkqD7voYrNsqm4CkxTfDgJfNHeCMbraJKsBAOkqVRcMjFU vF9O97/cI9CY76qf9MWvAYmAzE9lw3UE7Ezykm7tfV5Nevp+R1ELuSdLW/lPOiPDYUS8 ktOICz3wCrJodk38dTWtxABhMFYgSq1Arx0dXlNlAfyjGB6APiLfCxCWWyVe753vVtCP cstw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=Lt3jaGwVxKCIvZC7Hkn6qOt5guOz6wEvrjQhKp5vUGQ=; b=N3sE4WdGcC/YOyROtC2Iseczs9LGPALSWDdkWnU2WixsW4g3GN7t3NYltqgMG0DIEq Rerjwsq9xfr9OHRvzoC4ZYNsqwFnTmxyCEoq7U1eh9ES9Qb5aSgJq8AX1MVPa2oWzZOa NFBuz55lUobFzHLTVAfSGTpBOhYm0SH6u4/YaabiJRYU7qj9RvFWXmFsCjIUi3YF+5cE uuq3ggWp16lNN1I/dT3MNjemQwxlaQst+wcdWXXQEFBr7H7iXFHD75NKjwmFNumWfHEV munybISSqUISOGLzpzTogVi/GALbc3q0GHRgfN+1fiZvWIOUQQT2rQfF2Tyj5mInHT+F 48pg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id c6-v6si5735907pll.498.2018.04.20.07.52.53 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 20 Apr 2018 07:52:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1f9XPA-0006XY-8F; Fri, 20 Apr 2018 15:52:52 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, "Michael S . Tsirkin" , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Subject: [PATCH 03/13] hw/mips/boston.c: Don't create "null" chardevs for serial devices Date: Fri, 20 Apr 2018 15:52:39 +0100 Message-Id: <20180420145249.32435-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180420145249.32435-1-peter.maydell@linaro.org> References: <20180420145249.32435-1-peter.maydell@linaro.org> Following commit 12051d82f004024, UART devices should handle being passed a NULL pointer chardev, so we don't need to create "null" backends in board code. Remove the code that does this and updates serial_hds[]. Signed-off-by: Peter Maydell --- hw/mips/boston.c | 4 ---- 1 file changed, 4 deletions(-) -- 2.17.0 Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth diff --git a/hw/mips/boston.c b/hw/mips/boston.c index fb23161b33..14f0f6673b 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -505,10 +505,6 @@ static void boston_mach_init(MachineState *machine) "boston-platregs", 0x1000); memory_region_add_subregion_overlap(sys_mem, 0x17ffd000, platreg, 0); - if (!serial_hds[0]) { - serial_hds[0] = qemu_chr_new("serial0", "null"); - } - s->uart = serial_mm_init(sys_mem, 0x17ffe000, 2, get_cps_irq(s->cps, 3), 10000000, serial_hds[0], DEVICE_NATIVE_ENDIAN); From patchwork Fri Apr 20 14:52:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 133881 Delivered-To: patches@linaro.org Received: by 10.46.66.142 with SMTP id h14csp374895ljf; Fri, 20 Apr 2018 07:52:53 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpn57j/nfb4G7Pk7PspVrRxVcIj4F8tiGdksR3EhaMEz10INbqTP+d3ZSROdxlwaxgNDBG+ X-Received: by 10.28.111.7 with SMTP id k7mr2156376wmc.148.1524235973507; Fri, 20 Apr 2018 07:52:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524235973; cv=none; d=google.com; s=arc-20160816; b=t1E+D6MAS9cfeMHyAfJK2JwxSsI3hls/i7InZrtfH6u8nIcN/hofNWOr+VB6oO2JZV Ia5iWN4fIQ1fa3b/TbgnlFMJwBVcFsrJmdvw1pKcsYjK7NZE4eLTvAvBbYZk3jky6pu1 QCQAnUdmC+W6QH9134WuPpsUGFRKvWfdAbjv/o5rt9RZsykvo+znSIPsmdcMMzoFxtu2 CxDEykkFdqdYX/1bETHu+vk09W9AzXCUksPbOKRStsDjjwWa3iZx9tmo1mz2kqlXM5ps YiOlJhZbiLXwI6Wfa7AD0VxGsaS6JUpCRnRqBanHcEAbIHBPiCGfuskIDiIh0qMVNfmg vMLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=IWmJP37OwLpLnfBZoXaJRL/8eRZwfhTY3qNXO2JmkL8=; b=EDyRV0efL7Scn6JQgR04nGsnSAJ80RDJ8bOVpHutnFZPklGW24zIJfe3JD3pImkrhd YbDgOPrGpZauYPf0qW153CmU1JzQX3tx0VSpdpwG76lwAW/iU75unb3ead3mIJPme6yb PRTd5Aam22CHAOwM4cU8sE0NL++ojfrCrt34ZkUZLAm3D4V1XsFyUjuj33oNPStTuL51 7IlSuy8gBDMKSgtklXVonlvff16gCLXNaOARiSi15rxTXhSctf//6KTFoEpFZ/gjgvHH jRnlYT2yV2CghRHn3yOmUsW/drQV0Kj9aZFCVLTGMT3boipz2yPdOnrPQXUP0ecEBifK 7LbQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id b2si1184725wmh.214.2018.04.20.07.52.53 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 20 Apr 2018 07:52:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1f9XPB-0006Xr-0L; Fri, 20 Apr 2018 15:52:53 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, "Michael S . Tsirkin" , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Subject: [PATCH 04/13] hw/mips/mips_malta: Don't create "null" chardevs for serial devices Date: Fri, 20 Apr 2018 15:52:40 +0100 Message-Id: <20180420145249.32435-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180420145249.32435-1-peter.maydell@linaro.org> References: <20180420145249.32435-1-peter.maydell@linaro.org> Following commit 12051d82f004024, UART devices should handle being passed a NULL pointer chardev, so we don't need to create "null" backends in board code. Remove the code that does this and updates serial_hds[]. Signed-off-by: Peter Maydell --- hw/mips/mips_malta.c | 5 ----- 1 file changed, 5 deletions(-) -- 2.17.0 Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index f6513a4fd5..49fe7a0a72 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -1056,11 +1056,6 @@ void mips_malta_init(MachineState *machine) /* FPGA */ - /* Make sure the second serial port is associated with a device. */ - if (!serial_hds[2]) { - serial_hds[2] = qemu_chr_new("fpga-uart", "null"); - } - /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */ malta_fpga_init(system_memory, FPGA_ADDRESS, cbus_irq, serial_hds[2]); From patchwork Fri Apr 20 14:52:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 133882 Delivered-To: patches@linaro.org Received: by 10.46.66.142 with SMTP id h14csp374916ljf; Fri, 20 Apr 2018 07:52:54 -0700 (PDT) X-Google-Smtp-Source: AIpwx49icYg50baWj+Jm5CLEwq/SjotHZ6MM9X6KdpWaVAUv9mql5ujqXm1Tr6J21j361dJfzKp6 X-Received: by 2002:adf:df07:: with SMTP id y7-v6mr2664031wrl.279.1524235974410; Fri, 20 Apr 2018 07:52:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524235974; cv=none; d=google.com; s=arc-20160816; b=cB9HTA8DA5BT20FUbyBJQ1ARLsK3BgqjqTxqtDors3+ss9L8PQhdgRHABPRcxgSvY9 2hMuV5/Tuph1tpIatzwnckNHYUy5Js8a71UKz31r+D8eWC2ATBXiGl8XvM6SBHYPtFmD E1B3wbg/1gk9WN/HBd/F6Gv3PKxz4Dx9xcAi+o5Sp0/AP5QsKZCGonYpIc/amVUEhHpp W+59Rcvn5Y7cmiZlpe3Sv67rsapOrOwKiH82BRumXSOzURPBqteJ8tR0jNm3qa6ssArL EAQXjGyCne04CBvosUTYu6vp2SLVYozT0X429h0YPP1Vi5B+jzAdcV7wb9FiFWVgMGSa FnOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=Bph8DFMPlXKvzHIqMyoBWueTDveSq0k2W/AjsDjZyoQ=; b=T6jPrN0PHrLXOTT0Eoxe9CiXkptPmJSQV+6kGLiN+loUJ5kMyhsK19xNtsn4TQUOEZ kKZ0yt9XEpUSz76OEP129QzYM5zVpC4vNATHHKTHA4GPtv2Ems3p9wAUyX8aFqmweFYt WzIh0u8t3DU/aj7g8ZQduSzJE/cZlLWs1CiMJIhwe+IcuuWico66wj3AKywE0Cp2mayQ RIuUCLy0njSaYJfOYwmxBGqE3/5oJcLo70JeKRyzFxzjYNYei3e/Hhjne8vi4A3CnytH CimYEDZ8bGJC/RQocD+hl9YLyfgWFhWOhhW2ucDptVvpkS+mZrBozb0saULIEqCBiyc9 6n1A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id d12-v6si4557034wri.23.2018.04.20.07.52.54 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 20 Apr 2018 07:52:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1f9XPB-0006YB-PX; Fri, 20 Apr 2018 15:52:53 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, "Michael S . Tsirkin" , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Subject: [PATCH 05/13] hw/xtensa/xtfpga.c: Don't create "null" chardevs for serial devices Date: Fri, 20 Apr 2018 15:52:41 +0100 Message-Id: <20180420145249.32435-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180420145249.32435-1-peter.maydell@linaro.org> References: <20180420145249.32435-1-peter.maydell@linaro.org> Following commit 12051d82f004024, UART devices should handle being passed a NULL pointer chardev, so we don't need to create "null" backends in board code. Remove the code that does this and updates serial_hds[]. Signed-off-by: Peter Maydell --- hw/xtensa/xtfpga.c | 4 ---- 1 file changed, 4 deletions(-) -- 2.17.0 Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c index 70686a2eb1..9db99e1f7e 100644 --- a/hw/xtensa/xtfpga.c +++ b/hw/xtensa/xtfpga.c @@ -278,10 +278,6 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) xtensa_get_extint(env, 1), nd_table); } - if (!serial_hds[0]) { - serial_hds[0] = qemu_chr_new("serial0", "null"); - } - serial_mm_init(system_io, 0x0d050020, 2, xtensa_get_extint(env, 0), 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); From patchwork Fri Apr 20 14:52:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 133884 Delivered-To: patches@linaro.org Received: by 10.46.66.142 with SMTP id h14csp374924ljf; Fri, 20 Apr 2018 07:52:55 -0700 (PDT) X-Google-Smtp-Source: AIpwx48UZEVVmd/meDrNtUQl5m1emS+f5VYxlWhcBgjCiQzMxo1bo4YdszrEYUcfeRr4sf28J7C0 X-Received: by 2002:adf:9893:: with SMTP id w19-v6mr6374377wrb.34.1524235975030; Fri, 20 Apr 2018 07:52:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524235975; cv=none; d=google.com; s=arc-20160816; b=lkVtc7BbJ4s5PWvZOayC17jms/w7Twej+b4bxhw86fhLYOBbnUY97NSzngQgz/XHsn g6RFqi07EjMCp5PGHX/rYpd7mxM63LxnGjhjB2Vkn2AC20t65OddG22yc94+e+gCdsXz WAE57EBeTmgzE5FCSRDp4bphHde79+87vp5K4DYlj6dxAZDXrCe1d7XqHHy2XX85BjN0 OsM0Mi5PktgibIj7lSjVUqoHeQQ+J24bWAJX4Cj1hghI9qX5E4/lG2DzbtG1XU1wmuoq /HIf1h3N5C/quHeX+/Sxhsf4SwY6V5iN+moXUyNgNCZxYqlHCjOS6QKoy9R2XkmtfXlG 7CzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=DL2DZy9iKaBWIvXWzRzsHzUDMJOpbmCYEErUmRzHyFg=; b=TZI3bGjtia8rDqL8REHck9Czyu61bMAyTmLFkgfSqq3S7gSXSwLewrkb/FdjG5oxJw LmoarIpM95BgbY/nfS9Ws/4UEIIjUy1VvKfN85F18Hi0jS41rLRO8fBBtl2pRHljxF2K uUzsfDP50LwYjWqlmCvqQ0LnFtOVOh0VUcK/5utWyNS4zfZMzENje0MMNhCrwcsUq3Ip Zoi2kuZNHu3RB6IQ4nytYNPhd1LCC1BhX0SnHOb9OcRp+pRhuVBNo+j/tHLk1ESZUm7f j9/6LltU2eXUXKA967ICJ29aFikNgYCHLysYpohLblmZNOt/Gdc3SFT47xD/34Wc+b2N L5EA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id y110-v6si5055297wrb.305.2018.04.20.07.52.54 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 20 Apr 2018 07:52:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1f9XPC-0006Yj-Gy; Fri, 20 Apr 2018 15:52:54 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, "Michael S . Tsirkin" , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Subject: [PATCH 06/13] vl.c: Provide accessor function serial_hd() for serial_hds[] array Date: Fri, 20 Apr 2018 15:52:42 +0100 Message-Id: <20180420145249.32435-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180420145249.32435-1-peter.maydell@linaro.org> References: <20180420145249.32435-1-peter.maydell@linaro.org> Provide an accessor function serial_hd() to return the Chardev (if any) associated with the numbered serial port. This will be used to replace direct accesses to the serial_hds[] array, so that calling code doesn't need to care about the size of that array. Signed-off-by: Peter Maydell --- include/sysemu/sysemu.h | 3 +++ vl.c | 9 +++++++++ 2 files changed, 12 insertions(+) -- 2.17.0 Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h index 2b42151c63..bd5b55c514 100644 --- a/include/sysemu/sysemu.h +++ b/include/sysemu/sysemu.h @@ -163,6 +163,9 @@ void hmp_pcie_aer_inject_error(Monitor *mon, const QDict *qdict); extern Chardev *serial_hds[MAX_SERIAL_PORTS]; +/* Return the Chardev for serial port i, or NULL if none */ +Chardev *serial_hd(int i); + /* parallel ports */ #define MAX_PARALLEL_PORTS 3 diff --git a/vl.c b/vl.c index fce1fd12d8..6daf026da6 100644 --- a/vl.c +++ b/vl.c @@ -2516,6 +2516,15 @@ static int serial_parse(const char *devname) return 0; } +Chardev *serial_hd(int i) +{ + assert(i >= 0); + if (i < ARRAY_SIZE(serial_hds)) { + return serial_hds[i]; + } + return NULL; +} + static int parallel_parse(const char *devname) { static int index = 0; From patchwork Fri Apr 20 14:52:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 133888 Delivered-To: patches@linaro.org Received: by 10.46.66.142 with SMTP id h14csp374940ljf; Fri, 20 Apr 2018 07:52:56 -0700 (PDT) X-Google-Smtp-Source: AIpwx49jrv9HFIWKY6c3OQ3CKNnniInocWraIScPyyJnmIHQhwc2qF/VCMGAWnnRf0PbnMPkOT7e X-Received: by 2002:adf:9b83:: with SMTP id d3-v6mr8333077wrc.58.1524235976150; Fri, 20 Apr 2018 07:52:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524235976; cv=none; d=google.com; s=arc-20160816; b=YjGRWZ7eOQe7yswgeykJcNR7zKAGpMCJn+dIJKVmoN54DNtK7HZRRalfwEuw+x7eDo GhMQ2AttsybfehuKwBA/+QGtMKFSmYvAUzq6sx93vUIPBBMhpC8XlVTLfrhCbbqM2gfK p15huIRMul+uCPC1QSQ8MSEDOw+nTkh8C6VaZ4MPzqRn8sCB5C22sWTjyzJTN0eI3Pt/ ZMTsMSUg4hZn93UpHurM5Dj8At6IOa5BihfrWXp4H6TPRF219K195akrpBU5cXBQ285w Re8fdQUn4zLLAuBY4b4F0lo0vEoDNMAqwZaJMXeWdN8cJoaMEwl6UkfG3IPvwYrgBdBO Zzwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=4KA+FnxIX0Ge4oKFU5xodUeByiOAEeXrAgm3WNV+B5E=; b=ftBIIqcec+Ro7Kc9ofYk7zjGmr3bZVGHhi9UjUiaXt1RDPR/fSfrCYld4rw+e1ITCx WkFPTI7nV59h5fYZNWyxlpf0qmn4tklLB2pTxqzZZcXkkj4ySqzbmKkD/AD9/tya8uoI K9M1jwebDFDeTMNu8BSNCtRJBib64mFkYYZoKOXXc29Y/MqFbAwh26aSW6D3eCP8IfoM AK/SJMwMP5j188mAGixMn226kJNeVST1QdIztdsKahW/jZAd+DvD+xwYrsYhXFnvwFZR Zpg/LiVVikIMaZQddK3zvDKSAeEd+Je6izcbk8DoOht7ipM20Li3YnzOvAoFYzWLb0QK Pu2w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id g80-v6si4919453wrd.221.2018.04.20.07.52.55 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 20 Apr 2018 07:52:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1f9XPD-0006Zb-8B; Fri, 20 Apr 2018 15:52:55 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, "Michael S . Tsirkin" , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Subject: [PATCH 07/13] Change references to serial_hds[] to serial_hd() Date: Fri, 20 Apr 2018 15:52:43 +0100 Message-Id: <20180420145249.32435-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180420145249.32435-1-peter.maydell@linaro.org> References: <20180420145249.32435-1-peter.maydell@linaro.org> Change all the uses of serial_hds[] to go via the new serial_hd() function. Code change produced with: find hw -name '*.[ch]' | xargs sed -i -e 's/serial_hds\[\([^]]*\)\]/serial_hd(\1)/g' Signed-off-by: Peter Maydell --- hw/arm/allwinner-a10.c | 4 ++-- hw/arm/aspeed_soc.c | 4 ++-- hw/arm/bcm2835_peripherals.c | 4 ++-- hw/arm/digic.c | 2 +- hw/arm/fsl-imx25.c | 2 +- hw/arm/fsl-imx31.c | 2 +- hw/arm/fsl-imx6.c | 4 ++-- hw/arm/fsl-imx7.c | 2 +- hw/arm/highbank.c | 2 +- hw/arm/integratorcp.c | 4 ++-- hw/arm/kzm.c | 4 ++-- hw/arm/mps2-tz.c | 2 +- hw/arm/mps2.c | 4 ++-- hw/arm/msf2-soc.c | 4 ++-- hw/arm/musicpal.c | 8 ++++---- hw/arm/omap1.c | 6 +++--- hw/arm/omap2.c | 10 +++++----- hw/arm/pxa2xx.c | 16 ++++++++-------- hw/arm/realview.c | 8 ++++---- hw/arm/stellaris.c | 2 +- hw/arm/stm32f205_soc.c | 2 +- hw/arm/strongarm.c | 2 +- hw/arm/versatilepb.c | 8 ++++---- hw/arm/vexpress.c | 8 ++++---- hw/arm/virt.c | 4 ++-- hw/arm/xilinx_zynq.c | 4 ++-- hw/arm/xlnx-zynqmp.c | 2 +- hw/char/exynos4210_uart.c | 2 +- hw/char/serial-isa.c | 4 ++-- hw/char/xen_console.c | 2 +- hw/cris/axis_dev88.c | 2 +- hw/hppa/machine.c | 4 ++-- hw/isa/isa-superio.c | 4 ++-- hw/lm32/lm32_boards.c | 8 ++++---- hw/lm32/milkymist.c | 4 ++-- hw/m68k/mcf5206.c | 4 ++-- hw/m68k/mcf5208.c | 6 +++--- hw/microblaze/petalogix_ml605_mmu.c | 2 +- hw/microblaze/petalogix_s3adsp1800_mmu.c | 2 +- hw/mips/boston.c | 2 +- hw/mips/mips_jazz.c | 8 ++++---- hw/mips/mips_malta.c | 2 +- hw/mips/mips_mipssim.c | 4 ++-- hw/misc/macio/macio.c | 4 ++-- hw/moxie/moxiesim.c | 4 ++-- hw/nios2/10m50_devboard.c | 2 +- hw/openrisc/openrisc_sim.c | 2 +- hw/ppc/e500.c | 12 ++++++------ hw/ppc/ppc405_uc.c | 16 ++++++++-------- hw/ppc/ppc440_bamboo.c | 8 ++++---- hw/ppc/sam460ex.c | 8 ++++---- hw/ppc/spapr.c | 4 ++-- hw/ppc/virtex_ml507.c | 2 +- hw/riscv/sifive_e.c | 4 ++-- hw/riscv/sifive_u.c | 4 ++-- hw/riscv/spike.c | 4 ++-- hw/riscv/virt.c | 2 +- hw/sh4/r2d.c | 2 +- hw/sh4/sh7750.c | 4 ++-- hw/sparc/leon3.c | 4 ++-- hw/sparc/sun4m.c | 4 ++-- hw/sparc64/niagara.c | 4 ++-- hw/sparc64/sun4u.c | 2 +- hw/xtensa/sim.c | 4 ++-- hw/xtensa/xtfpga.c | 2 +- 65 files changed, 143 insertions(+), 143 deletions(-) -- 2.17.0 Reviewed-by: Thomas Huth diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index 5dbbacb7e8..c5fbc654f2 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -108,9 +108,9 @@ static void aw_a10_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE); sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, s->irq[56]); - /* FIXME use a qdev chardev prop instead of serial_hds[] */ + /* FIXME use a qdev chardev prop instead of serial_hd() */ serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1], - 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); + 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); } static void aw_a10_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 30d25f8b06..1219167a5e 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -229,11 +229,11 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, ASPEED_SOC_SCU_BASE); /* UART - attach an 8250 to the IO space as our UART5 */ - if (serial_hds[0]) { + if (serial_hd(0)) { qemu_irq uart5 = qdev_get_gpio_in(DEVICE(&s->vic), uart_irqs[4]); serial_mm_init(get_system_memory(), ASPEED_SOC_IOMEM_BASE + ASPEED_SOC_UART_5_BASE, 2, - uart5, 38400, serial_hds[0], DEVICE_LITTLE_ENDIAN); + uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); } /* I2C */ diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c index 13b63970d7..6be7660e8c 100644 --- a/hw/arm/bcm2835_peripherals.c +++ b/hw/arm/bcm2835_peripherals.c @@ -166,7 +166,7 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) sysbus_pass_irq(SYS_BUS_DEVICE(s), SYS_BUS_DEVICE(&s->ic)); /* UART0 */ - qdev_prop_set_chr(DEVICE(s->uart0), "chardev", serial_hds[0]); + qdev_prop_set_chr(DEVICE(s->uart0), "chardev", serial_hd(0)); object_property_set_bool(OBJECT(s->uart0), true, "realized", &err); if (err) { error_propagate(errp, err); @@ -179,7 +179,7 @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_UART)); /* AUX / UART1 */ - qdev_prop_set_chr(DEVICE(&s->aux), "chardev", serial_hds[1]); + qdev_prop_set_chr(DEVICE(&s->aux), "chardev", serial_hd(1)); object_property_set_bool(OBJECT(&s->aux), true, "realized", &err); if (err) { diff --git a/hw/arm/digic.c b/hw/arm/digic.c index 6184020985..726abb9b48 100644 --- a/hw/arm/digic.c +++ b/hw/arm/digic.c @@ -85,7 +85,7 @@ static void digic_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(sbd, 0, DIGIC4_TIMER_BASE(i)); } - qdev_prop_set_chr(DEVICE(&s->uart), "chardev", serial_hds[0]); + qdev_prop_set_chr(DEVICE(&s->uart), "chardev", serial_hd(0)); object_property_set_bool(OBJECT(&s->uart), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index d7d064e5ce..9731833fa5 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -118,7 +118,7 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp) }; if (i < MAX_SERIAL_PORTS) { - qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hds[i]); + qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); } object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c index e6c788049d..8509915200 100644 --- a/hw/arm/fsl-imx31.c +++ b/hw/arm/fsl-imx31.c @@ -107,7 +107,7 @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp) }; if (i < MAX_SERIAL_PORTS) { - qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hds[i]); + qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); } object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index ea14de33c6..535ad5888b 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -189,7 +189,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) }; if (i < MAX_SERIAL_PORTS) { - qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hds[i]); + qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); } object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); @@ -438,7 +438,7 @@ static void fsl_imx6_class_init(ObjectClass *oc, void *data) dc->realize = fsl_imx6_realize; dc->desc = "i.MX6 SOC"; - /* Reason: Uses serial_hds[] in the realize() function */ + /* Reason: Uses serial_hd() in the realize() function */ dc->user_creatable = false; } diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index 390b4310e6..2848d76d3c 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -391,7 +391,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) if (i < MAX_SERIAL_PORTS) { - qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hds[i]); + qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); } object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index 1742cf6f6c..0851d3b28a 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -342,7 +342,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id) busdev = SYS_BUS_DEVICE(dev); sysbus_mmio_map(busdev, 0, 0xfff34000); sysbus_connect_irq(busdev, 0, pic[18]); - pl011_create(0xfff36000, pic[20], serial_hds[0]); + pl011_create(0xfff36000, pic[20], serial_hd(0)); dev = qdev_create(NULL, TYPE_HIGHBANK_REGISTERS); qdev_init_nofail(dev); diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index 58b40efc19..4eceebb9ea 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -631,8 +631,8 @@ static void integratorcp_init(MachineState *machine) sysbus_create_varargs("integrator_pit", 0x13000000, pic[5], pic[6], pic[7], NULL); sysbus_create_simple("pl031", 0x15000000, pic[8]); - pl011_create(0x16000000, pic[1], serial_hds[0]); - pl011_create(0x17000000, pic[2], serial_hds[1]); + pl011_create(0x16000000, pic[1], serial_hd(0)); + pl011_create(0x17000000, pic[2], serial_hd(1)); icp = sysbus_create_simple(TYPE_ICP_CONTROL_REGS, 0xcb000000, qdev_get_gpio_in(sic, 3)); sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]); diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c index f9c2228e31..864c7bd411 100644 --- a/hw/arm/kzm.c +++ b/hw/arm/kzm.c @@ -121,10 +121,10 @@ static void kzm_init(MachineState *machine) qdev_get_gpio_in(DEVICE(&s->soc.avic), 52)); } - if (serial_hds[2]) { /* touchscreen */ + if (serial_hd(2)) { /* touchscreen */ serial_mm_init(get_system_memory(), KZM_FPGA_ADDR+0x10, 0, qdev_get_gpio_in(DEVICE(&s->soc.avic), 52), - 14745600, serial_hds[2], DEVICE_NATIVE_ENDIAN); + 14745600, serial_hd(2), DEVICE_NATIVE_ENDIAN); } kzm_binfo.ram_size = machine->ram_size; diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 8c86cffa9e..4ae4a5cb2a 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -172,7 +172,7 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, { CMSDKAPBUART *uart = opaque; int i = uart - &mms->uart[0]; - Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL; + Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hd(i) : NULL; int rxirqno = i * 2; int txirqno = i * 2 + 1; int combirqno = i + 10; diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 694fb36866..eb550fad34 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -230,7 +230,7 @@ static void mps2_common_init(MachineState *machine) static const hwaddr uartbase[] = {0x40004000, 0x40005000, 0x40006000, 0x40007000, 0x40009000}; - Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL; + Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hd(i) : NULL; /* RX irq number; TX irq is always one greater */ static const int uartirq[] = {0, 2, 4, 18, 20}; qemu_irq txovrint = NULL, rxovrint = NULL; @@ -270,7 +270,7 @@ static void mps2_common_init(MachineState *machine) static const hwaddr uartbase[] = {0x40004000, 0x40005000, 0x4002c000, 0x4002d000, 0x4002e000}; - Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL; + Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hd(i) : NULL; Object *txrx_orgate; DeviceState *txrx_orgate_dev; diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c index f68df56b97..75c44adf7d 100644 --- a/hw/arm/msf2-soc.c +++ b/hw/arm/msf2-soc.c @@ -138,10 +138,10 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) system_clock_scale = NANOSECONDS_PER_SECOND / s->m3clk; for (i = 0; i < MSF2_NUM_UARTS; i++) { - if (serial_hds[i]) { + if (serial_hd(i)) { serial_mm_init(get_system_memory(), uart_addr[i], 2, qdev_get_gpio_in(armv7m, uart_irq[i]), - 115200, serial_hds[i], DEVICE_NATIVE_ENDIAN); + 115200, serial_hd(i), DEVICE_NATIVE_ENDIAN); } } diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index 38d7322a19..c807010e83 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -1610,13 +1610,13 @@ static void musicpal_init(MachineState *machine) pic[MP_TIMER2_IRQ], pic[MP_TIMER3_IRQ], pic[MP_TIMER4_IRQ], NULL); - if (serial_hds[0]) { + if (serial_hd(0)) { serial_mm_init(address_space_mem, MP_UART1_BASE, 2, pic[MP_UART1_IRQ], - 1825000, serial_hds[0], DEVICE_NATIVE_ENDIAN); + 1825000, serial_hd(0), DEVICE_NATIVE_ENDIAN); } - if (serial_hds[1]) { + if (serial_hd(1)) { serial_mm_init(address_space_mem, MP_UART2_BASE, 2, pic[MP_UART2_IRQ], - 1825000, serial_hds[1], DEVICE_NATIVE_ENDIAN); + 1825000, serial_hd(1), DEVICE_NATIVE_ENDIAN); } /* Register flash */ diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c index b3a23a83d1..24673abfca 100644 --- a/hw/arm/omap1.c +++ b/hw/arm/omap1.c @@ -3963,21 +3963,21 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, omap_findclk(s, "uart1_ck"), s->drq[OMAP_DMA_UART1_TX], s->drq[OMAP_DMA_UART1_RX], "uart1", - serial_hds[0]); + serial_hd(0)); s->uart[1] = omap_uart_init(0xfffb0800, qdev_get_gpio_in(s->ih[1], OMAP_INT_UART2), omap_findclk(s, "uart2_ck"), omap_findclk(s, "uart2_ck"), s->drq[OMAP_DMA_UART2_TX], s->drq[OMAP_DMA_UART2_RX], "uart2", - serial_hds[0] ? serial_hds[1] : NULL); + serial_hd(0) ? serial_hd(1) : NULL); s->uart[2] = omap_uart_init(0xfffb9800, qdev_get_gpio_in(s->ih[0], OMAP_INT_UART3), omap_findclk(s, "uart3_ck"), omap_findclk(s, "uart3_ck"), s->drq[OMAP_DMA_UART3_TX], s->drq[OMAP_DMA_UART3_RX], "uart3", - serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL); + serial_hd(0) && serial_hd(1) ? serial_hd(2) : NULL); s->dpll[0] = omap_dpll_init(system_memory, 0xfffecf00, omap_findclk(s, "dpll1")); diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c index 647b119ba9..80663533e1 100644 --- a/hw/arm/omap2.c +++ b/hw/arm/omap2.c @@ -2349,7 +2349,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, s->drq[OMAP24XX_DMA_UART1_TX], s->drq[OMAP24XX_DMA_UART1_RX], "uart1", - serial_hds[0]); + serial_hd(0)); s->uart[1] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 20), qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_UART2_IRQ), @@ -2358,7 +2358,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, s->drq[OMAP24XX_DMA_UART2_TX], s->drq[OMAP24XX_DMA_UART2_RX], "uart2", - serial_hds[0] ? serial_hds[1] : NULL); + serial_hd(0) ? serial_hd(1) : NULL); s->uart[2] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 21), qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_UART3_IRQ), @@ -2367,7 +2367,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, s->drq[OMAP24XX_DMA_UART3_TX], s->drq[OMAP24XX_DMA_UART3_RX], "uart3", - serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL); + serial_hd(0) && serial_hd(1) ? serial_hd(2) : NULL); s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7), qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER1), @@ -2519,8 +2519,8 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, omap_sti_init(omap_l4ta(s->l4, 18), sysmem, 0x54000000, qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_STI), omap_findclk(s, "emul_ck"), - serial_hds[0] && serial_hds[1] && serial_hds[2] ? - serial_hds[3] : NULL); + serial_hd(0) && serial_hd(1) && serial_hd(2) ? + serial_hd(3) : NULL); s->eac = omap_eac_init(omap_l4ta(s->l4, 32), qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_EAC_IRQ), diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index 5805a2c858..928a0431d6 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -2106,21 +2106,21 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space, qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); for (i = 0; pxa270_serial[i].io_base; i++) { - if (serial_hds[i]) { + if (serial_hd(i)) { serial_mm_init(address_space, pxa270_serial[i].io_base, 2, qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn), - 14857000 / 16, serial_hds[i], + 14857000 / 16, serial_hd(i), DEVICE_NATIVE_ENDIAN); } else { break; } } - if (serial_hds[i]) + if (serial_hd(i)) s->fir = pxa2xx_fir_init(address_space, 0x40800000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), - serial_hds[i]); + serial_hd(i)); s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); @@ -2231,21 +2231,21 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); for (i = 0; pxa255_serial[i].io_base; i++) { - if (serial_hds[i]) { + if (serial_hd(i)) { serial_mm_init(address_space, pxa255_serial[i].io_base, 2, qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn), - 14745600 / 16, serial_hds[i], + 14745600 / 16, serial_hd(i), DEVICE_NATIVE_ENDIAN); } else { break; } } - if (serial_hds[i]) + if (serial_hd(i)) s->fir = pxa2xx_fir_init(address_space, 0x40800000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), - serial_hds[i]); + serial_hd(i)); s->lcd = pxa2xx_lcdc_init(address_space, 0x44000000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 2139a62e25..cd585d9469 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -195,10 +195,10 @@ static void realview_init(MachineState *machine, sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]); sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]); - pl011_create(0x10009000, pic[12], serial_hds[0]); - pl011_create(0x1000a000, pic[13], serial_hds[1]); - pl011_create(0x1000b000, pic[14], serial_hds[2]); - pl011_create(0x1000c000, pic[15], serial_hds[3]); + pl011_create(0x10009000, pic[12], serial_hd(0)); + pl011_create(0x1000a000, pic[13], serial_hd(1)); + pl011_create(0x1000b000, pic[14], serial_hd(2)); + pl011_create(0x1000c000, pic[15], serial_hd(3)); /* DMA controller is optional, apparently. */ sysbus_create_simple("pl081", 0x10030000, pic[24]); diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index de7c0fc4a6..e886f54976 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1353,7 +1353,7 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) if (board->dc2 & (1 << i)) { pl011_luminary_create(0x4000c000 + i * 0x1000, qdev_get_gpio_in(nvic, uart_irq[i]), - serial_hds[i]); + serial_hd(i)); } } if (board->dc2 & (1 << 4)) { diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c index 1cd6374e07..f59418e7d0 100644 --- a/hw/arm/stm32f205_soc.c +++ b/hw/arm/stm32f205_soc.c @@ -136,7 +136,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) for (i = 0; i < STM_NUM_USARTS; i++) { dev = DEVICE(&(s->usart[i])); qdev_prop_set_chr(dev, "chardev", - i < MAX_SERIAL_PORTS ? serial_hds[i] : NULL); + i < MAX_SERIAL_PORTS ? serial_hd(i) : NULL); object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c index 4cdb3a670b..ec2627374d 100644 --- a/hw/arm/strongarm.c +++ b/hw/arm/strongarm.c @@ -1622,7 +1622,7 @@ StrongARMState *sa1110_init(MemoryRegion *sysmem, for (i = 0; sa_serial[i].io_base; i++) { DeviceState *dev = qdev_create(NULL, TYPE_STRONGARM_UART); - qdev_prop_set_chr(dev, "chardev", serial_hds[i]); + qdev_prop_set_chr(dev, "chardev", serial_hd(i)); qdev_init_nofail(dev); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, sa_serial[i].io_base); diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index 418792cd02..e01e3192ff 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -283,10 +283,10 @@ static void versatile_init(MachineState *machine, int board_id) n--; } - pl011_create(0x101f1000, pic[12], serial_hds[0]); - pl011_create(0x101f2000, pic[13], serial_hds[1]); - pl011_create(0x101f3000, pic[14], serial_hds[2]); - pl011_create(0x10009000, sic[6], serial_hds[3]); + pl011_create(0x101f1000, pic[12], serial_hd(0)); + pl011_create(0x101f2000, pic[13], serial_hd(1)); + pl011_create(0x101f3000, pic[14], serial_hd(2)); + pl011_create(0x10009000, sic[6], serial_hd(3)); sysbus_create_simple("pl080", 0x10130000, pic[17]); sysbus_create_simple("sp804", 0x101e2000, pic[4]); diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 9fad79177a..f1e33c8a36 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -622,10 +622,10 @@ static void vexpress_common_init(MachineState *machine) sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]); sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]); - pl011_create(map[VE_UART0], pic[5], serial_hds[0]); - pl011_create(map[VE_UART1], pic[6], serial_hds[1]); - pl011_create(map[VE_UART2], pic[7], serial_hds[2]); - pl011_create(map[VE_UART3], pic[8], serial_hds[3]); + pl011_create(map[VE_UART0], pic[5], serial_hd(0)); + pl011_create(map[VE_UART1], pic[6], serial_hd(1)); + pl011_create(map[VE_UART2], pic[7], serial_hd(2)); + pl011_create(map[VE_UART3], pic[8], serial_hd(3)); sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]); sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]); diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 94dcb125d3..a18291c5d5 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1371,11 +1371,11 @@ static void machvirt_init(MachineState *machine) fdt_add_pmu_nodes(vms); - create_uart(vms, pic, VIRT_UART, sysmem, serial_hds[0]); + create_uart(vms, pic, VIRT_UART, sysmem, serial_hd(0)); if (vms->secure) { create_secure_ram(vms, secure_sysmem); - create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hds[1]); + create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); } create_rtc(vms, pic); diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 0f76333770..899a26326f 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -236,8 +236,8 @@ static void zynq_init(MachineState *machine) sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]); sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]); - cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hds[0]); - cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hds[1]); + cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0)); + cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1)); sysbus_create_varargs("cadence_ttc", 0xF8001000, pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL); diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 465796e97c..505253e0d2 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -374,7 +374,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) } for (i = 0; i < XLNX_ZYNQMP_NUM_UARTS; i++) { - qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hds[i]); + qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); if (err) { error_propagate(errp, err); diff --git a/hw/char/exynos4210_uart.c b/hw/char/exynos4210_uart.c index 3957e78abf..c2bba03362 100644 --- a/hw/char/exynos4210_uart.c +++ b/hw/char/exynos4210_uart.c @@ -600,7 +600,7 @@ DeviceState *exynos4210_uart_create(hwaddr addr, MAX_SERIAL_PORTS); exit(1); } - chr = serial_hds[channel]; + chr = serial_hd(channel); if (!chr) { snprintf(label, ARRAY_SIZE(label), "%s%d", chr_name, channel); chr = qemu_chr_new(label, "null"); diff --git a/hw/char/serial-isa.c b/hw/char/serial-isa.c index d7c5cc11fe..eb5996159d 100644 --- a/hw/char/serial-isa.c +++ b/hw/char/serial-isa.c @@ -141,8 +141,8 @@ void serial_hds_isa_init(ISABus *bus, int from, int to) assert(to <= MAX_SERIAL_PORTS); for (i = from; i < to; ++i) { - if (serial_hds[i]) { - serial_isa_init(bus, i, serial_hds[i]); + if (serial_hd(i)) { + serial_isa_init(bus, i, serial_hd(i)); } } } diff --git a/hw/char/xen_console.c b/hw/char/xen_console.c index 5e68326c19..bdfaa40ed3 100644 --- a/hw/char/xen_console.c +++ b/hw/char/xen_console.c @@ -201,7 +201,7 @@ static int con_init(struct XenDevice *xendev) /* no Xen override, use qemu output device */ if (output == NULL) { if (con->xendev.dev) { - qemu_chr_fe_init(&con->chr, serial_hds[con->xendev.dev], + qemu_chr_fe_init(&con->chr, serial_hd(con->xendev.dev), &error_abort); } } else { diff --git a/hw/cris/axis_dev88.c b/hw/cris/axis_dev88.c index 9ccc4350a5..409f3d581a 100644 --- a/hw/cris/axis_dev88.c +++ b/hw/cris/axis_dev88.c @@ -337,7 +337,7 @@ void axisdev88_init(MachineState *machine) sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL); for (i = 0; i < 4; i++) { - etraxfs_ser_create(0x30026000 + i * 0x2000, irq[0x14 + i], serial_hds[i]); + etraxfs_ser_create(0x30026000 + i * 0x2000, irq[0x14 + i], serial_hd(i)); } if (kernel_filename) { diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 19033e268d..a1d6b0ebfb 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -108,10 +108,10 @@ static void machine_hppa_init(MachineState *machine) mc146818_rtc_init(isa_bus, 2000, rtc_irq); /* Serial code setup. */ - if (serial_hds[0]) { + if (serial_hd(0)) { uint32_t addr = DINO_UART_HPA + 0x800; serial_mm_init(addr_space, addr, 0, serial_irq, - 115200, serial_hds[0], DEVICE_BIG_ENDIAN); + 115200, serial_hd(0), DEVICE_BIG_ENDIAN); } /* SCSI disk setup. */ diff --git a/hw/isa/isa-superio.c b/hw/isa/isa-superio.c index b95608a003..76286c81a1 100644 --- a/hw/isa/isa-superio.c +++ b/hw/isa/isa-superio.c @@ -81,8 +81,8 @@ static void isa_superio_realize(DeviceState *dev, Error **errp) break; } if (!k->serial.is_enabled || k->serial.is_enabled(sio, i)) { - /* FIXME use a qdev chardev prop instead of serial_hds[] */ - chr = serial_hds[i]; + /* FIXME use a qdev chardev prop instead of serial_hd() */ + chr = serial_hd(i); if (chr == NULL || chr->be) { name = g_strdup_printf("discarding-serial%d", i); chr = qemu_chr_new(name, "null"); diff --git a/hw/lm32/lm32_boards.c b/hw/lm32/lm32_boards.c index 527bcc229c..907e875d02 100644 --- a/hw/lm32/lm32_boards.c +++ b/hw/lm32/lm32_boards.c @@ -125,12 +125,12 @@ static void lm32_evr_init(MachineState *machine) irq[i] = qdev_get_gpio_in(env->pic_state, i); } - lm32_uart_create(uart0_base, irq[uart0_irq], serial_hds[0]); + lm32_uart_create(uart0_base, irq[uart0_irq], serial_hd(0)); sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]); sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]); /* make sure juart isn't the first chardev */ - env->juart_state = lm32_juart_init(serial_hds[1]); + env->juart_state = lm32_juart_init(serial_hd(1)); reset_info->bootstrap_pc = flash_base; @@ -217,13 +217,13 @@ static void lm32_uclinux_init(MachineState *machine) irq[i] = qdev_get_gpio_in(env->pic_state, i); } - lm32_uart_create(uart0_base, irq[uart0_irq], serial_hds[0]); + lm32_uart_create(uart0_base, irq[uart0_irq], serial_hd(0)); sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]); sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]); sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]); /* make sure juart isn't the first chardev */ - env->juart_state = lm32_juart_init(serial_hds[1]); + env->juart_state = lm32_juart_init(serial_hd(1)); reset_info->bootstrap_pc = flash_base; diff --git a/hw/lm32/milkymist.c b/hw/lm32/milkymist.c index 85d64fe58d..f9688e059e 100644 --- a/hw/lm32/milkymist.c +++ b/hw/lm32/milkymist.c @@ -151,7 +151,7 @@ milkymist_init(MachineState *machine) } g_free(bios_filename); - milkymist_uart_create(0x60000000, irq[0], serial_hds[0]); + milkymist_uart_create(0x60000000, irq[0], serial_hd(0)); milkymist_sysctl_create(0x60001000, irq[1], irq[2], irq[3], 80000000, 0x10014d31, 0x0000041f, 0x00000001); milkymist_hpdmc_create(0x60002000); @@ -167,7 +167,7 @@ milkymist_init(MachineState *machine) 0x20000000, 0x1000, 0x20020000, 0x2000); /* make sure juart isn't the first chardev */ - env->juart_state = lm32_juart_init(serial_hds[1]); + env->juart_state = lm32_juart_init(serial_hd(1)); if (kernel_filename) { uint64_t entry; diff --git a/hw/m68k/mcf5206.c b/hw/m68k/mcf5206.c index bd8e993c58..6ad1e4bd2d 100644 --- a/hw/m68k/mcf5206.c +++ b/hw/m68k/mcf5206.c @@ -543,8 +543,8 @@ qemu_irq *mcf5206_init(MemoryRegion *sysmem, uint32_t base, M68kCPU *cpu) pic = qemu_allocate_irqs(m5206_mbar_set_irq, s, 14); s->timer[0] = m5206_timer_init(pic[9]); s->timer[1] = m5206_timer_init(pic[10]); - s->uart[0] = mcf_uart_init(pic[12], serial_hds[0]); - s->uart[1] = mcf_uart_init(pic[13], serial_hds[1]); + s->uart[0] = mcf_uart_init(pic[12], serial_hd(0)); + s->uart[1] = mcf_uart_init(pic[13], serial_hd(1)); s->cpu = cpu; m5206_mbar_reset(s); diff --git a/hw/m68k/mcf5208.c b/hw/m68k/mcf5208.c index fac0d09cbc..7aca58542e 100644 --- a/hw/m68k/mcf5208.c +++ b/hw/m68k/mcf5208.c @@ -247,9 +247,9 @@ static void mcf5208evb_init(MachineState *machine) /* Internal peripherals. */ pic = mcf_intc_init(address_space_mem, 0xfc048000, cpu); - mcf_uart_mm_init(0xfc060000, pic[26], serial_hds[0]); - mcf_uart_mm_init(0xfc064000, pic[27], serial_hds[1]); - mcf_uart_mm_init(0xfc068000, pic[28], serial_hds[2]); + mcf_uart_mm_init(0xfc060000, pic[26], serial_hd(0)); + mcf_uart_mm_init(0xfc064000, pic[27], serial_hd(1)); + mcf_uart_mm_init(0xfc068000, pic[28], serial_hd(2)); mcf5208_sys_init(address_space_mem, pic); diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c index b664dc0f9c..cf6bf3f32a 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -125,7 +125,7 @@ petalogix_ml605_init(MachineState *machine) } serial_mm_init(address_space_mem, UART16550_BASEADDR + 0x1000, 2, - irq[UART16550_IRQ], 115200, serial_hds[0], + irq[UART16550_IRQ], 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); /* 2 timers at irq 2 @ 100 Mhz. */ diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c index 5cb4deb69e..1186002a76 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -103,7 +103,7 @@ petalogix_s3adsp1800_init(MachineState *machine) } xilinx_uartlite_create(UARTLITE_BASEADDR, irq[UARTLITE_IRQ], - serial_hds[0]); + serial_hd(0)); /* 2 timers at irq 2 @ 62 Mhz. */ dev = qdev_create(NULL, "xlnx.xps-timer"); diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 14f0f6673b..5302e5c885 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -507,7 +507,7 @@ static void boston_mach_init(MachineState *machine) s->uart = serial_mm_init(sys_mem, 0x17ffe000, 2, get_cps_irq(s->cps, 3), 10000000, - serial_hds[0], DEVICE_NATIVE_ENDIAN); + serial_hd(0), DEVICE_NATIVE_ENDIAN); lcd = g_new(MemoryRegion, 1); memory_region_init_io(lcd, NULL, &boston_lcd_ops, s, "boston-lcd", 0x8); diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c index 7223085547..90cb306f53 100644 --- a/hw/mips/mips_jazz.c +++ b/hw/mips/mips_jazz.c @@ -303,15 +303,15 @@ static void mips_jazz_init(MachineState *machine, memory_region_add_subregion(address_space, 0x80005000, i8042); /* Serial ports */ - if (serial_hds[0]) { + if (serial_hd(0)) { serial_mm_init(address_space, 0x80006000, 0, qdev_get_gpio_in(rc4030, 8), 8000000/16, - serial_hds[0], DEVICE_NATIVE_ENDIAN); + serial_hd(0), DEVICE_NATIVE_ENDIAN); } - if (serial_hds[1]) { + if (serial_hd(1)) { serial_mm_init(address_space, 0x80007000, 0, qdev_get_gpio_in(rc4030, 9), 8000000/16, - serial_hds[1], DEVICE_NATIVE_ENDIAN); + serial_hd(1), DEVICE_NATIVE_ENDIAN); } /* Parallel port */ diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 49fe7a0a72..af70ecffc0 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -1057,7 +1057,7 @@ void mips_malta_init(MachineState *machine) /* FPGA */ /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */ - malta_fpga_init(system_memory, FPGA_ADDRESS, cbus_irq, serial_hds[2]); + malta_fpga_init(system_memory, FPGA_ADDRESS, cbus_irq, serial_hd(2)); /* Load firmware in flash / BIOS. */ dinfo = drive_get(IF_PFLASH, 0, fl_idx); diff --git a/hw/mips/mips_mipssim.c b/hw/mips/mips_mipssim.c index e0ba5efc84..241faa1d0f 100644 --- a/hw/mips/mips_mipssim.c +++ b/hw/mips/mips_mipssim.c @@ -213,8 +213,8 @@ mips_mipssim_init(MachineState *machine) /* A single 16450 sits at offset 0x3f8. It is attached to MIPS CPU INT2, which is interrupt 4. */ - if (serial_hds[0]) - serial_init(0x3f8, env->irq[4], 115200, serial_hds[0], + if (serial_hd(0)) + serial_init(0x3f8, env->irq[4], 115200, serial_hd(0), get_system_io()); if (nd_table[0].used) diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c index b74a6572b0..a0cefe5719 100644 --- a/hw/misc/macio/macio.c +++ b/hw/misc/macio/macio.c @@ -118,8 +118,8 @@ static void macio_common_realize(PCIDevice *d, Error **errp) qdev_prop_set_uint32(DEVICE(&s->escc), "disabled", 0); qdev_prop_set_uint32(DEVICE(&s->escc), "frequency", ESCC_CLOCK); qdev_prop_set_uint32(DEVICE(&s->escc), "it_shift", 4); - qdev_prop_set_chr(DEVICE(&s->escc), "chrA", serial_hds[0]); - qdev_prop_set_chr(DEVICE(&s->escc), "chrB", serial_hds[1]); + qdev_prop_set_chr(DEVICE(&s->escc), "chrA", serial_hd(0)); + qdev_prop_set_chr(DEVICE(&s->escc), "chrB", serial_hd(1)); qdev_prop_set_uint32(DEVICE(&s->escc), "chnBtype", escc_serial); qdev_prop_set_uint32(DEVICE(&s->escc), "chnAtype", escc_serial); object_property_set_bool(OBJECT(&s->escc), true, "realized", &err); diff --git a/hw/moxie/moxiesim.c b/hw/moxie/moxiesim.c index 0bbf770795..d41247dbdc 100644 --- a/hw/moxie/moxiesim.c +++ b/hw/moxie/moxiesim.c @@ -141,9 +141,9 @@ static void moxiesim_init(MachineState *machine) } /* A single 16450 sits at offset 0x3f8. */ - if (serial_hds[0]) { + if (serial_hd(0)) { serial_mm_init(address_space_mem, 0x3f8, 0, env->irq[4], - 8000000/16, serial_hds[0], DEVICE_LITTLE_ENDIAN); + 8000000/16, serial_hd(0), DEVICE_LITTLE_ENDIAN); } } diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c index 42053b2ca9..36b49a420c 100644 --- a/hw/nios2/10m50_devboard.c +++ b/hw/nios2/10m50_devboard.c @@ -92,7 +92,7 @@ static void nios2_10m50_ghrd_init(MachineState *machine) /* Register: Altera 16550 UART */ serial_mm_init(address_space_mem, 0xf8001600, 2, irq[1], 115200, - serial_hds[0], DEVICE_NATIVE_ENDIAN); + serial_hd(0), DEVICE_NATIVE_ENDIAN); /* Register: Timer sys_clk_timer */ dev = qdev_create(NULL, "ALTR.timer"); diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index c755f11efd..a495a84a41 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -164,7 +164,7 @@ static void openrisc_sim_init(MachineState *machine) } serial_mm_init(get_system_memory(), 0x90000000, 0, serial_irq, - 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); + 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); openrisc_load_kernel(ram_size, kernel_filename); } diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 9a85a41362..2ddab7ed24 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -456,12 +456,12 @@ static int ppce500_load_device_tree(MachineState *machine, * device it finds in the dt as serial output device. And we generate * devices in reverse order to the dt. */ - if (serial_hds[1]) { + if (serial_hd(1)) { dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, soc, mpic, "serial1", 1, false); } - if (serial_hds[0]) { + if (serial_hd(0)) { dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, soc, mpic, "serial0", 0, true); } @@ -875,16 +875,16 @@ void ppce500_init(MachineState *machine, PPCE500Params *params) mpicdev = ppce500_init_mpic(machine, params, ccsr_addr_space, irqs); /* Serial */ - if (serial_hds[0]) { + if (serial_hd(0)) { serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, 0, qdev_get_gpio_in(mpicdev, 42), 399193, - serial_hds[0], DEVICE_BIG_ENDIAN); + serial_hd(0), DEVICE_BIG_ENDIAN); } - if (serial_hds[1]) { + if (serial_hd(1)) { serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, 0, qdev_get_gpio_in(mpicdev, 42), 399193, - serial_hds[1], DEVICE_BIG_ENDIAN); + serial_hd(1), DEVICE_BIG_ENDIAN); } /* General Utility device */ diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 205ebcea93..34f8d57b07 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -1660,14 +1660,14 @@ CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem, dma_irqs[3] = pic[23]; ppc405_dma_init(env, dma_irqs); /* Serial ports */ - if (serial_hds[0] != NULL) { + if (serial_hd(0) != NULL) { serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], - PPC_SERIAL_MM_BAUDBASE, serial_hds[0], + PPC_SERIAL_MM_BAUDBASE, serial_hd(0), DEVICE_BIG_ENDIAN); } - if (serial_hds[1] != NULL) { + if (serial_hd(1) != NULL) { serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], - PPC_SERIAL_MM_BAUDBASE, serial_hds[1], + PPC_SERIAL_MM_BAUDBASE, serial_hd(1), DEVICE_BIG_ENDIAN); } /* IIC controller */ @@ -2023,14 +2023,14 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, /* GPIO */ ppc405_gpio_init(0xef600700); /* Serial ports */ - if (serial_hds[0] != NULL) { + if (serial_hd(0) != NULL) { serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], - PPC_SERIAL_MM_BAUDBASE, serial_hds[0], + PPC_SERIAL_MM_BAUDBASE, serial_hd(0), DEVICE_BIG_ENDIAN); } - if (serial_hds[1] != NULL) { + if (serial_hd(1) != NULL) { serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], - PPC_SERIAL_MM_BAUDBASE, serial_hds[1], + PPC_SERIAL_MM_BAUDBASE, serial_hd(1), DEVICE_BIG_ENDIAN); } /* OCM */ diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index 8641986a71..44e6a0c21b 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -238,14 +238,14 @@ static void bamboo_init(MachineState *machine) get_system_io(), 0, PPC440EP_PCI_IOLEN); memory_region_add_subregion(get_system_memory(), PPC440EP_PCI_IO, isa); - if (serial_hds[0] != NULL) { + if (serial_hd(0) != NULL) { serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], - PPC_SERIAL_MM_BAUDBASE, serial_hds[0], + PPC_SERIAL_MM_BAUDBASE, serial_hd(0), DEVICE_BIG_ENDIAN); } - if (serial_hds[1] != NULL) { + if (serial_hd(1) != NULL) { serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], - PPC_SERIAL_MM_BAUDBASE, serial_hds[1], + PPC_SERIAL_MM_BAUDBASE, serial_hd(1), DEVICE_BIG_ENDIAN); } diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index dfff262f96..a48e6e6fce 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -522,14 +522,14 @@ static void sam460ex_init(MachineState *machine) /* SoC has 4 UARTs * but board has only one wired and two are present in fdt */ - if (serial_hds[0] != NULL) { + if (serial_hd(0) != NULL) { serial_mm_init(address_space_mem, 0x4ef600300, 0, uic[1][1], - PPC_SERIAL_MM_BAUDBASE, serial_hds[0], + PPC_SERIAL_MM_BAUDBASE, serial_hd(0), DEVICE_BIG_ENDIAN); } - if (serial_hds[1] != NULL) { + if (serial_hd(1) != NULL) { serial_mm_init(address_space_mem, 0x4ef600400, 0, uic[0][1], - PPC_SERIAL_MM_BAUDBASE, serial_hds[1], + PPC_SERIAL_MM_BAUDBASE, serial_hd(1), DEVICE_BIG_ENDIAN); } diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index a81570e7c8..b0ecfaca9e 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -2590,8 +2590,8 @@ static void spapr_machine_init(MachineState *machine) spapr->vio_bus = spapr_vio_bus_init(); for (i = 0; i < MAX_SERIAL_PORTS; i++) { - if (serial_hds[i]) { - spapr_vty_create(spapr->vio_bus, serial_hds[i]); + if (serial_hd(i)) { + spapr_vty_create(spapr->vio_bus, serial_hd(i)); } } diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c index 77a1778e07..a80cbdd7ee 100644 --- a/hw/ppc/virtex_ml507.c +++ b/hw/ppc/virtex_ml507.c @@ -251,7 +251,7 @@ static void virtex_init(MachineState *machine) } serial_mm_init(address_space_mem, UART16550_BASEADDR, 2, irq[UART16550_IRQ], - 115200, serial_hds[0], DEVICE_LITTLE_ENDIAN); + 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); /* 2 timers at irq 2 @ 62 Mhz. */ dev = qdev_create(NULL, "xlnx.xps-timer"); diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 19eca36ff4..487244890e 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -162,13 +162,13 @@ static void riscv_sifive_e_init(MachineState *machine) sifive_mmio_emulate(sys_mem, "riscv.sifive.e.gpio0", memmap[SIFIVE_E_GPIO0].base, memmap[SIFIVE_E_GPIO0].size); sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base, - serial_hds[0], SIFIVE_PLIC(s->plic)->irqs[SIFIVE_E_UART0_IRQ]); + serial_hd(0), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_E_UART0_IRQ]); sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi0", memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size); sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm0", memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size); /* sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base, - serial_hds[1], SIFIVE_PLIC(s->plic)->irqs[SIFIVE_E_UART1_IRQ]); */ + serial_hd(1), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_E_UART1_IRQ]); */ sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi1", memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size); sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm1", diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 1c2deefa6c..66616bacd7 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -296,9 +296,9 @@ static void riscv_sifive_u_init(MachineState *machine) SIFIVE_U_PLIC_CONTEXT_STRIDE, memmap[SIFIVE_U_PLIC].size); sifive_uart_create(sys_memory, memmap[SIFIVE_U_UART0].base, - serial_hds[0], SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART0_IRQ]); + serial_hd(0), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART0_IRQ]); /* sifive_uart_create(sys_memory, memmap[SIFIVE_U_UART1].base, - serial_hds[1], SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART1_IRQ]); */ + serial_hd(1), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART1_IRQ]); */ sifive_clint_create(memmap[SIFIVE_U_CLINT].base, memmap[SIFIVE_U_CLINT].size, smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 2d1f114d40..62857e4fa0 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -233,7 +233,7 @@ static void spike_v1_10_0_board_init(MachineState *machine) s->fdt, s->fdt_size); /* initialize HTIF using symbols found in load_kernel */ - htif_mm_init(system_memory, boot_rom, &s->soc.harts[0].env, serial_hds[0]); + htif_mm_init(system_memory, boot_rom, &s->soc.harts[0].env, serial_hd(0)); /* Core Local Interruptor (timer and IPI) */ sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, @@ -330,7 +330,7 @@ static void spike_v1_09_1_board_init(MachineState *machine) config_string, config_string_len); /* initialize HTIF using symbols found in load_kernel */ - htif_mm_init(system_memory, boot_rom, &s->soc.harts[0].env, serial_hds[0]); + htif_mm_init(system_memory, boot_rom, &s->soc.harts[0].env, serial_hd(0)); /* Core Local Interruptor (timer and IPI) */ sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index e2c214e86a..4f69eb2cff 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -382,7 +382,7 @@ static void riscv_virt_board_init(MachineState *machine) serial_mm_init(system_memory, memmap[VIRT_UART0].base, 0, SIFIVE_PLIC(s->plic)->irqs[UART0_IRQ], 399193, - serial_hds[0], DEVICE_LITTLE_ENDIAN); + serial_hd(0), DEVICE_LITTLE_ENDIAN); } static int riscv_virt_board_sysbus_device_init(SysBusDevice *sysbusdev) diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c index 458ed83297..6b01d6eed8 100644 --- a/hw/sh4/r2d.c +++ b/hw/sh4/r2d.c @@ -271,7 +271,7 @@ static void r2d_init(MachineState *machine) busdev = SYS_BUS_DEVICE(dev); qdev_prop_set_uint32(dev, "vram-size", SM501_VRAM_SIZE); qdev_prop_set_uint32(dev, "base", 0x10000000); - qdev_prop_set_ptr(dev, "chr-state", serial_hds[2]); + qdev_prop_set_ptr(dev, "chr-state", serial_hd(2)); qdev_init_nofail(dev); sysbus_mmio_map(busdev, 0, 0x10000000); sysbus_mmio_map(busdev, 1, 0x13e00000); diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index 166e4bd947..5a7d47d31e 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -773,7 +773,7 @@ SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem) cpu->env.intc_handle = &s->intc; sh_serial_init(sysmem, 0x1fe00000, - 0, s->periph_freq, serial_hds[0], + 0, s->periph_freq, serial_hd(0), s->intc.irqs[SCI1_ERI], s->intc.irqs[SCI1_RXI], s->intc.irqs[SCI1_TXI], @@ -781,7 +781,7 @@ SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem) NULL); sh_serial_init(sysmem, 0x1fe80000, SH_SERIAL_FEAT_SCIF, - s->periph_freq, serial_hds[1], + s->periph_freq, serial_hd(1), s->intc.irqs[SCIF_ERI], s->intc.irqs[SCIF_RXI], s->intc.irqs[SCIF_TXI], diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index bba3aa3dee..98fa6adae0 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -206,8 +206,8 @@ static void leon3_generic_hw_init(MachineState *machine) grlib_gptimer_create(0x80000300, 2, CPU_CLK, cpu_irqs, 6); /* Allocate uart */ - if (serial_hds[0]) { - grlib_apbuart_create(0x80000100, serial_hds[0], cpu_irqs[3]); + if (serial_hd(0)) { + grlib_apbuart_create(0x80000100, serial_hd(0), cpu_irqs[3]); } } diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 6471aca25d..0ee779fafe 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -943,8 +943,8 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, qdev_prop_set_uint32(dev, "disabled", 0); qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); qdev_prop_set_uint32(dev, "it_shift", 1); - qdev_prop_set_chr(dev, "chrB", serial_hds[1]); - qdev_prop_set_chr(dev, "chrA", serial_hds[0]); + qdev_prop_set_chr(dev, "chrB", serial_hd(1)); + qdev_prop_set_chr(dev, "chrA", serial_hd(0)); qdev_prop_set_uint32(dev, "chnBtype", escc_serial); qdev_prop_set_uint32(dev, "chnAtype", escc_serial); qdev_init_nofail(dev); diff --git a/hw/sparc64/niagara.c b/hw/sparc64/niagara.c index 1874477ef6..22c4655fde 100644 --- a/hw/sparc64/niagara.c +++ b/hw/sparc64/niagara.c @@ -156,9 +156,9 @@ static void niagara_init(MachineState *machine) exit(1); } } - if (serial_hds[0]) { + if (serial_hd(0)) { serial_mm_init(sysmem, NIAGARA_UART_BASE, 0, NULL, 115200, - serial_hds[0], DEVICE_BIG_ENDIAN); + serial_hd(0), DEVICE_BIG_ENDIAN); } empty_slot_init(NIAGARA_IOBBASE, NIAGARA_IOBSIZE); sun4v_rtc_init(NIAGARA_RTC_BASE); diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index 2044a52ded..9b441f704b 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -295,7 +295,7 @@ static void ebus_realize(PCIDevice *pci_dev, Error **errp) i = 0; if (s->console_serial_base) { serial_mm_init(pci_address_space(pci_dev), s->console_serial_base, - 0, NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN); + 0, NULL, 115200, serial_hd(i), DEVICE_BIG_ENDIAN); i++; } serial_hds_isa_init(s->isa_bus, i, MAX_SERIAL_PORTS); diff --git a/hw/xtensa/sim.c b/hw/xtensa/sim.c index 5c0ba231d1..b6ccb3cd4a 100644 --- a/hw/xtensa/sim.c +++ b/hw/xtensa/sim.c @@ -90,8 +90,8 @@ static void xtensa_sim_init(MachineState *machine) get_system_memory()); } - if (serial_hds[0]) { - xtensa_sim_open_console(serial_hds[0]); + if (serial_hd(0)) { + xtensa_sim_open_console(serial_hd(0)); } if (kernel_filename) { uint64_t elf_entry; diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c index 9db99e1f7e..63734c70ec 100644 --- a/hw/xtensa/xtfpga.c +++ b/hw/xtensa/xtfpga.c @@ -279,7 +279,7 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) } serial_mm_init(system_io, 0x0d050020, 2, xtensa_get_extint(env, 0), - 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); + 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); dinfo = drive_get(IF_PFLASH, 0, 0); if (dinfo) { From patchwork Fri Apr 20 14:52:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 133886 Delivered-To: patches@linaro.org Received: by 10.46.66.142 with SMTP id h14csp374955ljf; Fri, 20 Apr 2018 07:52:56 -0700 (PDT) X-Google-Smtp-Source: AIpwx4+xEwe0IDH2p2WsrLxhRA0xWdSiCsFRgXeIP7O2P730+ATj8ubpT/kqCJyk0weSHGxdHZcb X-Received: by 2002:adf:82c4:: with SMTP id 62-v6mr6993522wrc.273.1524235976851; Fri, 20 Apr 2018 07:52:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524235976; cv=none; d=google.com; s=arc-20160816; b=LwZ3s/gLljva+5R2DYASP29B4Vm520ZchqBOYlhhoVI8r7mzEFn7dPUBdeX8sejCZU npB3eLgAEaDg+M8A0r5RzjkbTSiDEJWr+h917RQHt9RIedBJk2G/KJO5aximUcdfdr8D 143U4LRVxp+obo9u5teYAzYbKpGkqB8k8unkwWm+8pJO8nMdyJHiO2F7kIno9M59cZTF njlvs37bfyjBizatMWC2ztFO7U94CIiHZQcLgY9+4R8IHWgxMH3ulcrn5dWLlB+15p7Z WInCplFhpsz8f4nWl0w+E3Dy+1gEM3+F0S7TJihFx0ljnC8cHL3GinWBbjXUsfXt9v7U jyIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=RedDuvdkTdAYUMJpfWx2Ac2fWnwkcA5fMJXIWzMUS2M=; b=WjbrezGVfq/BfyQnivr8KmW+4xzkI88xRJ7PTnJ0GhUV3ILtYtEO0DEAWliGKvMgs/ aOypF8SapDlBW/MjEKMZVr2EPIZXYceNyefuSZBoQCk+7IFnPDKXJpuOffeiWlUwZQyy 9uryL3MfM/cnB+tfs6R7RlAcNxwKMPGJtH/dMSy/8rcmY33d5O1r4GuWJOJLUjWKifV4 3RZPaY+QcD6aFGxHOWrFndiCNQ9FpQ51WQSZPTXRFlOhCDV51IcGghvvkIUEiSup0wLI EsnpPVkrc6DWX0q2pVgefGSBSq889+coEazMGsQkcb63vUOijVuXo4kkZfERTLEmzXXB wOBQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id l17-v6si4589468wra.111.2018.04.20.07.52.56 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 20 Apr 2018 07:52:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1f9XPE-0006aC-9z; Fri, 20 Apr 2018 15:52:56 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, "Michael S . Tsirkin" , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Subject: [PATCH 08/13] Remove checks on MAX_SERIAL_PORTS that are just bounds checks Date: Fri, 20 Apr 2018 15:52:44 +0100 Message-Id: <20180420145249.32435-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180420145249.32435-1-peter.maydell@linaro.org> References: <20180420145249.32435-1-peter.maydell@linaro.org> Remove checks on MAX_SERIAL_PORTS that were just checking whether they were within bounds for the serial_hds[] array and falling back to NULL if not. This isn't needed with the serial_hd() function, which returns NULL for all indexes beyond what the user set up. Signed-off-by: Peter Maydell --- hw/arm/fsl-imx25.c | 4 +--- hw/arm/fsl-imx31.c | 4 +--- hw/arm/fsl-imx6.c | 4 +--- hw/arm/fsl-imx7.c | 4 +--- hw/arm/mps2-tz.c | 3 +-- hw/arm/mps2.c | 6 ++---- hw/arm/stm32f205_soc.c | 3 +-- 7 files changed, 8 insertions(+), 20 deletions(-) -- 2.17.0 Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index 9731833fa5..37056f9e34 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -117,9 +117,7 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp) { FSL_IMX25_UART5_ADDR, FSL_IMX25_UART5_IRQ } }; - if (i < MAX_SERIAL_PORTS) { - qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); - } + qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); if (err) { diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c index 8509915200..891850cf18 100644 --- a/hw/arm/fsl-imx31.c +++ b/hw/arm/fsl-imx31.c @@ -106,9 +106,7 @@ static void fsl_imx31_realize(DeviceState *dev, Error **errp) { FSL_IMX31_UART2_ADDR, FSL_IMX31_UART2_IRQ }, }; - if (i < MAX_SERIAL_PORTS) { - qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); - } + qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); if (err) { diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index 535ad5888b..4f51bd9eb5 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -188,9 +188,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) { FSL_IMX6_UART5_ADDR, FSL_IMX6_UART5_IRQ }, }; - if (i < MAX_SERIAL_PORTS) { - qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); - } + qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &err); if (err) { diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index 2848d76d3c..26c1d27f7c 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -390,9 +390,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp) }; - if (i < MAX_SERIAL_PORTS) { - qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); - } + qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); object_property_set_bool(OBJECT(&s->uart[i]), true, "realized", &error_abort); diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index 4ae4a5cb2a..8dc8bfd4ab 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -172,7 +172,6 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, { CMSDKAPBUART *uart = opaque; int i = uart - &mms->uart[0]; - Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hd(i) : NULL; int rxirqno = i * 2; int txirqno = i * 2 + 1; int combirqno = i + 10; @@ -182,7 +181,7 @@ static MemoryRegion *make_uart(MPS2TZMachineState *mms, void *opaque, init_sysbus_child(OBJECT(mms), name, uart, sizeof(mms->uart[0]), TYPE_CMSDK_APB_UART); - qdev_prop_set_chr(DEVICE(uart), "chardev", uartchr); + qdev_prop_set_chr(DEVICE(uart), "chardev", serial_hd(i)); qdev_prop_set_uint32(DEVICE(uart), "pclk-frq", SYSCLK_FRQ); object_property_set_bool(OBJECT(uart), true, "realized", &error_fatal); s = SYS_BUS_DEVICE(uart); diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index eb550fad34..c3946da317 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -230,7 +230,6 @@ static void mps2_common_init(MachineState *machine) static const hwaddr uartbase[] = {0x40004000, 0x40005000, 0x40006000, 0x40007000, 0x40009000}; - Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hd(i) : NULL; /* RX irq number; TX irq is always one greater */ static const int uartirq[] = {0, 2, 4, 18, 20}; qemu_irq txovrint = NULL, rxovrint = NULL; @@ -245,7 +244,7 @@ static void mps2_common_init(MachineState *machine) qdev_get_gpio_in(armv7m, uartirq[i]), txovrint, rxovrint, NULL, - uartchr, SYSCLK_FRQ); + serial_hd(i), SYSCLK_FRQ); } break; } @@ -270,7 +269,6 @@ static void mps2_common_init(MachineState *machine) static const hwaddr uartbase[] = {0x40004000, 0x40005000, 0x4002c000, 0x4002d000, 0x4002e000}; - Chardev *uartchr = i < MAX_SERIAL_PORTS ? serial_hd(i) : NULL; Object *txrx_orgate; DeviceState *txrx_orgate_dev; @@ -287,7 +285,7 @@ static void mps2_common_init(MachineState *machine) qdev_get_gpio_in(orgate_dev, i * 2), qdev_get_gpio_in(orgate_dev, i * 2 + 1), NULL, - uartchr, SYSCLK_FRQ); + serial_hd(i), SYSCLK_FRQ); } break; } diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c index f59418e7d0..2b2135d382 100644 --- a/hw/arm/stm32f205_soc.c +++ b/hw/arm/stm32f205_soc.c @@ -135,8 +135,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) /* Attach UART (uses USART registers) and USART controllers */ for (i = 0; i < STM_NUM_USARTS; i++) { dev = DEVICE(&(s->usart[i])); - qdev_prop_set_chr(dev, "chardev", - i < MAX_SERIAL_PORTS ? serial_hd(i) : NULL); + qdev_prop_set_chr(dev, "chardev", serial_hd(i)); object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err); if (err != NULL) { error_propagate(errp, err); From patchwork Fri Apr 20 14:52:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 133887 Delivered-To: patches@linaro.org Received: by 10.46.66.142 with SMTP id h14csp374977ljf; Fri, 20 Apr 2018 07:52:57 -0700 (PDT) X-Google-Smtp-Source: AIpwx4/zXPPbgP/UC5jqSMDsm3neomrA8OZou9tZQMLn9K/g/i69m5BVPVTNmriO87sqIs8UZP9k X-Received: by 2002:adf:af65:: with SMTP id z92-v6mr8579565wrc.250.1524235977721; Fri, 20 Apr 2018 07:52:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524235977; cv=none; d=google.com; s=arc-20160816; b=oZfoZH68d12R/1eTMzx4ky8A9x2BTq4eW7ZgHcPmrzwwv0s0DdP5pg2uULMOJkMvS3 PEk+WqoNDEasOQ6nNSGECNHFRNni68tDx1a6gNz7lAbeH8fKpSPL4KIRc7uGz3qLukGL h1tuvuPQecjVQYaBDId2nOX0uRA4oR1Or7DTIzzPpUSH9u0rN6Ic/FCvn1zbLKbAIJZH TqxAbN4qfMJkpfE3GYSRcF06UlB1imqJR/5ISHO4XPBCYWT6N/Ji7P0UYMgreQwmtEdq uc+X4nfvxqCdtHKkoJXo56BLK/TMnX2CPWP5CfP2+gKWRhDUb3dZghnk9PYdg8jBcRCx u4Uw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=6Ru+VnvMxo5NuiWS0nLkdLdcXqLl8Z1ECiXwKWILwPg=; b=QwAZz52BP/yIdV+oTr4yuZr6KG8BFURHgkA/89esDFgavIOHE8tBkYsdlmfnSquQ/R yQrvg9XdA2cBbSoQRqdxzdgft7afZQrRhXZEY+6dhmpQlM8JvqmUEgM6ytpXm9KzGJ8V 5MxxWhSNuoXGB607Y4V3Zf6qpGm1qYjz7JWjMz+Dih+pqYuDpVW27R7o4Nox37yk3G0r sH0ILqPi1gARrkMuPjZYYcHa+t65ok5GH3JTVwxo1n2enQVG9T8MjjvlzmUqiNITAa/L v9bgkJQT9SRN0njimGMXu67KBUCeWGC2NP9BO0jczsdwjLR8l4827Wfc+lCzp3dpsdvz aTDA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id l12-v6si4906255wrc.160.2018.04.20.07.52.57 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 20 Apr 2018 07:52:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1f9XPF-0006ay-3D; Fri, 20 Apr 2018 15:52:57 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, "Michael S . Tsirkin" , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Subject: [PATCH 09/13] hw/char/exynos4210_uart.c: Remove unneeded handling of NULL chardev Date: Fri, 20 Apr 2018 15:52:45 +0100 Message-Id: <20180420145249.32435-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180420145249.32435-1-peter.maydell@linaro.org> References: <20180420145249.32435-1-peter.maydell@linaro.org> The handling of NULL chardevs in exynos4210_uart_create() is now all unnecessary: we don't need to create 'null' chardevs, and we don't need to enforce a bounds check on serial_hd(). Signed-off-by: Peter Maydell --- hw/char/exynos4210_uart.c | 20 -------------------- 1 file changed, 20 deletions(-) -- 2.17.0 Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth diff --git a/hw/char/exynos4210_uart.c b/hw/char/exynos4210_uart.c index c2bba03362..a5a285655f 100644 --- a/hw/char/exynos4210_uart.c +++ b/hw/char/exynos4210_uart.c @@ -589,28 +589,8 @@ DeviceState *exynos4210_uart_create(hwaddr addr, DeviceState *dev; SysBusDevice *bus; - const char chr_name[] = "serial"; - char label[ARRAY_SIZE(chr_name) + 1]; - dev = qdev_create(NULL, TYPE_EXYNOS4210_UART); - if (!chr) { - if (channel >= MAX_SERIAL_PORTS) { - error_report("Only %d serial ports are supported by QEMU", - MAX_SERIAL_PORTS); - exit(1); - } - chr = serial_hd(channel); - if (!chr) { - snprintf(label, ARRAY_SIZE(label), "%s%d", chr_name, channel); - chr = qemu_chr_new(label, "null"); - if (!(chr)) { - error_report("Can't assign serial port to UART%d", channel); - exit(1); - } - } - } - qdev_prop_set_chr(dev, "chardev", chr); qdev_prop_set_uint32(dev, "channel", channel); qdev_prop_set_uint32(dev, "rx-size", fifo_size); From patchwork Fri Apr 20 14:52:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 133889 Delivered-To: patches@linaro.org Received: by 10.46.66.142 with SMTP id h14csp374989ljf; Fri, 20 Apr 2018 07:52:58 -0700 (PDT) X-Google-Smtp-Source: AIpwx4/dOwYsKNH/kWev17EF5vEyJE3bYNuHm63r+7dGWP918/8hwsz6eWw+vkbVHpWlA8Nj7PHl X-Received: by 2002:adf:b685:: with SMTP id j5-v6mr8551997wre.10.1524235978311; Fri, 20 Apr 2018 07:52:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524235978; cv=none; d=google.com; s=arc-20160816; b=Reb9UTmQ+XokgqYji2XKUIVbJW9o2mOYLYFZBys9UQscUqKXLuOzWUBDAXzUEgAh8E UoZxj11Lehf1KOuUjk1ha7jWzQwnXu1B7VPlpL9UDUChnxsApdmGCOwVUHzfUd7DKqIK mShBXnbogGs0J4LIwDY4EkHWc5D34jvCToSg7z9dtMI++wnYg6O4mKxwf273Fcuwpqrg J7Xgmrsgfmcfphgvb0W3fdrVjH8RT2E58JonSbJc0cru0HHeLD9dFWYeedzIUS6E3msl hY9HV/0bXoHi8J8C246E4W4OVB1AVs5j4JjVDDntWMoRiLGEafkzyPjT0IPojLmM+rjl cPjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=a77bDVwFmi+Y0vaOpuXIqo2ipQf7XO7Z89aiAxfma3U=; b=CjSfxCiMY9HaNOd4U1p8mk98pv9IJ/EnrCy9tJWnlbASEW9ph82mzq+sEN6O3PCAqW XCdFVHPohN+D0fV12h8tswpE/wkpexBF9d4ZFschXFEwCndMX1onxieLcGfjGVyC8h7E HoPertlucFque4C05QZh4NQJb2mMRgA10cVUf7E9r77+01wFuZIqFGS4RdVeLfMk+6BW 70XSLGLwQyrO7P91osj1sqGLrCLL2THIfTYUEoHuOQhMSmi9mmjzG2pXpY7x7Vr8gOPD dqpC+z0UeJyNpcPHA8t4mGU4tOoHR1gjm1gmLC1iRQRxRPoywDOvDcGFD6ZCv7cROVSj Eksw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id w9-v6si4914063wrg.13.2018.04.20.07.52.58 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 20 Apr 2018 07:52:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1f9XPF-0006bT-QH; Fri, 20 Apr 2018 15:52:57 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, "Michael S . Tsirkin" , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Subject: [PATCH 10/13] serial-isa: Use MAX_ISA_SERIAL_PORTS instead of MAX_SERIAL_PORTS Date: Fri, 20 Apr 2018 15:52:46 +0100 Message-Id: <20180420145249.32435-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180420145249.32435-1-peter.maydell@linaro.org> References: <20180420145249.32435-1-peter.maydell@linaro.org> The ISA serial port handling in serial-isa.c imposes a limit of 4 serial ports. This is because we only know of 4 IO port and IRQ settings for them, and is unrelated to the generic MAX_SERIAL_PORTS limit, though they happen to both be set at 4 currently. Use a new MAX_ISA_SERIAL_PORTS wherever that is the correct limit to be checking against. Signed-off-by: Peter Maydell --- include/hw/char/serial.h | 3 +++ hw/char/serial-isa.c | 10 +++++----- hw/i386/pc.c | 2 +- hw/mips/mips_r4k.c | 2 +- hw/ppc/pnv.c | 2 +- hw/sparc64/sun4u.c | 2 +- 6 files changed, 12 insertions(+), 9 deletions(-) -- 2.17.0 Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth diff --git a/include/hw/char/serial.h b/include/hw/char/serial.h index c4daf11a14..0acfbbc382 100644 --- a/include/hw/char/serial.h +++ b/include/hw/char/serial.h @@ -95,6 +95,9 @@ SerialState *serial_mm_init(MemoryRegion *address_space, Chardev *chr, enum device_endian end); /* serial-isa.c */ + +#define MAX_ISA_SERIAL_PORTS 4 + #define TYPE_ISA_SERIAL "isa-serial" void serial_hds_isa_init(ISABus *bus, int from, int to); diff --git a/hw/char/serial-isa.c b/hw/char/serial-isa.c index eb5996159d..116b7b2e69 100644 --- a/hw/char/serial-isa.c +++ b/hw/char/serial-isa.c @@ -39,10 +39,10 @@ typedef struct ISASerialState { SerialState state; } ISASerialState; -static const int isa_serial_io[MAX_SERIAL_PORTS] = { +static const int isa_serial_io[MAX_ISA_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; -static const int isa_serial_irq[MAX_SERIAL_PORTS] = { +static const int isa_serial_irq[MAX_ISA_SERIAL_PORTS] = { 4, 3, 4, 3 }; @@ -56,9 +56,9 @@ static void serial_isa_realizefn(DeviceState *dev, Error **errp) if (isa->index == -1) { isa->index = index; } - if (isa->index >= MAX_SERIAL_PORTS) { + if (isa->index >= MAX_ISA_SERIAL_PORTS) { error_setg(errp, "Max. supported number of ISA serial ports is %d.", - MAX_SERIAL_PORTS); + MAX_ISA_SERIAL_PORTS); return; } if (isa->iobase == -1) { @@ -138,7 +138,7 @@ void serial_hds_isa_init(ISABus *bus, int from, int to) int i; assert(from >= 0); - assert(to <= MAX_SERIAL_PORTS); + assert(to <= MAX_ISA_SERIAL_PORTS); for (i = from; i < to; ++i) { if (serial_hd(i)) { diff --git a/hw/i386/pc.c b/hw/i386/pc.c index d36bac8c89..b297a5d63b 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1524,7 +1524,7 @@ static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, bool no_vmport) qemu_irq *a20_line; ISADevice *i8042, *port92, *vmmouse; - serial_hds_isa_init(isa_bus, 0, MAX_SERIAL_PORTS); + serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); for (i = 0; i < MAX_FD; i++) { diff --git a/hw/mips/mips_r4k.c b/hw/mips/mips_r4k.c index aeadc4a340..e04b49d3c5 100644 --- a/hw/mips/mips_r4k.c +++ b/hw/mips/mips_r4k.c @@ -274,7 +274,7 @@ void mips_r4k_init(MachineState *machine) pit = i8254_pit_init(isa_bus, 0x40, 0, NULL); - serial_hds_isa_init(isa_bus, 0, MAX_SERIAL_PORTS); + serial_hds_isa_init(isa_bus, 0, MAX_ISA_SERIAL_PORTS); isa_vga_init(isa_bus); diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 98ee3c607a..549cfccdcb 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -648,7 +648,7 @@ static void pnv_init(MachineState *machine) pnv->isa_bus = pnv_isa_create(pnv->chips[0]); /* Create serial port */ - serial_hds_isa_init(pnv->isa_bus, 0, MAX_SERIAL_PORTS); + serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); /* Create an RTC ISA device too */ mc146818_rtc_init(pnv->isa_bus, 2000, NULL); diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index 9b441f704b..1bede85370 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -298,7 +298,7 @@ static void ebus_realize(PCIDevice *pci_dev, Error **errp) 0, NULL, 115200, serial_hd(i), DEVICE_BIG_ENDIAN); i++; } - serial_hds_isa_init(s->isa_bus, i, MAX_SERIAL_PORTS); + serial_hds_isa_init(s->isa_bus, i, MAX_ISA_SERIAL_PORTS); /* Parallel ports */ parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS); From patchwork Fri Apr 20 14:52:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 133890 Delivered-To: patches@linaro.org Received: by 10.46.66.142 with SMTP id h14csp374996ljf; Fri, 20 Apr 2018 07:52:59 -0700 (PDT) X-Google-Smtp-Source: AIpwx48asi9hVCnjyFDN6VwEGbhCpaZ1WIdpWQnxyCnAbrVV1uLuyjeTyYZhk6m1o2qsnG28qPaf X-Received: by 10.28.23.148 with SMTP id 142mr486444wmx.0.1524235978990; Fri, 20 Apr 2018 07:52:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524235978; cv=none; d=google.com; s=arc-20160816; b=hBMWryK7ZDL0bSj2LZM30gB77Fwzzkx/UURsRgNDmn8Id8CvFcswE+BsJusziXLJr4 tY6kVeBuQIcp3kXgV3KPQOK/aE7b5N0ddBzN/OgJ6hJNrS+VZMoVTNJaStetJG2rBKfY wh9MgRaqPWX0FWgcpL+kWExLPCzr6F1kmv8Fws6O1WphzpIvEFfQqkhufp/NcbKiWqpP vDcV7HJK3iLbL7/wKIGOOODllrn19HnzNc3gvO+8daca+VXSpOMAQArtocR3y0UOsNCh 6XBfKSRjOp/T/3XX+RGKGFfCJ8e7hRkNRLma96/ujUYaFQJqIfqjM7iLIAhFPoiun6ku MXlQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=Dbv/xJO/ljNzO0FpN65M16Ku/BhmvGLi1QVmuN47ZuI=; b=M2ecpvg7FimJsPtlfMIudJ3dHmVnYOnzKy1mhWK1OvxbQphalxXmUl+AZ+v254HJAy FRzyZlVfdCwSveOo/2WAOLmR6xwwbbjt5wYPgj7Mf/AMmfzdMnAasg9qgCa+4U8n4QmC omz/r5qc9N7b6zFx+a5uZlk4E4WwUVvDl/6Jjipyq35dQkzwJbTwXUWTbrnaUJf2X8iT aXzi5XIAPpouLd3pjOSVarGPFbXrNxi1q0hlBLENEKIeo+78erI5A8WemxFETTsaLa8D M3+kUhO85Iqfz64M/m1BJbiLtXV+njtgsPK+naBeiOQyUpt6uwdS/dNA5KE01lkmAp6K OYYQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 140si1256659wmi.146.2018.04.20.07.52.58 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 20 Apr 2018 07:52:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1f9XPG-0006by-HM; Fri, 20 Apr 2018 15:52:58 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, "Michael S . Tsirkin" , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Subject: [PATCH 11/13] superio: Don't use MAX_SERIAL_PORTS for serial port limit Date: Fri, 20 Apr 2018 15:52:47 +0100 Message-Id: <20180420145249.32435-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180420145249.32435-1-peter.maydell@linaro.org> References: <20180420145249.32435-1-peter.maydell@linaro.org> The superio device has a limit on the number of serial ports it supports which is really only there because it has a fixed-size array serial[]. This limit isn't related particularly to the global MAX_SERIAL_PORTS limit, so use a different #define for it. (In practice the users of superio only ever want 2 serial ports.) Signed-off-by: Peter Maydell --- include/hw/isa/superio.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.17.0 Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé diff --git a/include/hw/isa/superio.h b/include/hw/isa/superio.h index f9ba29aa30..345f006081 100644 --- a/include/hw/isa/superio.h +++ b/include/hw/isa/superio.h @@ -22,13 +22,15 @@ #define ISA_SUPERIO_CLASS(klass) \ OBJECT_CLASS_CHECK(ISASuperIOClass, (klass), TYPE_ISA_SUPERIO) +#define SUPERIO_MAX_SERIAL_PORTS 4 + typedef struct ISASuperIODevice { /*< private >*/ ISADevice parent_obj; /*< public >*/ ISADevice *parallel[MAX_PARALLEL_PORTS]; - ISADevice *serial[MAX_SERIAL_PORTS]; + ISADevice *serial[SUPERIO_MAX_SERIAL_PORTS]; ISADevice *floppy; ISADevice *kbc; ISADevice *ide; From patchwork Fri Apr 20 14:52:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 133891 Delivered-To: patches@linaro.org Received: by 10.46.66.142 with SMTP id h14csp375007ljf; Fri, 20 Apr 2018 07:52:59 -0700 (PDT) X-Google-Smtp-Source: AIpwx49CZFGbkKDlH2RbvlwTnOMXi4tRANA9+IFwwjRd8IEIV6//G95BIqjuyE1R6Zrl8eUdshnL X-Received: by 10.28.152.143 with SMTP id a137mr2379944wme.137.1524235979873; Fri, 20 Apr 2018 07:52:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524235979; cv=none; d=google.com; s=arc-20160816; b=larkzlTtLSEyB9XXAgShNno6seZLUMR53R9Wj+/Wq6IPW/l1/9+R1FUeW924BljGJ/ fYdoTIpLRF0LCmv1TEt18Skp/KDBPjrcflGLhTIh0BeQOgBocQEnHBG3zVhRppvM61gp MA2UYHZWVinGfQ8liFFuDLzQEYtlPpdH1cryZl+1kYmRlV0Jfkf9a2w6LAHLi0yUau3i 9ySSyzDhA7Ctg2HEEZed8lgzNTnD3cNRWEt0k6GThRMVzV4nMmNrCH1wk8IT2RzCWL+f d2hVDyvLi9k3THf1uEQKa908d+bi7HXJA0eiBJVXShZApF4i9KXbsLxwrI6Xfh+m2KvI lDJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=mBTNKIC7PJ44KrIY+IWkfO1nYRrlah6PZX0UszYUh+8=; b=yqMSToxyKrSuiyovHnh0pUeEAOOzAO2i6W1mvpa2f37nLDoD9KMZAnVKbowhHhiZiY sCaGaqCBU493ksTSHZCLpfYthqOdpF19gGwztuw8EN3MSS4TVYE3jBoSV9nnxPkOVvw7 xvQlDYSdC2LkpdCgPt0aPy/j7eFG6UyRIzOciAJX3fAS/5qz7sE6WM8KJcE8yZwHzvce eqsc2GhTss8w5KRkErTyGQxj08t3MZFa8JHtnPlAzTmbUx1bcHtXdxbmMYexy/YXdLYb CSwPFMi3l0tDRd6wgu7A2/EiLRI6BKObHlwEl6Xe8i7wjXEv+IrsGWSBxU2fcBPWUMW8 abUA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id u10-v6si4792358wrd.157.2018.04.20.07.52.59 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 20 Apr 2018 07:52:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1f9XPH-0006cF-8Y; Fri, 20 Apr 2018 15:52:59 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, "Michael S . Tsirkin" , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Subject: [PATCH 12/13] vl.c: Remove compile time limit on number of serial ports Date: Fri, 20 Apr 2018 15:52:48 +0100 Message-Id: <20180420145249.32435-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180420145249.32435-1-peter.maydell@linaro.org> References: <20180420145249.32435-1-peter.maydell@linaro.org> Instead of having a fixed sized global serial_hds[] array, use a local dynamically reallocated one, so we don't have a compile time limit on how many serial ports a system has. Signed-off-by: Peter Maydell --- include/sysemu/sysemu.h | 2 -- vl.c | 15 +++++++-------- 2 files changed, 7 insertions(+), 10 deletions(-) -- 2.17.0 Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h index bd5b55c514..989cbc2b7b 100644 --- a/include/sysemu/sysemu.h +++ b/include/sysemu/sysemu.h @@ -161,8 +161,6 @@ void hmp_pcie_aer_inject_error(Monitor *mon, const QDict *qdict); #define MAX_SERIAL_PORTS 4 -extern Chardev *serial_hds[MAX_SERIAL_PORTS]; - /* Return the Chardev for serial port i, or NULL if none */ Chardev *serial_hd(int i); diff --git a/vl.c b/vl.c index 6daf026da6..a8a98c5a37 100644 --- a/vl.c +++ b/vl.c @@ -154,7 +154,8 @@ QEMUClockType rtc_clock; int vga_interface_type = VGA_NONE; static DisplayOptions dpy; int no_frame; -Chardev *serial_hds[MAX_SERIAL_PORTS]; +static int num_serial_hds = 0; +static Chardev **serial_hds = NULL; Chardev *parallel_hds[MAX_PARALLEL_PORTS]; Chardev *virtcon_hds[MAX_VIRTIO_CONSOLES]; Chardev *sclp_hds[MAX_SCLP_CONSOLES]; @@ -2496,30 +2497,28 @@ static int foreach_device_config(int type, int (*func)(const char *cmdline)) static int serial_parse(const char *devname) { - static int index = 0; + int index = num_serial_hds; char label[32]; if (strcmp(devname, "none") == 0) return 0; - if (index == MAX_SERIAL_PORTS) { - error_report("too many serial ports"); - exit(1); - } snprintf(label, sizeof(label), "serial%d", index); + serial_hds = g_renew(Chardev *, serial_hds, index + 1); + serial_hds[index] = qemu_chr_new(label, devname); if (!serial_hds[index]) { error_report("could not connect serial device" " to character backend '%s'", devname); return -1; } - index++; + num_serial_hds++; return 0; } Chardev *serial_hd(int i) { assert(i >= 0); - if (i < ARRAY_SIZE(serial_hds)) { + if (i < num_serial_hds) { return serial_hds[i]; } return NULL; From patchwork Fri Apr 20 14:52:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 133892 Delivered-To: patches@linaro.org Received: by 10.46.66.142 with SMTP id h14csp375022ljf; Fri, 20 Apr 2018 07:53:00 -0700 (PDT) X-Google-Smtp-Source: AB8JxZoJetsHmGdAaueiK6r9XGPbdY0IZqd0CqE8+GWEVLnmlIyk/nqhqLCyIrNxcHqhisMcl51K X-Received: by 10.28.51.79 with SMTP id z76mr2395554wmz.113.1524235980780; Fri, 20 Apr 2018 07:53:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524235980; cv=none; d=google.com; s=arc-20160816; b=X3EyRqgoLm5Dzm58FTc0GoepsgELOKDxrym03unXy964Ts4Pi/9eFGhD3AuiC3c1e7 BespD87rOFF1fJhFIzHeaJfhjElmqVCMfVKdzUrbgmqz7f/CFbCGZ52iWzJIfsIBXleg Oe/qdBQPZpqsQ00e0hpiEyoCxNi2FeGFPZDniUPInldiLAuCmWtv7qyI8XSKj7misVwo hwyPrWfeZSm5Ibo17lPhWM9O/0v1ol1GoYzQJT9hwhz9BDpV3HQ7OqRwGUDB1voUyfaz EEUj9tv9j4HKluDsaL+ueG9mpmfBfEpGkKD0Cm8YzHIHczS/XfeABW2sXxkJf7gc0mJx 9CXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=b4nQLPQc/v8IpBIoCmw00sSl5NHgt6zcgWe6DxcLNFQ=; b=qunDdhJ0s8uU09GiDYW+pE0EEaWdXnsiIZXILBsfw5Fm94jmZS1gZalco/yRITTjV/ kgWNd5LiAh23MBthdMwBmv/MNaj7iL0ZTJ5/n4TohJfUUuPJBgNudWJxYdJE9YfychW1 LPI9GYO19U0RDlBtkVxmu4ljh08FbA0dJj3Yhnc8Ca7jkPDdpWiHPLxC/9USD8uQJIRV wB/XIAvYGKhWpt3sCUTZ6DcY8Hhs3SqiS5cadTcb3JNyepF3YS9AaVDM+bUQQMcFLN7r xWekLFsK3DVBSE/PTgIPA2suUlV3r4v9sFspiOX1k0qnlIApvK8TgmR1WKm+5cGomFJO bnrg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id p21si1213013wmc.66.2018.04.20.07.53.00 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 20 Apr 2018 07:53:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1f9XPI-0006dC-97; Fri, 20 Apr 2018 15:53:00 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, "Michael S . Tsirkin" , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= Subject: [PATCH 13/13] vl.c: new function max_serial_hds() Date: Fri, 20 Apr 2018 15:52:49 +0100 Message-Id: <20180420145249.32435-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180420145249.32435-1-peter.maydell@linaro.org> References: <20180420145249.32435-1-peter.maydell@linaro.org> Create a new function max_serial_hds() which returns the number of serial ports defined by the user. This is needed only by spapr. This allows us to remove the MAX_SERIAL_PORTS define. Signed-off-by: Peter Maydell --- include/sysemu/sysemu.h | 6 ++++-- hw/ppc/spapr.c | 2 +- vl.c | 5 +++++ 3 files changed, 10 insertions(+), 3 deletions(-) -- 2.17.0 Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h index 989cbc2b7b..612659a718 100644 --- a/include/sysemu/sysemu.h +++ b/include/sysemu/sysemu.h @@ -159,10 +159,12 @@ void hmp_pcie_aer_inject_error(Monitor *mon, const QDict *qdict); /* serial ports */ -#define MAX_SERIAL_PORTS 4 - /* Return the Chardev for serial port i, or NULL if none */ Chardev *serial_hd(int i); +/* return the number of serial ports defined by the user. serial_hd(i) + * will always return NULL for any i which is greater than or equal to this. + */ +int max_serial_hds(void); /* parallel ports */ diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index b0ecfaca9e..8d2d36a606 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -2589,7 +2589,7 @@ static void spapr_machine_init(MachineState *machine) /* Set up VIO bus */ spapr->vio_bus = spapr_vio_bus_init(); - for (i = 0; i < MAX_SERIAL_PORTS; i++) { + for (i = 0; i < max_serial_hds(); i++) { if (serial_hd(i)) { spapr_vty_create(spapr->vio_bus, serial_hd(i)); } diff --git a/vl.c b/vl.c index a8a98c5a37..b587187052 100644 --- a/vl.c +++ b/vl.c @@ -2524,6 +2524,11 @@ Chardev *serial_hd(int i) return NULL; } +int max_serial_hds(void) +{ + return num_serial_hds; +} + static int parallel_parse(const char *devname) { static int index = 0;