From patchwork Fri Apr 20 15:50:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 133899 Delivered-To: patch@linaro.org Received: by 10.46.66.142 with SMTP id h14csp439132ljf; Fri, 20 Apr 2018 08:53:44 -0700 (PDT) X-Google-Smtp-Source: AIpwx49P8G5Yo791CZ+6QcFbKM6Utv1cpwuGifMiiPmUOduZyFwRu20148qFkL7+ryI0V6uUJ0ez X-Received: by 2002:a25:2185:: with SMTP id h127-v6mr6557307ybh.206.1524239624132; Fri, 20 Apr 2018 08:53:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524239624; cv=none; d=google.com; s=arc-20160816; b=jrnqaxr31LrjCqEWf7iD7YdPzm8z2TulaJnrp8IS8I76FQJJ7L7ENxTjLejo4HP713 F/ZpW9J15z5hXNXA6pit86HihJRkuupjVSOm2uUuDiDY1Sr1m3DTWF0UXeWiredhkpuj JaF0xUqxaO4oxcCNVjU3D842dfx0vmAzYkkDvGyuWD/IsrMV21npVfT4s2yaTsWGEOiY SmddcizukG5VNuQ6AdFgowv42ZrOTn4KlSjVI64qxXxrL97DHnGDMo7KumdIqNLyuGBf nB9+BmkKuAp229COkpRnnU6bCq9wAD6qPihrYeeDyDaxuJFpsvG27s0LPSE49I3BLruQ SXkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=NKRTWPx9XJvd8tXI8smZeEGIKMjvBcvS6l3yK5hH9tM=; b=L7CY4oMDWZ6ECoP7ZQUe6c/emrnknRVHB4G8hcjDAcaVxxXL8OtMh2qsD8sS5y/ij3 ifHJijzgL8JDO7fGMc1znT17BJfxbCkj8NW5ObZq8ZXNFDAb6ZEJyVYdLSCgVYLPn3OJ T6ggNclHUtvpxM3id+nttND7NLcDUvUK2qFlm03UhOzp8uGM5IDSb251ev5hRsFADQAZ Z47td4YvqqAjvzhVGFlAei3ta9+3VSFo3kJINx1HGS26JtL0dPTTWp+uybNZrsQnz9f7 /sKbol1tZy6+a/tFepk2ePvLQWxl+FUap23fCyWVPUPuzrpoVrX0ATd4BKHm8lEvjPHc FBHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Jvh4DbHp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 129si2669260vkv.336.2018.04.20.08.53.43 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 20 Apr 2018 08:53:44 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Jvh4DbHp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39043 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f9YM3-00076n-HS for patch@linaro.org; Fri, 20 Apr 2018 11:53:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50793) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f9YJH-0005v7-Ka for qemu-devel@nongnu.org; Fri, 20 Apr 2018 11:50:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f9YJG-0005qL-7S for qemu-devel@nongnu.org; Fri, 20 Apr 2018 11:50:51 -0400 Received: from mail-wr0-x241.google.com ([2a00:1450:400c:c0c::241]:37852) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f9YJG-0005pY-0y for qemu-devel@nongnu.org; Fri, 20 Apr 2018 11:50:50 -0400 Received: by mail-wr0-x241.google.com with SMTP id f14-v6so24222140wre.4 for ; Fri, 20 Apr 2018 08:50:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NKRTWPx9XJvd8tXI8smZeEGIKMjvBcvS6l3yK5hH9tM=; b=Jvh4DbHp9TUmR3rg9sSVDaKbOx2Mo5lR2YwtHF34LrS/W2rXNIyp+EDNex0wjbjZsB OdeOl+WqbfJXB9IVHsBJPZr7VLOE2YjZKf7vOsjJWqZHfU+ewj7ky01HgMCf5AILxV6m qY5FYC7+i9dqaig8uPG1xXbpO7C78YK9yfg24= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NKRTWPx9XJvd8tXI8smZeEGIKMjvBcvS6l3yK5hH9tM=; b=ALF+heuznChuNbYkJ0v9SXRH8HWk+nab8mVUYAAaVSdPPjxz0gQoyucyI30F/pZ5Ip Melc82b0zcPV+qqTvaUDDJl2rqJW54aDHPj9E0cvszeBdjXY3untwC9q50DXZcpL5HFt m1aAnbpVYQd8AViDO8gWkp0ReOT+7BtNCNouKdcmOjEfe0/gR1dkpiwigxWyTwNog4WL NbTfg9dvpVda7FPm/uswSydR5QKhJs8sAdKKJKzTMglE0tr4CtUZSLUXN9jTZh3NLnUW Zs8xYCLq/3XeBPlOIl1sSWB25i+GxbEmQZYC9QpBoS8B7b6rGEBArLFSKHKlGdn+mHnU CS/g== X-Gm-Message-State: ALQs6tDxsdaJgUSHAyHgaHEi+haQsfKUPtyZLRahBmAxhCUajZGnTMC3 Mm9HFWzV/0enk4GRYq/4Cze7Xw== X-Received: by 10.28.184.21 with SMTP id i21mr2432119wmf.94.1524239448798; Fri, 20 Apr 2018 08:50:48 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id v111-v6sm7825434wrb.30.2018.04.20.08.50.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 20 Apr 2018 08:50:46 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 391553E0321; Fri, 20 Apr 2018 16:50:45 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Fri, 20 Apr 2018 16:50:40 +0100 Message-Id: <20180420155045.18862-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180420155045.18862-1-alex.bennee@linaro.org> References: <20180420155045.18862-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::241 Subject: [Qemu-devel] [RFC PATCH 1/6] accel/tcg: export some cputlb functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Peter Crosthwaite , richard.henderson@linaro.org, pbonzini@redhat.com, =?utf-8?q?Alex_Ben?= =?utf-8?q?n=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In preparation for having softmmu helpers in their own file rather than generated as part of softmmu-template.h we need to make a couple of helper functions public outside of cputlb. Signed-off-by: Alex Bennée --- accel/tcg/cputlb.c | 19 ++++++++++--------- accel/tcg/cputlb.h | 20 ++++++++++++++++++++ 2 files changed, 30 insertions(+), 9 deletions(-) create mode 100644 accel/tcg/cputlb.h -- 2.17.0 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 05439039e9..43a89d3010 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" #include "cpu.h" +#include "cputlb.h" #include "exec/exec-all.h" #include "exec/memory.h" #include "exec/address-spaces.h" @@ -760,9 +761,9 @@ static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr) return ram_addr; } -static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, - int mmu_idx, - target_ulong addr, uintptr_t retaddr, int size) +uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, + int mmu_idx, + target_ulong addr, uintptr_t retaddr, int size) { CPUState *cpu = ENV_GET_CPU(env); hwaddr physaddr = iotlbentry->addr; @@ -796,10 +797,10 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, return val; } -static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, - int mmu_idx, - uint64_t val, target_ulong addr, - uintptr_t retaddr, int size) +void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, + int mmu_idx, + uint64_t val, target_ulong addr, + uintptr_t retaddr, int size) { CPUState *cpu = ENV_GET_CPU(env); hwaddr physaddr = iotlbentry->addr; @@ -831,8 +832,8 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, /* Return true if ADDR is present in the victim tlb, and has been copied back to the main tlb. */ -static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index, - size_t elt_ofs, target_ulong page) +bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index, + size_t elt_ofs, target_ulong page) { size_t vidx; for (vidx = 0; vidx < CPU_VTLB_SIZE; ++vidx) { diff --git a/accel/tcg/cputlb.h b/accel/tcg/cputlb.h new file mode 100644 index 0000000000..4645693eb5 --- /dev/null +++ b/accel/tcg/cputlb.h @@ -0,0 +1,20 @@ +/* + * CPU TLB Helperss + */ + +#ifndef CPUTLB_H +#define CPUTBL_H + +uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, + int mmu_idx, + target_ulong addr, uintptr_t retaddr, int size); + +void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, + int mmu_idx, + uint64_t val, target_ulong addr, + uintptr_t retaddr, int size); + +bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index, + size_t elt_ofs, target_ulong page); + +#endif From patchwork Fri Apr 20 15:50:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 133900 Delivered-To: patch@linaro.org Received: by 10.46.66.142 with SMTP id h14csp439269ljf; Fri, 20 Apr 2018 08:53:52 -0700 (PDT) X-Google-Smtp-Source: AIpwx48M+u5mAy0j2gIUB/226QGSN/GeZVY9QvNeqTurVR9Tocfb1bD1+X2C1J5TX8WpXTAxR7PO X-Received: by 2002:a81:a1d2:: with SMTP id y201-v6mr4251847ywg.330.1524239632567; Fri, 20 Apr 2018 08:53:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524239632; cv=none; d=google.com; s=arc-20160816; b=G+xWDCCBuT29WYcMKa7y/CUjwMPChJIGiFceJdydfazTDGnRc0YgdNexIKSLKrut9Y +nHRxsVhEWcXHB2mCxDHSCylE9uhr0HXtUvytkTvbki60bmyCCk66/4jaKsqYspV2ma6 G39RSC1yo5uOFwC3FSY96hP2egy6PydWX/9BucqoEW7VqvkDSR+0VcFj2kVGCWAvdkL1 CJLxKDYjqXF2e3mxUk5rv1LpK316vhTOgVTUQwjOF5Vd8Z4bgB+RUBgR3dWc/mDhwRwi KqDpmILIPk+Vt0dfVk4tOCYf3/srJDGueF685aMUU0Nx+vIxTdeWT1sVwx4dmgL/CNdh 337A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=uaMjiWujckEaCec6HwgcVvqvj2iyAdax4PlRwxIMGc4=; b=fkYj1cuBv/LYOrbWnbHKglPEzqLzEYLTTh36t64OMHFQX/NlkcG3BA9rNnQHzwIGeN O0q6jRc1GBavTGfMCwKAleB6Q0ilFer9kkKL7P4ExUjYQ/DG8JRP1+cLyd4XU2iOhXFS 0dgShoqTIwGNBzUUISdKgBbfZcsEeYRRsrGUJjl6tmZ2eEmeizDQNUg9h1i4I1tbB0xc RRTxcIOHYa1/QrWgZi0aye8mebPy6tMQvt49EDvdFZiT6gZjwZdvg5qpfhX15LNEfVhk 9cnbEKyCNY3UQ6f1d6u4S4mSvp3W9sckicg9C0Z/XWBnhenc9KHVDQN/rjeb/WmA+tGV 2x4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cJrtiz9D; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id p73si2809580uap.259.2018.04.20.08.53.52 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 20 Apr 2018 08:53:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cJrtiz9D; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39045 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f9YMB-0007Cg-WE for patch@linaro.org; Fri, 20 Apr 2018 11:53:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50815) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f9YJI-0005vf-UF for qemu-devel@nongnu.org; Fri, 20 Apr 2018 11:50:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f9YJH-0005rh-FP for qemu-devel@nongnu.org; Fri, 20 Apr 2018 11:50:52 -0400 Received: from mail-wr0-x242.google.com ([2a00:1450:400c:c0c::242]:37853) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f9YJH-0005qb-4a for qemu-devel@nongnu.org; Fri, 20 Apr 2018 11:50:51 -0400 Received: by mail-wr0-x242.google.com with SMTP id f14-v6so24222277wre.4 for ; Fri, 20 Apr 2018 08:50:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uaMjiWujckEaCec6HwgcVvqvj2iyAdax4PlRwxIMGc4=; b=cJrtiz9Dip6YfmWuTRoKhbs1gPxt77XC41NKOdNFW0KkB3GnskWub7PQcmUTdg4N28 gCRguwMPhDVl2LpTWZE+XA01LEtdR+DeS5+du8GhIAZGk5A7P80HW+xgC7s/u74S2fy3 XM9vxP7pwMfnYDvcBtgHEpemTdzZe3LgaamMs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uaMjiWujckEaCec6HwgcVvqvj2iyAdax4PlRwxIMGc4=; b=qNHoTSEVpN56YOy5R9Dz3gs6w54ou3veXXAqrDER4VuKsQwZL/xEwNq1DAh3OOoJNl sGNJ2Osj50hmnkjjoIQixa8MvBnu0ep0d/Do+mnP5eu9Qkn4XJjMD3udCBMqsDbaWRuX wie1F1G8eOhy7qcIRAV8rrdSCNIzfP42mNXlN5zi3QuCvuG/+e2K9NB2FICahk5llWkO FN68SIN19+511ZAS5Q0Bmr8Joho5ZcK0ajiV159GMt8R3qlmyv3d6tgkg2aCNtSYf/ok 3ivE4YSq+vUKlNQCoUgsb2CZ3OwSeJpzDTtkUl5KTvh+XZ1sxPNnmJarLbHXKnZ0Ijgc +L0w== X-Gm-Message-State: ALQs6tAvRzd70EWVOLMnsmbA484LutW6TFJDvhneFUwPY5pKtMq6u+AE yDd2qonWv3zAwsTXJWjLhp1OMw== X-Received: by 10.28.13.205 with SMTP id 196mr2421837wmn.73.1524239449827; Fri, 20 Apr 2018 08:50:49 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id o17-v6sm10079693wrc.71.2018.04.20.08.50.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 20 Apr 2018 08:50:46 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 4F4E83E0342; Fri, 20 Apr 2018 16:50:45 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Fri, 20 Apr 2018 16:50:41 +0100 Message-Id: <20180420155045.18862-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180420155045.18862-1-alex.bennee@linaro.org> References: <20180420155045.18862-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [RFC PATCH 2/6] accel/tcg: new softmmu.c with DATA_SIZE=1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Peter Crosthwaite , richard.henderson@linaro.org, pbonzini@redhat.com, =?utf-8?q?Alex_Ben?= =?utf-8?q?n=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Expand the results of softmmu-template.h with DATA_SIZE 1. Currently there are no changes and areas will get dead-coded away. This is going to form the basis of the re-factoring. Signed-off-by: Alex Bennée --- accel/tcg/Makefile.objs | 1 + accel/tcg/cputlb.c | 6 - accel/tcg/softmmu.c | 255 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 256 insertions(+), 6 deletions(-) create mode 100644 accel/tcg/softmmu.c -- 2.17.0 diff --git a/accel/tcg/Makefile.objs b/accel/tcg/Makefile.objs index d381a02f34..6b0b96633d 100644 --- a/accel/tcg/Makefile.objs +++ b/accel/tcg/Makefile.objs @@ -1,5 +1,6 @@ obj-$(CONFIG_SOFTMMU) += tcg-all.o obj-$(CONFIG_SOFTMMU) += cputlb.o +obj-$(CONFIG_SOFTMMU) += softmmu.o obj-y += tcg-runtime.o tcg-runtime-gvec.o obj-y += cpu-exec.o cpu-exec-common.o translate-all.o obj-y += translator.o diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 43a89d3010..7104bacc0f 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1032,9 +1032,6 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, #define MMUSUFFIX _mmu -#define DATA_SIZE 1 -#include "softmmu_template.h" - #define DATA_SIZE 2 #include "softmmu_template.h" @@ -1109,9 +1106,6 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, #define GETPC() ((uintptr_t)0) #define SOFTMMU_CODE_ACCESS -#define DATA_SIZE 1 -#include "softmmu_template.h" - #define DATA_SIZE 2 #include "softmmu_template.h" diff --git a/accel/tcg/softmmu.c b/accel/tcg/softmmu.c new file mode 100644 index 0000000000..f09aff453a --- /dev/null +++ b/accel/tcg/softmmu.c @@ -0,0 +1,255 @@ +/* + * Software MMU support + * + * Originally this was a set of generated helpers using macro magic. + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "cputlb.h" +#include "exec/exec-all.h" +#include "tcg/tcg.h" + +/* Macro to call the above, with local variables from the use context. */ +#define VICTIM_TLB_HIT(TY, ADDR) \ + victim_tlb_hit(env, mmu_idx, index, offsetof(CPUTLBEntry, TY), \ + (ADDR) & TARGET_PAGE_MASK) + +/* For the benefit of TCG generated code, we want to avoid the complication + of ABI-specific return type promotion and always return a value extended + to the register size of the host. This is tcg_target_long, except in the + case of a 32-bit host and 64-bit data, and for that we always have + uint64_t. Don't bother with this widened value for SOFTMMU_CODE_ACCESS. */ +static inline uint8_t io_readb(CPUArchState *env, + size_t mmu_idx, size_t index, + target_ulong addr, + uintptr_t retaddr) +{ + CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index]; + return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, 1); +} + + +tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + unsigned mmu_idx = get_mmuidx(oi); + int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_read; + unsigned a_bits = get_alignment_bits(get_memop(oi)); + uintptr_t haddr; + uint8_t res; + + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_LOAD, + mmu_idx, retaddr); + } + + /* If the TLB entry is for a different page, reload and try again. */ + if ((addr & TARGET_PAGE_MASK) + != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { + if (!VICTIM_TLB_HIT(addr_read, addr)) { + tlb_fill(ENV_GET_CPU(env), addr, 1, MMU_DATA_LOAD, + mmu_idx, retaddr); + } + tlb_addr = env->tlb_table[mmu_idx][index].addr_read; + } + + /* Handle an IO access. */ + if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { + if ((addr & (1 - 1)) != 0) { + goto do_unaligned_access; + } + + /* ??? Note that the io helpers always read data in the target + byte ordering. We should push the LE/BE request down into io. */ + res = io_readb(env, mmu_idx, index, addr, retaddr); + res = (res); + return res; + } + + /* Handle slow unaligned access (it spans two pages or IO). */ + if (1 > 1 + && unlikely((addr & ~TARGET_PAGE_MASK) + 1 - 1 + >= TARGET_PAGE_SIZE)) { + target_ulong addr1, addr2; + uint8_t res1, res2; + unsigned shift; + do_unaligned_access: + addr1 = addr & ~(1 - 1); + addr2 = addr1 + 1; + res1 = helper_ret_ldub_mmu(env, addr1, oi, retaddr); + res2 = helper_ret_ldub_mmu(env, addr2, oi, retaddr); + shift = (addr & (1 - 1)) * 8; + + /* Little-endian combine. */ + res = (res1 >> shift) | (res2 << ((1 * 8) - shift)); + return res; + } + + haddr = addr + env->tlb_table[mmu_idx][index].addend; + + res = ldub_p((uint8_t *)haddr); + + + + return res; +} +/* Provide signed versions of the load routines as well. We can of course + avoid this for 64-bit data, or for 32-bit data on 32-bit host. */ +static inline void io_writeb(CPUArchState *env, + size_t mmu_idx, size_t index, + uint8_t val, + target_ulong addr, + uintptr_t retaddr) +{ + CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index]; + return io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, 1); +} + +void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + unsigned mmu_idx = get_mmuidx(oi); + int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write; + unsigned a_bits = get_alignment_bits(get_memop(oi)); + uintptr_t haddr; + + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, + mmu_idx, retaddr); + } + + /* If the TLB entry is for a different page, reload and try again. */ + if ((addr & TARGET_PAGE_MASK) + != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { + if (!VICTIM_TLB_HIT(addr_write, addr)) { + tlb_fill(ENV_GET_CPU(env), addr, 1, MMU_DATA_STORE, + mmu_idx, retaddr); + } + tlb_addr = env->tlb_table[mmu_idx][index].addr_write & ~TLB_INVALID_MASK; + } + + /* Handle an IO access. */ + if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { + if ((addr & (1 - 1)) != 0) { + goto do_unaligned_access; + } + + /* ??? Note that the io helpers always read data in the target + byte ordering. We should push the LE/BE request down into io. */ + val = (val); + io_writeb(env, mmu_idx, index, val, addr, retaddr); + return; + } + + /* Handle slow unaligned access (it spans two pages or IO). */ + if (1 > 1 + && unlikely((addr & ~TARGET_PAGE_MASK) + 1 - 1 + >= TARGET_PAGE_SIZE)) { + int i, index2; + target_ulong page2, tlb_addr2; + do_unaligned_access: + /* Ensure the second page is in the TLB. Note that the first page + is already guaranteed to be filled, and that the second page + cannot evict the first. */ + page2 = (addr + 1) & TARGET_PAGE_MASK; + index2 = (page2 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + tlb_addr2 = env->tlb_table[mmu_idx][index2].addr_write; + if (page2 != (tlb_addr2 & (TARGET_PAGE_MASK | TLB_INVALID_MASK)) + && !VICTIM_TLB_HIT(addr_write, page2)) { + tlb_fill(ENV_GET_CPU(env), page2, 1, MMU_DATA_STORE, + mmu_idx, retaddr); + } + + /* XXX: not efficient, but simple. */ + /* This loop must go in the forward direction to avoid issues + with self-modifying code in Windows 64-bit. */ + for (i = 0; i < 1; ++i) { + /* Little-endian extract. */ + uint8_t val8 = val >> (i * 8); + helper_ret_stb_mmu(env, addr + i, val8, + oi, retaddr); + } + return; + } + + haddr = addr + env->tlb_table[mmu_idx][index].addend; + + stb_p((uint8_t *)haddr, val); + + + +} + +/* For the benefit of TCG generated code, we want to avoid the complication + of ABI-specific return type promotion and always return a value extended + to the register size of the host. This is tcg_target_long, except in the + case of a 32-bit host and 64-bit data, and for that we always have + uint64_t. Don't bother with this widened value for SOFTMMU_CODE_ACCESS. */ +uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + unsigned mmu_idx = get_mmuidx(oi); + int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_code; + unsigned a_bits = get_alignment_bits(get_memop(oi)); + uintptr_t haddr; + uint8_t res; + + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_INST_FETCH, + mmu_idx, retaddr); + } + + /* If the TLB entry is for a different page, reload and try again. */ + if ((addr & TARGET_PAGE_MASK) + != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { + if (!VICTIM_TLB_HIT(addr_code, addr)) { + tlb_fill(ENV_GET_CPU(env), addr, 1, MMU_INST_FETCH, + mmu_idx, retaddr); + } + tlb_addr = env->tlb_table[mmu_idx][index].addr_code; + } + + /* Handle an IO access. */ + if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { + if ((addr & (1 - 1)) != 0) { + goto do_unaligned_access; + } + + /* ??? Note that the io helpers always read data in the target + byte ordering. We should push the LE/BE request down into io. */ + res = io_readb(env, mmu_idx, index, addr, retaddr); + res = (res); + return res; + } + + /* Handle slow unaligned access (it spans two pages or IO). */ + if (1 > 1 + && unlikely((addr & ~TARGET_PAGE_MASK) + 1 - 1 + >= TARGET_PAGE_SIZE)) { + target_ulong addr1, addr2; + uint8_t res1, res2; + unsigned shift; + do_unaligned_access: + addr1 = addr & ~(1 - 1); + addr2 = addr1 + 1; + res1 = helper_ret_ldb_cmmu(env, addr1, oi, retaddr); + res2 = helper_ret_ldb_cmmu(env, addr2, oi, retaddr); + shift = (addr & (1 - 1)) * 8; + + /* Little-endian combine. */ + res = (res1 >> shift) | (res2 << ((1 * 8) - shift)); + return res; + } + + haddr = addr + env->tlb_table[mmu_idx][index].addend; + + res = ldub_p((uint8_t *)haddr); + + + + return res; +} From patchwork Fri Apr 20 15:50:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 133901 Delivered-To: patch@linaro.org Received: by 10.46.66.142 with SMTP id h14csp439437ljf; Fri, 20 Apr 2018 08:54:02 -0700 (PDT) X-Google-Smtp-Source: AIpwx48GCeSJFi8SDGw+jfsmQyaQadQStnpZMiSqD4jg4LkmLqX75+/j/8VQqdnEPEw8MsvKHGw7 X-Received: by 10.31.74.1 with SMTP id x1mr7792722vka.44.1524239642645; Fri, 20 Apr 2018 08:54:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524239642; cv=none; d=google.com; s=arc-20160816; b=BmAAU3vSIlNq42wLMbauK7mG2VTQKvVRh5sbkXMnbnlWM0ZYC8a1WVtYkjq1A6olxh 2m+sQuDSt7aKY/wreeNAuyl+jO7bBvcNd+yCxcFgxLFjUdE4p984CYnPhr0KJCBEItnE kmslgSVap/ZmBVLjV25BK7s2jd77nS59Sf9sO88oYoi27LbzvVAOMeW+vXsgnXkTRRsk t7Pk3b83PJUYMcMhTW/n6P+zqRBoIPSAWoBcSUtxmYY96Szi8b6BuLj3wIqz5DBrm/zV njqA1QzX2zhCmxBSTd57HrrNhz0oSRVRqR2yXvpX1Juf+EaGcmPkqMB0ap2g2zUa9XNF aGhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=10C7gb7y3X07HVK5/4Y7SQ9388otHlidEii+FWlqpe0=; b=nqt1CNlU7qcHYUsJDDRZUa/QOYwSiR+O/+Ob9UCw9SWuo3jnRdbAU70YdWHUE8xKwV 9RkW2crEftSnRfDaVuylf8252Jv3AhG/jrHUUqNn/xj1K3p/GwjcGZxYiMacbzxVYtzx jQJcV4eU1gjIZvB7supIbJkITqB6cDN8bvuf0f3SHnySUPxysERqJsqoJccng42pfJv2 CEy/8cz6aoUlL14zaVTzPl0ZcemYFOg53RHtqgcTGymFNnF8emmLRJPnhi3WmcP89OMw LiIFfuyAqbTYakb0t/5gCdNktKTH7T7yy4HA42DAiD6Q8ZUAphvvs0iECD6fKv5yWwX8 mXSw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XqGRI1HE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id s25si2735480uaa.267.2018.04.20.08.54.02 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 20 Apr 2018 08:54:02 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=XqGRI1HE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39048 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f9YML-0007Gs-TV for patch@linaro.org; Fri, 20 Apr 2018 11:54:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50832) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f9YJL-0005x6-53 for qemu-devel@nongnu.org; Fri, 20 Apr 2018 11:50:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f9YJJ-0005tO-3I for qemu-devel@nongnu.org; Fri, 20 Apr 2018 11:50:55 -0400 Received: from mail-wr0-x243.google.com ([2a00:1450:400c:c0c::243]:43810) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f9YJI-0005sV-PC for qemu-devel@nongnu.org; Fri, 20 Apr 2018 11:50:53 -0400 Received: by mail-wr0-x243.google.com with SMTP id v15-v6so6124574wrm.10 for ; Fri, 20 Apr 2018 08:50:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=10C7gb7y3X07HVK5/4Y7SQ9388otHlidEii+FWlqpe0=; b=XqGRI1HEz8r8KFFbqK8efGtDzH8HyfZ9FL2MmNAfEO9lbAEg5wlATrVANR+xZT2IgP O0y5Sa956C2tD0uUdrEUq9VxjUodSk/yV4RRvKk8MvOlVdVIHDDsUx5CbhcL379dImMg Wq/xAxNMVDh5VsUHx5vI+yXx+Ik9EgTOrTZHI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=10C7gb7y3X07HVK5/4Y7SQ9388otHlidEii+FWlqpe0=; b=XGobpkH3pl0lv9zsqmF9J4nBWO2l4KsF4EOx5V66q0sP6PJHvmkLRgMkEAKCu+Mlz+ oNG9OwqF28pfQNBVT8B2fDeRRE49SOaBuWhE+sBcn/e/nkV96nqfJC2JcLi1I8pJjN45 RbgK0zENMhlmISXbzzxi5tq/oFO6wwJ3DlUCeO0wkufkgdNdTWVlBnXr72VlJvf1oPn7 5ezQYfPB/6pLf93WbgzeeOmryNHjB4IJXzpGxCb1Mr7PP/2gIaHVLjPMKLaXXwqBx3pg typ5z1N9+41aPoxEFN03pplekoA72PNSOcq2utwBg6sFgjqtJPGN/0yfZKeYN+NMkeRi 6rBw== X-Gm-Message-State: ALQs6tD8RSNmS8p/KlpwlLST2fbaGrpwCCT1gGj2OgwOsnfxALJd36WZ gvFCCcgyESi+QWgmMUJGNEKyPA== X-Received: by 10.28.214.84 with SMTP id n81mr2420408wmg.80.1524239451203; Fri, 20 Apr 2018 08:50:51 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id e11sm2251968wma.4.2018.04.20.08.50.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 20 Apr 2018 08:50:46 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 63BB63E03B9; Fri, 20 Apr 2018 16:50:45 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Fri, 20 Apr 2018 16:50:42 +0100 Message-Id: <20180420155045.18862-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180420155045.18862-1-alex.bennee@linaro.org> References: <20180420155045.18862-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::243 Subject: [Qemu-devel] [RFC PATCH 3/6] accel/tcg: add DATA_SIZE = 2 to softmmu X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Peter Crosthwaite , richard.henderson@linaro.org, pbonzini@redhat.com, =?utf-8?q?Alex_Ben?= =?utf-8?q?n=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Expand the results of softmmu-template.h with DATA_SIZE 2. We have to ensure we expand with TCG_TARGET_REG_BITS @ 32 to make sure we get all the helpers as needed for all guests. Signed-off-by: Alex Bennée --- accel/tcg/cputlb.c | 6 - accel/tcg/softmmu.c | 452 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 452 insertions(+), 6 deletions(-) -- 2.17.0 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 7104bacc0f..3747657a97 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1032,9 +1032,6 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, #define MMUSUFFIX _mmu -#define DATA_SIZE 2 -#include "softmmu_template.h" - #define DATA_SIZE 4 #include "softmmu_template.h" @@ -1106,9 +1103,6 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, #define GETPC() ((uintptr_t)0) #define SOFTMMU_CODE_ACCESS -#define DATA_SIZE 2 -#include "softmmu_template.h" - #define DATA_SIZE 4 #include "softmmu_template.h" diff --git a/accel/tcg/softmmu.c b/accel/tcg/softmmu.c index f09aff453a..fcad3d360f 100644 --- a/accel/tcg/softmmu.c +++ b/accel/tcg/softmmu.c @@ -251,5 +251,457 @@ uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr, + return res; +} + +static inline uint16_t io_readw(CPUArchState *env, + size_t mmu_idx, size_t index, + target_ulong addr, + uintptr_t retaddr) +{ + CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index]; + return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, 2); +} + + +tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + unsigned mmu_idx = get_mmuidx(oi); + int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_read; + unsigned a_bits = get_alignment_bits(get_memop(oi)); + uintptr_t haddr; + uint16_t res; + + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_LOAD, + mmu_idx, retaddr); + } + + /* If the TLB entry is for a different page, reload and try again. */ + if ((addr & TARGET_PAGE_MASK) + != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { + if (!VICTIM_TLB_HIT(addr_read, addr)) { + tlb_fill(ENV_GET_CPU(env), addr, 2, MMU_DATA_LOAD, + mmu_idx, retaddr); + } + tlb_addr = env->tlb_table[mmu_idx][index].addr_read; + } + + /* Handle an IO access. */ + if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { + if ((addr & (2 - 1)) != 0) { + goto do_unaligned_access; + } + + /* ??? Note that the io helpers always read data in the target + byte ordering. We should push the LE/BE request down into io. */ + res = io_readw(env, mmu_idx, index, addr, retaddr); + res = (res); + return res; + } + + /* Handle slow unaligned access (it spans two pages or IO). */ + if (2 > 1 + && unlikely((addr & ~TARGET_PAGE_MASK) + 2 - 1 + >= TARGET_PAGE_SIZE)) { + target_ulong addr1, addr2; + uint16_t res1, res2; + unsigned shift; + do_unaligned_access: + addr1 = addr & ~(2 - 1); + addr2 = addr1 + 2; + res1 = helper_le_lduw_mmu(env, addr1, oi, retaddr); + res2 = helper_le_lduw_mmu(env, addr2, oi, retaddr); + shift = (addr & (2 - 1)) * 8; + + /* Little-endian combine. */ + res = (res1 >> shift) | (res2 << ((2 * 8) - shift)); + return res; + } + + haddr = addr + env->tlb_table[mmu_idx][index].addend; + + + + res = lduw_le_p((uint8_t *)haddr); + + return res; +} + + +tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + unsigned mmu_idx = get_mmuidx(oi); + int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_read; + unsigned a_bits = get_alignment_bits(get_memop(oi)); + uintptr_t haddr; + uint16_t res; + + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_LOAD, + mmu_idx, retaddr); + } + + /* If the TLB entry is for a different page, reload and try again. */ + if ((addr & TARGET_PAGE_MASK) + != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { + if (!VICTIM_TLB_HIT(addr_read, addr)) { + tlb_fill(ENV_GET_CPU(env), addr, 2, MMU_DATA_LOAD, + mmu_idx, retaddr); + } + tlb_addr = env->tlb_table[mmu_idx][index].addr_read; + } + + /* Handle an IO access. */ + if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { + if ((addr & (2 - 1)) != 0) { + goto do_unaligned_access; + } + + /* ??? Note that the io helpers always read data in the target + byte ordering. We should push the LE/BE request down into io. */ + res = io_readw(env, mmu_idx, index, addr, retaddr); + res = bswap16(res); + return res; + } + + /* Handle slow unaligned access (it spans two pages or IO). */ + if (2 > 1 + && unlikely((addr & ~TARGET_PAGE_MASK) + 2 - 1 + >= TARGET_PAGE_SIZE)) { + target_ulong addr1, addr2; + uint16_t res1, res2; + unsigned shift; + do_unaligned_access: + addr1 = addr & ~(2 - 1); + addr2 = addr1 + 2; + res1 = helper_be_lduw_mmu(env, addr1, oi, retaddr); + res2 = helper_be_lduw_mmu(env, addr2, oi, retaddr); + shift = (addr & (2 - 1)) * 8; + + /* Big-endian combine. */ + res = (res1 << shift) | (res2 >> ((2 * 8) - shift)); + return res; + } + + haddr = addr + env->tlb_table[mmu_idx][index].addend; + res = lduw_be_p((uint8_t *)haddr); + return res; +} + + +/* Provide signed versions of the load routines as well. We can of course + avoid this for 64-bit data, or for 32-bit data on 32-bit host. */ + +tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + return (int16_t)helper_le_lduw_mmu(env, addr, oi, retaddr); +} + + +tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + return (int16_t)helper_be_lduw_mmu(env, addr, oi, retaddr); +} + + +/* Provide signed versions of the load routines as well. We can of course + avoid this for 64-bit data, or for 32-bit data on 32-bit host. */ +static inline void io_writew(CPUArchState *env, + size_t mmu_idx, size_t index, + uint16_t val, + target_ulong addr, + uintptr_t retaddr) +{ + CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index]; + return io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, 2); +} + +void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + unsigned mmu_idx = get_mmuidx(oi); + int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write; + unsigned a_bits = get_alignment_bits(get_memop(oi)); + uintptr_t haddr; + + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, + mmu_idx, retaddr); + } + + /* If the TLB entry is for a different page, reload and try again. */ + if ((addr & TARGET_PAGE_MASK) + != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { + if (!VICTIM_TLB_HIT(addr_write, addr)) { + tlb_fill(ENV_GET_CPU(env), addr, 2, MMU_DATA_STORE, + mmu_idx, retaddr); + } + tlb_addr = env->tlb_table[mmu_idx][index].addr_write & ~TLB_INVALID_MASK; + } + + /* Handle an IO access. */ + if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { + if ((addr & (2 - 1)) != 0) { + goto do_unaligned_access; + } + + /* ??? Note that the io helpers always read data in the target + byte ordering. We should push the LE/BE request down into io. */ + val = (val); + io_writew(env, mmu_idx, index, val, addr, retaddr); + return; + } + + /* Handle slow unaligned access (it spans two pages or IO). */ + if (2 > 1 + && unlikely((addr & ~TARGET_PAGE_MASK) + 2 - 1 + >= TARGET_PAGE_SIZE)) { + int i, index2; + target_ulong page2, tlb_addr2; + do_unaligned_access: + /* Ensure the second page is in the TLB. Note that the first page + is already guaranteed to be filled, and that the second page + cannot evict the first. */ + page2 = (addr + 2) & TARGET_PAGE_MASK; + index2 = (page2 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + tlb_addr2 = env->tlb_table[mmu_idx][index2].addr_write; + if (page2 != (tlb_addr2 & (TARGET_PAGE_MASK | TLB_INVALID_MASK)) + && !VICTIM_TLB_HIT(addr_write, page2)) { + tlb_fill(ENV_GET_CPU(env), page2, 2, MMU_DATA_STORE, + mmu_idx, retaddr); + } + + /* XXX: not efficient, but simple. */ + /* This loop must go in the forward direction to avoid issues + with self-modifying code in Windows 64-bit. */ + for (i = 0; i < 2; ++i) { + /* Little-endian extract. */ + uint8_t val8 = val >> (i * 8); + helper_ret_stb_mmu(env, addr + i, val8, + oi, retaddr); + } + return; + } + + haddr = addr + env->tlb_table[mmu_idx][index].addend; + + + + stw_le_p((uint8_t *)haddr, val); + +} + + +void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + unsigned mmu_idx = get_mmuidx(oi); + int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write; + unsigned a_bits = get_alignment_bits(get_memop(oi)); + uintptr_t haddr; + + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, + mmu_idx, retaddr); + } + + /* If the TLB entry is for a different page, reload and try again. */ + if ((addr & TARGET_PAGE_MASK) + != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { + if (!VICTIM_TLB_HIT(addr_write, addr)) { + tlb_fill(ENV_GET_CPU(env), addr, 2, MMU_DATA_STORE, + mmu_idx, retaddr); + } + tlb_addr = env->tlb_table[mmu_idx][index].addr_write & ~TLB_INVALID_MASK; + } + + /* Handle an IO access. */ + if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { + if ((addr & (2 - 1)) != 0) { + goto do_unaligned_access; + } + + /* ??? Note that the io helpers always read data in the target + byte ordering. We should push the LE/BE request down into io. */ + val = bswap16(val); + io_writew(env, mmu_idx, index, val, addr, retaddr); + return; + } + + /* Handle slow unaligned access (it spans two pages or IO). */ + if (2 > 1 + && unlikely((addr & ~TARGET_PAGE_MASK) + 2 - 1 + >= TARGET_PAGE_SIZE)) { + int i, index2; + target_ulong page2, tlb_addr2; + do_unaligned_access: + /* Ensure the second page is in the TLB. Note that the first page + is already guaranteed to be filled, and that the second page + cannot evict the first. */ + page2 = (addr + 2) & TARGET_PAGE_MASK; + index2 = (page2 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + tlb_addr2 = env->tlb_table[mmu_idx][index2].addr_write; + if (page2 != (tlb_addr2 & (TARGET_PAGE_MASK | TLB_INVALID_MASK)) + && !VICTIM_TLB_HIT(addr_write, page2)) { + tlb_fill(ENV_GET_CPU(env), page2, 2, MMU_DATA_STORE, + mmu_idx, retaddr); + } + + /* XXX: not efficient, but simple */ + /* This loop must go in the forward direction to avoid issues + with self-modifying code. */ + for (i = 0; i < 2; ++i) { + /* Big-endian extract. */ + uint8_t val8 = val >> (((2 - 1) * 8) - (i * 8)); + helper_ret_stb_mmu(env, addr + i, val8, + oi, retaddr); + } + return; + } + + haddr = addr + env->tlb_table[mmu_idx][index].addend; + stw_be_p((uint8_t *)haddr, val); +} + +/* For the benefit of TCG generated code, we want to avoid the complication + of ABI-specific return type promotion and always return a value extended + to the register size of the host. This is tcg_target_long, except in the + case of a 32-bit host and 64-bit data, and for that we always have + uint64_t. Don't bother with this widened value for SOFTMMU_CODE_ACCESS. */ +uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + unsigned mmu_idx = get_mmuidx(oi); + int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_code; + unsigned a_bits = get_alignment_bits(get_memop(oi)); + uintptr_t haddr; + uint16_t res; + + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_INST_FETCH, + mmu_idx, retaddr); + } + + /* If the TLB entry is for a different page, reload and try again. */ + if ((addr & TARGET_PAGE_MASK) + != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { + if (!VICTIM_TLB_HIT(addr_code, addr)) { + tlb_fill(ENV_GET_CPU(env), addr, 2, MMU_INST_FETCH, + mmu_idx, retaddr); + } + tlb_addr = env->tlb_table[mmu_idx][index].addr_code; + } + + /* Handle an IO access. */ + if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { + if ((addr & (2 - 1)) != 0) { + goto do_unaligned_access; + } + + /* ??? Note that the io helpers always read data in the target + byte ordering. We should push the LE/BE request down into io. */ + res = io_readw(env, mmu_idx, index, addr, retaddr); + res = (res); + return res; + } + + /* Handle slow unaligned access (it spans two pages or IO). */ + if (2 > 1 + && unlikely((addr & ~TARGET_PAGE_MASK) + 2 - 1 + >= TARGET_PAGE_SIZE)) { + target_ulong addr1, addr2; + uint16_t res1, res2; + unsigned shift; + do_unaligned_access: + addr1 = addr & ~(2 - 1); + addr2 = addr1 + 2; + res1 = helper_le_ldw_cmmu(env, addr1, oi, retaddr); + res2 = helper_le_ldw_cmmu(env, addr2, oi, retaddr); + shift = (addr & (2 - 1)) * 8; + + /* Little-endian combine. */ + res = (res1 >> shift) | (res2 << ((2 * 8) - shift)); + return res; + } + + haddr = addr + env->tlb_table[mmu_idx][index].addend; + + + + res = lduw_le_p((uint8_t *)haddr); + + return res; +} + + +uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) +{ + unsigned mmu_idx = get_mmuidx(oi); + int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); + target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_code; + unsigned a_bits = get_alignment_bits(get_memop(oi)); + uintptr_t haddr; + uint16_t res; + + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_INST_FETCH, + mmu_idx, retaddr); + } + + /* If the TLB entry is for a different page, reload and try again. */ + if ((addr & TARGET_PAGE_MASK) + != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { + if (!VICTIM_TLB_HIT(addr_code, addr)) { + tlb_fill(ENV_GET_CPU(env), addr, 2, MMU_INST_FETCH, + mmu_idx, retaddr); + } + tlb_addr = env->tlb_table[mmu_idx][index].addr_code; + } + + /* Handle an IO access. */ + if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { + if ((addr & (2 - 1)) != 0) { + goto do_unaligned_access; + } + + /* ??? Note that the io helpers always read data in the target + byte ordering. We should push the LE/BE request down into io. */ + res = io_readw(env, mmu_idx, index, addr, retaddr); + res = bswap16(res); + return res; + } + + /* Handle slow unaligned access (it spans two pages or IO). */ + if (2 > 1 + && unlikely((addr & ~TARGET_PAGE_MASK) + 2 - 1 + >= TARGET_PAGE_SIZE)) { + target_ulong addr1, addr2; + uint16_t res1, res2; + unsigned shift; + do_unaligned_access: + addr1 = addr & ~(2 - 1); + addr2 = addr1 + 2; + res1 = helper_be_ldw_cmmu(env, addr1, oi, retaddr); + res2 = helper_be_ldw_cmmu(env, addr2, oi, retaddr); + shift = (addr & (2 - 1)) * 8; + + /* Big-endian combine. */ + res = (res1 << shift) | (res2 >> ((2 * 8) - shift)); + return res; + } + + haddr = addr + env->tlb_table[mmu_idx][index].addend; + res = lduw_be_p((uint8_t *)haddr); return res; } From patchwork Fri Apr 20 15:50:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 133904 Delivered-To: patch@linaro.org Received: by 10.46.66.142 with SMTP id h14csp441933ljf; Fri, 20 Apr 2018 08:56:38 -0700 (PDT) X-Google-Smtp-Source: AIpwx48xkU/JwXNsS2C2KK6J9ZFG3KP+JHE/o8oWiYkQB+GRNIIPONVTXwVbKtspKjTNfl7xI9be X-Received: by 10.31.193.135 with SMTP id r129mr7903877vkf.112.1524239798596; Fri, 20 Apr 2018 08:56:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524239798; cv=none; d=google.com; s=arc-20160816; b=pMV/mL8TsW8+dSMwjLCw162ts7H6Wpc1P4i0puwgzXyQc3eG7pnb0YEjhOUOJ8RGAT aZkD9HyrtRYQo8l8eLqs9EdAgjT2MXLXQoNbbL+pqVOpYRIjHMDipvwuPA9CYwl7LXGf r1y/ik+8b2Er+wa65PKzupeEV9BBbQHUyvHQ/bqFxB7mzuenx6zmUeDeIajTW1RosNmN Zw35RsUj5OITaZCRxRzcokKUtPUCdA7Hi//UYWQoeB62GY6yRNSPBo7RUtn5kQc/XBbm L2keaHm04zbJmVQEWEWncJQcKKCHBLMyP57ofBwND0+E5YrhslX5lKxuYRdfIZz9afCp IfEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=xIZZrhq2WxxKKT4vh353l4y0ShsBHkRTXQp9P0XvCNQ=; b=Voo169x+Devja0lif7Vt59MvZ2rQMQSL8UncEOfJxJ01grb5LF/bxqRGaBYvZecdH8 BYSXJuWHxZpR6OBaf5uanQ+sBen3QMVsM6bIXWrt5MWILkOQOHOtAwdtX3ZRR1DjCuCj Jff0D1IPNh4+CDdtpbOjAHHW937OwsLj09dkRE8pQViYpZV5OQq4yoOGtw/XDGa10Ohr Ml9Pcv3pjxY591hDKKWTdSjGsRJgF2SZOfTbvI0K8zoMJ5++uAJhwbjZlnHv2NPFRVBp tMmT/44ZjUmaM7I1cUFuF3KbZ2qjtdmSL/yBs+ThrZ9YjLrxS5kjuc229Gmiw7RKauCE kIng== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ep/yGLja; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id b80si2810461vkd.144.2018.04.20.08.56.38 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 20 Apr 2018 08:56:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ep/yGLja; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39146 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f9YOr-0001NK-UG for patch@linaro.org; Fri, 20 Apr 2018 11:56:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50849) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f9YJM-0005yq-SI for qemu-devel@nongnu.org; Fri, 20 Apr 2018 11:51:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f9YJK-0005uU-DE for qemu-devel@nongnu.org; Fri, 20 Apr 2018 11:50:56 -0400 Received: from mail-wr0-x242.google.com ([2a00:1450:400c:c0c::242]:34108) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f9YJK-0005u2-1d for qemu-devel@nongnu.org; Fri, 20 Apr 2018 11:50:54 -0400 Received: by mail-wr0-x242.google.com with SMTP id p18-v6so5051992wrm.1 for ; Fri, 20 Apr 2018 08:50:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xIZZrhq2WxxKKT4vh353l4y0ShsBHkRTXQp9P0XvCNQ=; b=Ep/yGLjaFZOigRamF+jVOXv46cxPv5rN44WCwMfIddKhr1bDUTtziXG/PeJUFpseNP axGWJee4GT05iqIyrmRzAm9D7lVRlwzKYX5fufu5BcPW0tBo5J6fYlpxBm+LZ5XlbVPB rpkqaRkssfbHjkqhtabhoPkJTzpvy0PLeeWQI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xIZZrhq2WxxKKT4vh353l4y0ShsBHkRTXQp9P0XvCNQ=; b=rFeHEzSklc5HPO2IOh/ZifoQ+eUvtropTidwoliGa1KFjL4A7+4uo8GdOU+C1YRpdT Gb0CbC/fuSGz+tjFImpk7MxKhzMR1A2y8zDA3gr6U5Vq+eiGq6N1j/4eiB8Z9kAldxwg OddWVzwvbPQf243qk1Hfp7kT5wldQjKtxlWE/gBMLikeeIri+2gSYB3DOlR9iS+jfBKu 8htwOuzn+GBcvQntNHR3BWWtePAni0uWu28bQqR9Colxd88zA/+m/yF1IwuR2lroXWQK wSTBKI0oK9JU4vT5e+91KG2I7zL7kXp446v9l1YoymiZWA2UJy2i9axZqzD09T2VF4Jz NtIQ== X-Gm-Message-State: ALQs6tA8pE9YfYjhAp3sAY/lVXEMkbEK+vqMJ18cF4GYOz8ZnnQRRsHL f0yqJTt+ducwcJdPnLlGSk3EVw== X-Received: by 2002:adf:dc4b:: with SMTP id m11-v6mr8830285wrj.174.1524239452580; Fri, 20 Apr 2018 08:50:52 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id b10-v6sm355599wrn.42.2018.04.20.08.50.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 20 Apr 2018 08:50:46 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 776AB3E03CC; Fri, 20 Apr 2018 16:50:45 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Fri, 20 Apr 2018 16:50:43 +0100 Message-Id: <20180420155045.18862-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180420155045.18862-1-alex.bennee@linaro.org> References: <20180420155045.18862-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [RFC PATCH 4/6] accel/tcg: create load_helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Peter Crosthwaite , richard.henderson@linaro.org, pbonzini@redhat.com, =?utf-8?q?Alex_Ben?= =?utf-8?q?n=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Collapse all the helpers so far into a common load_helper which can be used for mmu/cmmu and little/big endian functions. Signed-off-by: Alex Bennée --- accel/tcg/softmmu.c | 578 ++++++++++++++------------------------------ 1 file changed, 183 insertions(+), 395 deletions(-) -- 2.17.0 diff --git a/accel/tcg/softmmu.c b/accel/tcg/softmmu.c index fcad3d360f..e6f93250f9 100644 --- a/accel/tcg/softmmu.c +++ b/accel/tcg/softmmu.c @@ -15,88 +15,236 @@ victim_tlb_hit(env, mmu_idx, index, offsetof(CPUTLBEntry, TY), \ (ADDR) & TARGET_PAGE_MASK) -/* For the benefit of TCG generated code, we want to avoid the complication - of ABI-specific return type promotion and always return a value extended - to the register size of the host. This is tcg_target_long, except in the - case of a 32-bit host and 64-bit data, and for that we always have - uint64_t. Don't bother with this widened value for SOFTMMU_CODE_ACCESS. */ -static inline uint8_t io_readb(CPUArchState *env, - size_t mmu_idx, size_t index, - target_ulong addr, - uintptr_t retaddr) + +/* + * Load Helpers + * + * We support two different access types. SOFTMMU_CODE_ACCESS is + * specifically for reading instructions from system memory. It is + * called by the translation loop and in some helpers where the code + * is disassembled. It shouldn't be called directly by guest code. + */ + +static inline uint8_t io_readb(CPUArchState *env, size_t mmu_idx, size_t index, + target_ulong addr, uintptr_t retaddr) { CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index]; return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, 1); } +static inline uint16_t io_readw(CPUArchState *env, size_t mmu_idx, size_t index, + target_ulong addr, uintptr_t retaddr) +{ + CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index]; + return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, 2); +} -tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) +static tcg_target_ulong load_helper(CPUArchState *env, target_ulong addr, + size_t size, bool big_endian, + bool code_read, TCGMemOpIdx oi, + uintptr_t retaddr) { unsigned mmu_idx = get_mmuidx(oi); int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_read; + target_ulong tlb_addr; unsigned a_bits = get_alignment_bits(get_memop(oi)); uintptr_t haddr; - uint8_t res; + tcg_target_ulong res; + + if (code_read) { + tlb_addr = env->tlb_table[mmu_idx][index].addr_code; + } else { + tlb_addr = env->tlb_table[mmu_idx][index].addr_read; + } + /* Handle unaligned */ if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_LOAD, - mmu_idx, retaddr); + if (code_read) { + cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_INST_FETCH, + mmu_idx, retaddr); + } else { + cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_LOAD, + mmu_idx, retaddr); + } } /* If the TLB entry is for a different page, reload and try again. */ if ((addr & TARGET_PAGE_MASK) != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { - if (!VICTIM_TLB_HIT(addr_read, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, 1, MMU_DATA_LOAD, - mmu_idx, retaddr); + if (code_read) { + if (!VICTIM_TLB_HIT(addr_code, addr)) { + tlb_fill(ENV_GET_CPU(env), addr, size, MMU_INST_FETCH, + mmu_idx, retaddr); + } + tlb_addr = env->tlb_table[mmu_idx][index].addr_code; + } else { + if (!VICTIM_TLB_HIT(addr_read, addr)) { + tlb_fill(ENV_GET_CPU(env), addr, size, MMU_DATA_LOAD, + mmu_idx, retaddr); + } + tlb_addr = env->tlb_table[mmu_idx][index].addr_read; } - tlb_addr = env->tlb_table[mmu_idx][index].addr_read; } /* Handle an IO access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - if ((addr & (1 - 1)) != 0) { + if ((addr & (size - 1)) != 0) { goto do_unaligned_access; } /* ??? Note that the io helpers always read data in the target byte ordering. We should push the LE/BE request down into io. */ - res = io_readb(env, mmu_idx, index, addr, retaddr); - res = (res); + switch (size) { + case 1: + { + uint8_t rv = io_readb(env, mmu_idx, index, addr, retaddr); + res = rv; + break; + } + case 2: + { + uint16_t rv = io_readw(env, mmu_idx, index, addr, retaddr); + if (big_endian) { + res = bswap16(rv); + } else { + res = rv; + } + break; + } + default: + g_assert_not_reached(); + break; + } + return res; } /* Handle slow unaligned access (it spans two pages or IO). */ - if (1 > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + 1 - 1 + if (size > 1 + && unlikely((addr & ~TARGET_PAGE_MASK) + size - 1 >= TARGET_PAGE_SIZE)) { target_ulong addr1, addr2; - uint8_t res1, res2; + tcg_target_ulong res1, res2; unsigned shift; do_unaligned_access: - addr1 = addr & ~(1 - 1); - addr2 = addr1 + 1; - res1 = helper_ret_ldub_mmu(env, addr1, oi, retaddr); - res2 = helper_ret_ldub_mmu(env, addr2, oi, retaddr); - shift = (addr & (1 - 1)) * 8; - - /* Little-endian combine. */ - res = (res1 >> shift) | (res2 << ((1 * 8) - shift)); + addr1 = addr & ~(size - 1); + addr2 = addr1 + size; + res1 = load_helper(env, addr1, size, big_endian, code_read, oi, retaddr); + res2 = load_helper(env, addr2, size, big_endian, code_read, oi, retaddr); + shift = (addr & (size - 1)) * 8; + + if (big_endian) { + /* Big-endian combine. */ + res = (res1 << shift) | (res2 >> ((size * 8) - shift)); + } else { + /* Little-endian combine. */ + res = (res1 >> shift) | (res2 << ((size * 8) - shift)); + } return res; } haddr = addr + env->tlb_table[mmu_idx][index].addend; - res = ldub_p((uint8_t *)haddr); + switch (size) { + case 1: + res = ldub_p((uint8_t *)haddr); + break; + case 2: + if (big_endian) { + res = lduw_be_p((uint8_t *)haddr); + } else { + res = lduw_le_p((uint8_t *)haddr); + } + break; + default: + g_assert_not_reached(); + break; + } + return res; +} +/* + * For the benefit of TCG generated code, we want to avoid the + * complication of ABI-specific return type promotion and always + * return a value extended to the register size of the host. This is + * tcg_target_long, except in the case of a 32-bit host and 64-bit + * data, and for that we always have uint64_t. + * + * We don't bother with this widened value for SOFTMMU_CODE_ACCESS. + */ - return res; +tcg_target_ulong __attribute__((flatten)) helper_ret_ldub_mmu(CPUArchState *env, + target_ulong addr, + TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, 1, false, false, oi, retaddr); +} + + + +tcg_target_ulong __attribute__((flatten)) helper_le_lduw_mmu(CPUArchState *env, + target_ulong addr, + TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, 2, false, false, oi, retaddr); } + + +tcg_target_ulong __attribute__((flatten)) helper_be_lduw_mmu(CPUArchState *env, + target_ulong addr, + TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, 2, true, false, oi, retaddr); +} + +uint8_t __attribute__((flatten)) helper_ret_ldb_cmmu (CPUArchState *env, + target_ulong addr, + TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, 1, false, true, oi, retaddr); +} + +uint16_t __attribute__((flatten)) helper_le_ldw_cmmu(CPUArchState *env, + target_ulong addr, + TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, 2, false, true, oi, retaddr); +} + +uint16_t __attribute__((flatten)) helper_be_ldw_cmmu(CPUArchState *env, + target_ulong addr, + TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, 2, true, true, oi, retaddr); +} + /* Provide signed versions of the load routines as well. We can of course avoid this for 64-bit data, or for 32-bit data on 32-bit host. */ + +tcg_target_ulong __attribute__((flatten)) helper_le_ldsw_mmu(CPUArchState *env, + target_ulong addr, + TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return (int16_t)helper_le_lduw_mmu(env, addr, oi, retaddr); +} + + +tcg_target_ulong __attribute__((flatten)) helper_be_ldsw_mmu(CPUArchState *env, + target_ulong addr, + TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return (int16_t)helper_be_lduw_mmu(env, addr, oi, retaddr); +} + static inline void io_writeb(CPUArchState *env, size_t mmu_idx, size_t index, uint8_t val, @@ -183,232 +331,6 @@ void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, } -/* For the benefit of TCG generated code, we want to avoid the complication - of ABI-specific return type promotion and always return a value extended - to the register size of the host. This is tcg_target_long, except in the - case of a 32-bit host and 64-bit data, and for that we always have - uint64_t. Don't bother with this widened value for SOFTMMU_CODE_ACCESS. */ -uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - unsigned mmu_idx = get_mmuidx(oi); - int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_code; - unsigned a_bits = get_alignment_bits(get_memop(oi)); - uintptr_t haddr; - uint8_t res; - - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_INST_FETCH, - mmu_idx, retaddr); - } - - /* If the TLB entry is for a different page, reload and try again. */ - if ((addr & TARGET_PAGE_MASK) - != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { - if (!VICTIM_TLB_HIT(addr_code, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, 1, MMU_INST_FETCH, - mmu_idx, retaddr); - } - tlb_addr = env->tlb_table[mmu_idx][index].addr_code; - } - - /* Handle an IO access. */ - if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - if ((addr & (1 - 1)) != 0) { - goto do_unaligned_access; - } - - /* ??? Note that the io helpers always read data in the target - byte ordering. We should push the LE/BE request down into io. */ - res = io_readb(env, mmu_idx, index, addr, retaddr); - res = (res); - return res; - } - - /* Handle slow unaligned access (it spans two pages or IO). */ - if (1 > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + 1 - 1 - >= TARGET_PAGE_SIZE)) { - target_ulong addr1, addr2; - uint8_t res1, res2; - unsigned shift; - do_unaligned_access: - addr1 = addr & ~(1 - 1); - addr2 = addr1 + 1; - res1 = helper_ret_ldb_cmmu(env, addr1, oi, retaddr); - res2 = helper_ret_ldb_cmmu(env, addr2, oi, retaddr); - shift = (addr & (1 - 1)) * 8; - - /* Little-endian combine. */ - res = (res1 >> shift) | (res2 << ((1 * 8) - shift)); - return res; - } - - haddr = addr + env->tlb_table[mmu_idx][index].addend; - - res = ldub_p((uint8_t *)haddr); - - - - return res; -} - -static inline uint16_t io_readw(CPUArchState *env, - size_t mmu_idx, size_t index, - target_ulong addr, - uintptr_t retaddr) -{ - CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index]; - return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, 2); -} - - -tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - unsigned mmu_idx = get_mmuidx(oi); - int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_read; - unsigned a_bits = get_alignment_bits(get_memop(oi)); - uintptr_t haddr; - uint16_t res; - - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_LOAD, - mmu_idx, retaddr); - } - - /* If the TLB entry is for a different page, reload and try again. */ - if ((addr & TARGET_PAGE_MASK) - != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { - if (!VICTIM_TLB_HIT(addr_read, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, 2, MMU_DATA_LOAD, - mmu_idx, retaddr); - } - tlb_addr = env->tlb_table[mmu_idx][index].addr_read; - } - - /* Handle an IO access. */ - if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - if ((addr & (2 - 1)) != 0) { - goto do_unaligned_access; - } - - /* ??? Note that the io helpers always read data in the target - byte ordering. We should push the LE/BE request down into io. */ - res = io_readw(env, mmu_idx, index, addr, retaddr); - res = (res); - return res; - } - - /* Handle slow unaligned access (it spans two pages or IO). */ - if (2 > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + 2 - 1 - >= TARGET_PAGE_SIZE)) { - target_ulong addr1, addr2; - uint16_t res1, res2; - unsigned shift; - do_unaligned_access: - addr1 = addr & ~(2 - 1); - addr2 = addr1 + 2; - res1 = helper_le_lduw_mmu(env, addr1, oi, retaddr); - res2 = helper_le_lduw_mmu(env, addr2, oi, retaddr); - shift = (addr & (2 - 1)) * 8; - - /* Little-endian combine. */ - res = (res1 >> shift) | (res2 << ((2 * 8) - shift)); - return res; - } - - haddr = addr + env->tlb_table[mmu_idx][index].addend; - - - - res = lduw_le_p((uint8_t *)haddr); - - return res; -} - - -tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - unsigned mmu_idx = get_mmuidx(oi); - int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_read; - unsigned a_bits = get_alignment_bits(get_memop(oi)); - uintptr_t haddr; - uint16_t res; - - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_LOAD, - mmu_idx, retaddr); - } - - /* If the TLB entry is for a different page, reload and try again. */ - if ((addr & TARGET_PAGE_MASK) - != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { - if (!VICTIM_TLB_HIT(addr_read, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, 2, MMU_DATA_LOAD, - mmu_idx, retaddr); - } - tlb_addr = env->tlb_table[mmu_idx][index].addr_read; - } - - /* Handle an IO access. */ - if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - if ((addr & (2 - 1)) != 0) { - goto do_unaligned_access; - } - - /* ??? Note that the io helpers always read data in the target - byte ordering. We should push the LE/BE request down into io. */ - res = io_readw(env, mmu_idx, index, addr, retaddr); - res = bswap16(res); - return res; - } - - /* Handle slow unaligned access (it spans two pages or IO). */ - if (2 > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + 2 - 1 - >= TARGET_PAGE_SIZE)) { - target_ulong addr1, addr2; - uint16_t res1, res2; - unsigned shift; - do_unaligned_access: - addr1 = addr & ~(2 - 1); - addr2 = addr1 + 2; - res1 = helper_be_lduw_mmu(env, addr1, oi, retaddr); - res2 = helper_be_lduw_mmu(env, addr2, oi, retaddr); - shift = (addr & (2 - 1)) * 8; - - /* Big-endian combine. */ - res = (res1 << shift) | (res2 >> ((2 * 8) - shift)); - return res; - } - - haddr = addr + env->tlb_table[mmu_idx][index].addend; - res = lduw_be_p((uint8_t *)haddr); - return res; -} - - -/* Provide signed versions of the load routines as well. We can of course - avoid this for 64-bit data, or for 32-bit data on 32-bit host. */ - -tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - return (int16_t)helper_le_lduw_mmu(env, addr, oi, retaddr); -} - - -tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - return (int16_t)helper_be_lduw_mmu(env, addr, oi, retaddr); -} /* Provide signed versions of the load routines as well. We can of course @@ -571,137 +493,3 @@ void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, haddr = addr + env->tlb_table[mmu_idx][index].addend; stw_be_p((uint8_t *)haddr, val); } - -/* For the benefit of TCG generated code, we want to avoid the complication - of ABI-specific return type promotion and always return a value extended - to the register size of the host. This is tcg_target_long, except in the - case of a 32-bit host and 64-bit data, and for that we always have - uint64_t. Don't bother with this widened value for SOFTMMU_CODE_ACCESS. */ -uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - unsigned mmu_idx = get_mmuidx(oi); - int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_code; - unsigned a_bits = get_alignment_bits(get_memop(oi)); - uintptr_t haddr; - uint16_t res; - - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_INST_FETCH, - mmu_idx, retaddr); - } - - /* If the TLB entry is for a different page, reload and try again. */ - if ((addr & TARGET_PAGE_MASK) - != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { - if (!VICTIM_TLB_HIT(addr_code, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, 2, MMU_INST_FETCH, - mmu_idx, retaddr); - } - tlb_addr = env->tlb_table[mmu_idx][index].addr_code; - } - - /* Handle an IO access. */ - if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - if ((addr & (2 - 1)) != 0) { - goto do_unaligned_access; - } - - /* ??? Note that the io helpers always read data in the target - byte ordering. We should push the LE/BE request down into io. */ - res = io_readw(env, mmu_idx, index, addr, retaddr); - res = (res); - return res; - } - - /* Handle slow unaligned access (it spans two pages or IO). */ - if (2 > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + 2 - 1 - >= TARGET_PAGE_SIZE)) { - target_ulong addr1, addr2; - uint16_t res1, res2; - unsigned shift; - do_unaligned_access: - addr1 = addr & ~(2 - 1); - addr2 = addr1 + 2; - res1 = helper_le_ldw_cmmu(env, addr1, oi, retaddr); - res2 = helper_le_ldw_cmmu(env, addr2, oi, retaddr); - shift = (addr & (2 - 1)) * 8; - - /* Little-endian combine. */ - res = (res1 >> shift) | (res2 << ((2 * 8) - shift)); - return res; - } - - haddr = addr + env->tlb_table[mmu_idx][index].addend; - - - - res = lduw_le_p((uint8_t *)haddr); - - return res; -} - - -uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - unsigned mmu_idx = get_mmuidx(oi); - int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_code; - unsigned a_bits = get_alignment_bits(get_memop(oi)); - uintptr_t haddr; - uint16_t res; - - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_INST_FETCH, - mmu_idx, retaddr); - } - - /* If the TLB entry is for a different page, reload and try again. */ - if ((addr & TARGET_PAGE_MASK) - != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { - if (!VICTIM_TLB_HIT(addr_code, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, 2, MMU_INST_FETCH, - mmu_idx, retaddr); - } - tlb_addr = env->tlb_table[mmu_idx][index].addr_code; - } - - /* Handle an IO access. */ - if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - if ((addr & (2 - 1)) != 0) { - goto do_unaligned_access; - } - - /* ??? Note that the io helpers always read data in the target - byte ordering. We should push the LE/BE request down into io. */ - res = io_readw(env, mmu_idx, index, addr, retaddr); - res = bswap16(res); - return res; - } - - /* Handle slow unaligned access (it spans two pages or IO). */ - if (2 > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + 2 - 1 - >= TARGET_PAGE_SIZE)) { - target_ulong addr1, addr2; - uint16_t res1, res2; - unsigned shift; - do_unaligned_access: - addr1 = addr & ~(2 - 1); - addr2 = addr1 + 2; - res1 = helper_be_ldw_cmmu(env, addr1, oi, retaddr); - res2 = helper_be_ldw_cmmu(env, addr2, oi, retaddr); - shift = (addr & (2 - 1)) * 8; - - /* Big-endian combine. */ - res = (res1 << shift) | (res2 >> ((2 * 8) - shift)); - return res; - } - - haddr = addr + env->tlb_table[mmu_idx][index].addend; - res = lduw_be_p((uint8_t *)haddr); - return res; -} From patchwork Fri Apr 20 15:50:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 133903 Delivered-To: patch@linaro.org Received: by 10.46.66.142 with SMTP id h14csp441750ljf; Fri, 20 Apr 2018 08:56:24 -0700 (PDT) X-Google-Smtp-Source: AIpwx49OnRzaws4ByLFwFN4FYDe0Ot7NlFfemhFeuTOD0tZoGbWnEujPcNNs1cuHXJ5bbbpgGoIa X-Received: by 10.176.6.5 with SMTP id f5mr7860768uaf.37.1524239784329; Fri, 20 Apr 2018 08:56:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524239784; cv=none; d=google.com; s=arc-20160816; b=Njfbx/RAiK6IL7qFdt3UHQ1OhnbUlM8RjKZBY30dgR3LoS+EB97AMhRdl54ludSZRJ g6i/iSaMLjvw3lpdoAwfG9Htn+xhaowxmtK29QXj3Yrq5MoWO5eiEKrEhxi6cqZpSueR Ft33IIFkW1xWQPKyupH8zb5UDOmBCk8q0C0mtAmWsQQD8zCBqtOESAcC8DZekZh9bRLH FUYoP1RaJ9p524NKzp29ne0Jv/lGKSvdNZ4eJP43OeYaa4Jol4yKMfBeK742doqAK2qm z8SQnB9hkLIORrRaU7dpoluv3yFLSYW12AHHWcsva6TAe6Y4+/YIryxpgx0cD9AzGhUo E6dg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=IQUsxXl0UZdkYa7y532hBMAgXe8ET9AN63dldcNKruY=; b=GGb2jwYmeeJEovq+MAxdYTAJlIRW+Vs0ITqta/E0xgxnX0Frf5/fO90IDBd4zUV0cr L8fw2/w7tuG0WEKmmhCPx0s1lzpGSVcaj6XygabvhnrNdT2x1FhLjhjvL5//UTmioHCq niNjM0lrC+yH0l1w/FzTTpWV6e1A52++3TByYUtdmNkVSGoBM5V8uA45YpwbXY74B1JC dCFzhijhs5phS6mTu9xW5KkTBFHdBeEKwOAv8fXIEjSxlK2QaawOX7zpCgzpKwQ80CRf G5u0fK9CEm2t81JhclqOSzsfYoIcTCbi20/aposg6Lb1S/57ayQC/Lh3jP4fNJM0snB+ grXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DmfV74OT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id b64si2790163vke.295.2018.04.20.08.56.24 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 20 Apr 2018 08:56:24 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DmfV74OT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39137 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f9YOd-0001BD-Dl for patch@linaro.org; Fri, 20 Apr 2018 11:56:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50895) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f9YJQ-000629-8R for qemu-devel@nongnu.org; Fri, 20 Apr 2018 11:51:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f9YJM-0005wb-WC for qemu-devel@nongnu.org; Fri, 20 Apr 2018 11:51:00 -0400 Received: from mail-wr0-x242.google.com ([2a00:1450:400c:c0c::242]:38261) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f9YJM-0005vZ-Lp for qemu-devel@nongnu.org; Fri, 20 Apr 2018 11:50:56 -0400 Received: by mail-wr0-x242.google.com with SMTP id h3-v6so24247423wrh.5 for ; Fri, 20 Apr 2018 08:50:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IQUsxXl0UZdkYa7y532hBMAgXe8ET9AN63dldcNKruY=; b=DmfV74OTNzGMWxS+p4cXnNFdJj4QExgkV6dX9hX36LwVQTi7iyqeEYlrKUOWnU/F/9 Pu5dEyROFGvJLTY2wKA4qyhXFvnGlS3m0AQ25TuQ7a25PJvDTI4S6mC1Fq7JbenbXpPB HDmgcC4+xKXKbhMZIuP9dsh+cun1zNV5lJ2+Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IQUsxXl0UZdkYa7y532hBMAgXe8ET9AN63dldcNKruY=; b=FddllCySgthYjVJc6gsIIF7RmVbwUzTCXbxQ3guUZP05eLeSTxw0znM4dCnQkReKq1 Q0WBVFAC1In06v8Nk+U7iLmDIqwBwXT6zvKLzCFxHDhn/z9Q8ZTx0rYGi77AENuptq3s GL42UQDe744pkmJGDQkl08Maqgcqp0ztCo3lZyaCf+vePpRj5FZDu444+cZ3yHLQ7gpq xsVICAegeKalYYNAVoB93q+b/fAWAwVp17YUrsVbxAl/qgDYI5TcFgR4TtQD+RySqqB4 bW/FGIbdZAG8vB2yUF9qOSTfGXo06eaqG7uUrcqbuyBr9SwjbdpyIjpY3ldBCF+CBGMG wUFw== X-Gm-Message-State: ALQs6tDH3XiLxb19or71Gr4OBTVyTONG36Rha3sAH6+WMoTCz+LnqD+s iMMs91WOkb9C/9mrzkOwLT/l5A== X-Received: by 2002:adf:b595:: with SMTP id c21-v6mr8682758wre.233.1524239455421; Fri, 20 Apr 2018 08:50:55 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id l53-v6sm7096855wrc.80.2018.04.20.08.50.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 20 Apr 2018 08:50:52 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 8A5193E0402; Fri, 20 Apr 2018 16:50:45 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Fri, 20 Apr 2018 16:50:44 +0100 Message-Id: <20180420155045.18862-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180420155045.18862-1-alex.bennee@linaro.org> References: <20180420155045.18862-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [RFC PATCH 5/6] accel/tcg: create store_helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Peter Crosthwaite , richard.henderson@linaro.org, pbonzini@redhat.com, =?utf-8?q?Alex_Ben?= =?utf-8?q?n=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is a common helper for all stores (currently 1 and 2 byte operations). It takes a size and endian parameter. Signed-off-by: Alex Bennée --- accel/tcg/softmmu.c | 244 ++++++++++++++------------------------------ 1 file changed, 79 insertions(+), 165 deletions(-) -- 2.17.0 diff --git a/accel/tcg/softmmu.c b/accel/tcg/softmmu.c index e6f93250f9..2be2d9025f 100644 --- a/accel/tcg/softmmu.c +++ b/accel/tcg/softmmu.c @@ -245,6 +245,10 @@ tcg_target_ulong __attribute__((flatten)) helper_be_ldsw_mmu(CPUArchState *env, return (int16_t)helper_be_lduw_mmu(env, addr, oi, retaddr); } +/* + * Store Helpers + */ + static inline void io_writeb(CPUArchState *env, size_t mmu_idx, size_t index, uint8_t val, @@ -255,86 +259,6 @@ static inline void io_writeb(CPUArchState *env, return io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, 1); } -void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - unsigned mmu_idx = get_mmuidx(oi); - int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write; - unsigned a_bits = get_alignment_bits(get_memop(oi)); - uintptr_t haddr; - - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, - mmu_idx, retaddr); - } - - /* If the TLB entry is for a different page, reload and try again. */ - if ((addr & TARGET_PAGE_MASK) - != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { - if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, 1, MMU_DATA_STORE, - mmu_idx, retaddr); - } - tlb_addr = env->tlb_table[mmu_idx][index].addr_write & ~TLB_INVALID_MASK; - } - - /* Handle an IO access. */ - if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - if ((addr & (1 - 1)) != 0) { - goto do_unaligned_access; - } - - /* ??? Note that the io helpers always read data in the target - byte ordering. We should push the LE/BE request down into io. */ - val = (val); - io_writeb(env, mmu_idx, index, val, addr, retaddr); - return; - } - - /* Handle slow unaligned access (it spans two pages or IO). */ - if (1 > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + 1 - 1 - >= TARGET_PAGE_SIZE)) { - int i, index2; - target_ulong page2, tlb_addr2; - do_unaligned_access: - /* Ensure the second page is in the TLB. Note that the first page - is already guaranteed to be filled, and that the second page - cannot evict the first. */ - page2 = (addr + 1) & TARGET_PAGE_MASK; - index2 = (page2 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - tlb_addr2 = env->tlb_table[mmu_idx][index2].addr_write; - if (page2 != (tlb_addr2 & (TARGET_PAGE_MASK | TLB_INVALID_MASK)) - && !VICTIM_TLB_HIT(addr_write, page2)) { - tlb_fill(ENV_GET_CPU(env), page2, 1, MMU_DATA_STORE, - mmu_idx, retaddr); - } - - /* XXX: not efficient, but simple. */ - /* This loop must go in the forward direction to avoid issues - with self-modifying code in Windows 64-bit. */ - for (i = 0; i < 1; ++i) { - /* Little-endian extract. */ - uint8_t val8 = val >> (i * 8); - helper_ret_stb_mmu(env, addr + i, val8, - oi, retaddr); - } - return; - } - - haddr = addr + env->tlb_table[mmu_idx][index].addend; - - stb_p((uint8_t *)haddr, val); - - - -} - - - -/* Provide signed versions of the load routines as well. We can of course - avoid this for 64-bit data, or for 32-bit data on 32-bit host. */ static inline void io_writew(CPUArchState *env, size_t mmu_idx, size_t index, uint16_t val, @@ -345,8 +269,9 @@ static inline void io_writew(CPUArchState *env, return io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, 2); } -void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, - TCGMemOpIdx oi, uintptr_t retaddr) +static void store_helper(CPUArchState *env, target_ulong addr, uint64_t val, + size_t size, bool big_endian, TCGMemOpIdx oi, + uintptr_t retaddr) { unsigned mmu_idx = get_mmuidx(oi); int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); @@ -363,7 +288,7 @@ void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, if ((addr & TARGET_PAGE_MASK) != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, 2, MMU_DATA_STORE, + tlb_fill(ENV_GET_CPU(env), addr, size, MMU_DATA_STORE, mmu_idx, retaddr); } tlb_addr = env->tlb_table[mmu_idx][index].addr_write & ~TLB_INVALID_MASK; @@ -371,20 +296,40 @@ void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, /* Handle an IO access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - if ((addr & (2 - 1)) != 0) { + if ((addr & (size - 1)) != 0) { goto do_unaligned_access; } /* ??? Note that the io helpers always read data in the target byte ordering. We should push the LE/BE request down into io. */ - val = (val); - io_writew(env, mmu_idx, index, val, addr, retaddr); + switch (size) { + case 1: + { + uint8_t wv = (val); + io_writeb(env, mmu_idx, index, wv, addr, retaddr); + break; + } + case 2: + { + uint16_t wv; + if (big_endian) { + wv = bswap16( (uint16_t) val); + } else { + wv = (val); + } + io_writew(env, mmu_idx, index, wv, addr, retaddr); + break; + } + default: + g_assert_not_reached(); + break; + } return; } /* Handle slow unaligned access (it spans two pages or IO). */ - if (2 > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + 2 - 1 + if (size > 1 + && unlikely((addr & ~TARGET_PAGE_MASK) + size - 1 >= TARGET_PAGE_SIZE)) { int i, index2; target_ulong page2, tlb_addr2; @@ -392,104 +337,73 @@ void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, /* Ensure the second page is in the TLB. Note that the first page is already guaranteed to be filled, and that the second page cannot evict the first. */ - page2 = (addr + 2) & TARGET_PAGE_MASK; + page2 = (addr + size) & TARGET_PAGE_MASK; index2 = (page2 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); tlb_addr2 = env->tlb_table[mmu_idx][index2].addr_write; if (page2 != (tlb_addr2 & (TARGET_PAGE_MASK | TLB_INVALID_MASK)) && !VICTIM_TLB_HIT(addr_write, page2)) { - tlb_fill(ENV_GET_CPU(env), page2, 2, MMU_DATA_STORE, + tlb_fill(ENV_GET_CPU(env), page2, size, MMU_DATA_STORE, mmu_idx, retaddr); } /* XXX: not efficient, but simple. */ /* This loop must go in the forward direction to avoid issues with self-modifying code in Windows 64-bit. */ - for (i = 0; i < 2; ++i) { - /* Little-endian extract. */ - uint8_t val8 = val >> (i * 8); - helper_ret_stb_mmu(env, addr + i, val8, - oi, retaddr); + for (i = 0; i < size; ++i) { + uint8_t val8; + if (big_endian) { + /* Big-endian extract. */ + val8 = val >> (((size - 1) * 8) - (i * 8)); + } else { + /* Little-endian extract. */ + val8 = val >> (i * 8); + } + store_helper(env, addr + i, val8, 1, big_endian, oi, retaddr); } return; } haddr = addr + env->tlb_table[mmu_idx][index].addend; - - - stw_le_p((uint8_t *)haddr, val); - -} - - -void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - unsigned mmu_idx = get_mmuidx(oi); - int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write; - unsigned a_bits = get_alignment_bits(get_memop(oi)); - uintptr_t haddr; - - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, - mmu_idx, retaddr); - } - - /* If the TLB entry is for a different page, reload and try again. */ - if ((addr & TARGET_PAGE_MASK) - != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { - if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, 2, MMU_DATA_STORE, - mmu_idx, retaddr); + switch(size) { + case 1: + stb_p((uint8_t *)haddr, val); + break; + case 2: + if (big_endian) { + stw_be_p((uint8_t *)haddr, val); + } else { + stw_le_p((uint8_t *)haddr, val); } - tlb_addr = env->tlb_table[mmu_idx][index].addr_write & ~TLB_INVALID_MASK; + break; + default: + g_assert_not_reached(); + break; } +} - /* Handle an IO access. */ - if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - if ((addr & (2 - 1)) != 0) { - goto do_unaligned_access; - } +void __attribute__((flatten)) helper_ret_stb_mmu(CPUArchState *env, + target_ulong addr, uint8_t val, + TCGMemOpIdx oi, + uintptr_t retaddr) +{ + store_helper(env, addr, val, 1, false, oi, retaddr); +} - /* ??? Note that the io helpers always read data in the target - byte ordering. We should push the LE/BE request down into io. */ - val = bswap16(val); - io_writew(env, mmu_idx, index, val, addr, retaddr); - return; - } - /* Handle slow unaligned access (it spans two pages or IO). */ - if (2 > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + 2 - 1 - >= TARGET_PAGE_SIZE)) { - int i, index2; - target_ulong page2, tlb_addr2; - do_unaligned_access: - /* Ensure the second page is in the TLB. Note that the first page - is already guaranteed to be filled, and that the second page - cannot evict the first. */ - page2 = (addr + 2) & TARGET_PAGE_MASK; - index2 = (page2 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - tlb_addr2 = env->tlb_table[mmu_idx][index2].addr_write; - if (page2 != (tlb_addr2 & (TARGET_PAGE_MASK | TLB_INVALID_MASK)) - && !VICTIM_TLB_HIT(addr_write, page2)) { - tlb_fill(ENV_GET_CPU(env), page2, 2, MMU_DATA_STORE, - mmu_idx, retaddr); - } +void __attribute__((flatten)) helper_le_stw_mmu(CPUArchState *env, + target_ulong addr, uint16_t val, + TCGMemOpIdx oi, + uintptr_t retaddr) +{ + store_helper(env, addr, val, 2, false, oi, retaddr); +} - /* XXX: not efficient, but simple */ - /* This loop must go in the forward direction to avoid issues - with self-modifying code. */ - for (i = 0; i < 2; ++i) { - /* Big-endian extract. */ - uint8_t val8 = val >> (((2 - 1) * 8) - (i * 8)); - helper_ret_stb_mmu(env, addr + i, val8, - oi, retaddr); - } - return; - } - haddr = addr + env->tlb_table[mmu_idx][index].addend; - stw_be_p((uint8_t *)haddr, val); +void __attribute__((flatten)) helper_be_stw_mmu(CPUArchState *env, + target_ulong addr, uint16_t val, + TCGMemOpIdx oi, + uintptr_t retaddr) +{ + store_helper(env, addr, val, 2, true, oi, retaddr); } From patchwork Fri Apr 20 15:50:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 133905 Delivered-To: patch@linaro.org Received: by 10.46.66.142 with SMTP id h14csp442907ljf; Fri, 20 Apr 2018 08:57:39 -0700 (PDT) X-Google-Smtp-Source: AB8JxZr+yI6HLEeYyke7k94oZ3hJe11WvqIRJfJiGJhd4x/TcWtc+hUICyt58zFqq7iLnvrBwuta X-Received: by 10.55.140.130 with SMTP id o124mr10742233qkd.187.1524239859734; Fri, 20 Apr 2018 08:57:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524239859; cv=none; d=google.com; s=arc-20160816; b=seEfoCAeH5hqIcm9K6vgqfPbSiuJZUeKfhRTgpXH1p6BXXWS8T3yiN8lLSYSTNzXJh AZkyw4MRPi2O6zpSr6Ifl7fRql0BdaOn3g3Chm5UIeuAevklj66/QxiCV8gF2Fz47C4w wZIq2+XoZMEe4hKo3nD2oLN4VxyFDrz6feq+XaukQ3Jyfx6CxXiebwrkQkdRl5bHkPXB HI97apGo3OY4a45m8Bk3dfxG5iOymPjmmIvcAMMf3uOjZwePgaecN93/DkkxDgsMsW5z uC+Z+PTjilGpjEaq1Aap3F3D7kVTBNxUv6boil4NGfs6EjcoCw4PAnedgBYydtvZll68 7FdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=b0A7NmNL0OaeT5BVjOXcve9sxW3NXNelFrO6xHd0zoQ=; b=iMrLE35UDpcjs+rkX5sX2sW2U303d7zbvE99iwNomcO5TVlhwu+3VN7bMrRsyMcOPD CAHQ1oxipM98E1wB2ds+aVI4yschH4AlRVk63hnS5mOXqT1QpCKScEGbbDrNP4gwT1EA Xbyo3qoHrw6pouKKW0uKqN1IVgOvOrS2jfEzYnBB1KRCSRcPrPT5OVxV7pbMZKQPR/jY VxniUxVpXBoJ0rjIzpjS1RpbggLOrF76KFOqFWY7gpoHIZxW5pjlrQFeAkVjEDqjx5GX PJK23EQaP0AMfCVNp7ltjNM667lWYsY9RqlaEV2CzVNiwbvR2w8m4nrm9ZkF6fviUADY fZEw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Cu3Ca1bz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id l8-v6si6205394qtp.285.2018.04.20.08.57.39 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 20 Apr 2018 08:57:39 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Cu3Ca1bz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39154 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f9YPr-00021F-4b for patch@linaro.org; Fri, 20 Apr 2018 11:57:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50893) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f9YJP-00061d-O5 for qemu-devel@nongnu.org; Fri, 20 Apr 2018 11:51:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f9YJM-0005wJ-PQ for qemu-devel@nongnu.org; Fri, 20 Apr 2018 11:50:59 -0400 Received: from mail-wr0-x241.google.com ([2a00:1450:400c:c0c::241]:38260) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1f9YJM-0005vT-Af for qemu-devel@nongnu.org; Fri, 20 Apr 2018 11:50:56 -0400 Received: by mail-wr0-x241.google.com with SMTP id h3-v6so24247382wrh.5 for ; Fri, 20 Apr 2018 08:50:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b0A7NmNL0OaeT5BVjOXcve9sxW3NXNelFrO6xHd0zoQ=; b=Cu3Ca1bzpOq2nztqEDB7jLfwHaamig0OkYSwgDs9a7I5Xjkx+aY8Dzx/qSHPldO5UY 4wCPWdsY1w6PwPl/o6nusmN+LwkvpB4+1UMWFZojYPqvkawVempwQwfsO261H/eVa3Nq POKSS6XLxrjpkwqZ+nSekK3CgFb9YlxrSYIPQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=b0A7NmNL0OaeT5BVjOXcve9sxW3NXNelFrO6xHd0zoQ=; b=YM8CDoDDwI2sWVzDhWoEE2K4ygtXu1sC/4FEOlu2ox1XMNYGNFa9DTixyNG1Rc27GV WistbkmpU1Fu+TF31ZOiQxGUpJlJ17seNJKT3ey/4f0kjDmRP6L7mgpxKglGDlToKEYj 6/BvNlwRf/sBqiXABJLAJKXN7DnFqDlScdok0kb+gg7DhnTRuCZRmSJ+mjYyxQQDxxdo EvyW+/7mUvWbwl3JGDxB6DSizHEqAvlJEEruEHxdHBconmYk12jQLDkdL324SFSn6Nfd Fz/h/zTRNg9fAs7KS9wyvEW1UJ9kp2h5TC+6PzIw87N6br5Ps1fG9zLursB41G7RhM1K S5aA== X-Gm-Message-State: ALQs6tAbDLv4DcWSJr/VKH+TiDZLOmUgF/KSKsgHH9MkVZ1iY/H8Ph7O 58HA76n5482d+drWNZfkDRKYH11nZ14= X-Received: by 10.28.198.202 with SMTP id w193mr301007wmf.68.1524239454622; Fri, 20 Apr 2018 08:50:54 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id e50-v6sm11924304wre.4.2018.04.20.08.50.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 20 Apr 2018 08:50:52 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id A36493E0410; Fri, 20 Apr 2018 16:50:45 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Fri, 20 Apr 2018 16:50:45 +0100 Message-Id: <20180420155045.18862-7-alex.bennee@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180420155045.18862-1-alex.bennee@linaro.org> References: <20180420155045.18862-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::241 Subject: [Qemu-devel] [RFC PATCH 6/6] accel/tcg: convert 4/8 byte access and remove softmmu_template X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Peter Crosthwaite , richard.henderson@linaro.org, pbonzini@redhat.com, =?utf-8?q?Alex_Ben?= =?utf-8?q?n=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" With the basic helpers in place adding stubs for the remaining SoftMMU helpers is easy. We shuffle handling of byte-swapping into a little helper function and directly call io_readx/io_writex. Signed-off-by: Alex Bennée --- accel/tcg/cputlb.c | 30 --- accel/tcg/softmmu.c | 254 +++++++++++++------- accel/tcg/softmmu_template.h | 435 ----------------------------------- 3 files changed, 171 insertions(+), 548 deletions(-) delete mode 100644 accel/tcg/softmmu_template.h -- 2.17.0 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 3747657a97..7e7b698eeb 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1022,22 +1022,6 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, cpu_loop_exit_atomic(ENV_GET_CPU(env), retaddr); } -#ifdef TARGET_WORDS_BIGENDIAN -# define TGT_BE(X) (X) -# define TGT_LE(X) BSWAP(X) -#else -# define TGT_BE(X) BSWAP(X) -# define TGT_LE(X) (X) -#endif - -#define MMUSUFFIX _mmu - -#define DATA_SIZE 4 -#include "softmmu_template.h" - -#define DATA_SIZE 8 -#include "softmmu_template.h" - /* First set of helpers allows passing in of OI and RETADDR. This makes them callable from other helpers. */ @@ -1094,17 +1078,3 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, #define DATA_SIZE 8 #include "atomic_template.h" #endif - -/* Code access functions. */ - -#undef MMUSUFFIX -#define MMUSUFFIX _cmmu -#undef GETPC -#define GETPC() ((uintptr_t)0) -#define SOFTMMU_CODE_ACCESS - -#define DATA_SIZE 4 -#include "softmmu_template.h" - -#define DATA_SIZE 8 -#include "softmmu_template.h" diff --git a/accel/tcg/softmmu.c b/accel/tcg/softmmu.c index 2be2d9025f..a0106cd9c0 100644 --- a/accel/tcg/softmmu.c +++ b/accel/tcg/softmmu.c @@ -10,12 +10,42 @@ #include "exec/exec-all.h" #include "tcg/tcg.h" +#ifdef TARGET_WORDS_BIGENDIAN +#define NEED_BE_BSWAP 0 +#define NEED_LE_BSWAP 1 +#else +#define NEED_BE_BSWAP 1 +#define NEED_LE_BSWAP 0 +#endif + +/* + * Byte Swap Helper + * + * This should all dead code away depending on the build host and + * access type. + */ + +static inline uint64_t handle_bswap(uint64_t val, int size, bool big_endian) +{ + if ((big_endian && NEED_BE_BSWAP) || (!big_endian && NEED_LE_BSWAP)) { + switch (size) { + case 1: return val; + case 2: return bswap16(val); + case 4: return bswap32(val); + case 8: return bswap64(val); + default: + g_assert_not_reached(); + } + } else { + return val; + } +} + /* Macro to call the above, with local variables from the use context. */ #define VICTIM_TLB_HIT(TY, ADDR) \ victim_tlb_hit(env, mmu_idx, index, offsetof(CPUTLBEntry, TY), \ (ADDR) & TARGET_PAGE_MASK) - /* * Load Helpers * @@ -25,19 +55,6 @@ * is disassembled. It shouldn't be called directly by guest code. */ -static inline uint8_t io_readb(CPUArchState *env, size_t mmu_idx, size_t index, - target_ulong addr, uintptr_t retaddr) -{ - CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index]; - return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, 1); -} - -static inline uint16_t io_readw(CPUArchState *env, size_t mmu_idx, size_t index, - target_ulong addr, uintptr_t retaddr) -{ - CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index]; - return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, 2); -} static tcg_target_ulong load_helper(CPUArchState *env, target_ulong addr, size_t size, bool big_endian, @@ -88,35 +105,15 @@ static tcg_target_ulong load_helper(CPUArchState *env, target_ulong addr, /* Handle an IO access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { + CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index]; + uint64_t tmp; + if ((addr & (size - 1)) != 0) { goto do_unaligned_access; } - /* ??? Note that the io helpers always read data in the target - byte ordering. We should push the LE/BE request down into io. */ - switch (size) { - case 1: - { - uint8_t rv = io_readb(env, mmu_idx, index, addr, retaddr); - res = rv; - break; - } - case 2: - { - uint16_t rv = io_readw(env, mmu_idx, index, addr, retaddr); - if (big_endian) { - res = bswap16(rv); - } else { - res = rv; - } - break; - } - default: - g_assert_not_reached(); - break; - } - - return res; + tmp = io_readx(env, iotlbentry, mmu_idx, addr, retaddr, size); + return handle_bswap(tmp, size, big_endian); } /* Handle slow unaligned access (it spans two pages or IO). */ @@ -156,6 +153,20 @@ static tcg_target_ulong load_helper(CPUArchState *env, target_ulong addr, res = lduw_le_p((uint8_t *)haddr); } break; + case 4: + if (big_endian) { + res = ldl_be_p((uint8_t *)haddr); + } else { + res = ldl_le_p((uint8_t *)haddr); + } + break; + case 8: + if (big_endian) { + res = ldq_be_p((uint8_t *)haddr); + } else { + res = ldq_le_p((uint8_t *)haddr); + } + break; default: g_assert_not_reached(); break; @@ -201,6 +212,42 @@ tcg_target_ulong __attribute__((flatten)) helper_be_lduw_mmu(CPUArchState *env, return load_helper(env, addr, 2, true, false, oi, retaddr); } +tcg_target_ulong __attribute__((flatten)) helper_le_ldul_mmu(CPUArchState *env, + target_ulong addr, + TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, 4, false, false, oi, retaddr); +} + +tcg_target_ulong __attribute__((flatten)) helper_be_ldul_mmu(CPUArchState *env, + target_ulong addr, + TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, 4, true, false, oi, retaddr); +} + +tcg_target_ulong __attribute__((flatten)) helper_le_ldq_mmu(CPUArchState *env, + target_ulong addr, + TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, 8, false, false, oi, retaddr); +} + +tcg_target_ulong __attribute__((flatten)) helper_be_ldq_mmu(CPUArchState *env, + target_ulong addr, + TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, 8, true, false, oi, retaddr); +} + +/* + * Code Access + */ + uint8_t __attribute__((flatten)) helper_ret_ldb_cmmu (CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, @@ -225,6 +272,38 @@ uint16_t __attribute__((flatten)) helper_be_ldw_cmmu(CPUArchState *env, return load_helper(env, addr, 2, true, true, oi, retaddr); } +uint32_t __attribute__((flatten)) helper_le_ldl_cmmu(CPUArchState *env, + target_ulong addr, + TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, 4, false, true, oi, retaddr); +} + +uint32_t __attribute__((flatten)) helper_be_ldl_cmmu(CPUArchState *env, + target_ulong addr, + TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, 4, true, true, oi, retaddr); +} + +uint64_t __attribute__((flatten)) helper_le_ldq_cmmu(CPUArchState *env, + target_ulong addr, + TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, 8, false, true, oi, retaddr); +} + +uint64_t __attribute__((flatten)) helper_be_ldq_cmmu(CPUArchState *env, + target_ulong addr, + TCGMemOpIdx oi, + uintptr_t retaddr) +{ + return load_helper(env, addr, 8, true, true, oi, retaddr); +} + /* Provide signed versions of the load routines as well. We can of course avoid this for 64-bit data, or for 32-bit data on 32-bit host. */ @@ -249,26 +328,6 @@ tcg_target_ulong __attribute__((flatten)) helper_be_ldsw_mmu(CPUArchState *env, * Store Helpers */ -static inline void io_writeb(CPUArchState *env, - size_t mmu_idx, size_t index, - uint8_t val, - target_ulong addr, - uintptr_t retaddr) -{ - CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index]; - return io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, 1); -} - -static inline void io_writew(CPUArchState *env, - size_t mmu_idx, size_t index, - uint16_t val, - target_ulong addr, - uintptr_t retaddr) -{ - CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index]; - return io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, 2); -} - static void store_helper(CPUArchState *env, target_ulong addr, uint64_t val, size_t size, bool big_endian, TCGMemOpIdx oi, uintptr_t retaddr) @@ -296,34 +355,15 @@ static void store_helper(CPUArchState *env, target_ulong addr, uint64_t val, /* Handle an IO access. */ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { + CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index]; + if ((addr & (size - 1)) != 0) { goto do_unaligned_access; } - /* ??? Note that the io helpers always read data in the target - byte ordering. We should push the LE/BE request down into io. */ - switch (size) { - case 1: - { - uint8_t wv = (val); - io_writeb(env, mmu_idx, index, wv, addr, retaddr); - break; - } - case 2: - { - uint16_t wv; - if (big_endian) { - wv = bswap16( (uint16_t) val); - } else { - wv = (val); - } - io_writew(env, mmu_idx, index, wv, addr, retaddr); - break; - } - default: - g_assert_not_reached(); - break; - } + io_writex(env, iotlbentry, mmu_idx, + handle_bswap(val, size, big_endian), + addr, retaddr, size); return; } @@ -376,6 +416,20 @@ static void store_helper(CPUArchState *env, target_ulong addr, uint64_t val, stw_le_p((uint8_t *)haddr, val); } break; + case 4: + if (big_endian) { + stl_be_p((uint8_t *)haddr, val); + } else { + stl_le_p((uint8_t *)haddr, val); + } + break; + case 8: + if (big_endian) { + stq_be_p((uint8_t *)haddr, val); + } else { + stq_le_p((uint8_t *)haddr, val); + } + break; default: g_assert_not_reached(); break; @@ -407,3 +461,37 @@ void __attribute__((flatten)) helper_be_stw_mmu(CPUArchState *env, { store_helper(env, addr, val, 2, true, oi, retaddr); } + +void __attribute__((flatten)) helper_le_stl_mmu(CPUArchState *env, + target_ulong addr, uint32_t val, + TCGMemOpIdx oi, + uintptr_t retaddr) +{ + store_helper(env, addr, val, 4, false, oi, retaddr); +} + + +void __attribute__((flatten)) helper_be_stl_mmu(CPUArchState *env, + target_ulong addr, uint32_t val, + TCGMemOpIdx oi, + uintptr_t retaddr) +{ + store_helper(env, addr, val, 4, true, oi, retaddr); +} + +void __attribute__((flatten)) helper_le_stq_mmu(CPUArchState *env, + target_ulong addr, uint64_t val, + TCGMemOpIdx oi, + uintptr_t retaddr) +{ + store_helper(env, addr, val, 8, false, oi, retaddr); +} + + +void __attribute__((flatten)) helper_be_stq_mmu(CPUArchState *env, + target_ulong addr, uint64_t val, + TCGMemOpIdx oi, + uintptr_t retaddr) +{ + store_helper(env, addr, val, 8, true, oi, retaddr); +} diff --git a/accel/tcg/softmmu_template.h b/accel/tcg/softmmu_template.h deleted file mode 100644 index 239ea6692b..0000000000 --- a/accel/tcg/softmmu_template.h +++ /dev/null @@ -1,435 +0,0 @@ -/* - * Software MMU support - * - * Generate helpers used by TCG for qemu_ld/st ops and code load - * functions. - * - * Included from target op helpers and exec.c. - * - * Copyright (c) 2003 Fabrice Bellard - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . - */ -#if DATA_SIZE == 8 -#define SUFFIX q -#define LSUFFIX q -#define SDATA_TYPE int64_t -#define DATA_TYPE uint64_t -#elif DATA_SIZE == 4 -#define SUFFIX l -#define LSUFFIX l -#define SDATA_TYPE int32_t -#define DATA_TYPE uint32_t -#elif DATA_SIZE == 2 -#define SUFFIX w -#define LSUFFIX uw -#define SDATA_TYPE int16_t -#define DATA_TYPE uint16_t -#elif DATA_SIZE == 1 -#define SUFFIX b -#define LSUFFIX ub -#define SDATA_TYPE int8_t -#define DATA_TYPE uint8_t -#else -#error unsupported data size -#endif - - -/* For the benefit of TCG generated code, we want to avoid the complication - of ABI-specific return type promotion and always return a value extended - to the register size of the host. This is tcg_target_long, except in the - case of a 32-bit host and 64-bit data, and for that we always have - uint64_t. Don't bother with this widened value for SOFTMMU_CODE_ACCESS. */ -#if defined(SOFTMMU_CODE_ACCESS) || DATA_SIZE == 8 -# define WORD_TYPE DATA_TYPE -# define USUFFIX SUFFIX -#else -# define WORD_TYPE tcg_target_ulong -# define USUFFIX glue(u, SUFFIX) -# define SSUFFIX glue(s, SUFFIX) -#endif - -#ifdef SOFTMMU_CODE_ACCESS -#define READ_ACCESS_TYPE MMU_INST_FETCH -#define ADDR_READ addr_code -#else -#define READ_ACCESS_TYPE MMU_DATA_LOAD -#define ADDR_READ addr_read -#endif - -#if DATA_SIZE == 8 -# define BSWAP(X) bswap64(X) -#elif DATA_SIZE == 4 -# define BSWAP(X) bswap32(X) -#elif DATA_SIZE == 2 -# define BSWAP(X) bswap16(X) -#else -# define BSWAP(X) (X) -#endif - -#if DATA_SIZE == 1 -# define helper_le_ld_name glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX) -# define helper_be_ld_name helper_le_ld_name -# define helper_le_lds_name glue(glue(helper_ret_ld, SSUFFIX), MMUSUFFIX) -# define helper_be_lds_name helper_le_lds_name -# define helper_le_st_name glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX) -# define helper_be_st_name helper_le_st_name -#else -# define helper_le_ld_name glue(glue(helper_le_ld, USUFFIX), MMUSUFFIX) -# define helper_be_ld_name glue(glue(helper_be_ld, USUFFIX), MMUSUFFIX) -# define helper_le_lds_name glue(glue(helper_le_ld, SSUFFIX), MMUSUFFIX) -# define helper_be_lds_name glue(glue(helper_be_ld, SSUFFIX), MMUSUFFIX) -# define helper_le_st_name glue(glue(helper_le_st, SUFFIX), MMUSUFFIX) -# define helper_be_st_name glue(glue(helper_be_st, SUFFIX), MMUSUFFIX) -#endif - -#ifndef SOFTMMU_CODE_ACCESS -static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env, - size_t mmu_idx, size_t index, - target_ulong addr, - uintptr_t retaddr) -{ - CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index]; - return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, DATA_SIZE); -} -#endif - -WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - unsigned mmu_idx = get_mmuidx(oi); - int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ; - unsigned a_bits = get_alignment_bits(get_memop(oi)); - uintptr_t haddr; - DATA_TYPE res; - - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, - mmu_idx, retaddr); - } - - /* If the TLB entry is for a different page, reload and try again. */ - if ((addr & TARGET_PAGE_MASK) - != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { - if (!VICTIM_TLB_HIT(ADDR_READ, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE, - mmu_idx, retaddr); - } - tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ; - } - - /* Handle an IO access. */ - if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - if ((addr & (DATA_SIZE - 1)) != 0) { - goto do_unaligned_access; - } - - /* ??? Note that the io helpers always read data in the target - byte ordering. We should push the LE/BE request down into io. */ - res = glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr); - res = TGT_LE(res); - return res; - } - - /* Handle slow unaligned access (it spans two pages or IO). */ - if (DATA_SIZE > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1 - >= TARGET_PAGE_SIZE)) { - target_ulong addr1, addr2; - DATA_TYPE res1, res2; - unsigned shift; - do_unaligned_access: - addr1 = addr & ~(DATA_SIZE - 1); - addr2 = addr1 + DATA_SIZE; - res1 = helper_le_ld_name(env, addr1, oi, retaddr); - res2 = helper_le_ld_name(env, addr2, oi, retaddr); - shift = (addr & (DATA_SIZE - 1)) * 8; - - /* Little-endian combine. */ - res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift)); - return res; - } - - haddr = addr + env->tlb_table[mmu_idx][index].addend; -#if DATA_SIZE == 1 - res = glue(glue(ld, LSUFFIX), _p)((uint8_t *)haddr); -#else - res = glue(glue(ld, LSUFFIX), _le_p)((uint8_t *)haddr); -#endif - return res; -} - -#if DATA_SIZE > 1 -WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - unsigned mmu_idx = get_mmuidx(oi); - int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - target_ulong tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ; - unsigned a_bits = get_alignment_bits(get_memop(oi)); - uintptr_t haddr; - DATA_TYPE res; - - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, - mmu_idx, retaddr); - } - - /* If the TLB entry is for a different page, reload and try again. */ - if ((addr & TARGET_PAGE_MASK) - != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { - if (!VICTIM_TLB_HIT(ADDR_READ, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, READ_ACCESS_TYPE, - mmu_idx, retaddr); - } - tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ; - } - - /* Handle an IO access. */ - if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - if ((addr & (DATA_SIZE - 1)) != 0) { - goto do_unaligned_access; - } - - /* ??? Note that the io helpers always read data in the target - byte ordering. We should push the LE/BE request down into io. */ - res = glue(io_read, SUFFIX)(env, mmu_idx, index, addr, retaddr); - res = TGT_BE(res); - return res; - } - - /* Handle slow unaligned access (it spans two pages or IO). */ - if (DATA_SIZE > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1 - >= TARGET_PAGE_SIZE)) { - target_ulong addr1, addr2; - DATA_TYPE res1, res2; - unsigned shift; - do_unaligned_access: - addr1 = addr & ~(DATA_SIZE - 1); - addr2 = addr1 + DATA_SIZE; - res1 = helper_be_ld_name(env, addr1, oi, retaddr); - res2 = helper_be_ld_name(env, addr2, oi, retaddr); - shift = (addr & (DATA_SIZE - 1)) * 8; - - /* Big-endian combine. */ - res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift)); - return res; - } - - haddr = addr + env->tlb_table[mmu_idx][index].addend; - res = glue(glue(ld, LSUFFIX), _be_p)((uint8_t *)haddr); - return res; -} -#endif /* DATA_SIZE > 1 */ - -#ifndef SOFTMMU_CODE_ACCESS - -/* Provide signed versions of the load routines as well. We can of course - avoid this for 64-bit data, or for 32-bit data on 32-bit host. */ -#if DATA_SIZE * 8 < TCG_TARGET_REG_BITS -WORD_TYPE helper_le_lds_name(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - return (SDATA_TYPE)helper_le_ld_name(env, addr, oi, retaddr); -} - -# if DATA_SIZE > 1 -WORD_TYPE helper_be_lds_name(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - return (SDATA_TYPE)helper_be_ld_name(env, addr, oi, retaddr); -} -# endif -#endif - -static inline void glue(io_write, SUFFIX)(CPUArchState *env, - size_t mmu_idx, size_t index, - DATA_TYPE val, - target_ulong addr, - uintptr_t retaddr) -{ - CPUIOTLBEntry *iotlbentry = &env->iotlb[mmu_idx][index]; - return io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, DATA_SIZE); -} - -void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - unsigned mmu_idx = get_mmuidx(oi); - int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write; - unsigned a_bits = get_alignment_bits(get_memop(oi)); - uintptr_t haddr; - - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, - mmu_idx, retaddr); - } - - /* If the TLB entry is for a different page, reload and try again. */ - if ((addr & TARGET_PAGE_MASK) - != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { - if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE, - mmu_idx, retaddr); - } - tlb_addr = env->tlb_table[mmu_idx][index].addr_write & ~TLB_INVALID_MASK; - } - - /* Handle an IO access. */ - if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - if ((addr & (DATA_SIZE - 1)) != 0) { - goto do_unaligned_access; - } - - /* ??? Note that the io helpers always read data in the target - byte ordering. We should push the LE/BE request down into io. */ - val = TGT_LE(val); - glue(io_write, SUFFIX)(env, mmu_idx, index, val, addr, retaddr); - return; - } - - /* Handle slow unaligned access (it spans two pages or IO). */ - if (DATA_SIZE > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1 - >= TARGET_PAGE_SIZE)) { - int i, index2; - target_ulong page2, tlb_addr2; - do_unaligned_access: - /* Ensure the second page is in the TLB. Note that the first page - is already guaranteed to be filled, and that the second page - cannot evict the first. */ - page2 = (addr + DATA_SIZE) & TARGET_PAGE_MASK; - index2 = (page2 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - tlb_addr2 = env->tlb_table[mmu_idx][index2].addr_write; - if (page2 != (tlb_addr2 & (TARGET_PAGE_MASK | TLB_INVALID_MASK)) - && !VICTIM_TLB_HIT(addr_write, page2)) { - tlb_fill(ENV_GET_CPU(env), page2, DATA_SIZE, MMU_DATA_STORE, - mmu_idx, retaddr); - } - - /* XXX: not efficient, but simple. */ - /* This loop must go in the forward direction to avoid issues - with self-modifying code in Windows 64-bit. */ - for (i = 0; i < DATA_SIZE; ++i) { - /* Little-endian extract. */ - uint8_t val8 = val >> (i * 8); - glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8, - oi, retaddr); - } - return; - } - - haddr = addr + env->tlb_table[mmu_idx][index].addend; -#if DATA_SIZE == 1 - glue(glue(st, SUFFIX), _p)((uint8_t *)haddr, val); -#else - glue(glue(st, SUFFIX), _le_p)((uint8_t *)haddr, val); -#endif -} - -#if DATA_SIZE > 1 -void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, - TCGMemOpIdx oi, uintptr_t retaddr) -{ - unsigned mmu_idx = get_mmuidx(oi); - int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write; - unsigned a_bits = get_alignment_bits(get_memop(oi)); - uintptr_t haddr; - - if (addr & ((1 << a_bits) - 1)) { - cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, - mmu_idx, retaddr); - } - - /* If the TLB entry is for a different page, reload and try again. */ - if ((addr & TARGET_PAGE_MASK) - != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { - if (!VICTIM_TLB_HIT(addr_write, addr)) { - tlb_fill(ENV_GET_CPU(env), addr, DATA_SIZE, MMU_DATA_STORE, - mmu_idx, retaddr); - } - tlb_addr = env->tlb_table[mmu_idx][index].addr_write & ~TLB_INVALID_MASK; - } - - /* Handle an IO access. */ - if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) { - if ((addr & (DATA_SIZE - 1)) != 0) { - goto do_unaligned_access; - } - - /* ??? Note that the io helpers always read data in the target - byte ordering. We should push the LE/BE request down into io. */ - val = TGT_BE(val); - glue(io_write, SUFFIX)(env, mmu_idx, index, val, addr, retaddr); - return; - } - - /* Handle slow unaligned access (it spans two pages or IO). */ - if (DATA_SIZE > 1 - && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1 - >= TARGET_PAGE_SIZE)) { - int i, index2; - target_ulong page2, tlb_addr2; - do_unaligned_access: - /* Ensure the second page is in the TLB. Note that the first page - is already guaranteed to be filled, and that the second page - cannot evict the first. */ - page2 = (addr + DATA_SIZE) & TARGET_PAGE_MASK; - index2 = (page2 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); - tlb_addr2 = env->tlb_table[mmu_idx][index2].addr_write; - if (page2 != (tlb_addr2 & (TARGET_PAGE_MASK | TLB_INVALID_MASK)) - && !VICTIM_TLB_HIT(addr_write, page2)) { - tlb_fill(ENV_GET_CPU(env), page2, DATA_SIZE, MMU_DATA_STORE, - mmu_idx, retaddr); - } - - /* XXX: not efficient, but simple */ - /* This loop must go in the forward direction to avoid issues - with self-modifying code. */ - for (i = 0; i < DATA_SIZE; ++i) { - /* Big-endian extract. */ - uint8_t val8 = val >> (((DATA_SIZE - 1) * 8) - (i * 8)); - glue(helper_ret_stb, MMUSUFFIX)(env, addr + i, val8, - oi, retaddr); - } - return; - } - - haddr = addr + env->tlb_table[mmu_idx][index].addend; - glue(glue(st, SUFFIX), _be_p)((uint8_t *)haddr, val); -} -#endif /* DATA_SIZE > 1 */ -#endif /* !defined(SOFTMMU_CODE_ACCESS) */ - -#undef READ_ACCESS_TYPE -#undef DATA_TYPE -#undef SUFFIX -#undef LSUFFIX -#undef DATA_SIZE -#undef ADDR_READ -#undef WORD_TYPE -#undef SDATA_TYPE -#undef USUFFIX -#undef SSUFFIX -#undef BSWAP -#undef helper_le_ld_name -#undef helper_be_ld_name -#undef helper_le_lds_name -#undef helper_be_lds_name -#undef helper_le_st_name -#undef helper_be_st_name