From patchwork Wed Apr 25 16:32:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 134375 Delivered-To: patch@linaro.org Received: by 10.46.151.6 with SMTP id r6csp1086167lji; Wed, 25 Apr 2018 09:35:03 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrJVz6l/u0+rrKW2uKPEY/Zfi0Rg2iv+MCCTQAUMLT7q0zyYWli1Gucf1u9BP8WDd1qxDTW X-Received: by 2002:a17:902:526f:: with SMTP id z102-v6mr5728446plh.223.1524674103235; Wed, 25 Apr 2018 09:35:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524674103; cv=none; d=google.com; s=arc-20160816; b=JQG30NzWfn5N1+tiizoRprMyso7mxy/BHqpMylSbtOOhKhDCEYATvIoFKDOhR4xg49 b/lXZgvAL1ZRBlcTfipGXFa2rjNp2aEIujnWK1nR45tdXH/5j6xSvhjEnl+/LkuCv334 SWoAyXxiZx0YcBUpMUFhqGFV+gfIAxt4hXoygyg06N4xq41ge8vcXhnQepRDv0/bM9vd nGJPpGdQyAOZThBs7vmooOn2riTTodJ3c0Qef/73VAZfFOf7ZvjDIZxyRibq/Z+i3q0U 1JTmJWtSIcawWovSwPsuUfN7LI+HZuLv7G97wtT5MLeWhtnS9Xgw85qgh8FTcm5LxxyT N45g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=c8OVRpj5z6OzmWuKtWcM3FG0JE0giH8UWwSn5Hh8N40=; b=Ls3KcuIrdK0UyzqNOFV8uX3iMDLs8MCUzNwLjI/wy2gBbPLAjF3ejDMuUKJ1Vpwez/ QLo2M/xn+orOAdx3j7jiVwHw/oQ+QHCMbHItXRU+YdIVpu8wVRmUHOLgBdWWn6wng3hQ nLIQGYWK2WrITb8pxl9ua3+QK1pBYzJcv+UbWIKIUIxXq6bATKcKwJnq44ZLkSzJ+imh vKJtbAXrLXbKCDiqGMDYAN8CvfOckezlmcYLvMdRKTELI12+Cy0n01zDuG0R2tGlbIGl DiRBgFQA4QumbS+XZPVzOR7TkkqAv01LuCX0XloGjmJ7U2JEqOVkJhfsQuG9U+dKRwEQ e4Fg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=ZrYwsoF9; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p61-v6si12573005plb.472.2018.04.25.09.35.03; Wed, 25 Apr 2018 09:35:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=ZrYwsoF9; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755290AbeDYQfB (ORCPT + 6 others); Wed, 25 Apr 2018 12:35:01 -0400 Received: from mail-wm0-f68.google.com ([74.125.82.68]:50586 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755157AbeDYQdL (ORCPT ); Wed, 25 Apr 2018 12:33:11 -0400 Received: by mail-wm0-f68.google.com with SMTP id t11so1340027wmt.0 for ; Wed, 25 Apr 2018 09:33:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oe3iSFs6rR/cpO/i5Ge2+XFrl6fggq0RKMuv2kYb5kI=; b=ZrYwsoF9VKjTYuwXCJURtpxEpm9SSa7iZo8f8O5bTVoTTBE4e095fSKLYK0yYDjQO8 imQe3YxcB82ih0q71blL9GuMhlUTftep9C0W4+BNYW4mSgYLIbVLwhjSVdFd8U5y1/hh MPTFrDdCbvZW9dYcuNNXFodEuxx1O/lGsbkMldlvZgi6jw7GRzZoqtz2MOqwWX1JaZDQ LVSx8MpnD6utOKjKbu6DdMsf/tfMe+9CX0J1IlSu0RqMavuaJr3Zr4Y09QQtGt8S7gJU gT7GjL8Ojml6hrA87rxdF8J3pk/MTrijCuOzeh0JLTmrEX7u4d5HCUILEvk/5tJ23ZoS 2rlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oe3iSFs6rR/cpO/i5Ge2+XFrl6fggq0RKMuv2kYb5kI=; b=hkNNM7i3TP5Vi2qbBSYzz7sbfo2GnWbwz4sccdcYMDxembSnX/jGQ8oY2C213qQVcP Maf7MiY9bSvvYiw+f8zrfDW1SFMDdc3t5eav0ewFDhNUFPeFAgSmanpJKqcAPxWMlJsI CRmZ0Mahljx3Pipht375K3X4Tu3pPfxa9HJvqoQQDXPcFBiQjIR4kl7Ig1ljZ4n2NeYH sbnXcGzvO/ty14jlalhWdVLokA94Pm3U8xVj2cWD0EHCPekIAIsqKLpp72Axaoeugpa0 Nx/sn0BM0H47SvE2JTGyAPTH3ommhLgBty15lK88h5fFTIpISGWXB1pzVCv9oEvwdQnk 35rw== X-Gm-Message-State: ALQs6tDiAoeJ3DQagaBcC6TJzqn5ALOjv9R8/DCIr/HZ/uxlqZ4z5hjG OLI5PUkBAXlFmO7H2ldYQ/0MdA== X-Received: by 10.28.72.196 with SMTP id v187mr2157425wma.115.1524673990717; Wed, 25 Apr 2018 09:33:10 -0700 (PDT) Received: from boomer.baylibre.local ([2a01:e34:eeb6:4690:3146:aafc:91d9:4b96]) by smtp.googlemail.com with ESMTPSA id 44-v6sm17300548wrk.48.2018.04.25.09.33.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Apr 2018 09:33:10 -0700 (PDT) From: Jerome Brunet To: Neil Armstrong , Carlo Caione , Kevin Hilman Cc: Jerome Brunet , Michael Turquette , Stephen Boyd , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/7] clk: meson: clean-up meson clock configuration Date: Wed, 25 Apr 2018 18:32:58 +0200 Message-Id: <20180425163304.10852-2-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180425163304.10852-1-jbrunet@baylibre.com> References: <20180425163304.10852-1-jbrunet@baylibre.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Clean the dependencies in meson clock Kconfig. CLK_AMLOGIC should actually select CLK_REGMAP_MESON which it uses. Also, each platform should select CLK_AMLOGIC, so everything is properly turned on when the platform Kconfig enable each configuration flag Signed-off-by: Jerome Brunet --- drivers/clk/meson/Kconfig | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) -- 2.14.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index d5cbec522aec..87d69573e172 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -1,7 +1,7 @@ config COMMON_CLK_AMLOGIC bool - depends on OF depends on ARCH_MESON || COMPILE_TEST + select COMMON_CLK_REGMAP_MESON config COMMON_CLK_REGMAP_MESON bool @@ -9,9 +9,8 @@ config COMMON_CLK_REGMAP_MESON config COMMON_CLK_MESON8B bool - depends on COMMON_CLK_AMLOGIC + select COMMON_CLK_AMLOGIC select RESET_CONTROLLER - select COMMON_CLK_REGMAP_MESON help Support for the clock controller on AmLogic S802 (Meson8), S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you @@ -19,9 +18,8 @@ config COMMON_CLK_MESON8B config COMMON_CLK_GXBB bool - depends on COMMON_CLK_AMLOGIC + select COMMON_CLK_AMLOGIC select RESET_CONTROLLER - select COMMON_CLK_REGMAP_MESON select MFD_SYSCON help Support for the clock controller on AmLogic S905 devices, aka gxbb. @@ -29,9 +27,8 @@ config COMMON_CLK_GXBB config COMMON_CLK_AXG bool - depends on COMMON_CLK_AMLOGIC + select COMMON_CLK_AMLOGIC select RESET_CONTROLLER - select COMMON_CLK_REGMAP_MESON select MFD_SYSCON help Support for the clock controller on AmLogic A113D devices, aka axg. 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Wed, 25 Apr 2018 09:33:12 -0700 (PDT) Received: from boomer.baylibre.local ([2a01:e34:eeb6:4690:3146:aafc:91d9:4b96]) by smtp.googlemail.com with ESMTPSA id 44-v6sm17300548wrk.48.2018.04.25.09.33.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Apr 2018 09:33:11 -0700 (PDT) From: Jerome Brunet To: Neil Armstrong , Carlo Caione , Kevin Hilman Cc: Jerome Brunet , Michael Turquette , Stephen Boyd , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/7] clk: meson: add clk-phase clock driver Date: Wed, 25 Apr 2018 18:32:59 +0200 Message-Id: <20180425163304.10852-3-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180425163304.10852-1-jbrunet@baylibre.com> References: <20180425163304.10852-1-jbrunet@baylibre.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a driver based meson clk-regmap to control clock phase on amlogic SoCs Signed-off-by: Jerome Brunet --- drivers/clk/meson/Makefile | 1 + drivers/clk/meson/clk-phase.c | 63 +++++++++++++++++++++++++++++++++++++++++++ drivers/clk/meson/clkc.h | 8 ++++++ 3 files changed, 72 insertions(+) create mode 100644 drivers/clk/meson/clk-phase.c -- 2.14.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Neil Armstrong diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index ffee82e60b7a..352fb848c406 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -3,6 +3,7 @@ # obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o +obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-phase.o obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o obj-$(CONFIG_COMMON_CLK_AXG) += axg.o diff --git a/drivers/clk/meson/clk-phase.c b/drivers/clk/meson/clk-phase.c new file mode 100644 index 000000000000..96e70497ef1b --- /dev/null +++ b/drivers/clk/meson/clk-phase.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 BayLibre, SAS. + * Author: Jerome Brunet + */ + +#include +#include "clkc.h" + +#define phase_step(_width) (360 / (1 << (_width))) + +static inline struct meson_clk_phase_data * +meson_clk_phase_data(struct clk_regmap *clk) +{ + return (struct meson_clk_phase_data *)clk->data; +} + +int meson_clk_degrees_from_val(unsigned int val, unsigned int width) +{ + return phase_step(width) * val; +} +EXPORT_SYMBOL_GPL(meson_clk_degrees_from_val); + +unsigned int meson_clk_degrees_to_val(int degrees, unsigned int width) +{ + unsigned int val = DIV_ROUND_CLOSEST(degrees, phase_step(width)); + + /* + * This last calculation is here for cases when degrees is rounded + * to 360, in which case val == (1 << width). + */ + return val % (1 << width); +} +EXPORT_SYMBOL_GPL(meson_clk_degrees_to_val); + +static int meson_clk_phase_get_phase(struct clk_hw *hw) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); + unsigned int val; + + val = meson_parm_read(clk->map, &phase->ph); + + return meson_clk_degrees_from_val(val, phase->ph.width); +} + +static int meson_clk_phase_set_phase(struct clk_hw *hw, int degrees) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); + unsigned int val; + + val = meson_clk_degrees_to_val(degrees, phase->ph.width); + meson_parm_write(clk->map, &phase->ph, val); + + return 0; +} + +const struct clk_ops meson_clk_phase_ops = { + .get_phase = meson_clk_phase_get_phase, + .set_phase = meson_clk_phase_set_phase, +}; +EXPORT_SYMBOL_GPL(meson_clk_phase_ops); diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index 8fe73c4edca8..9a17d6705e0a 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -104,6 +104,13 @@ struct meson_clk_audio_div_data { u8 flags; }; +struct meson_clk_phase_data { + struct parm ph; +}; + +int meson_clk_degrees_from_val(unsigned int val, unsigned int width); +unsigned int meson_clk_degrees_to_val(int degrees, unsigned int width); + #define MESON_GATE(_name, _reg, _bit) \ struct clk_regmap _name = { \ .data = &(struct clk_regmap_gate_data){ \ @@ -127,5 +134,6 @@ extern const struct clk_ops meson_clk_mpll_ro_ops; extern const struct clk_ops meson_clk_mpll_ops; extern const struct clk_ops meson_clk_audio_divider_ro_ops; extern const struct clk_ops meson_clk_audio_divider_ops; +extern const struct clk_ops meson_clk_phase_ops; #endif /* __CLKC_H */ From patchwork Wed Apr 25 16:33:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 134371 Delivered-To: patch@linaro.org Received: by 10.46.151.6 with SMTP id r6csp1085008lji; Wed, 25 Apr 2018 09:34:01 -0700 (PDT) X-Google-Smtp-Source: AIpwx49LrD1WNh0ipeDPYoHQt9vnN4bOL6NaKCDY3qqxVPVQYjUz+i3P3FckAQyniP4MeQtlJk9V X-Received: by 10.98.223.76 with SMTP id u73mr28362931pfg.10.1524674041394; Wed, 25 Apr 2018 09:34:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524674041; cv=none; d=google.com; s=arc-20160816; b=QM1xh1KmUhJH/CUoOi8e9dS3YVqsYSM1rnRIunxxaCaQueDOeh9BK7H0JtBtZY09UK smCH5roIRK37WQGd62oiBjQPsV74qg+OkEF1+zSI5isPGcKI8lv6SQlJGCRj+dbdhzcP dUtMQc2uvYl6fBeM59VEZBjE6JUUbJbxPdWfkNMtBrSxT18iruMdtp2QNIRo8j7VnxKD NV/BOZcHjF7xBjomgXbX2Sy++MRDjx3spgCk32QIpU+oTH4HLIcQpN0YmM9jfe54FKzN 5S+8NNluIWkUixBsm4wYT+jXxzPtpD4Y4I0AcQtvbmzUAQDnyBTFS40TTmy4qXWBWrLd BUGA== ARC-Message-Signature: i=1; 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The goal of this driver is to coherently control the phase provided to the different element using the sample clock generator. This simplify the usage of the sample clock generator a lot, without comprising the ability of the SoC. Signed-off-by: Jerome Brunet --- drivers/clk/meson/Kconfig | 5 +++ drivers/clk/meson/Makefile | 1 + drivers/clk/meson/clk-triphase.c | 68 ++++++++++++++++++++++++++++++++++++++++ drivers/clk/meson/clkc-audio.h | 20 ++++++++++++ 4 files changed, 94 insertions(+) create mode 100644 drivers/clk/meson/clk-triphase.c create mode 100644 drivers/clk/meson/clkc-audio.h -- 2.14.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 87d69573e172..7f7fd6fb3809 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -3,6 +3,11 @@ config COMMON_CLK_AMLOGIC depends on ARCH_MESON || COMPILE_TEST select COMMON_CLK_REGMAP_MESON +config COMMON_CLK_AMLOGIC_AUDIO + bool + depends on ARCH_MESON || COMPILE_TEST + select COMMON_CLK_AMLOGIC + config COMMON_CLK_REGMAP_MESON bool select REGMAP diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 352fb848c406..64bb917fe1f0 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-phase.o +obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o obj-$(CONFIG_COMMON_CLK_AXG) += axg.o diff --git a/drivers/clk/meson/clk-triphase.c b/drivers/clk/meson/clk-triphase.c new file mode 100644 index 000000000000..9508c03c73c1 --- /dev/null +++ b/drivers/clk/meson/clk-triphase.c @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 BayLibre, SAS. + * Author: Jerome Brunet + */ + +#include +#include "clkc-audio.h" + +/* + * This is a special clock for the audio controller. + * The phase of mst_sclk clock output can be controlled independently + * for the outside world (ph0), the tdmout (ph1) and tdmin (ph2). + * Controlling these 3 phases as just one makes things simpler and + * give the same clock view to all the element on the i2s bus. + * If necessary, we can still control the phase in the tdm block + * which makes these independent control redundant. + */ +static inline struct meson_clk_triphase_data * +meson_clk_triphase_data(struct clk_regmap *clk) +{ + return (struct meson_clk_triphase_data *)clk->data; +} + +static void meson_clk_triphase_sync(struct clk_hw *hw) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_triphase_data *tph = meson_clk_triphase_data(clk); + unsigned int val; + + /* Get phase 0 and sync it to phase 1 and 2 */ + val = meson_parm_read(clk->map, &tph->ph0); + meson_parm_write(clk->map, &tph->ph1, val); + meson_parm_write(clk->map, &tph->ph2, val); +} + +static int meson_clk_triphase_get_phase(struct clk_hw *hw) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_triphase_data *tph = meson_clk_triphase_data(clk); + unsigned int val; + + /* Phase are in sync, reading phase 0 is enough */ + val = meson_parm_read(clk->map, &tph->ph0); + + return meson_clk_degrees_from_val(val, tph->ph0.width); +} + +static int meson_clk_triphase_set_phase(struct clk_hw *hw, int degrees) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_triphase_data *tph = meson_clk_triphase_data(clk); + unsigned int val; + + val = meson_clk_degrees_to_val(degrees, tph->ph0.width); + meson_parm_write(clk->map, &tph->ph0, val); + meson_parm_write(clk->map, &tph->ph1, val); + meson_parm_write(clk->map, &tph->ph2, val); + + return 0; +} + +const struct clk_ops meson_clk_triphase_ops = { + .init = meson_clk_triphase_sync, + .get_phase = meson_clk_triphase_get_phase, + .set_phase = meson_clk_triphase_set_phase, +}; +EXPORT_SYMBOL_GPL(meson_clk_triphase_ops); diff --git a/drivers/clk/meson/clkc-audio.h b/drivers/clk/meson/clkc-audio.h new file mode 100644 index 000000000000..286ff1201258 --- /dev/null +++ b/drivers/clk/meson/clkc-audio.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018 BayLibre, SAS. + * Author: Jerome Brunet + */ + +#ifndef __MESON_CLKC_AUDIO_H +#define __MESON_CLKC_AUDIO_H + +#include "clkc.h" + +struct meson_clk_triphase_data { + struct parm ph0; + struct parm ph1; + struct parm ph2; +}; + +extern const struct clk_ops meson_clk_triphase_ops; + +#endif /* __MESON_CLKC_AUDIO_H */ From patchwork Wed Apr 25 16:33:03 2018 Content-Type: text/plain; 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Wed, 25 Apr 2018 09:33:20 -0700 (PDT) Received: from boomer.baylibre.local ([2a01:e34:eeb6:4690:3146:aafc:91d9:4b96]) by smtp.googlemail.com with ESMTPSA id 44-v6sm17300548wrk.48.2018.04.25.09.33.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Apr 2018 09:33:19 -0700 (PDT) From: Jerome Brunet To: Neil Armstrong , Carlo Caione , Kevin Hilman Cc: Jerome Brunet , Michael Turquette , Stephen Boyd , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/7] clk: meson: axg: document bindings for the audio clock controller Date: Wed, 25 Apr 2018 18:33:03 +0200 Message-Id: <20180425163304.10852-7-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180425163304.10852-1-jbrunet@baylibre.com> References: <20180425163304.10852-1-jbrunet@baylibre.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add documentation for the device tree bindings of the audio clock controller of the A113 based SoCs Signed-off-by: Jerome Brunet --- .../bindings/clock/amlogic,axg-audio-clkc.txt | 56 ++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt -- 2.14.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt new file mode 100644 index 000000000000..1b989ceda567 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt @@ -0,0 +1,56 @@ +* Amlogic AXG Audio Clock Controllers + +The Amlogic AXG audio clock controller generates and supplies clock to the +other elements of the audio subsystem, such as fifos, i2s, spdif and pdm +devices. + +Required Properties: + +- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D +- reg : physical base address of the clock controller and length of + memory mapped region. +- clocks : a list of phandle + clock-specifier pairs for the clocks listed + in clock-names. +- clock-names : must contain the following: + * "pclk" - Main peripheral bus clock + may contain the following: + * "mst_in[0-7]" - 8 input plls to generate clock signals + * "slv_sclk[0-9]" - 10 slave bit clocks provided by external + components. + * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external + components. +- reset : phandle of the internal reset line +- #clock-cells : should be 1. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. All available clocks are defined as +preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be +used in device tree sources. + +Example: + +clkc_audio: clock-controller { + compatible = "amlogic,axg-audio-clkc"; + reg = <0x0 0x0 0x0 0xb4>; + #clock-cells = <1>; + + clocks = <&clkc CLKID_AUDIO>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL3>, + <&clkc CLKID_HIFI_PLL>, + <&clkc CLKID_FCLK_DIV3>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_GP0_PLL>; + clock-names = "pclk", + "mst_in0", + "mst_in1", + "mst_in2", + "mst_in3", + "mst_in4", + "mst_in5", + "mst_in6", + "mst_in7"; + resets = <&reset RESET_AUDIO>; +};