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[122.58.167.38]) by smtp.gmail.com with ESMTPSA id e10sm29577549pfn.67.2018.04.25.16.48.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 25 Apr 2018 16:48:57 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Thu, 26 Apr 2018 11:45:33 +1200 Message-Id: <1524699938-6764-31-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1524699938-6764-1-git-send-email-mjc@sifive.com> References: <1524699938-6764-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH v8 30/35] RISC-V: Split out mstatus_fs from tb_flags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Richard Henderson , Michael Clark , Alistair Francis , patches@groups.riscv.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Alistair Francis Cc: Richard Henderson Signed-off-by: Michael Clark --- target/riscv/cpu.h | 6 +++--- target/riscv/translate.c | 10 +++++----- 2 files changed, 8 insertions(+), 8 deletions(-) -- 2.7.0 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3fed92d..6fb0014 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -270,8 +270,8 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env, target_ulong cpu_riscv_get_fflags(CPURISCVState *env); void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong); -#define TB_FLAGS_MMU_MASK 3 -#define TB_FLAGS_FP_ENABLE MSTATUS_FS +#define TB_FLAGS_MMU_MASK 3 +#define TB_FLAGS_MSTATUS_FS MSTATUS_FS static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) @@ -279,7 +279,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, *pc = env->pc; *cs_base = 0; #ifdef CONFIG_USER_ONLY - *flags = TB_FLAGS_FP_ENABLE; + *flags = TB_FLAGS_MSTATUS_FS; #else *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS); #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index c0e6a04..4180c42 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -43,7 +43,7 @@ typedef struct DisasContext { target_ulong pc; target_ulong next_pc; uint32_t opcode; - uint32_t flags; + uint32_t mstatus_fs; uint32_t mem_idx; int singlestep_enabled; int bstate; @@ -664,7 +664,7 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, { TCGv t0; - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) { + if (ctx->mstatus_fs == 0) { gen_exception_illegal(ctx); return; } @@ -694,7 +694,7 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1, { TCGv t0; - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) { + if (ctx->mstatus_fs == 0) { gen_exception_illegal(ctx); return; } @@ -985,7 +985,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, { TCGv t0 = NULL; - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) { + if (ctx->mstatus_fs == 0) { goto do_illegal; } @@ -1863,8 +1863,8 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) ctx.tb = tb; ctx.bstate = BS_NONE; - ctx.flags = tb->flags; ctx.mem_idx = tb->flags & TB_FLAGS_MMU_MASK; + ctx.mstatus_fs = tb->flags & TB_FLAGS_MSTATUS_FS; ctx.frm = -1; /* unknown rounding mode */ num_insns = 0; From patchwork Wed Apr 25 23:45:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Clark X-Patchwork-Id: 134383 Delivered-To: patch@linaro.org Received: by 10.46.151.6 with SMTP id r6csp1512408lji; Wed, 25 Apr 2018 17:03:22 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrl1fiyZjzSdqyGk/97jgCIZHMs/2etG3X3i7MoR4gyhCoiWlA4c9sie6ofAb1A5Wg8FbRC X-Received: by 10.55.77.66 with SMTP id a63mr31123144qkb.93.1524701002565; Wed, 25 Apr 2018 17:03:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1524701002; cv=none; d=google.com; s=arc-20160816; b=uym0F6jwEIrRj3oFDu6bvJ42IW1XFS6gH8Y+ZV96q3SvHDYj/RpTd0R+YcXW51hn38 2lOKWF+jpDjLs8BLpeEJQBJNepBmGz+gBJC5UG54YBc78sW9Hn8FHyCUWsSgO2DnjIvf rQNuAd97PaC7TY63sUK2jfu28hHaSaeaIrviBE4uyHLe6Bew4x3ULpFUE6KD/BMNpASJ 6A6hl8zTzb5Cm8wnzG4xo1WidBswDtznkelwy9R4/i4ykaoJf8LV0G4PqUmvr6q72JDw T9EfhCSGDIJGJ7OZSUCD5IhDGP4Cp2gbyoZMlNYRbB/pbwbMl4HBHQLMinnjb1Zbe3AF CFLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=aI3BivjFBLG1vHiBfjWYV3Ovq/X93VcFRBeSrrOCFvY=; b=qudno5UNVqNp51klT1wYZA71l2LXbaiTPVVafta18GHv5Nbr5n3DNz5msWJ7qQa4th SffrwU9v8Ap8lcAD6nUVnsiGBLzHQ3R8AOs5pFYyGCBdF5lczN3J2Sv+lxpuNI1WCDab 2FwDcNdbh4L/CaLBGZ9AeXQGzBci2Rl/DmavZWGIyOrb5JkYurjqlGkI0w5eyyyEABn5 X9aSbdebBGXs3eyRlihWNmTb7sIPnU/xKtw4c3WsdBaF2Z3D7MMJ5jyN5rEH3ijeU9uS vxgckPqr75pqhx4OkjVg5tN/DjeOhNE27XisQG/7tdvAYwcihV5b3twZthSgtb4d/T/l xa7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@sifive.com header.s=google header.b=h3k71J1w; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[122.58.167.38]) by smtp.gmail.com with ESMTPSA id e10sm29577549pfn.67.2018.04.25.16.48.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 25 Apr 2018 16:49:01 -0700 (PDT) From: Michael Clark To: qemu-devel@nongnu.org Date: Thu, 26 Apr 2018 11:45:34 +1200 Message-Id: <1524699938-6764-32-git-send-email-mjc@sifive.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1524699938-6764-1-git-send-email-mjc@sifive.com> References: <1524699938-6764-1-git-send-email-mjc@sifive.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH v8 31/35] RISC-V: Mark mstatus.fs dirty X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Richard Henderson , Michael Clark , Alistair Francis , patches@groups.riscv.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Modifed from Richard Henderson's patch [1] to integrate with the new control and status register implementation. [1] https://lists.nongnu.org/archive/html/qemu-devel/2018-03/msg07034.html Note: the f* CSRs already mark mstatus.FS dirty using env->mstatus |= mstatus.FS so the bug in the first spin of this patch has been fixed in a prior commit. Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: Palmer Dabbelt Cc: Alistair Francis Cc: Richard Henderson Signed-off-by: Michael Clark Co-authored-by: Richard Henderson Co-authored-by: Michael Clark --- target/riscv/csr.c | 12 ------------ target/riscv/translate.c | 40 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 39 insertions(+), 13 deletions(-) -- 2.7.0 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ecf74a0..e005285 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -325,18 +325,6 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) mstatus = (mstatus & ~mask) | (val & mask); - /* Note: this is a workaround for an issue where mstatus.FS - does not report dirty after floating point operations - that modify floating point state. This workaround is - technically compliant with the RISC-V Privileged - specification as it is legal to return only off, or dirty. - at the expense of extra floating point save/restore. */ - - /* FP is always dirty or off */ - if (mstatus & MSTATUS_FS) { - mstatus |= MSTATUS_FS; - } - int dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | ((mstatus & MSTATUS_XS) == MSTATUS_XS); mstatus = set_field(mstatus, MSTATUS_SD, dirty); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 4180c42..442c8cd 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -659,6 +659,31 @@ static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2, tcg_temp_free(dat); } +#ifndef CONFIG_USER_ONLY +/* The states of mstatus_fs are: + * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty + * We will have already diagnosed disabled state, + * and need to turn initial/clean into dirty. + */ +static void mark_fs_dirty(DisasContext *ctx) +{ + TCGv tmp; + if (ctx->mstatus_fs == MSTATUS_FS) { + return; + } + /* Remember the state change for the rest of the TB. */ + ctx->mstatus_fs = MSTATUS_FS; + + tmp = tcg_temp_new(); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); + tcg_temp_free(tmp); +} +#else +static inline void mark_fs_dirty(DisasContext *ctx) { } +#endif + static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, int rs1, target_long imm) { @@ -687,6 +712,8 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, break; } tcg_temp_free(t0); + + mark_fs_dirty(ctx); } static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1, @@ -984,6 +1011,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1, int rs2, int rm) { TCGv t0 = NULL; + bool fp_output = true; if (ctx->mstatus_fs == 0) { goto do_illegal; @@ -1046,6 +1074,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } gen_set_gpr(rd, t0); tcg_temp_free(t0); + fp_output = false; break; case OPC_RISC_FCVT_W_S: @@ -1075,6 +1104,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } gen_set_gpr(rd, t0); tcg_temp_free(t0); + fp_output = false; break; case OPC_RISC_FCVT_S_W: @@ -1125,6 +1155,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } gen_set_gpr(rd, t0); tcg_temp_free(t0); + fp_output = false; break; case OPC_RISC_FMV_S_X: @@ -1217,6 +1248,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } gen_set_gpr(rd, t0); tcg_temp_free(t0); + fp_output = false; break; case OPC_RISC_FCVT_W_D: @@ -1246,6 +1278,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } gen_set_gpr(rd, t0); tcg_temp_free(t0); + fp_output = false; break; case OPC_RISC_FCVT_D_W: @@ -1293,6 +1326,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, default: goto do_illegal; } + fp_output = false; break; case OPC_RISC_FMV_D_X: @@ -1309,7 +1343,11 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, tcg_temp_free(t0); } gen_exception_illegal(ctx); - break; + return; + } + + if (fp_output) { + mark_fs_dirty(ctx); } }