From patchwork Tue May 1 08:59:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 134744 Delivered-To: patches@linaro.org Received: by 10.46.151.6 with SMTP id r6csp4727011lji; Tue, 1 May 2018 01:59:46 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrlG/pqhuYcgWoUYqTImXASor+GSh9FdrOGMs0ZvOlAPvBTz53I9BYL/wvkpyQceaqBSyOM X-Received: by 2002:a65:5088:: with SMTP id r8-v6mr7187765pgp.80.1525165186172; Tue, 01 May 2018 01:59:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525165186; cv=none; d=google.com; s=arc-20160816; b=ozWE2sxeQA6z+tt9yySmUWylOCN4c4iLzMKe1lC5BNEMExIN5rZs7GeyZ9UhF0fGa+ QiUey5N/J9++6VwyCki3YYe9MeTIkCfGreyF3y8GXVS8duln03tbXKr3lbRd5jARao82 HsWZv+ilYBzrCUmcK0rFlkO9V8awKavkCi6ESn0aOcHIzmh0bwjJzpMagHCWcYozYeba 2B9XJWjE9a/8CHnGXDWb89jsH7uXNeSjeLLbUBoa8M5q8VwfNabjI+juOm4OEqo9Lut0 +L2xTM0CyWGBMC0Yjm6IJUz0YwkNxFz6rfskVLq42kiW9eh3V+YvtALoi/qrycALHFKs s2DA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=FDmGTJyJ53+VLbqnVf/0PZihcU8CZKKDROugiG+bFvE=; b=jBdCdzioXxZNxLcDI9kd+gEa8dn1aQaNzwEpHRcixmMpEehlDGjnf5udZy34thpIRu 0EmR0/EDoLHHgrj4IThrsWeXnUYjXQK5uYcM7VRbeQilGRWAaWLh2aazMwKJPdUHFcRz FXvxJ1JRnLUHxEdrlRN6mlesKD/HgHiNbfGqWuS15luY+BPLibImnFwsb6skYUgf/V/U PiyFugVYQONTZDnEgik+B/sAqqeQYEGWlKV73vBeMOYpaDzmYBIF4xxbyFzVwpIVl0Il YU9KkRNzzE7NxTrWiHDd0sF2QV8qG/GfLWStgk1X8F+XyFUcU237I9LUf0/aNlJeMSL6 kJIQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id s1-v6si7606562pgb.281.2018.05.01.01.59.45 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 01 May 2018 01:59:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fDR8P-0007Ll-9E; Tue, 01 May 2018 09:59:41 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paolo Bonzini , Eric Auger Subject: [RFC PATCH v2 01/12] Make tb_invalidate_phys_addr() take a MemTxAttrs argument Date: Tue, 1 May 2018 09:59:28 +0100 Message-Id: <20180501085939.6201-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180501085939.6201-1-peter.maydell@linaro.org> References: <20180501085939.6201-1-peter.maydell@linaro.org> As part of plumbing MemTxAttrs down to the IOMMU translate method, add MemTxAttrs as an argument to tb_invalidate_phys_addr(). Its callers either have an attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED. Signed-off-by: Peter Maydell --- include/exec/exec-all.h | 5 +++-- accel/tcg/translate-all.c | 2 +- exec.c | 2 +- target/xtensa/op_helper.c | 3 ++- 4 files changed, 7 insertions(+), 5 deletions(-) -- 2.17.0 diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index bd68328ed9..4d09eaba72 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -255,7 +255,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, void tlb_set_page(CPUState *cpu, target_ulong vaddr, hwaddr paddr, int prot, int mmu_idx, target_ulong size); -void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr); +void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs); void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx, uintptr_t retaddr); #else @@ -303,7 +303,8 @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap) { } -static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr) +static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, + MemTxAttrs attrs) { } #endif diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index f409d42d54..f04a922ef7 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1672,7 +1672,7 @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr) } #if !defined(CONFIG_USER_ONLY) -void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr) +void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs) { ram_addr_t ram_addr; MemoryRegion *mr; diff --git a/exec.c b/exec.c index c7fcefa851..df35e6dd85 100644 --- a/exec.c +++ b/exec.c @@ -863,7 +863,7 @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) if (phys != -1) { /* Locks grabbed by tb_invalidate_phys_addr */ tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as, - phys | (pc & ~TARGET_PAGE_MASK)); + phys | (pc & ~TARGET_PAGE_MASK), attrs); } } #endif diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index e3bcbe10d6..8a8c763c63 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -105,7 +105,8 @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr) int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0, &paddr, &page_size, &access); if (ret == 0) { - tb_invalidate_phys_addr(&address_space_memory, paddr); + tb_invalidate_phys_addr(&address_space_memory, paddr, + MEMTXATTRS_UNSPECIFIED); } } From patchwork Tue May 1 08:59:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 134738 Delivered-To: patches@linaro.org Received: by 10.46.151.6 with SMTP id r6csp4726971lji; Tue, 1 May 2018 01:59:43 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqsHxwcDYMB4p/gTPo0yuHLrzlU+aLtQ0JJGrXe6SUrjpigpOBOT0qxQdnW4iH7HV7phCuE X-Received: by 2002:a2e:4949:: with SMTP id b9-v6mr5557114ljd.116.1525165183071; Tue, 01 May 2018 01:59:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525165183; cv=none; d=google.com; s=arc-20160816; b=c2KQpiyAUch7WorM3fE7cdxWFy2tcOIlNMGoaRVXhXRS1ottJlE1FjKYfJ5vwsOdJF Sy2C8fDTZrRWbUI9TXiqCHB3o153XcI9eoxVGY35jPdq0RuKhs9sl0eMNae/d8w8dPkc Bwv6Z3NyC9dvKcv9CeZDSOv/SLnbgP2kievqUtlF7MsOlXMEy5hp6aAW4TQOVdnO6fZL M8bVqqwPEAk5SESeBrlsxu8/z3HuTZirUiQpVpTHxbTgxKYOs7TciKL65M6trGrPM9YW tHEm4LuFFCqnih547czLXdJE+BsF06ylRapNrtjgRXXjtuyQ3xz3gwTUfvenaYVP5hmn xjag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=VrXHnW+B58dz5RNxtyiM91IG8FQd6DwEUbe8GGrEJgA=; b=LuR/bppl58l5xHxhphMh4ExpXIvXMRDfscqiGHyN113UANvzrmq9rNp8P0YF1pX7Vd /d9xKQ2/OTIZeQmdO3A5sA95oDU30R8pMgcJGWDtnzTvJjDVOKEd1Z/k/Z+x7hMXfNsh 04uNa1X1EPh5QV/GnR81IlSOolNuHzhOpPc3KfEJ1LXmYJ69vCdfDOxIV0vvou+/ILDp jWV0ZTljl+o6gCDwI4zUEE7gYISVTNRUrzbm1JnBfJF+tlwHRUIjGDsDbNGkj4Y738Gl vY6/guDjo+1DzFGA9waeLMMumUUJNmR6ifeJeOB7ODXixneko2POncYTq3zKmJvRyW3k Ry0g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id t6-v6si1400096lfe.79.2018.05.01.01.59.42 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 01 May 2018 01:59:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fDR8P-0007M3-VR; Tue, 01 May 2018 09:59:41 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paolo Bonzini , Eric Auger Subject: [RFC PATCH v2 02/12] Make address_space_translate() take a MemTxAttrs argument Date: Tue, 1 May 2018 09:59:29 +0100 Message-Id: <20180501085939.6201-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180501085939.6201-1-peter.maydell@linaro.org> References: <20180501085939.6201-1-peter.maydell@linaro.org> As part of plumbing MemTxAttrs down to the IOMMU translate method, add MemTxAttrs as an argument to address_space_translate(). Its callers either have an attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED. Signed-off-by: Peter Maydell --- include/exec/memory.h | 4 +++- accel/tcg/translate-all.c | 2 +- exec.c | 6 ++++-- hw/vfio/common.c | 3 ++- memory_ldst.inc.c | 18 +++++++++--------- target/riscv/helper.c | 2 +- 6 files changed, 20 insertions(+), 15 deletions(-) -- 2.17.0 diff --git a/include/exec/memory.h b/include/exec/memory.h index e62965a0c8..f416d1e985 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -1909,6 +1909,7 @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr, * #MemoryRegion. * @len: pointer to length * @is_write: indicates the transfer direction + * @attrs: memory attributes */ MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat, @@ -1916,7 +1917,8 @@ MemoryRegion *flatview_translate(FlatView *fv, static inline MemoryRegion *address_space_translate(AddressSpace *as, hwaddr addr, hwaddr *xlat, - hwaddr *len, bool is_write) + hwaddr *len, bool is_write, + MemTxAttrs attrs) { return flatview_translate(address_space_to_flatview(as), addr, xlat, len, is_write); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index f04a922ef7..52f7bd59a9 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1679,7 +1679,7 @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs) hwaddr l = 1; rcu_read_lock(); - mr = address_space_translate(as, addr, &addr, &l, false); + mr = address_space_translate(as, addr, &addr, &l, false, attrs); if (!(memory_region_is_ram(mr) || memory_region_is_romd(mr))) { rcu_read_unlock(); diff --git a/exec.c b/exec.c index df35e6dd85..a0f27b7b8c 100644 --- a/exec.c +++ b/exec.c @@ -3287,7 +3287,8 @@ static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as, rcu_read_lock(); while (len > 0) { l = len; - mr = address_space_translate(as, addr, &addr1, &l, true); + mr = address_space_translate(as, addr, &addr1, &l, true, + MEMTXATTRS_UNSPECIFIED); if (!(memory_region_is_ram(mr) || memory_region_is_romd(mr))) { @@ -3716,7 +3717,8 @@ bool cpu_physical_memory_is_io(hwaddr phys_addr) rcu_read_lock(); mr = address_space_translate(&address_space_memory, - phys_addr, &phys_addr, &l, false); + phys_addr, &phys_addr, &l, false, + MEMTXATTRS_UNSPECIFIED); res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr)); rcu_read_unlock(); diff --git a/hw/vfio/common.c b/hw/vfio/common.c index 07ffa0ba10..8e57265edf 100644 --- a/hw/vfio/common.c +++ b/hw/vfio/common.c @@ -324,7 +324,8 @@ static bool vfio_get_vaddr(IOMMUTLBEntry *iotlb, void **vaddr, */ mr = address_space_translate(&address_space_memory, iotlb->translated_addr, - &xlat, &len, writable); + &xlat, &len, writable, + MEMTXATTRS_UNSPECIFIED); if (!memory_region_is_ram(mr)) { error_report("iommu map to non memory area %"HWADDR_PRIx"", xlat); diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c index 5dbff9cef8..860ba31ac8 100644 --- a/memory_ldst.inc.c +++ b/memory_ldst.inc.c @@ -33,7 +33,7 @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL, bool release_lock = false; RCU_READ_LOCK(); - mr = TRANSLATE(addr, &addr1, &l, false); + mr = TRANSLATE(addr, &addr1, &l, false, attrs); if (l < 4 || !IS_DIRECT(mr, false)) { release_lock |= prepare_mmio_access(mr); @@ -127,7 +127,7 @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL, bool release_lock = false; RCU_READ_LOCK(); - mr = TRANSLATE(addr, &addr1, &l, false); + mr = TRANSLATE(addr, &addr1, &l, false, attrs); if (l < 8 || !IS_DIRECT(mr, false)) { release_lock |= prepare_mmio_access(mr); @@ -219,7 +219,7 @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL, bool release_lock = false; RCU_READ_LOCK(); - mr = TRANSLATE(addr, &addr1, &l, false); + mr = TRANSLATE(addr, &addr1, &l, false, attrs); if (!IS_DIRECT(mr, false)) { release_lock |= prepare_mmio_access(mr); @@ -261,7 +261,7 @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL, bool release_lock = false; RCU_READ_LOCK(); - mr = TRANSLATE(addr, &addr1, &l, false); + mr = TRANSLATE(addr, &addr1, &l, false, attrs); if (l < 2 || !IS_DIRECT(mr, false)) { release_lock |= prepare_mmio_access(mr); @@ -356,7 +356,7 @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL, bool release_lock = false; RCU_READ_LOCK(); - mr = TRANSLATE(addr, &addr1, &l, true); + mr = TRANSLATE(addr, &addr1, &l, true, attrs); if (l < 4 || !IS_DIRECT(mr, true)) { release_lock |= prepare_mmio_access(mr); @@ -399,7 +399,7 @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL, bool release_lock = false; RCU_READ_LOCK(); - mr = TRANSLATE(addr, &addr1, &l, true); + mr = TRANSLATE(addr, &addr1, &l, true, attrs); if (l < 4 || !IS_DIRECT(mr, true)) { release_lock |= prepare_mmio_access(mr); @@ -489,7 +489,7 @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL, bool release_lock = false; RCU_READ_LOCK(); - mr = TRANSLATE(addr, &addr1, &l, true); + mr = TRANSLATE(addr, &addr1, &l, true, attrs); if (!IS_DIRECT(mr, true)) { release_lock |= prepare_mmio_access(mr); r = memory_region_dispatch_write(mr, addr1, val, 1, attrs); @@ -528,7 +528,7 @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL, bool release_lock = false; RCU_READ_LOCK(); - mr = TRANSLATE(addr, &addr1, &l, true); + mr = TRANSLATE(addr, &addr1, &l, true, attrs); if (l < 2 || !IS_DIRECT(mr, true)) { release_lock |= prepare_mmio_access(mr); @@ -619,7 +619,7 @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL, bool release_lock = false; RCU_READ_LOCK(); - mr = TRANSLATE(addr, &addr1, &l, true); + mr = TRANSLATE(addr, &addr1, &l, true, attrs); if (l < 8 || !IS_DIRECT(mr, true)) { release_lock |= prepare_mmio_access(mr); diff --git a/target/riscv/helper.c b/target/riscv/helper.c index 02cbcea2b7..d7023ad78e 100644 --- a/target/riscv/helper.c +++ b/target/riscv/helper.c @@ -210,7 +210,7 @@ restart: MemoryRegion *mr; hwaddr l = sizeof(target_ulong), addr1; mr = address_space_translate(cs->as, pte_addr, - &addr1, &l, false); + &addr1, &l, false, MEMTXATTRS_UNSPECIFIED); if (memory_access_is_direct(mr, true)) { target_ulong *pte_pa = qemu_map_ram_ptr(mr->ram_block, addr1); From patchwork Tue May 1 08:59:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 134739 Delivered-To: patches@linaro.org Received: by 10.46.151.6 with SMTP id r6csp4726973lji; Tue, 1 May 2018 01:59:43 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrDq1uQXanpYoztrBuGQuZwV8cPFkwIs/JSlszp1+j3reYOd7SjIEc0b2DL0NcLCFxsFQKt X-Received: by 2002:adf:df02:: with SMTP id y2-v6mr11739454wrl.92.1525165183202; Tue, 01 May 2018 01:59:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525165183; cv=none; d=google.com; s=arc-20160816; b=pYPQwbF/0NntLxglYonAPuJXX/oG//x+Qp+juFM5Phy44WQIoX/Z6OzwcvYkvrXdMz om/ONi8QndpZI58H9jplk5pyJgrkPMwtmUDk5baDW8ODaAgOpGeSu5s6GD7Adhjb59h8 C3SIA48DN7T5S1QFDQaW1wuk5VIpcyfR/ZcBnoBQLhly8fVWwaK/9WdYeZP7tUr/bcOH 1+81H+prqINhRxaXNpPDX4kzARkTPfGy1lneH+IM9HwC4VTM1rvc8rxZEgMCLMcRumUF 6yK12uqksfVK74gNHWoYdn91llfYmUXwT1CN49JcTzQ1K+0P/3WDjH0UKM65klQxzLb9 AFgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=7rt1kA8zfjNs6NW67yzsnbZLUHEZuF3yPBvLAUFo5W0=; b=Hfy0UOXnMO0EXR6cvz9cdwh6tky2ejQzCpvqHSq1Wg99CJ55VnRfPNqvGuzF2/FCO2 CPJJY6TqmhuSBih+FLJRh3p/+1vfNe535vRC2mxfxWalF1ciCF9mbmBVxHyIBQ6Y93rX EiEpbhFZ7HkN6RlulCLMynHZzktt0yVdqdY7L2PcxP6VXQ76AX2RJM1uf4tUQoX3aNqe mOJgPmFhmuCpqijG92AeWbqv+Qpb8o5pypKk4Lpcaz0UD9elq9Ii4nyI/AFhdzsBQSRk VRiz56dWoNwmh+qKFwomkfWB1d/LyNbqEUqp2YIm9wrp62RncUiTjNi+Doeko3qTTgqA EW/g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id f54-v6si7418710wrf.60.2018.05.01.01.59.43 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 01 May 2018 01:59:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fDR8Q-0007MK-M4; Tue, 01 May 2018 09:59:42 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paolo Bonzini , Eric Auger Subject: [RFC PATCH v2 03/12] Make address_space_map() take a MemTxAttrs argument Date: Tue, 1 May 2018 09:59:30 +0100 Message-Id: <20180501085939.6201-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180501085939.6201-1-peter.maydell@linaro.org> References: <20180501085939.6201-1-peter.maydell@linaro.org> As part of plumbing MemTxAttrs down to the IOMMU translate method, add MemTxAttrs as an argument to address_space_map(). Its callers either have an attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED. Signed-off-by: Peter Maydell --- include/exec/memory.h | 3 ++- include/sysemu/dma.h | 3 ++- exec.c | 6 ++++-- target/ppc/mmu-hash64.c | 3 ++- 4 files changed, 10 insertions(+), 5 deletions(-) -- 2.17.0 diff --git a/include/exec/memory.h b/include/exec/memory.h index f416d1e985..1af4e3cd5b 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -1953,9 +1953,10 @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_ * @addr: address within that address space * @plen: pointer to length of buffer; updated on return * @is_write: indicates the transfer direction + * @attrs: memory attributes */ void *address_space_map(AddressSpace *as, hwaddr addr, - hwaddr *plen, bool is_write); + hwaddr *plen, bool is_write, MemTxAttrs attrs); /* address_space_unmap: Unmaps a memory region previously mapped by address_space_map() * diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h index c228c66513..0d73902634 100644 --- a/include/sysemu/dma.h +++ b/include/sysemu/dma.h @@ -132,7 +132,8 @@ static inline void *dma_memory_map(AddressSpace *as, hwaddr xlen = *len; void *p; - p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE); + p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE, + MEMTXATTRS_UNSPECIFIED); *len = xlen; return p; } diff --git a/exec.c b/exec.c index a0f27b7b8c..eb6471abfe 100644 --- a/exec.c +++ b/exec.c @@ -3494,7 +3494,8 @@ flatview_extend_translation(FlatView *fv, hwaddr addr, void *address_space_map(AddressSpace *as, hwaddr addr, hwaddr *plen, - bool is_write) + bool is_write, + MemTxAttrs attrs) { hwaddr len = *plen; hwaddr l, xlat; @@ -3581,7 +3582,8 @@ void *cpu_physical_memory_map(hwaddr addr, hwaddr *plen, int is_write) { - return address_space_map(&address_space_memory, addr, plen, is_write); + return address_space_map(&address_space_memory, addr, plen, is_write, + MEMTXATTRS_UNSPECIFIED); } void cpu_physical_memory_unmap(void *buffer, hwaddr len, diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 7e0adecfd9..4839dc22f0 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -431,7 +431,8 @@ const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu, return NULL; } - hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false); + hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false, + MEMTXATTRS_UNSPECIFIED); if (plen < (n * HASH_PTE_SIZE_64)) { hw_error("%s: Unable to map all requested HPTEs\n", __func__); } From patchwork Tue May 1 08:59:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 134740 Delivered-To: patches@linaro.org Received: by 10.46.151.6 with SMTP id r6csp4726988lji; Tue, 1 May 2018 01:59:44 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpy4V7jHfETX8Wc2apTdfDhXy8lv9wpqk9Hbp0EhoYpVPIDRLJx+YHBeaiE0Ju16FqQy/1u X-Received: by 2002:adf:a925:: with SMTP id u34-v6mr12282603wrc.248.1525165183960; Tue, 01 May 2018 01:59:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525165183; cv=none; d=google.com; s=arc-20160816; b=TrX7UXrMh48lUGrIjU6MGrSwk7hwMqJliT/SO0zq2AIz4C/FzGaG7YhxwFILV0coue O8QoQlHn1JLxgG8RoCLE2TpzADflOyA2ip81STvwDm5YmcSC3Uwms7DnpZ8258rcl/5I 6OKPlcBN7htrd76G+rHCHHXtJ17O3eoHcDtH/A4aRMY40Efq18ITxdinmol9FHPsEE5R PjmcN76ly/gNhXFLKzpM3XW730nn+jQ03eZHIPF45WLsM1f3M6cFZr6LCzcGB9LTJRSe kTFo5AWrudFSltxArZ4jKFYkV7LUZt6MiXyykTvsGp0dOEbiQzpeMiqucSz/Y9a5XrRA 3mJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=UeZPkjdD16azuUGTRiQQEzGOX/XB9yhOSpriy/STCD0=; b=Q7tfZEwoKsni+SX3zBq2EKr2OwmQ8PksDZdsqykO6/pRp+sFdu7tAqqlKE1IxMHr1M Hix4KWgoQ6bXvEdSUZjNXemX/MUHLBFM4239U1jD8zFQuaVOjqDiS4JMJt8Fogi1Hxf9 02ZMDYz8064249yTO/NMqUFrREYD4dJBk/i+VLC3ZOSi7+tdyd7tJAYtXpFQIfDZ/adF YEYhmwNAW9txxFfLs2H7nQ/r6R88d+Xbi+4oPq9tXttNunHcfd3SnC8No6A7gcOT1ULY wgO9kR1cawTo6+GVBKnYEBlwZ3Sb1vb5eGYaiuOENrLAAOm0MRb0LfitzYEQtYXGNfBb bWiQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id v195si6728417wmd.60.2018.05.01.01.59.43 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 01 May 2018 01:59:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fDR8R-0007Ma-EM; Tue, 01 May 2018 09:59:43 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paolo Bonzini , Eric Auger Subject: [RFC PATCH v2 04/12] Make address_space_access_valid() take a MemTxAttrs argument Date: Tue, 1 May 2018 09:59:31 +0100 Message-Id: <20180501085939.6201-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180501085939.6201-1-peter.maydell@linaro.org> References: <20180501085939.6201-1-peter.maydell@linaro.org> As part of plumbing MemTxAttrs down to the IOMMU translate method, add MemTxAttrs as an argument to address_space_access_valid(). Its callers either have an attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED. Signed-off-by: Peter Maydell --- include/exec/memory.h | 4 +++- include/sysemu/dma.h | 3 ++- exec.c | 3 ++- target/s390x/diag.c | 6 ++++-- target/s390x/excp_helper.c | 3 ++- target/s390x/mmu_helper.c | 3 ++- target/s390x/sigp.c | 3 ++- 7 files changed, 17 insertions(+), 8 deletions(-) -- 2.17.0 diff --git a/include/exec/memory.h b/include/exec/memory.h index 1af4e3cd5b..eb1ceace27 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -1938,8 +1938,10 @@ static inline MemoryRegion *address_space_translate(AddressSpace *as, * @addr: address within that address space * @len: length of the area to be checked * @is_write: indicates the transfer direction + * @attrs: memory attributes */ -bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write); +bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, + bool is_write, MemTxAttrs attrs); /* address_space_map: map a physical memory region into a host virtual address * diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h index 0d73902634..5da3c4e3c5 100644 --- a/include/sysemu/dma.h +++ b/include/sysemu/dma.h @@ -77,7 +77,8 @@ static inline bool dma_memory_valid(AddressSpace *as, DMADirection dir) { return address_space_access_valid(as, addr, len, - dir == DMA_DIRECTION_FROM_DEVICE); + dir == DMA_DIRECTION_FROM_DEVICE, + MEMTXATTRS_UNSPECIFIED); } static inline int dma_memory_rw_relaxed(AddressSpace *as, dma_addr_t addr, diff --git a/exec.c b/exec.c index eb6471abfe..87650dc7ed 100644 --- a/exec.c +++ b/exec.c @@ -3445,7 +3445,8 @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len, } bool address_space_access_valid(AddressSpace *as, hwaddr addr, - int len, bool is_write) + int len, bool is_write, + MemTxAttrs attrs) { FlatView *fv; bool result; diff --git a/target/s390x/diag.c b/target/s390x/diag.c index a755837ad5..6ab473e7b6 100644 --- a/target/s390x/diag.c +++ b/target/s390x/diag.c @@ -140,7 +140,8 @@ void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra) return; } if (!address_space_access_valid(&address_space_memory, addr, - sizeof(IplParameterBlock), false)) { + sizeof(IplParameterBlock), false, + MEMTXATTRS_UNSPECIFIED)) { s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra); return; } @@ -169,7 +170,8 @@ out: return; } if (!address_space_access_valid(&address_space_memory, addr, - sizeof(IplParameterBlock), true)) { + sizeof(IplParameterBlock), true, + MEMTXATTRS_UNSPECIFIED)) { s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra); return; } diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index dfee221111..f0ce60cff2 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -120,7 +120,8 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, int size, /* check out of RAM access */ if (!address_space_access_valid(&address_space_memory, raddr, - TARGET_PAGE_SIZE, rw)) { + TARGET_PAGE_SIZE, rw, + MEMTXATTRS_UNSPECIFIED)) { DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__, (uint64_t)raddr, (uint64_t)ram_size); trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_AUTO); diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index a25deef5dd..145b62a7ef 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -461,7 +461,8 @@ static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages, return ret; } if (!address_space_access_valid(&address_space_memory, pages[i], - TARGET_PAGE_SIZE, is_write)) { + TARGET_PAGE_SIZE, is_write, + MEMTXATTRS_UNSPECIFIED)) { trigger_access_exception(env, PGM_ADDRESSING, ILEN_AUTO, 0); return -EFAULT; } diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c index aff1530c82..c1f9245797 100644 --- a/target/s390x/sigp.c +++ b/target/s390x/sigp.c @@ -280,7 +280,8 @@ static void sigp_set_prefix(CPUState *cs, run_on_cpu_data arg) cpu_synchronize_state(cs); if (!address_space_access_valid(&address_space_memory, addr, - sizeof(struct LowCore), false)) { + sizeof(struct LowCore), false, + MEMTXATTRS_UNSPECIFIED)) { set_sigp_status(si, SIGP_STAT_INVALID_PARAMETER); return; } From patchwork Tue May 1 08:59:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 134741 Delivered-To: patches@linaro.org Received: by 10.46.151.6 with SMTP id r6csp4726994lji; Tue, 1 May 2018 01:59:44 -0700 (PDT) X-Google-Smtp-Source: AB8JxZr7uS3xWNzjrsB/fWMQBLsxqVJTxutSxFBZVxc6IPck+RiLTNyR96J67zsXEkEKyNdggAxR X-Received: by 10.28.125.74 with SMTP id y71mr8966564wmc.89.1525165184631; Tue, 01 May 2018 01:59:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525165184; cv=none; d=google.com; s=arc-20160816; b=E0xLEGr2hEX5Nbgn8lv4VqxTkOps7VbOJY1mhBOgWjsIxe03QKqLHlDaraoeeg27yc oeYzzCacGFJtLG3xQk2RWa2E5zrnCzK8Eq5g/gGSlDyx9XVlm+4qPiEaVBFcu5yWkrCV nOM9W1SaVYds+AM9dNRGhxlfSgoqpQiBpmA0MOmk+NulMloyv6SOcMYus0THnorRhHnR FLUj+aPePVJh/PpUGmYT2ZKoSNq2UKPWMz3cG7x+D38rjB+ZyMkQe+JrCvXy9zdr3WLs hd/UTwgvDzXTQ308Oilvc5AGcBC3OglezH4bzF3wvLYWjoEJqk+Zi43R0y1v/8NKFYv5 awbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=3TeXuL6VqfVGwfaUblOMO5MSA1zDllE393cEcp06tk8=; b=uQOqAfJUYQGtNX8bW2tRko66U2PcN/yShErlvd8Jg5G0EDugZI4TTtifWfwFQGA7hS u9U7LHiFwpc8HkwO4LVhejs0D9iscFHtDvTlAUy46QrQeWFpnNCmjtvAdg1vuvYz0EGu gqFNZ6nng/2ufpWY2QUA80t+CnG6wiKHeI38Ridr6bP7BYdrkMdJ5a03g2FBLckKlEF3 IKL3iwCc9bHSFcNewg1RexTTGjiQrtU6dINLXmbLHgvTrt9oAfB7Vpt3N5n/cMq478LM EftI2XMHLq//CwIqyWYHrJ2LADkGvdlJSgZQ8oyEC2DtBjdjRsQQxaKTBvjmGdmawrGO rVOw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id a204si6790040wmf.129.2018.05.01.01.59.44 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 01 May 2018 01:59:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fDR8S-0007N9-68; Tue, 01 May 2018 09:59:44 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paolo Bonzini , Eric Auger Subject: [RFC PATCH v2 05/12] Make flatview_extend_translation() take a MemTxAttrs argument Date: Tue, 1 May 2018 09:59:32 +0100 Message-Id: <20180501085939.6201-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180501085939.6201-1-peter.maydell@linaro.org> References: <20180501085939.6201-1-peter.maydell@linaro.org> As part of plumbing MemTxAttrs down to the IOMMU translate method, add MemTxAttrs as an argument to flatview_extend_translation(). Its callers either have an attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED. Signed-off-by: Peter Maydell --- exec.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.17.0 diff --git a/exec.c b/exec.c index 87650dc7ed..e56c3442c7 100644 --- a/exec.c +++ b/exec.c @@ -3460,9 +3460,9 @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr, static hwaddr flatview_extend_translation(FlatView *fv, hwaddr addr, - hwaddr target_len, - MemoryRegion *mr, hwaddr base, hwaddr len, - bool is_write) + hwaddr target_len, + MemoryRegion *mr, hwaddr base, hwaddr len, + bool is_write, MemTxAttrs attrs) { hwaddr done = 0; hwaddr xlat; @@ -3539,7 +3539,7 @@ void *address_space_map(AddressSpace *as, memory_region_ref(mr); *plen = flatview_extend_translation(fv, addr, len, mr, xlat, - l, is_write); + l, is_write, attrs); ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true); rcu_read_unlock(); From patchwork Tue May 1 08:59:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 134742 Delivered-To: patches@linaro.org Received: by 10.46.151.6 with SMTP id r6csp4727002lji; Tue, 1 May 2018 01:59:45 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqO0J6nFYitEanwONdZC1ULjyNQlvCZGWkRrfwGI+HTKABGwoGfERrwiDT7tyhRR5fP/Z6S X-Received: by 2002:adf:8b85:: with SMTP id o5-v6mr4434587wra.169.1525165185352; Tue, 01 May 2018 01:59:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525165185; cv=none; d=google.com; s=arc-20160816; b=Tz67LVm3x7oWymW2guS8liOrjaCxraUigdPN4bNnmvm13w+m8P+98h2Q7wVc1hvCFJ SLfRYqPwOaOMb0u78zJQV3lPMxf3XugSWn68X20aQnCF9JqjkVrJN/WtvXj3mIGIT5vW 8X+9kXHGjmw/KFyr4FSH3L98F36R62fd4E/PnQtX4TLyF3H1u3yLxLZ2yssxxxO+Tgo7 ZBRo0ByNGmXaeTHKiMkijty+AmkZ2r3OC9mOerPx7d4uPVhVXmAx6G9Lj+fnDGCMDU+Z e7cVWRjsg0LJr5OiW8hJBRVISihRqxvueuFKZB3WkncGsoRaFTdZLEzgSo7OW30rf5Sh C9nQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=B4DnJpvUy0lpH3tDnV3xA0zOh3ZzpfM57+/CpKbf9M8=; b=gM0hzESgmUIbELonX31ymGIY7mCwYpLc/DK2XEPZ67AatIZSW0MMlXjFw7n36xQ6Ba /hMIuQnUuXhw4l3NVINYtO7kaSnBANj638RLyV6XFdrzrBXar+EUb+La6EbjUx2h92Al +oYEg5I1rfjaTBVaa+2OE9ERArwlz5LkGpT2tifPE3hE6woK8dVPngLLyhxtSkzrWbYi 7W/AgIB7dG6CtRKY03IrbiBZy2tvmZMlBuzWWcg9CRkG8bQzGk88q7OzEYBZFqpIqlJq dIv/XtPfGGU50Jsa7LXaCNLOlz8CcIqQP5/Ayn41h/lor588l4tyd0hW1sjafUHEBvyw Qk7w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 62-v6si703138wrr.454.2018.05.01.01.59.45 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 01 May 2018 01:59:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fDR8S-0007Nf-Sf; Tue, 01 May 2018 09:59:44 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paolo Bonzini , Eric Auger Subject: [RFC PATCH v2 06/12] Make memory_region_access_valid() take a MemTxAttrs argument Date: Tue, 1 May 2018 09:59:33 +0100 Message-Id: <20180501085939.6201-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180501085939.6201-1-peter.maydell@linaro.org> References: <20180501085939.6201-1-peter.maydell@linaro.org> As part of plumbing MemTxAttrs down to the IOMMU translate method, add MemTxAttrs as an argument to memory_region_access_valid(). Its callers either have an attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED. The callsite in flatview_access_valid() is part of a recursive loop flatview_access_valid() -> memory_region_access_valid() -> subpage_accepts() -> flatview_access_valid(); we make it pass MEMTXATTRS_UNSPECIFIED for now, until the next several commits have plumbed an attrs parameter through the rest of the loop and we can add an attrs parameter to flatview_access_valid(). Signed-off-by: Peter Maydell --- include/exec/memory-internal.h | 3 ++- exec.c | 4 +++- hw/s390x/s390-pci-inst.c | 3 ++- memory.c | 7 ++++--- 4 files changed, 11 insertions(+), 6 deletions(-) -- 2.17.0 diff --git a/include/exec/memory-internal.h b/include/exec/memory-internal.h index 6a5ee42d36..063dca0475 100644 --- a/include/exec/memory-internal.h +++ b/include/exec/memory-internal.h @@ -34,7 +34,8 @@ static inline AddressSpaceDispatch *address_space_to_dispatch(AddressSpace *as) extern const MemoryRegionOps unassigned_mem_ops; bool memory_region_access_valid(MemoryRegion *mr, hwaddr addr, - unsigned size, bool is_write); + unsigned size, bool is_write, + MemTxAttrs attrs); void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section); AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv); diff --git a/exec.c b/exec.c index e56c3442c7..57a984758e 100644 --- a/exec.c +++ b/exec.c @@ -3433,7 +3433,9 @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len, mr = flatview_translate(fv, addr, &xlat, &l, is_write); if (!memory_access_is_direct(mr, is_write)) { l = memory_access_size(mr, l, addr); - if (!memory_region_access_valid(mr, xlat, l, is_write)) { + /* When our callers all have attrs we'll pass them through here */ + if (!memory_region_access_valid(mr, xlat, l, is_write, + MEMTXATTRS_UNSPECIFIED)) { return false; } } diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c index 3fcc330fe3..2e7b4068c0 100644 --- a/hw/s390x/s390-pci-inst.c +++ b/hw/s390x/s390-pci-inst.c @@ -770,7 +770,8 @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr, mr = s390_get_subregion(mr, offset, len); offset -= mr->addr; - if (!memory_region_access_valid(mr, offset, len, true)) { + if (!memory_region_access_valid(mr, offset, len, true, + MEMTXATTRS_UNSPECIFIED)) { s390_program_interrupt(env, PGM_OPERAND, 6, ra); return 0; } diff --git a/memory.c b/memory.c index e70b64b8b9..0f8f37a57b 100644 --- a/memory.c +++ b/memory.c @@ -1347,7 +1347,8 @@ static const MemoryRegionOps ram_device_mem_ops = { bool memory_region_access_valid(MemoryRegion *mr, hwaddr addr, unsigned size, - bool is_write) + bool is_write, + MemTxAttrs attrs) { int access_size_min, access_size_max; int access_size, i; @@ -1416,7 +1417,7 @@ MemTxResult memory_region_dispatch_read(MemoryRegion *mr, { MemTxResult r; - if (!memory_region_access_valid(mr, addr, size, false)) { + if (!memory_region_access_valid(mr, addr, size, false, attrs)) { *pval = unassigned_mem_read(mr, addr, size); return MEMTX_DECODE_ERROR; } @@ -1458,7 +1459,7 @@ MemTxResult memory_region_dispatch_write(MemoryRegion *mr, unsigned size, MemTxAttrs attrs) { - if (!memory_region_access_valid(mr, addr, size, true)) { + if (!memory_region_access_valid(mr, addr, size, true, attrs)) { unassigned_mem_write(mr, addr, data, size); return MEMTX_DECODE_ERROR; } From patchwork Tue May 1 08:59:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 134743 Delivered-To: patches@linaro.org Received: by 10.46.151.6 with SMTP id r6csp4727009lji; Tue, 1 May 2018 01:59:46 -0700 (PDT) X-Google-Smtp-Source: AB8JxZoT6I7BKJhQsWMb6b9LLKgBkYejpsFhzFN7OuqRcprIMc4sLJnQcX07OZZLLRS10TFmyKV+ X-Received: by 2002:adf:a194:: with SMTP id u20-v6mr8216738wru.262.1525165186117; Tue, 01 May 2018 01:59:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525165186; cv=none; d=google.com; s=arc-20160816; b=rtag8RfAdBHZ4FIjy2pUHDO60OPXOkn3m9NewTVmgp833H11bvwzUw9O07tEY7GsGS Fp2thxnZhiVdi7FN4qBADViIIkVlugOGy+bGoPgSanQzALDfuQBxA/FRebx/GF8xQxwN hyC1R5BOfBlWh+qNiCxf56lurxuUbwInBngljtoaC3UcSdBu09tJk1vrU7Rq3okncnFu gqjj6RLOB3x+7K7/ZPyFSmNfeG3VEqzNMbsYFjKsa6HuuVStyeCvi6tepoCOudhtmgRG 0qRFbeGndofymzakkW6PGDWnV2vctLOagRDulwqyErxhB50U7ZaeLtIw3qAQXu8s3+lp tR7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=bPifvAV6mhPu9crjXBn63Hf3oH3eC9jCqFq/YzzrTpc=; b=g8dbOb6ILp9uBdRVemgPg0qoMcvM2IO5ooUjid8XqTVXPpUhYEoArZ3VstQDpgwlyJ CQaGcjW5Y74B1IF6F3fs+QjPsoqCIRSiqlDll+QlarKtPXT//LNpeQDYmTWMe49d/Up7 2tmueJwfhIinxFCI5Yuk1MquwCk4a6D7FNx3Lgrb4cHwRb0gxbO8s6QHzuq2IowUc2XW MZU4DM25vWIf2FMAwL6rFFc1feXGTLGMXcw7bfwduf2RDxKC2rG9D7yHRqkxtCtEZZpq KIW5QOb2LlIyg9jzTwbC78gbSO6cxdLWBPHO3vjn/oqEjBP2G6rW7APnmeQAgnmg9kba ZSsw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id r4si4721611wma.6.2018.05.01.01.59.45 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 01 May 2018 01:59:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fDR8T-0007OR-JI; Tue, 01 May 2018 09:59:45 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paolo Bonzini , Eric Auger Subject: [RFC PATCH v2 07/12] Make MemoryRegion valid.accepts callback take a MemTxAttrs argument Date: Tue, 1 May 2018 09:59:34 +0100 Message-Id: <20180501085939.6201-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180501085939.6201-1-peter.maydell@linaro.org> References: <20180501085939.6201-1-peter.maydell@linaro.org> As part of plumbing MemTxAttrs down to the IOMMU translate method, add MemTxAttrs as an argument to the MemoryRegion valid.accepts callback. We'll need this for subpage_accepts(). We could take the approach we used with the read and write callbacks and add new a new _with_attrs version, but since there are so few implementations of the accepts hook we just change them all. Signed-off-by: Peter Maydell --- include/exec/memory.h | 3 ++- exec.c | 9 ++++++--- hw/hppa/dino.c | 3 ++- hw/nvram/fw_cfg.c | 12 ++++++++---- hw/scsi/esp.c | 3 ++- hw/xen/xen_pt_msi.c | 3 ++- memory.c | 5 +++-- 7 files changed, 25 insertions(+), 13 deletions(-) -- 2.17.0 diff --git a/include/exec/memory.h b/include/exec/memory.h index eb1ceace27..7c461b9718 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -166,7 +166,8 @@ struct MemoryRegionOps { * as a machine check exception). */ bool (*accepts)(void *opaque, hwaddr addr, - unsigned size, bool is_write); + unsigned size, bool is_write, + MemTxAttrs attrs); } valid; /* Internal implementation constraints: */ struct { diff --git a/exec.c b/exec.c index 57a984758e..3ceeb0643f 100644 --- a/exec.c +++ b/exec.c @@ -2504,7 +2504,8 @@ static void notdirty_mem_write(void *opaque, hwaddr ram_addr, } static bool notdirty_mem_accepts(void *opaque, hwaddr addr, - unsigned size, bool is_write) + unsigned size, bool is_write, + MemTxAttrs attrs) { return is_write; } @@ -2727,7 +2728,8 @@ static MemTxResult subpage_write(void *opaque, hwaddr addr, } static bool subpage_accepts(void *opaque, hwaddr addr, - unsigned len, bool is_write) + unsigned len, bool is_write, + MemTxAttrs attrs) { subpage_t *subpage = opaque; #if defined(DEBUG_SUBPAGE) @@ -2810,7 +2812,8 @@ static void readonly_mem_write(void *opaque, hwaddr addr, } static bool readonly_mem_accepts(void *opaque, hwaddr addr, - unsigned size, bool is_write) + unsigned size, bool is_write, + MemTxAttrs attrs) { return is_write; } diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c index 15aefde09c..77463672a3 100644 --- a/hw/hppa/dino.c +++ b/hw/hppa/dino.c @@ -137,7 +137,8 @@ static void gsc_to_pci_forwarding(DinoState *s) } static bool dino_chip_mem_valid(void *opaque, hwaddr addr, - unsigned size, bool is_write) + unsigned size, bool is_write, + MemTxAttrs attrs) { switch (addr) { case DINO_IAR0: diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c index 2a0739d0e9..b23e7f64a8 100644 --- a/hw/nvram/fw_cfg.c +++ b/hw/nvram/fw_cfg.c @@ -420,14 +420,16 @@ static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr, } static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr, - unsigned size, bool is_write) + unsigned size, bool is_write, + MemTxAttrs attrs) { return !is_write || ((size == 4 && (addr == 0 || addr == 4)) || (size == 8 && addr == 0)); } static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr, - unsigned size, bool is_write) + unsigned size, bool is_write, + MemTxAttrs attrs) { return addr == 0; } @@ -439,7 +441,8 @@ static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr, } static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr, - unsigned size, bool is_write) + unsigned size, bool is_write, + MemTxAttrs attrs) { return is_write && size == 2; } @@ -458,7 +461,8 @@ static void fw_cfg_comb_write(void *opaque, hwaddr addr, } static bool fw_cfg_comb_valid(void *opaque, hwaddr addr, - unsigned size, bool is_write) + unsigned size, bool is_write, + MemTxAttrs attrs) { return (size == 1) || (is_write && size == 2); } diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c index 64ec285826..9ed9727744 100644 --- a/hw/scsi/esp.c +++ b/hw/scsi/esp.c @@ -564,7 +564,8 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val) } static bool esp_mem_accepts(void *opaque, hwaddr addr, - unsigned size, bool is_write) + unsigned size, bool is_write, + MemTxAttrs attrs) { return (size == 1) || (is_write && size == 4); } diff --git a/hw/xen/xen_pt_msi.c b/hw/xen/xen_pt_msi.c index 6d1e3bdeb4..cc514f9157 100644 --- a/hw/xen/xen_pt_msi.c +++ b/hw/xen/xen_pt_msi.c @@ -498,7 +498,8 @@ static uint64_t pci_msix_read(void *opaque, hwaddr addr, } static bool pci_msix_accepts(void *opaque, hwaddr addr, - unsigned size, bool is_write) + unsigned size, bool is_write, + MemTxAttrs attrs) { return !(addr & (size - 1)); } diff --git a/memory.c b/memory.c index 0f8f37a57b..a729c29862 100644 --- a/memory.c +++ b/memory.c @@ -1269,7 +1269,8 @@ static void unassigned_mem_write(void *opaque, hwaddr addr, } static bool unassigned_mem_accepts(void *opaque, hwaddr addr, - unsigned size, bool is_write) + unsigned size, bool is_write, + MemTxAttrs attrs) { return false; } @@ -1374,7 +1375,7 @@ bool memory_region_access_valid(MemoryRegion *mr, access_size = MAX(MIN(size, access_size_max), access_size_min); for (i = 0; i < size; i += access_size) { if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size, - is_write)) { + is_write, attrs)) { return false; } } From patchwork Tue May 1 08:59:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 134745 Delivered-To: patches@linaro.org Received: by 10.46.151.6 with SMTP id r6csp4727016lji; Tue, 1 May 2018 01:59:46 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqbHlGwzrfUsdlaRqdII9h4gkVLzloqN5gjtlqSfo3OqEZwR3yPfjlNf+ENprw7+6o2sKdN X-Received: by 2002:adf:c613:: with SMTP id n19-v6mr7592509wrg.177.1525165186864; Tue, 01 May 2018 01:59:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525165186; cv=none; d=google.com; s=arc-20160816; b=rwolY2stbfUOsrs8lBaUuTmChjeyRFDmD1ZD5skqnpNgWtwTdY7yEtQJff8vx99BEV VXceIcDLrQKCxmhQrHkLE4DX4OSqKlAZjALlECHl90upmnjvzKtBmiRXVdheLLWKjsh5 TIwAutI+kO42FC1O5qgQpHTL6PyRAmK4fIRAOYfjbcxRV4kilEy/IBPnwZH0ndJoN7Ke 3iedu77iCrY6vjeMlKpMfABfIN11u5yqPuXJCzFT3xr/aaFnlmVZ0tabQzc1po35ptHc 05QWIH6SnARQk3GS2A1GmX0QDY1hc8xGGW+84hqT7qBf1ex6dUwPv6yWlyNaM2t2TY5F Pivw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=7jWbA1knPJNxKhkZeFjcwEeSR82tCg7DrF8wITE7wh0=; b=TDKxt8j1HlCwLhxOR5llFeO892Ecr/dzp0tvS0d8nCKZAbPecZPJTi2kEfKmLhRnDu Qi4a+Ak4xUGM1JWZTwqUW+gNJfQg66wlp2cV+T6C8kNQAWhzRwZAZXK7wm54CwDWXCHZ vLms1lb4aa2IDi972VPzkgm/qBV9qq6s9sa+XkuPpbifdE0inctVMaIiNk7nIt5GRCWz M/3wN2Ifu61tR9kIwuT8p1KI5mBh5EX4/tQQIRPjOxpAco3m0kPMMqbB5l14UrVHPay0 fQy3tw2f74p5ctnWeoKQGunPCe3KKjsSe0v+7uPgrV2myNINhL2MZtb5QJZG6JKZktC0 DR3w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id m126si6597087wmd.104.2018.05.01.01.59.46 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 01 May 2018 01:59:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fDR8U-0007Oy-B5; Tue, 01 May 2018 09:59:46 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paolo Bonzini , Eric Auger Subject: [RFC PATCH v2 08/12] Make flatview_access_valid() take a MemTxAttrs argument Date: Tue, 1 May 2018 09:59:35 +0100 Message-Id: <20180501085939.6201-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180501085939.6201-1-peter.maydell@linaro.org> References: <20180501085939.6201-1-peter.maydell@linaro.org> As part of plumbing MemTxAttrs down to the IOMMU translate method, add MemTxAttrs as an argument to flatview_access_valid(). Its callers now all have an attrs value to hand, so we can correct our earlier temporary use of MEMTXATTRS_UNSPECIFIED. Signed-off-by: Peter Maydell --- exec.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) -- 2.17.0 diff --git a/exec.c b/exec.c index 3ceeb0643f..0eef4702a5 100644 --- a/exec.c +++ b/exec.c @@ -2662,7 +2662,7 @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr, static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs, const uint8_t *buf, int len); static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len, - bool is_write); + bool is_write, MemTxAttrs attrs); static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data, unsigned len, MemTxAttrs attrs) @@ -2738,7 +2738,7 @@ static bool subpage_accepts(void *opaque, hwaddr addr, #endif return flatview_access_valid(subpage->fv, addr + subpage->base, - len, is_write); + len, is_write, attrs); } static const MemoryRegionOps subpage_ops = { @@ -3426,7 +3426,7 @@ static void cpu_notify_map_clients(void) } static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len, - bool is_write) + bool is_write, MemTxAttrs attrs) { MemoryRegion *mr; hwaddr l, xlat; @@ -3437,8 +3437,7 @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len, if (!memory_access_is_direct(mr, is_write)) { l = memory_access_size(mr, l, addr); /* When our callers all have attrs we'll pass them through here */ - if (!memory_region_access_valid(mr, xlat, l, is_write, - MEMTXATTRS_UNSPECIFIED)) { + if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) { return false; } } @@ -3458,7 +3457,7 @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr, rcu_read_lock(); fv = address_space_to_flatview(as); - result = flatview_access_valid(fv, addr, len, is_write); + result = flatview_access_valid(fv, addr, len, is_write, attrs); rcu_read_unlock(); return result; } From patchwork Tue May 1 08:59:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 134746 Delivered-To: patches@linaro.org Received: by 10.46.151.6 with SMTP id r6csp4727026lji; Tue, 1 May 2018 01:59:47 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrYtD2jOyXteuY14Ihd+eaV7nYmhsWGjsxvlKrQlGCJWjC79u3hFPvPgvNAnjsG0artKzWz X-Received: by 10.28.118.25 with SMTP id r25mr9715525wmc.5.1525165187653; Tue, 01 May 2018 01:59:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525165187; cv=none; d=google.com; s=arc-20160816; b=OnPtKGfVeOegUcctCEhcUa/QG2YbJkjkWgBDJ6IFxZGXg8QVmwM95sUb0GhkenFNWZ e4tutdVRf0tyjXs7qFB8Y98Md8JA91GQj54VjHZ3YDyym8KIC35apAUpQjG1wEYFuSIK 88JSBeouUZHzDax7+4aaWqepwa4G2RiggfsKNkJFB06aQs3nzaEROrz2NtP9TItK/09d pOtbWgzfxwStImSD34oxHWUIsiBanHrj3rd49oB77m6Rr6YPhThmiBjtRmVc9yfMSguc fUY4w1MT84YT4wuPTPTtZK5d3MwXsGV/evPY2E4Yogrly2INrg10H8AHAAVxFzF3ercK d0wg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=0maqH6MEUtce+JdoAjtCx6Kd66xvVPM+jl8PINAiU0Y=; b=q0xp/iofnev7Fyv46kGmY20LuaYBfXmHNVW3KNwhMqUMttpA0lciB6P2H6GlZGbclk oJEeYLY3h7nFpFk8gxGg5sTuJ4e7rIt7FSx8H+Y6i9vVLTfZIWtJBnr56E8Fql5TSK2G XZNVMUXUVhBLQ64BYWSp1n4mRPm9rP+doFJGqM5ZviG/ltOZnEyRxwxcFJvod7UK9L3A 0VtmfydXPjRlUPNqm+7EtNO599P7pC1i/RGEVsgTR0BIxG6sAEbJML38YhMP+D9YU3TG xz4gIsjPmexOSnJysoGsdwmoqgD2tg8OaNlMz1bP5FTAfQQBl4gALMEiyVzyP9JrQrry S2qQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id y81-v6si8137873wrc.314.2018.05.01.01.59.47 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 01 May 2018 01:59:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fDR8V-0007PX-4G; Tue, 01 May 2018 09:59:47 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paolo Bonzini , Eric Auger Subject: [RFC PATCH v2 09/12] Make flatview_translate() take a MemTxAttrs argument Date: Tue, 1 May 2018 09:59:36 +0100 Message-Id: <20180501085939.6201-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180501085939.6201-1-peter.maydell@linaro.org> References: <20180501085939.6201-1-peter.maydell@linaro.org> As part of plumbing MemTxAttrs down to the IOMMU translate method, add MemTxAttrs as an argument to flatview_translate(); all its callers now have attrs available. Signed-off-by: Peter Maydell --- include/exec/memory.h | 7 ++++--- exec.c | 17 +++++++++-------- 2 files changed, 13 insertions(+), 11 deletions(-) -- 2.17.0 diff --git a/include/exec/memory.h b/include/exec/memory.h index 7c461b9718..bd50424804 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -1914,7 +1914,8 @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr, */ MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat, - hwaddr *len, bool is_write); + hwaddr *len, bool is_write, + MemTxAttrs attrs); static inline MemoryRegion *address_space_translate(AddressSpace *as, hwaddr addr, hwaddr *xlat, @@ -1922,7 +1923,7 @@ static inline MemoryRegion *address_space_translate(AddressSpace *as, MemTxAttrs attrs) { return flatview_translate(address_space_to_flatview(as), - addr, xlat, len, is_write); + addr, xlat, len, is_write, attrs); } /* address_space_access_valid: check for validity of accessing an address @@ -2024,7 +2025,7 @@ MemTxResult address_space_read(AddressSpace *as, hwaddr addr, rcu_read_lock(); fv = address_space_to_flatview(as); l = len; - mr = flatview_translate(fv, addr, &addr1, &l, false); + mr = flatview_translate(fv, addr, &addr1, &l, false, attrs); if (len == l && memory_access_is_direct(mr, false)) { ptr = qemu_map_ram_ptr(mr->ram_block, addr1); memcpy(buf, ptr, len); diff --git a/exec.c b/exec.c index 0eef4702a5..41f7a7f5c4 100644 --- a/exec.c +++ b/exec.c @@ -583,7 +583,8 @@ iotlb_fail: /* Called from RCU critical section */ MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat, - hwaddr *plen, bool is_write) + hwaddr *plen, bool is_write, + MemTxAttrs attrs) { MemoryRegion *mr; MemoryRegionSection section; @@ -3117,7 +3118,7 @@ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr, } l = len; - mr = flatview_translate(fv, addr, &addr1, &l, true); + mr = flatview_translate(fv, addr, &addr1, &l, true, attrs); } return result; @@ -3133,7 +3134,7 @@ static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs, MemTxResult result = MEMTX_OK; l = len; - mr = flatview_translate(fv, addr, &addr1, &l, true); + mr = flatview_translate(fv, addr, &addr1, &l, true, attrs); result = flatview_write_continue(fv, addr, attrs, buf, len, addr1, l, mr); @@ -3204,7 +3205,7 @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr, } l = len; - mr = flatview_translate(fv, addr, &addr1, &l, false); + mr = flatview_translate(fv, addr, &addr1, &l, false, attrs); } return result; @@ -3219,7 +3220,7 @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr, MemoryRegion *mr; l = len; - mr = flatview_translate(fv, addr, &addr1, &l, false); + mr = flatview_translate(fv, addr, &addr1, &l, false, attrs); return flatview_read_continue(fv, addr, attrs, buf, len, addr1, l, mr); } @@ -3433,7 +3434,7 @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len, while (len > 0) { l = len; - mr = flatview_translate(fv, addr, &xlat, &l, is_write); + mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs); if (!memory_access_is_direct(mr, is_write)) { l = memory_access_size(mr, l, addr); /* When our callers all have attrs we'll pass them through here */ @@ -3482,7 +3483,7 @@ flatview_extend_translation(FlatView *fv, hwaddr addr, len = target_len; this_mr = flatview_translate(fv, addr, &xlat, - &len, is_write); + &len, is_write, attrs); if (this_mr != mr || xlat != base + done) { return done; } @@ -3515,7 +3516,7 @@ void *address_space_map(AddressSpace *as, l = len; rcu_read_lock(); fv = address_space_to_flatview(as); - mr = flatview_translate(fv, addr, &xlat, &l, is_write); + mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs); if (!memory_access_is_direct(mr, is_write)) { if (atomic_xchg(&bounce.in_use, true)) { From patchwork Tue May 1 08:59:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 134747 Delivered-To: patches@linaro.org Received: by 10.46.151.6 with SMTP id r6csp4727029lji; Tue, 1 May 2018 01:59:48 -0700 (PDT) X-Google-Smtp-Source: AB8JxZoil5OprOMs8HE0a2iAkGHFeASEcXzuiWXd09Z04jcxniRnNFfGRCQjufdUY+va4wbmsOLh X-Received: by 10.28.110.30 with SMTP id j30mr8598400wmc.62.1525165188456; Tue, 01 May 2018 01:59:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525165188; cv=none; d=google.com; s=arc-20160816; b=pzhyHLB7fhqHt/Nv6qpTNIhgc7NxUMExkwrmxRKxm1ZjBNA7pEnuBUsP985z0+tuor 6Cr+L7Cp4ICxpDw7Fj5rNFdrNjlyYjEcL+iYCBiGoMJXNQpXHv/lELRpKco7693EOPn2 o7UADHG36CYKc4FqLz39gmcE3DkU2J1IWUwitR+/rHMRMc2PP6cIP6SNAs5UFV5SlNQM mAT9xOlDuB0OtWlviY2bUwi+10mAlDKlRqJf9fh9reassmjpNaUPmDS1zhWT0vJpfUUs NKK2xXAysQF78V43etMiZTzWurx28Jkmb4oCcK9e2WZYfNblWB3FD0VIUKTKygQqC+CX n5CA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=6r3STZ1DcgXLGr3MH6j+8z2hEmtBeT1gOcuM2bHgRzU=; b=EOKezoLGuH9/ePbyb9Ib6+z5LKPlbkOsq0MokLHXq3rd2xw0ohDK8nboiIOdNjJooW 6CVGVQW0i/UvkfwG1OZcg1G0v5gw8esFIzgKAXO40lKT8/efQNSNELQIA9vFzZ41jVSZ T5ioNe2IlPmehyDdOxaGup/ulnz4DhXRlbYWBVRAm1GF+Uy2CQzK5uUPC82pIIeAOg/p e3zl6HkkRH0v3hSq+W9KtFGWYPdnUw80aQRoBTtg7+K2FV2Npl7nLk0erSySZk++VcvM wFuZik/ORL3NFDDVsRNwKVaDpJL546Dp6pu/XMkNvgTA4nLJyIuFGj5JArLEYCXH0GYl vWdA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id v12-v6si7739213wrc.334.2018.05.01.01.59.48 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 01 May 2018 01:59:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fDR8V-0007Q5-Tg; Tue, 01 May 2018 09:59:47 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paolo Bonzini , Eric Auger Subject: [RFC PATCH v2 10/12] Make address_space_get_iotlb_entry() take a MemTxAttrs argument Date: Tue, 1 May 2018 09:59:37 +0100 Message-Id: <20180501085939.6201-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180501085939.6201-1-peter.maydell@linaro.org> References: <20180501085939.6201-1-peter.maydell@linaro.org> As part of plumbing MemTxAttrs down to the IOMMU translate method, add MemTxAttrs as an argument to address_space_get_iotlb_entry(). Signed-off-by: Peter Maydell --- include/exec/memory.h | 2 +- exec.c | 2 +- hw/virtio/vhost.c | 3 ++- 3 files changed, 4 insertions(+), 3 deletions(-) -- 2.17.0 diff --git a/include/exec/memory.h b/include/exec/memory.h index bd50424804..16a82d9722 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -1897,7 +1897,7 @@ void stq_be_phys_cached(MemoryRegionCache *cache, hwaddr addr, uint64_t val); * entry. Should be called from an RCU critical section. */ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr, - bool is_write); + bool is_write, MemTxAttrs attrs); /* address_space_translate: translate an address range into an address space * into a MemoryRegion and an address range into that section. Should be diff --git a/exec.c b/exec.c index 41f7a7f5c4..c29bf47ce2 100644 --- a/exec.c +++ b/exec.c @@ -547,7 +547,7 @@ translate_fail: /* Called from RCU critical section */ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr, - bool is_write) + bool is_write, MemTxAttrs attrs) { MemoryRegionSection section; hwaddr xlat, page_mask; diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c index 9d5850a7d7..48f4fd7cc9 100644 --- a/hw/virtio/vhost.c +++ b/hw/virtio/vhost.c @@ -895,7 +895,8 @@ int vhost_device_iotlb_miss(struct vhost_dev *dev, uint64_t iova, int write) rcu_read_lock(); iotlb = address_space_get_iotlb_entry(dev->vdev->dma_as, - iova, write); + iova, write, + MEMTXATTRS_UNSPECIFIED); if (iotlb.target_as != NULL) { ret = vhost_memory_region_lookup(dev, iotlb.translated_addr, &uaddr, &len); From patchwork Tue May 1 08:59:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 134748 Delivered-To: patches@linaro.org Received: by 10.46.151.6 with SMTP id r6csp4727038lji; Tue, 1 May 2018 01:59:49 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpf0wSwifN5CCxqaJyj+Jby4v/juQtPGG1DDrdyfHFCfPEsP/zA3DhQbVYuFI7//HzShO/t X-Received: by 2002:adf:dfcc:: with SMTP id q12-v6mr11170590wrn.68.1525165189153; Tue, 01 May 2018 01:59:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525165189; cv=none; d=google.com; s=arc-20160816; b=zyGI8HG6NjAI0u12aedtrCgBx91bPWUj8GIddR4Z623YhUwicheUmulhUEvU7Yt9KP 5X9V0IC3/SDO4bXh/xhu70TjxBRLhfi0WWpUUAxa8L7op+TKEHQSAtAtF1CR5PwOIfwI 9g9R5MJhRQCFjokcG6IY/64YzVGu93XLok8IAtmQ+vVA1dwzTF7h6I+ticBAHdy91wSx RYYVhZ/uQPWngf7upvzDV8ZtyDEhVTVRE50bGn41++9Dx706tBy+dpVWsz+JRT4rWoNV 4nmouhTFAeEBrm5eFi5DGDgQkxh82c4JhpHBljGnk2bFBA0dltkjzBEJx1OQfkjjFab9 jneA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=dbwPFcZbDeHYa2Qx29bldIe4dKEgHeUjga9KUJL8fjY=; b=0ug1OjM8wje7A5aEqmzXSvkMSRTSXqb+6C7J//WeEXJtVc9GSO6B7qBWEtSXc8OXNz QMu2+M6byTxxDQr2/ZqW3VQzs40SNnEJ9G18nWaXJYMIjddzQlHno7VwNI6Y+O/hE//c ZErTcjFvCp6GYMMUnYHGyRPzn2q6A/suQm8vYOzuOlb7U+UNFmbY5i4Kfn8ly+NmssJz hNWyHD4BGtQPNHNB125jzAl6n2IlsZNXOdRE6LE1ynVeGuiDZFymOX9zvezyXEyaO6Sy xeLTMMP1PJV1dx3fyCSPERpV2DbygKlPVeFPa6B3Fot4gcuVCntfBS9yiVvP1gOZLu5q BYPQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id 10si6571005wme.114.2018.05.01.01.59.49 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 01 May 2018 01:59:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fDR8W-0007Qm-M4; Tue, 01 May 2018 09:59:48 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paolo Bonzini , Eric Auger Subject: [RFC PATCH v2 11/12] Make flatview_do_translate() take a MemTxAttrs argument Date: Tue, 1 May 2018 09:59:38 +0100 Message-Id: <20180501085939.6201-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180501085939.6201-1-peter.maydell@linaro.org> References: <20180501085939.6201-1-peter.maydell@linaro.org> As part of plumbing MemTxAttrs down to the IOMMU translate method, add MemTxAttrs as an argument to flatview_do_translate(). Signed-off-by: Peter Maydell --- exec.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) -- 2.17.0 diff --git a/exec.c b/exec.c index c29bf47ce2..9c6d9aae28 100644 --- a/exec.c +++ b/exec.c @@ -476,6 +476,7 @@ address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *x * would tell. It can be @NULL if we don't care about it. * @is_write: whether the translation operation is for write * @is_mmio: whether this can be MMIO, set true if it can + * @attrs: memory transaction attributes * * This function is called from RCU critical section */ @@ -486,7 +487,8 @@ static MemoryRegionSection flatview_do_translate(FlatView *fv, hwaddr *page_mask_out, bool is_write, bool is_mmio, - AddressSpace **target_as) + AddressSpace **target_as, + MemTxAttrs attrs) { IOMMUTLBEntry iotlb; MemoryRegionSection *section; @@ -557,7 +559,8 @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr, * but page mask. */ section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat, - NULL, &page_mask, is_write, false, &as); + NULL, &page_mask, is_write, false, &as, + attrs); /* Illegal translation */ if (section.mr == &io_mem_unassigned) { @@ -592,7 +595,7 @@ MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat, /* This can be MMIO, so setup MMIO bit. */ section = flatview_do_translate(fv, addr, xlat, plen, NULL, - is_write, true, &as); + is_write, true, &as, attrs); mr = section.mr; if (xen_enabled() && memory_access_is_direct(mr, is_write)) { From patchwork Tue May 1 08:59:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 134749 Delivered-To: patches@linaro.org Received: by 10.46.151.6 with SMTP id r6csp4727043lji; Tue, 1 May 2018 01:59:49 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqDRYeW9nERbLO7qy4ltLGn/goQD8xtjN2Mq2Z1HSy9C8DEnsQAYVBP7oGY/TOV3d6EpKKS X-Received: by 10.28.55.194 with SMTP id e185mr9096719wma.20.1525165189860; Tue, 01 May 2018 01:59:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525165189; cv=none; d=google.com; s=arc-20160816; b=Q1lcNVeujybrKkV5WBCdEymZK6mkcFRqNQG8CmlxpnUruDeZ+lpTHEg8JFxAxKR28M ErtfrTrd2sUpLlXmTbBzX3V+WHQRgvv+lIMoHvf3ZmK+lz5NZOdSHFqwNGB4k83TAYxM DJMHtkBg7IUl5tquS8GvJfBBgZ+vvML+REvBFvFnhS1g/IUK/WgNhU3ZAzu5H9zTvIUu XUlvINZcGHZ9TSLSJYEMrL5+yphGexw3xsmWe15saSGMMxYRLN44pHPq/RZNzYzGZHix 0GpQoWi5MK7WWc6GPke3mkg6BOi/EWkPjIJklKLfH0Cfw9bXMiNFvIUDBrphhX/8r3lU Hkag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=references:in-reply-to:message-id:date:subject:cc:to:from :arc-authentication-results; bh=EROKIGZhiPUu4DVqbyEMYPMGDTGM3HpjXnNog6UCvbY=; b=eNtcCCBb5LY+2vfQoDqmbEX8UOS85bGNxFdiNX5nLlaCeo4DExSTSwkHyCegDLnRul HXr104P8b1Jm4+mFSkbw+iDXDmurFDMZsiMuHgtE8KhNGaPvs6+L9tW8mKBSfPhqnnaW jOcILDz18N3pGpZ548IF9AEYEbKZmEgKODTFYQGZTx748ZrDQiinb70mRNFJmhkhWSqk mLN9IIdsudxi4ui+seKOEQTMih91SCN9euULc4b6hcZvX2t5J15EUGeqVPitKNFHI+Lb 4dQssDCa6Zqe158HYCQrk1mlDYLLoz9/2TuN2Lt/KWI8hKNjX1w03PQwwyCaKhbB83gV Z/yQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id w19-v6si7833398wrb.286.2018.05.01.01.59.49 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 01 May 2018 01:59:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fDR8X-0007RI-BZ; Tue, 01 May 2018 09:59:49 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, Paolo Bonzini , Eric Auger Subject: [RFC PATCH v2 12/12] Add MemTxAttrs argument to IOMMU translate function Date: Tue, 1 May 2018 09:59:39 +0100 Message-Id: <20180501085939.6201-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180501085939.6201-1-peter.maydell@linaro.org> References: <20180501085939.6201-1-peter.maydell@linaro.org> Add a MemTxAttrs argument to the IOMMU translate function; this is necessary for IOMMU implementations that care about transaction attributes such as user/privileged or secure/nonsecure when deciding whether a transaction is permitted. Signed-off-by: Peter Maydell --- include/exec/memory.h | 3 ++- exec.c | 2 +- hw/alpha/typhoon.c | 3 ++- hw/dma/rc4030.c | 3 ++- hw/i386/amd_iommu.c | 3 ++- hw/i386/intel_iommu.c | 3 ++- hw/ppc/spapr_iommu.c | 3 ++- hw/s390x/s390-pci-bus.c | 3 ++- hw/sparc/sun4m_iommu.c | 3 ++- hw/sparc64/sun4u_iommu.c | 3 ++- memory.c | 3 ++- 11 files changed, 21 insertions(+), 11 deletions(-) -- 2.17.0 diff --git a/include/exec/memory.h b/include/exec/memory.h index 16a82d9722..2c7dd4b373 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -221,9 +221,10 @@ typedef struct IOMMUMemoryRegionClass { * @iommu: the IOMMUMemoryRegion * @hwaddr: address to be translated within the memory region * @flag: requested access permissions + * @attrs: memory transaction attributes */ IOMMUTLBEntry (*translate)(IOMMUMemoryRegion *iommu, hwaddr addr, - IOMMUAccessFlags flag); + IOMMUAccessFlags flag, MemTxAttrs attrs); /* Returns minimum supported page size in bytes. * If this method is not provided then the minimum is assumed to * be TARGET_PAGE_SIZE. diff --git a/exec.c b/exec.c index 9c6d9aae28..e346424172 100644 --- a/exec.c +++ b/exec.c @@ -513,7 +513,7 @@ static MemoryRegionSection flatview_do_translate(FlatView *fv, imrc = memory_region_get_iommu_class_nocheck(iommu_mr); iotlb = imrc->translate(iommu_mr, addr, is_write ? - IOMMU_WO : IOMMU_RO); + IOMMU_WO : IOMMU_RO, attrs); addr = ((iotlb.translated_addr & ~iotlb.addr_mask) | (addr & iotlb.addr_mask)); page_mask &= iotlb.addr_mask; diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c index 6a40869488..49192ab24d 100644 --- a/hw/alpha/typhoon.c +++ b/hw/alpha/typhoon.c @@ -666,7 +666,8 @@ static bool window_translate(TyphoonWindow *win, hwaddr addr, Pchip and generate a machine check interrupt. */ static IOMMUTLBEntry typhoon_translate_iommu(IOMMUMemoryRegion *iommu, hwaddr addr, - IOMMUAccessFlags flag) + IOMMUAccessFlags flag, + MemTxAttrs attrs) { TyphoonPchip *pchip = container_of(iommu, TyphoonPchip, iommu); IOMMUTLBEntry ret; diff --git a/hw/dma/rc4030.c b/hw/dma/rc4030.c index 5d4833eeca..89686ae7dc 100644 --- a/hw/dma/rc4030.c +++ b/hw/dma/rc4030.c @@ -491,7 +491,8 @@ static const MemoryRegionOps jazzio_ops = { }; static IOMMUTLBEntry rc4030_dma_translate(IOMMUMemoryRegion *iommu, hwaddr addr, - IOMMUAccessFlags flag) + IOMMUAccessFlags flag, + MemTxAttrs attrs) { rc4030State *s = container_of(iommu, rc4030State, dma_mr); IOMMUTLBEntry ret = { diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 63d46ff6ee..5f530b5fe6 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -991,7 +991,8 @@ static inline bool amdvi_is_interrupt_addr(hwaddr addr) } static IOMMUTLBEntry amdvi_translate(IOMMUMemoryRegion *iommu, hwaddr addr, - IOMMUAccessFlags flag) + IOMMUAccessFlags flag, + MemTxAttrs attrs) { AMDVIAddressSpace *as = container_of(iommu, AMDVIAddressSpace, iommu); AMDVIState *s = as->iommu_state; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index fb31de9416..483ff305f8 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2282,7 +2282,8 @@ static void vtd_mem_write(void *opaque, hwaddr addr, } static IOMMUTLBEntry vtd_iommu_translate(IOMMUMemoryRegion *iommu, hwaddr addr, - IOMMUAccessFlags flag) + IOMMUAccessFlags flag, + MemTxAttrs attrs) { VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu); IntelIOMMUState *s = vtd_as->iommu_state; diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c index aaa6010d5c..199612095a 100644 --- a/hw/ppc/spapr_iommu.c +++ b/hw/ppc/spapr_iommu.c @@ -112,7 +112,8 @@ static void spapr_tce_free_table(uint64_t *table, int fd, uint32_t nb_table) /* Called from RCU critical section */ static IOMMUTLBEntry spapr_tce_translate_iommu(IOMMUMemoryRegion *iommu, hwaddr addr, - IOMMUAccessFlags flag) + IOMMUAccessFlags flag, + MemTxAttrs attrs) { sPAPRTCETable *tcet = container_of(iommu, sPAPRTCETable, iommu); uint64_t tce; diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c index 10da87458e..77588c2355 100644 --- a/hw/s390x/s390-pci-bus.c +++ b/hw/s390x/s390-pci-bus.c @@ -484,7 +484,8 @@ uint16_t s390_guest_io_table_walk(uint64_t g_iota, hwaddr addr, } static IOMMUTLBEntry s390_translate_iommu(IOMMUMemoryRegion *mr, hwaddr addr, - IOMMUAccessFlags flag) + IOMMUAccessFlags flag, + MemTxAttrs attrs) { S390PCIIOMMU *iommu = container_of(mr, S390PCIIOMMU, iommu_mr); S390IOTLBEntry *entry; diff --git a/hw/sparc/sun4m_iommu.c b/hw/sparc/sun4m_iommu.c index b677601fc6..f68bcade3c 100644 --- a/hw/sparc/sun4m_iommu.c +++ b/hw/sparc/sun4m_iommu.c @@ -282,7 +282,8 @@ static void iommu_bad_addr(IOMMUState *s, hwaddr addr, /* Called from RCU critical section */ static IOMMUTLBEntry sun4m_translate_iommu(IOMMUMemoryRegion *iommu, hwaddr addr, - IOMMUAccessFlags flags) + IOMMUAccessFlags flags, + MemTxAttrs attrs) { IOMMUState *is = container_of(iommu, IOMMUState, iommu); hwaddr page, pa; diff --git a/hw/sparc64/sun4u_iommu.c b/hw/sparc64/sun4u_iommu.c index eb3aaa87e6..7a5a588aed 100644 --- a/hw/sparc64/sun4u_iommu.c +++ b/hw/sparc64/sun4u_iommu.c @@ -73,7 +73,8 @@ /* Called from RCU critical section */ static IOMMUTLBEntry sun4u_translate_iommu(IOMMUMemoryRegion *iommu, hwaddr addr, - IOMMUAccessFlags flag) + IOMMUAccessFlags flag, + MemTxAttrs attrs) { IOMMUState *is = container_of(iommu, IOMMUState, iommu); hwaddr baseaddr, offset; diff --git a/memory.c b/memory.c index a729c29862..dbb9718bea 100644 --- a/memory.c +++ b/memory.c @@ -1832,7 +1832,8 @@ void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n) granularity = memory_region_iommu_get_min_page_size(iommu_mr); for (addr = 0; addr < memory_region_size(mr); addr += granularity) { - iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE); + iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, + MEMTXATTRS_UNSPECIFIED); if (iotlb.perm != IOMMU_NONE) { n->notify(n, &iotlb); }