From patchwork Tue Mar 16 11:14:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Seiya Wang X-Patchwork-Id: 402205 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C86A3C4321A for ; Tue, 16 Mar 2021 11:16:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B1FF76502A for ; Tue, 16 Mar 2021 11:16:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237140AbhCPLP3 (ORCPT ); Tue, 16 Mar 2021 07:15:29 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:54067 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S233919AbhCPLPV (ORCPT ); Tue, 16 Mar 2021 07:15:21 -0400 X-UUID: 1f096de308704c78b5f555427e26c585-20210316 X-UUID: 1f096de308704c78b5f555427e26c585-20210316 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 532000923; Tue, 16 Mar 2021 19:15:16 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 16 Mar 2021 19:15:13 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 16 Mar 2021 19:15:14 +0800 From: Seiya Wang To: Rob Herring , Matthias Brugger CC: Jonathan Cameron , Lars-Peter Clausen , Peter Meerwald-Stadler , Ulf Hansson , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Greg Kroah-Hartman , Mark Brown , Daniel Lezcano , Thomas Gleixner , Wim Van Sebroeck , Guenter Roeck , Enric Balletbo i Serra , Hsin-Yi Wang , Seiya Wang , Fabien Parent , Sean Wang , Zhiyong Tao , Chaotian Jing , Wenbin Mei , Stanley Chu , Bayi Cheng , Chuanhong Guo , , , , , , , , , , Subject: [PATCH 01/10] dt-bindings: timer: Add compatible for Mediatek MT8195 Date: Tue, 16 Mar 2021 19:14:34 +0800 Message-ID: <20210316111443.3332-2-seiya.wang@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210316111443.3332-1-seiya.wang@mediatek.com> References: <20210316111443.3332-1-seiya.wang@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 7DBB21F2AB5E02307627BB7A18E5EFF7B6C6C158DF453B6D49922F794F81B9BC2000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org This commit adds dt-binding documentation of timer for Mediatek MT8195 SoC Platform. Signed-off-by: Seiya Wang --- Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt index 690a9c0966ac..e5c57d6e0186 100644 --- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt +++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt @@ -23,6 +23,7 @@ Required properties: For those SoCs that use SYST * "mediatek,mt8183-timer" for MT8183 compatible timers (SYST) * "mediatek,mt8192-timer" for MT8192 compatible timers (SYST) + * "mediatek,mt8195-timer" for MT8195 compatible timers (SYST) * "mediatek,mt7629-timer" for MT7629 compatible timers (SYST) * "mediatek,mt6765-timer" for MT6765 and all above compatible timers (SYST) From patchwork Tue Mar 16 11:14:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Seiya Wang X-Patchwork-Id: 402204 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7D90C2BA1A for ; Tue, 16 Mar 2021 11:16:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CB7B765027 for ; Tue, 16 Mar 2021 11:16:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237217AbhCPLQL (ORCPT ); Tue, 16 Mar 2021 07:16:11 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:48912 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S237118AbhCPLP0 (ORCPT ); Tue, 16 Mar 2021 07:15:26 -0400 X-UUID: b8b8bb1b26394cfa838bb4501282a019-20210316 X-UUID: b8b8bb1b26394cfa838bb4501282a019-20210316 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1381749629; Tue, 16 Mar 2021 19:15:21 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 16 Mar 2021 19:15:19 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 16 Mar 2021 19:15:19 +0800 From: Seiya Wang To: Rob Herring , Matthias Brugger CC: Jonathan Cameron , Lars-Peter Clausen , Peter Meerwald-Stadler , Ulf Hansson , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Greg Kroah-Hartman , Mark Brown , Daniel Lezcano , Thomas Gleixner , Wim Van Sebroeck , Guenter Roeck , Enric Balletbo i Serra , Hsin-Yi Wang , Seiya Wang , Fabien Parent , Sean Wang , Zhiyong Tao , Chaotian Jing , Wenbin Mei , Stanley Chu , Bayi Cheng , Chuanhong Guo , , , , , , , , , , Subject: [PATCH 02/10] dt-bindings: serial: Add compatible for Mediatek MT8195 Date: Tue, 16 Mar 2021 19:14:35 +0800 Message-ID: <20210316111443.3332-3-seiya.wang@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210316111443.3332-1-seiya.wang@mediatek.com> References: <20210316111443.3332-1-seiya.wang@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 710D83FF007C2822D4FF14E9AA594A7B428033586ACDF8B86D3933F89E6055C62000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org This commit adds dt-binding documentation of uart for Mediatek MT8195 SoC Platform. Signed-off-by: Seiya Wang --- Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt b/Documentation/devicetree/bindings/serial/mtk-uart.txt index 647b5aee86f3..64c4fb59acd1 100644 --- a/Documentation/devicetree/bindings/serial/mtk-uart.txt +++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt @@ -20,6 +20,7 @@ Required properties: * "mediatek,mt8173-uart" for MT8173 compatible UARTS * "mediatek,mt8183-uart", "mediatek,mt6577-uart" for MT8183 compatible UARTS * "mediatek,mt8192-uart", "mediatek,mt6577-uart" for MT8192 compatible UARTS + * "mediatek,mt8195-uart", "mediatek,mt6577-uart" for MT8195 compatible UARTS * "mediatek,mt8516-uart" for MT8516 compatible UARTS * "mediatek,mt6577-uart" for MT6577 and all of the above From patchwork Tue Mar 16 11:14:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Seiya Wang X-Patchwork-Id: 403718 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BB6BC2BA2B for ; Tue, 16 Mar 2021 11:16:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 12B3C65026 for ; Tue, 16 Mar 2021 11:16:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237220AbhCPLQN (ORCPT ); Tue, 16 Mar 2021 07:16:13 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:54201 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S237139AbhCPLPa (ORCPT ); Tue, 16 Mar 2021 07:15:30 -0400 X-UUID: ad61ad8806fa42098474167292e6db5b-20210316 X-UUID: ad61ad8806fa42098474167292e6db5b-20210316 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1228090784; Tue, 16 Mar 2021 19:15:26 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 16 Mar 2021 19:15:25 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 16 Mar 2021 19:15:24 +0800 From: Seiya Wang To: Rob Herring , Matthias Brugger CC: Jonathan Cameron , Lars-Peter Clausen , Peter Meerwald-Stadler , Ulf Hansson , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Greg Kroah-Hartman , Mark Brown , Daniel Lezcano , Thomas Gleixner , Wim Van Sebroeck , Guenter Roeck , Enric Balletbo i Serra , Hsin-Yi Wang , Seiya Wang , Fabien Parent , Sean Wang , Zhiyong Tao , Chaotian Jing , Wenbin Mei , Stanley Chu , Bayi Cheng , Chuanhong Guo , , , , , , , , , , Subject: [PATCH 03/10] dt-bindings: watchdog: Add compatible for Mediatek MT8195 Date: Tue, 16 Mar 2021 19:14:36 +0800 Message-ID: <20210316111443.3332-4-seiya.wang@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210316111443.3332-1-seiya.wang@mediatek.com> References: <20210316111443.3332-1-seiya.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org This commit adds dt-binding documentation of watchdog for Mediatek MT8195 SoC Platform. Signed-off-by: Seiya Wang --- Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt index e36ba60de829..a658a0b92b9a 100644 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt @@ -13,6 +13,7 @@ Required properties: "mediatek,mt8183-wdt": for MT8183 "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516 "mediatek,mt8192-wdt": for MT8192 + "mediatek,mt8195-wdt", "mediatek,mt6589-wdt": for MT8195 - reg : Specifies base physical address and size of the registers. From patchwork Tue Mar 16 11:14:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Seiya Wang X-Patchwork-Id: 402203 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC883C2BB4C for ; Tue, 16 Mar 2021 11:16:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C4D5D6502A for ; Tue, 16 Mar 2021 11:16:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237226AbhCPLQO (ORCPT ); Tue, 16 Mar 2021 07:16:14 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:49032 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S237159AbhCPLPg (ORCPT ); Tue, 16 Mar 2021 07:15:36 -0400 X-UUID: 674ce6305dfa4723a676d4675b0ec9d7-20210316 X-UUID: 674ce6305dfa4723a676d4675b0ec9d7-20210316 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2014399900; Tue, 16 Mar 2021 19:15:30 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 16 Mar 2021 19:15:28 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 16 Mar 2021 19:15:28 +0800 From: Seiya Wang To: Rob Herring , Matthias Brugger CC: Jonathan Cameron , Lars-Peter Clausen , Peter Meerwald-Stadler , Ulf Hansson , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Greg Kroah-Hartman , Mark Brown , Daniel Lezcano , Thomas Gleixner , Wim Van Sebroeck , Guenter Roeck , Enric Balletbo i Serra , Hsin-Yi Wang , Seiya Wang , Fabien Parent , Sean Wang , Zhiyong Tao , Chaotian Jing , Wenbin Mei , Stanley Chu , Bayi Cheng , Chuanhong Guo , , , , , , , , , , Subject: [PATCH 04/10] dt-bindings: mmc: Add compatible for Mediatek MT8195 Date: Tue, 16 Mar 2021 19:14:37 +0800 Message-ID: <20210316111443.3332-5-seiya.wang@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210316111443.3332-1-seiya.wang@mediatek.com> References: <20210316111443.3332-1-seiya.wang@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 40EFA065568D92D6DF6C39E654DC24CB95C56C62A7E2E2FEE8C06C69D71643032000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org This commit adds dt-binding documentation of mmc for Mediatek MT8195 SoC Platform. Signed-off-by: Seiya Wang --- Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml index 01630b0ecea7..8648d48dbbfd 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -31,6 +31,7 @@ properties: - const: mediatek,mt2701-mmc - items: - const: mediatek,mt8192-mmc + - const: mediatek,mt8195-mmc - const: mediatek,mt8183-mmc clocks: From patchwork Tue Mar 16 11:14:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Seiya Wang X-Patchwork-Id: 403717 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7D4EC433E9 for ; Tue, 16 Mar 2021 11:16:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8E78F65026 for ; Tue, 16 Mar 2021 11:16:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237230AbhCPLQP (ORCPT ); Tue, 16 Mar 2021 07:16:15 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:49095 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S237162AbhCPLPh (ORCPT ); Tue, 16 Mar 2021 07:15:37 -0400 X-UUID: baf2f9497ff34e92916c8c90d9008a51-20210316 X-UUID: baf2f9497ff34e92916c8c90d9008a51-20210316 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 280902845; Tue, 16 Mar 2021 19:15:33 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 16 Mar 2021 19:15:32 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 16 Mar 2021 19:15:32 +0800 From: Seiya Wang To: Rob Herring , Matthias Brugger CC: Jonathan Cameron , Lars-Peter Clausen , Peter Meerwald-Stadler , Ulf Hansson , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Greg Kroah-Hartman , Mark Brown , Daniel Lezcano , Thomas Gleixner , Wim Van Sebroeck , Guenter Roeck , Enric Balletbo i Serra , Hsin-Yi Wang , Seiya Wang , Fabien Parent , Sean Wang , Zhiyong Tao , Chaotian Jing , Wenbin Mei , Stanley Chu , Bayi Cheng , Chuanhong Guo , , , , , , , , , , Subject: [PATCH 05/10] dt-bindings: spi: Add compatible for Mediatek MT8195 Date: Tue, 16 Mar 2021 19:14:38 +0800 Message-ID: <20210316111443.3332-6-seiya.wang@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210316111443.3332-1-seiya.wang@mediatek.com> References: <20210316111443.3332-1-seiya.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org This commit adds dt-binding documentation of spi nor for Mediatek MT8195 SoC Platform. Signed-off-by: Seiya Wang --- Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml index 55c239446a5b..7393f30535df 100644 --- a/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml +++ b/Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml @@ -31,6 +31,7 @@ properties: - mediatek,mt7623-nor - mediatek,mt7629-nor - mediatek,mt8192-nor + - mediatek,mt8195-nor - enum: - mediatek,mt8173-nor - items: From patchwork Tue Mar 16 11:14:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Seiya Wang X-Patchwork-Id: 403716 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11178C2BB1F for ; Tue, 16 Mar 2021 11:16:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EF65F65027 for ; Tue, 16 Mar 2021 11:16:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231304AbhCPLQQ (ORCPT ); Tue, 16 Mar 2021 07:16:16 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:54331 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229686AbhCPLPm (ORCPT ); Tue, 16 Mar 2021 07:15:42 -0400 X-UUID: 1790d00b9f5e42f8b96766990c9e2341-20210316 X-UUID: 1790d00b9f5e42f8b96766990c9e2341-20210316 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 174938970; Tue, 16 Mar 2021 19:15:37 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 16 Mar 2021 19:15:35 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 16 Mar 2021 19:15:35 +0800 From: Seiya Wang To: Rob Herring , Matthias Brugger CC: Jonathan Cameron , Lars-Peter Clausen , Peter Meerwald-Stadler , Ulf Hansson , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Greg Kroah-Hartman , Mark Brown , Daniel Lezcano , Thomas Gleixner , Wim Van Sebroeck , Guenter Roeck , Enric Balletbo i Serra , Hsin-Yi Wang , Seiya Wang , Fabien Parent , Sean Wang , Zhiyong Tao , Chaotian Jing , Wenbin Mei , Stanley Chu , Bayi Cheng , Chuanhong Guo , , , , , , , , , , Subject: [PATCH 06/10] dt-bindings: iio: adc: Add compatible for Mediatek MT8195 Date: Tue, 16 Mar 2021 19:14:39 +0800 Message-ID: <20210316111443.3332-7-seiya.wang@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210316111443.3332-1-seiya.wang@mediatek.com> References: <20210316111443.3332-1-seiya.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org This commit adds dt-binding documentation of auxadc for Mediatek MT8195 SoC Platform. Signed-off-by: Seiya Wang --- Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml b/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml index 5b21a9fba5dd..b939f9652e3a 100644 --- a/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml @@ -34,6 +34,7 @@ properties: - items: - enum: - mediatek,mt8183-auxadc + - mediatek,mt8195-auxadc - mediatek,mt8516-auxadc - const: mediatek,mt8173-auxadc From patchwork Tue Mar 16 11:14:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Seiya Wang X-Patchwork-Id: 402202 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4986C4332B for ; Tue, 16 Mar 2021 11:16:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A4FDF65016 for ; Tue, 16 Mar 2021 11:16:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237236AbhCPLQR (ORCPT ); Tue, 16 Mar 2021 07:16:17 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:49173 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S237163AbhCPLPn (ORCPT ); Tue, 16 Mar 2021 07:15:43 -0400 X-UUID: f1a4022007bb4819ad7a605d5b39a2e9-20210316 X-UUID: f1a4022007bb4819ad7a605d5b39a2e9-20210316 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 30823269; Tue, 16 Mar 2021 19:15:39 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 16 Mar 2021 19:15:38 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 16 Mar 2021 19:15:38 +0800 From: Seiya Wang To: Rob Herring , Matthias Brugger CC: Jonathan Cameron , Lars-Peter Clausen , Peter Meerwald-Stadler , Ulf Hansson , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Greg Kroah-Hartman , Mark Brown , Daniel Lezcano , Thomas Gleixner , Wim Van Sebroeck , Guenter Roeck , Enric Balletbo i Serra , Hsin-Yi Wang , Seiya Wang , Fabien Parent , Sean Wang , Zhiyong Tao , Chaotian Jing , Wenbin Mei , Stanley Chu , Bayi Cheng , Chuanhong Guo , , , , , , , , , , Subject: [PATCH 07/10] dt-bindings: phy: Add compatible for Mediatek MT8195 Date: Tue, 16 Mar 2021 19:14:40 +0800 Message-ID: <20210316111443.3332-8-seiya.wang@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210316111443.3332-1-seiya.wang@mediatek.com> References: <20210316111443.3332-1-seiya.wang@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org This commit adds dt-binding documentation of T-Phy for Mediatek MT8195 SoC Platform. Signed-off-by: Seiya Wang --- Documentation/devicetree/bindings/phy/mediatek,tphy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml index 602e6ff45785..c5b436ad6239 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml @@ -79,6 +79,7 @@ properties: - mediatek,mt2712-tphy - mediatek,mt7629-tphy - mediatek,mt8183-tphy + - mediatek,mt8195-tphy - const: mediatek,generic-tphy-v2 - const: mediatek,mt2701-u3phy deprecated: true From patchwork Tue Mar 16 11:14:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Seiya Wang X-Patchwork-Id: 403715 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3019BC2BB4D for ; Tue, 16 Mar 2021 11:16:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 167166502D for ; Tue, 16 Mar 2021 11:16:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237243AbhCPLQR (ORCPT ); Tue, 16 Mar 2021 07:16:17 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:54413 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S233127AbhCPLPr (ORCPT ); Tue, 16 Mar 2021 07:15:47 -0400 X-UUID: 72df0c343868459cb5dc24a45721ee02-20210316 X-UUID: 72df0c343868459cb5dc24a45721ee02-20210316 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2049234079; Tue, 16 Mar 2021 19:15:43 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 16 Mar 2021 19:15:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 16 Mar 2021 19:15:41 +0800 From: Seiya Wang To: Rob Herring , Matthias Brugger CC: Jonathan Cameron , Lars-Peter Clausen , Peter Meerwald-Stadler , Ulf Hansson , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Greg Kroah-Hartman , Mark Brown , Daniel Lezcano , Thomas Gleixner , Wim Van Sebroeck , Guenter Roeck , Enric Balletbo i Serra , Hsin-Yi Wang , Seiya Wang , Fabien Parent , Sean Wang , Zhiyong Tao , Chaotian Jing , Wenbin Mei , Stanley Chu , Bayi Cheng , Chuanhong Guo , , , , , , , , , , Subject: [PATCH 08/10] dt-bindings: phy: Add compatible for Mediatek MT8195 Date: Tue, 16 Mar 2021 19:14:41 +0800 Message-ID: <20210316111443.3332-9-seiya.wang@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210316111443.3332-1-seiya.wang@mediatek.com> References: <20210316111443.3332-1-seiya.wang@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: E403C581C9AB4B436BEFED640EB0C314C96044C875937C9663CAB78296373CF32000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org This commit adds dt-binding documentation of UFS M-Phy for Mediatek MT8195 SoC Platform. Signed-off-by: Seiya Wang --- Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml index 3a9be82e7f13..5235b1a0d188 100644 --- a/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml @@ -22,6 +22,7 @@ properties: pattern: "^ufs-phy@[0-9a-f]+$" compatible: + enum: mediatek,mt8195-ufsphy const: mediatek,mt8183-ufsphy reg: From patchwork Tue Mar 16 11:14:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Seiya Wang X-Patchwork-Id: 402201 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D882C2BB85 for ; Tue, 16 Mar 2021 11:16:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 567CA65026 for ; Tue, 16 Mar 2021 11:16:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237250AbhCPLQU (ORCPT ); Tue, 16 Mar 2021 07:16:20 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:49255 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S237164AbhCPLPt (ORCPT ); Tue, 16 Mar 2021 07:15:49 -0400 X-UUID: 42179b8708ba47c39f044b8a965d052d-20210316 X-UUID: 42179b8708ba47c39f044b8a965d052d-20210316 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 212771105; Tue, 16 Mar 2021 19:15:46 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 16 Mar 2021 19:15:44 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 16 Mar 2021 19:15:44 +0800 From: Seiya Wang To: Rob Herring , Matthias Brugger CC: Jonathan Cameron , Lars-Peter Clausen , Peter Meerwald-Stadler , Ulf Hansson , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Greg Kroah-Hartman , Mark Brown , Daniel Lezcano , Thomas Gleixner , Wim Van Sebroeck , Guenter Roeck , Enric Balletbo i Serra , Hsin-Yi Wang , Seiya Wang , Fabien Parent , Sean Wang , Zhiyong Tao , Chaotian Jing , Wenbin Mei , Stanley Chu , Bayi Cheng , Chuanhong Guo , , , , , , , , , , Subject: [PATCH 09/10] dt-bindings: arm: Add compatible for Mediatek MT8195 Date: Tue, 16 Mar 2021 19:14:42 +0800 Message-ID: <20210316111443.3332-10-seiya.wang@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210316111443.3332-1-seiya.wang@mediatek.com> References: <20210316111443.3332-1-seiya.wang@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 8F886DB36CF4E8DFBAC87582214747023E00CBD53B2B5085642E423E236B81C62000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org This commit adds dt-binding documentation for the Mediatek MT8195 reference board. Signed-off-by: Seiya Wang --- Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 93b3bdf6eaeb..a95224fcff9f 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -118,6 +118,10 @@ properties: - enum: - mediatek,mt8183-evb - const: mediatek,mt8183 + - items: + - enum: + - mediatek,mt8195-evb + - const: mediatek,mt8195 - description: Google Krane (Lenovo IdeaPad Duet, 10e,...) items: - enum: From patchwork Tue Mar 16 11:14:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Seiya Wang X-Patchwork-Id: 403714 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81CA0C2BB9A for ; Tue, 16 Mar 2021 11:16:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6A0BE64FA5 for ; Tue, 16 Mar 2021 11:16:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237252AbhCPLQW (ORCPT ); Tue, 16 Mar 2021 07:16:22 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:54503 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S237165AbhCPLPy (ORCPT ); Tue, 16 Mar 2021 07:15:54 -0400 X-UUID: caee0172b9444f32ba568eb01bbdf3aa-20210316 X-UUID: caee0172b9444f32ba568eb01bbdf3aa-20210316 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1559240439; Tue, 16 Mar 2021 19:15:50 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 16 Mar 2021 19:15:47 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 16 Mar 2021 19:15:47 +0800 From: Seiya Wang To: Rob Herring , Matthias Brugger CC: Jonathan Cameron , Lars-Peter Clausen , Peter Meerwald-Stadler , Ulf Hansson , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Greg Kroah-Hartman , Mark Brown , Daniel Lezcano , Thomas Gleixner , Wim Van Sebroeck , Guenter Roeck , Enric Balletbo i Serra , Hsin-Yi Wang , Seiya Wang , Fabien Parent , Sean Wang , Zhiyong Tao , Chaotian Jing , Wenbin Mei , Stanley Chu , Bayi Cheng , Chuanhong Guo , , , , , , , , , , Subject: [PATCH 10/10] arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile Date: Tue, 16 Mar 2021 19:14:43 +0800 Message-ID: <20210316111443.3332-11-seiya.wang@mediatek.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20210316111443.3332-1-seiya.wang@mediatek.com> References: <20210316111443.3332-1-seiya.wang@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: B9DB7DD2E633F284CF959A8FEAC37E05E53E7C6ABFFA4583C0A63A2D61DF0A162000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Add basic chip support for Mediatek MT8195 Signed-off-by: Seiya Wang --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 29 ++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 477 ++++++++++++++++++++++++++++ 3 files changed, 507 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8195-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8195.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index deba27ab7657..aee4b9715d2f 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -16,4 +16,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts new file mode 100644 index 000000000000..82bb10e9a531 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Seiya Wang + */ +/dts-v1/; +#include "mt8195.dtsi" + +/ { + model = "MediaTek MT8195 evaluation board"; + compatible = "mediatek,mt8195-evb", "mediatek,mt8195"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi new file mode 100644 index 000000000000..356583fe4f03 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -0,0 +1,477 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Seiya Wang + */ + +/dts-v1/; + +#include +#include + +/ { + compatible = "mediatek,mt8195"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + clocks { + clk26m: oscillator0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + clk32k: oscillator1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "clk32k"; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55", "arm,armv8"; + reg = <0x000>; + enable-method = "psci"; + clock-frequency = <1701000000>; + capacity-dmips-mhz = <578>; + cpu-idle-states = <&cpuoff_l &clusteroff_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55", "arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + clock-frequency = <1701000000>; + capacity-dmips-mhz = <578>; + cpu-idle-states = <&cpuoff_l &clusteroff_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55", "arm,armv8"; + reg = <0x200>; + enable-method = "psci"; + clock-frequency = <1701000000>; + capacity-dmips-mhz = <578>; + cpu-idle-states = <&cpuoff_l &clusteroff_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55", "arm,armv8"; + reg = <0x300>; + enable-method = "psci"; + clock-frequency = <1701000000>; + capacity-dmips-mhz = <578>; + cpu-idle-states = <&cpuoff_l &clusteroff_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a78", "arm,armv8"; + reg = <0x400>; + enable-method = "psci"; + clock-frequency = <2171000000>; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&cpuoff_b &clusteroff_b>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a78", "arm,armv8"; + reg = <0x500>; + enable-method = "psci"; + clock-frequency = <2171000000>; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&cpuoff_b &clusteroff_b>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a78", "arm,armv8"; + reg = <0x600>; + enable-method = "psci"; + clock-frequency = <2171000000>; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&cpuoff_b &clusteroff_b>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a78", "arm,armv8"; + reg = <0x700>; + enable-method = "psci"; + clock-frequency = <2171000000>; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&cpuoff_b &clusteroff_b>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + idle-states { + entry-method = "arm,psci"; + cpuoff_l: cpuoff_l { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x00010001>; + local-timer-stop; + entry-latency-us = <50>; + exit-latency-us = <95>; + min-residency-us = <580>; + }; + cpuoff_b: cpuoff_b { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x00010001>; + local-timer-stop; + entry-latency-us = <45>; + exit-latency-us = <140>; + min-residency-us = <740>; + }; + clusteroff_l: clusteroff_l { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x01010002>; + local-timer-stop; + entry-latency-us = <55>; + exit-latency-us = <155>; + min-residency-us = <840>; + }; + clusteroff_b: clusteroff_b { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x01010002>; + local-timer-stop; + entry-latency-us = <50>; + exit-latency-us = <200>; + min-residency-us = <1000>; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + next-level-cache = <&l3_0>; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + next-level-cache = <&l3_0>; + }; + + l3_0: l3-cache { + compatible = "cache"; + }; + }; + + dsu-pmu { + compatible = "arm,dsu-pmu"; + interrupts = ; + cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, + <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + }; + + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupt-parent = <&gic>; + interrupts = ; + }; + + pmu-a78 { + compatible = "arm,cortex-a78-pmu"; + interrupt-parent = <&gic>; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer: timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + clock-frequency = <13000000>; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + #redistributor-regions = <1>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, + <0 0x0c040000 0 0x200000>; + interrupts = ; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; + }; + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; + }; + }; + }; + + watchdog: watchdog@10007000 { + compatible = "mediatek,mt8195-wdt", "mediatek,mt6589-wdt"; + reg = <0 0x10007000 0 0x100>; + }; + + systimer: timer@10017000 { + compatible = "mediatek,mt8195-timer", "mediatek,mt6765-timer"; + reg = <0 0x10017000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>; + }; + + uart0: serial@11001100 { + compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart"; + reg = <0 0x11001100 0 0x100>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11001200 { + compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart"; + reg = <0 0x11001200 0 0x100>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "baud", "bus"; + }; + + uart2: serial@11001300 { + compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart"; + reg = <0 0x11001300 0 0x100>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart3: serial@11001400 { + compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart"; + reg = <0 0x11001400 0 0x100>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart4: serial@11001500 { + compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart"; + reg = <0 0x11001500 0 0x100>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart5: serial@11001600 { + compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart"; + reg = <0 0x11001600 0 0x100>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + auxadc: auxadc@11002000 { + compatible = "mediatek,mt8195-auxadc", "mediatek,mt8173-auxadc"; + reg = <0 0x11002000 0 0x1000>; + clocks = <&clk26m>; + clock-names = "main"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc"; + reg = <0 0x11230000 0 0x10000>, + <0 0x11f50000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>, <&clk26m>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc"; + reg = <0 0x11240000 0 0x1000>, + <0 0x11c70000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>, <&clk26m>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + nor_flash: nor@1132c000 { + compatible = "mediatek,mt8195-nor", "mediatek,mt8173-nor"; + reg = <0 0x1132c000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&clk26m>; + clock-names = "spi", "sf"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + u3phy2: usb-phy2@11c40000 { + compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2"; + clocks = <&clk26m>; + clock-names = "u3phya_ref"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11c40000 0x700>; + status = "disabled"; + + u2port2: usb2-phy2@0 { + reg = <0x0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "disabled"; + }; + }; + + u3phy3: usb-phy3@11c50000 { + compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2"; + clocks = <&clk26m>; + clock-names = "u3phya_ref"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11c50000 0x700>; + status = "disabled"; + + u2port3: usb2-phy3@0 { + reg = <0x0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "disabled"; + }; + }; + + u3phy1: usb-phy1@11e30000 { + compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2"; + clocks = <&clk26m>; + clock-names = "u3phya_ref"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11e30000 0xe00>; + status = "disabled"; + + u2port1: usb2-phy1@0 { + reg = <0x0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "disabled"; + }; + + u3port1: usb3-phy1@700 { + reg = <0x700 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "disabled"; + }; + }; + + u3phy0: usb-phy0@11e40000 { + compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2"; + clocks = <&clk26m>; + clock-names = "u3phya_ref"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11e40000 0xe00>; + status = "disabled"; + + u2port0: usb2-phy0@0 { + reg = <0x0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "disabled"; + }; + + u3port0: usb3-phy0@700 { + reg = <0x700 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "disabled"; + }; + }; + + ufsphy: phy@11fa0000 { + compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; + reg = <0 0x11fa0000 0 0xc000>; + clocks = <&clk26m>, <&clk26m>; + clock-names = "unipro", "mp"; + #phy-cells = <0>; + }; + }; +};