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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id y24-v6sm4216728pfn.23.2018.05.10.17.43.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 17:43:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 17:43:27 -0700 Message-Id: <20180511004345.26708-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511004345.26708-1-richard.henderson@linaro.org> References: <20180511004345.26708-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH 01/19] fpu/softfloat: Merge NO_SIGNALING_NANS definitions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the ifdef inside the relevant functions instead of duplicating the function declarations. Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 100 +++++++++++++++---------------------- 1 file changed, 40 insertions(+), 60 deletions(-) -- 2.17.0 Reviewed-by: Alex Bennée diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index a20b440159..8bd553abd2 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -233,17 +233,6 @@ typedef struct { uint64_t high, low; } commonNaNT; -#ifdef NO_SIGNALING_NANS -int float16_is_quiet_nan(float16 a_, float_status *status) -{ - return float16_is_any_nan(a_); -} - -int float16_is_signaling_nan(float16 a_, float_status *status) -{ - return 0; -} -#else /*---------------------------------------------------------------------------- | Returns 1 if the half-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -251,12 +240,16 @@ int float16_is_signaling_nan(float16 a_, float_status *status) int float16_is_quiet_nan(float16 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return float16_is_any_nan(a_); +#else uint16_t a = float16_val(a_); if (status->snan_bit_is_one) { return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); } else { return ((a & ~0x8000) >= 0x7C80); } +#endif } /*---------------------------------------------------------------------------- @@ -266,14 +259,17 @@ int float16_is_quiet_nan(float16 a_, float_status *status) int float16_is_signaling_nan(float16 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return 0; +#else uint16_t a = float16_val(a_); if (status->snan_bit_is_one) { return ((a & ~0x8000) >= 0x7C80); } else { return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); } -} #endif +} /*---------------------------------------------------------------------------- | Returns a quiet NaN if the half-precision floating point value `a' is a @@ -293,17 +289,6 @@ float16 float16_maybe_silence_nan(float16 a_, float_status *status) return a_; } -#ifdef NO_SIGNALING_NANS -int float32_is_quiet_nan(float32 a_, float_status *status) -{ - return float32_is_any_nan(a_); -} - -int float32_is_signaling_nan(float32 a_, float_status *status) -{ - return 0; -} -#else /*---------------------------------------------------------------------------- | Returns 1 if the single-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -311,12 +296,16 @@ int float32_is_signaling_nan(float32 a_, float_status *status) int float32_is_quiet_nan(float32 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return float32_is_any_nan(a_); +#else uint32_t a = float32_val(a_); if (status->snan_bit_is_one) { return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); } else { return ((uint32_t)(a << 1) >= 0xFF800000); } +#endif } /*---------------------------------------------------------------------------- @@ -326,14 +315,17 @@ int float32_is_quiet_nan(float32 a_, float_status *status) int float32_is_signaling_nan(float32 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return 0; +#else uint32_t a = float32_val(a_); if (status->snan_bit_is_one) { return ((uint32_t)(a << 1) >= 0xFF800000); } else { return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); } -} #endif +} /*---------------------------------------------------------------------------- | Returns a quiet NaN if the single-precision floating point value `a' is a @@ -704,17 +696,6 @@ static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status) } } -#ifdef NO_SIGNALING_NANS -int float64_is_quiet_nan(float64 a_, float_status *status) -{ - return float64_is_any_nan(a_); -} - -int float64_is_signaling_nan(float64 a_, float_status *status) -{ - return 0; -} -#else /*---------------------------------------------------------------------------- | Returns 1 if the double-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -722,6 +703,9 @@ int float64_is_signaling_nan(float64 a_, float_status *status) int float64_is_quiet_nan(float64 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return float64_is_any_nan(a_); +#else uint64_t a = float64_val(a_); if (status->snan_bit_is_one) { return (((a >> 51) & 0xFFF) == 0xFFE) @@ -729,6 +713,7 @@ int float64_is_quiet_nan(float64 a_, float_status *status) } else { return ((a << 1) >= 0xFFF0000000000000ULL); } +#endif } /*---------------------------------------------------------------------------- @@ -738,6 +723,9 @@ int float64_is_quiet_nan(float64 a_, float_status *status) int float64_is_signaling_nan(float64 a_, float_status *status) { +#ifdef NO_SIGNALING_NANS + return 0; +#else uint64_t a = float64_val(a_); if (status->snan_bit_is_one) { return ((a << 1) >= 0xFFF0000000000000ULL); @@ -745,8 +733,8 @@ int float64_is_signaling_nan(float64 a_, float_status *status) return (((a >> 51) & 0xFFF) == 0xFFE) && (a & LIT64(0x0007FFFFFFFFFFFF)); } -} #endif +} /*---------------------------------------------------------------------------- | Returns a quiet NaN if the double-precision floating point value `a' is a @@ -859,17 +847,6 @@ static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status) } } -#ifdef NO_SIGNALING_NANS -int floatx80_is_quiet_nan(floatx80 a_, float_status *status) -{ - return floatx80_is_any_nan(a_); -} - -int floatx80_is_signaling_nan(floatx80 a_, float_status *status) -{ - return 0; -} -#else /*---------------------------------------------------------------------------- | Returns 1 if the extended double-precision floating-point value `a' is a | quiet NaN; otherwise returns 0. This slightly differs from the same @@ -878,6 +855,9 @@ int floatx80_is_signaling_nan(floatx80 a_, float_status *status) int floatx80_is_quiet_nan(floatx80 a, float_status *status) { +#ifdef NO_SIGNALING_NANS + return floatx80_is_any_nan(a); +#else if (status->snan_bit_is_one) { uint64_t aLow; @@ -889,6 +869,7 @@ int floatx80_is_quiet_nan(floatx80 a, float_status *status) return ((a.high & 0x7FFF) == 0x7FFF) && (LIT64(0x8000000000000000) <= ((uint64_t)(a.low << 1))); } +#endif } /*---------------------------------------------------------------------------- @@ -899,6 +880,9 @@ int floatx80_is_quiet_nan(floatx80 a, float_status *status) int floatx80_is_signaling_nan(floatx80 a, float_status *status) { +#ifdef NO_SIGNALING_NANS + return 0; +#else if (status->snan_bit_is_one) { return ((a.high & 0x7FFF) == 0x7FFF) && ((a.low << 1) >= 0x8000000000000000ULL); @@ -910,8 +894,8 @@ int floatx80_is_signaling_nan(floatx80 a, float_status *status) && (uint64_t)(aLow << 1) && (a.low == aLow); } -} #endif +} /*---------------------------------------------------------------------------- | Returns a quiet NaN if the extended double-precision floating point value @@ -1020,17 +1004,6 @@ floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) } } -#ifdef NO_SIGNALING_NANS -int float128_is_quiet_nan(float128 a_, float_status *status) -{ - return float128_is_any_nan(a_); -} - -int float128_is_signaling_nan(float128 a_, float_status *status) -{ - return 0; -} -#else /*---------------------------------------------------------------------------- | Returns 1 if the quadruple-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -1038,6 +1011,9 @@ int float128_is_signaling_nan(float128 a_, float_status *status) int float128_is_quiet_nan(float128 a, float_status *status) { +#ifdef NO_SIGNALING_NANS + return float128_is_any_nan(a); +#else if (status->snan_bit_is_one) { return (((a.high >> 47) & 0xFFFF) == 0xFFFE) && (a.low || (a.high & 0x00007FFFFFFFFFFFULL)); @@ -1045,6 +1021,7 @@ int float128_is_quiet_nan(float128 a, float_status *status) return ((a.high << 1) >= 0xFFFF000000000000ULL) && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); } +#endif } /*---------------------------------------------------------------------------- @@ -1054,6 +1031,9 @@ int float128_is_quiet_nan(float128 a, float_status *status) int float128_is_signaling_nan(float128 a, float_status *status) { +#ifdef NO_SIGNALING_NANS + return 0; +#else if (status->snan_bit_is_one) { return ((a.high << 1) >= 0xFFFF000000000000ULL) && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); @@ -1061,8 +1041,8 @@ int float128_is_signaling_nan(float128 a, float_status *status) return (((a.high >> 47) & 0xFFFF) == 0xFFFE) && (a.low || (a.high & LIT64(0x00007FFFFFFFFFFF))); } -} #endif +} /*---------------------------------------------------------------------------- | Returns a quiet NaN if the quadruple-precision floating point value `a' is From patchwork Fri May 11 00:43:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135447 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp246195lji; Thu, 10 May 2018 17:47:45 -0700 (PDT) X-Google-Smtp-Source: AB8JxZo1EkETTVASdXJlffhTTmyepklbQhmSyUm95C8IHIT+n7zSegkRFIrcWnixfzBYQBF8okzT X-Received: by 2002:a37:a085:: with SMTP id j127-v6mr3130432qke.18.1525999665447; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id y24-v6sm4216728pfn.23.2018.05.10.17.43.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 17:43:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 17:43:28 -0700 Message-Id: <20180511004345.26708-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511004345.26708-1-richard.henderson@linaro.org> References: <20180511004345.26708-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH 02/19] fpu/softfloat: Split floatXX_silence_nan from floatXX_maybe_silence_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The new function assumes that the input is an SNaN and does not double-check. Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 174 +++++++++++++++++++++++++------------ include/fpu/softfloat.h | 5 ++ 2 files changed, 123 insertions(+), 56 deletions(-) -- 2.17.0 Reviewed-by: Alex Bennée diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 8bd553abd2..b59356f6a5 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -271,22 +271,35 @@ int float16_is_signaling_nan(float16 a_, float_status *status) #endif } +/*---------------------------------------------------------------------------- +| Returns a quiet NaN from a signalling NaN for the half-precision +| floating point value `a'. +*----------------------------------------------------------------------------*/ + +float16 float16_silence_nan(float16 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#else + if (status->snan_bit_is_one) { + return float16_default_nan(status); + } else { + return a | (1 << 9); + } +#endif +} + /*---------------------------------------------------------------------------- | Returns a quiet NaN if the half-precision floating point value `a' is a | signaling NaN; otherwise returns `a'. *----------------------------------------------------------------------------*/ -float16 float16_maybe_silence_nan(float16 a_, float_status *status) + +float16 float16_maybe_silence_nan(float16 a, float_status *status) { - if (float16_is_signaling_nan(a_, status)) { - if (status->snan_bit_is_one) { - return float16_default_nan(status); - } else { - uint16_t a = float16_val(a_); - a |= (1 << 9); - return make_float16(a); - } + if (float16_is_signaling_nan(a, status)) { + float16_silence_nan(a, status); } - return a_; + return a; } /*---------------------------------------------------------------------------- @@ -327,30 +340,40 @@ int float32_is_signaling_nan(float32 a_, float_status *status) #endif } +/*---------------------------------------------------------------------------- +| Returns a quiet NaN from a signalling NaN for the single-precision +| floating point value `a'. +*----------------------------------------------------------------------------*/ + +float32 float32_silence_nan(float32 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#else + if (status->snan_bit_is_one) { +# ifdef TARGET_HPPA + a &= ~0x00400000; + a |= 0x00200000; + return a; +# else + return float32_default_nan(status); +# endif + } else { + return a | (1 << 22); + } +#endif +} /*---------------------------------------------------------------------------- | Returns a quiet NaN if the single-precision floating point value `a' is a | signaling NaN; otherwise returns `a'. *----------------------------------------------------------------------------*/ -float32 float32_maybe_silence_nan(float32 a_, float_status *status) +float32 float32_maybe_silence_nan(float32 a, float_status *status) { - if (float32_is_signaling_nan(a_, status)) { - if (status->snan_bit_is_one) { -#ifdef TARGET_HPPA - uint32_t a = float32_val(a_); - a &= ~0x00400000; - a |= 0x00200000; - return make_float32(a); -#else - return float32_default_nan(status); -#endif - } else { - uint32_t a = float32_val(a_); - a |= (1 << 22); - return make_float32(a); - } + if (float32_is_signaling_nan(a, status)) { + float32_silence_nan(a, status); } - return a_; + return a; } /*---------------------------------------------------------------------------- @@ -736,30 +759,41 @@ int float64_is_signaling_nan(float64 a_, float_status *status) #endif } +/*---------------------------------------------------------------------------- +| Returns a quiet NaN from a signalling NaN for the double-precision +| floating point value `a'. +*----------------------------------------------------------------------------*/ + +float64 float64_silence_nan(float64 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#else + if (status->snan_bit_is_one) { +# ifdef TARGET_HPPA + a &= ~0x0008000000000000ULL; + a |= 0x0004000000000000ULL; + return a; +# else + return float64_default_nan(status); +# endif + } else { + return a | LIT64(0x0008000000000000); + } +#endif +} + /*---------------------------------------------------------------------------- | Returns a quiet NaN if the double-precision floating point value `a' is a | signaling NaN; otherwise returns `a'. *----------------------------------------------------------------------------*/ -float64 float64_maybe_silence_nan(float64 a_, float_status *status) +float64 float64_maybe_silence_nan(float64 a, float_status *status) { - if (float64_is_signaling_nan(a_, status)) { - if (status->snan_bit_is_one) { -#ifdef TARGET_HPPA - uint64_t a = float64_val(a_); - a &= ~0x0008000000000000ULL; - a |= 0x0004000000000000ULL; - return make_float64(a); -#else - return float64_default_nan(status); -#endif - } else { - uint64_t a = float64_val(a_); - a |= LIT64(0x0008000000000000); - return make_float64(a); - } + if (float64_is_signaling_nan(a, status)) { + return float64_silence_nan(a, status); } - return a_; + return a; } /*---------------------------------------------------------------------------- @@ -897,6 +931,25 @@ int floatx80_is_signaling_nan(floatx80 a, float_status *status) #endif } +/*---------------------------------------------------------------------------- +| Returns a quiet NaN from a signalling NaN for the extended double-precision +| floating point value `a'. +*----------------------------------------------------------------------------*/ + +floatx80 floatx80_silence_nan(floatx80 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#else + if (status->snan_bit_is_one) { + return floatx80_default_nan(status); + } else { + a.low |= LIT64(0xC000000000000000); + return a; + } +#endif +} + /*---------------------------------------------------------------------------- | Returns a quiet NaN if the extended double-precision floating point value | `a' is a signaling NaN; otherwise returns `a'. @@ -905,12 +958,7 @@ int floatx80_is_signaling_nan(floatx80 a, float_status *status) floatx80 floatx80_maybe_silence_nan(floatx80 a, float_status *status) { if (floatx80_is_signaling_nan(a, status)) { - if (status->snan_bit_is_one) { - a = floatx80_default_nan(status); - } else { - a.low |= LIT64(0xC000000000000000); - return a; - } + return floatx80_silence_nan(a, status); } return a; } @@ -1044,6 +1092,25 @@ int float128_is_signaling_nan(float128 a, float_status *status) #endif } +/*---------------------------------------------------------------------------- +| Returns a quiet NaN from a signalling NaN for the quadruple-precision +| floating point value `a'. +*----------------------------------------------------------------------------*/ + +float128 float128_silence_nan(float128 a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#else + if (status->snan_bit_is_one) { + return float128_default_nan(status); + } else { + a.high |= LIT64(0x0000800000000000); + return a; + } +#endif +} + /*---------------------------------------------------------------------------- | Returns a quiet NaN if the quadruple-precision floating point value `a' is | a signaling NaN; otherwise returns `a'. @@ -1052,12 +1119,7 @@ int float128_is_signaling_nan(float128 a, float_status *status) float128 float128_maybe_silence_nan(float128 a, float_status *status) { if (float128_is_signaling_nan(a, status)) { - if (status->snan_bit_is_one) { - a = float128_default_nan(status); - } else { - a.high |= LIT64(0x0000800000000000); - return a; - } + return float128_silence_nan(a, status); } return a; } diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 01ef1c6b81..a6860e858d 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -257,6 +257,7 @@ int float16_compare_quiet(float16, float16, float_status *status); int float16_is_quiet_nan(float16, float_status *status); int float16_is_signaling_nan(float16, float_status *status); +float16 float16_silence_nan(float16, float_status *status); float16 float16_maybe_silence_nan(float16, float_status *status); static inline int float16_is_any_nan(float16 a) @@ -368,6 +369,7 @@ float32 float32_minnummag(float32, float32, float_status *status); float32 float32_maxnummag(float32, float32, float_status *status); int float32_is_quiet_nan(float32, float_status *status); int float32_is_signaling_nan(float32, float_status *status); +float32 float32_silence_nan(float32, float_status *status); float32 float32_maybe_silence_nan(float32, float_status *status); float32 float32_scalbn(float32, int, float_status *status); @@ -497,6 +499,7 @@ float64 float64_minnummag(float64, float64, float_status *status); float64 float64_maxnummag(float64, float64, float_status *status); int float64_is_quiet_nan(float64 a, float_status *status); int float64_is_signaling_nan(float64, float_status *status); +float64 float64_silence_nan(float64, float_status *status); float64 float64_maybe_silence_nan(float64, float_status *status); float64 float64_scalbn(float64, int, float_status *status); @@ -600,6 +603,7 @@ int floatx80_compare(floatx80, floatx80, float_status *status); int floatx80_compare_quiet(floatx80, floatx80, float_status *status); int floatx80_is_quiet_nan(floatx80, float_status *status); int floatx80_is_signaling_nan(floatx80, float_status *status); +floatx80 floatx80_silence_nan(floatx80, float_status *status); floatx80 floatx80_maybe_silence_nan(floatx80, float_status *status); floatx80 floatx80_scalbn(floatx80, int, float_status *status); @@ -811,6 +815,7 @@ int float128_compare(float128, float128, float_status *status); int float128_compare_quiet(float128, float128, float_status *status); int float128_is_quiet_nan(float128, float_status *status); int float128_is_signaling_nan(float128, float_status *status); +float128 float128_silence_nan(float128, float_status *status); float128 float128_maybe_silence_nan(float128, float_status *status); float128 float128_scalbn(float128, int, float_status *status); From patchwork Fri May 11 00:43:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135448 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp247778lji; Thu, 10 May 2018 17:50:14 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrEUeTvsviUeGqaY0ZyTDFJj9Df0PygOFlJi7s0lkSkzTEiBsS5WPQB2WIKHnbc4o0hYY2t X-Received: by 2002:a37:a94f:: with SMTP id s76-v6mr3111899qke.284.1525999814173; Thu, 10 May 2018 17:50:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525999814; cv=none; d=google.com; s=arc-20160816; b=z1PCJERPFz3d9Yg5QVFZjGw6ilUuVy8H6AOv/I8Pu+2C6kIdeXo/yXgPRriIMOCAYX fhxOGt4uUOHxIHeRBTIYpOaF0Qg6FqKB4ze6PrArhfcUmpHj366fCsJr1OGmCfUGf3uq p8B0Jz2hV5CgS+AsizccCA74HZbEWiKB2N6Ok5lewIHzOjNJIET/301xXErt96z/7+gb AOtpCHWeiqK6uzbGC63+mTIyeROwd85Pn5Q67ulTCwE/zW4s2C1BOKsgM8TaVi3fibKl VltNe45Rzu/5jQ0ikfmJVmjIBLnAKFXTgMpGhq+frwVZDI5e26ZdVQr6J23KjpXYbarj IYpQ== ARC-Message-Signature: i=1; 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X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PATCH 03/19] fpu/softfloat: Move softfloat-specialize.h below FloatParts definition X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We want to be able to specialize on the canonical representation. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) -- 2.17.0 Reviewed-by: Alex Bennée diff --git a/fpu/softfloat.c b/fpu/softfloat.c index e7c8213a5e..5e4982b035 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -95,16 +95,6 @@ this code that are retained. *----------------------------------------------------------------------------*/ #include "fpu/softfloat-macros.h" -/*---------------------------------------------------------------------------- -| Functions and definitions to determine: (1) whether tininess for underflow -| is detected before or after rounding by default, (2) what (if anything) -| happens when exceptions are raised, (3) how signaling NaNs are distinguished -| from quiet NaNs, (4) the default generated quiet NaNs, and (5) how NaNs -| are propagated from function inputs to output. These details are target- -| specific. -*----------------------------------------------------------------------------*/ -#include "softfloat-specialize.h" - /*---------------------------------------------------------------------------- | Returns the fraction bits of the half-precision floating-point value `a'. *----------------------------------------------------------------------------*/ @@ -241,6 +231,16 @@ typedef struct { bool arm_althp; } FloatFmt; +/*---------------------------------------------------------------------------- +| Functions and definitions to determine: (1) whether tininess for underflow +| is detected before or after rounding by default, (2) what (if anything) +| happens when exceptions are raised, (3) how signaling NaNs are distinguished +| from quiet NaNs, (4) the default generated quiet NaNs, and (5) how NaNs +| are propagated from function inputs to output. These details are target- +| specific. +*----------------------------------------------------------------------------*/ +#include "softfloat-specialize.h" + /* Expand fields based on the size of exponent and fraction */ #define FLOAT_PARAMS(E, F) \ .exp_size = E, \ From patchwork Fri May 11 00:43:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135445 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp245876lji; Thu, 10 May 2018 17:47:13 -0700 (PDT) X-Google-Smtp-Source: AB8JxZonmHfq6+qYes7xMoNBqOXgs9HGSiT1+zXPpesqHWURMlEYYVSKrg2vFOAIdVXVHrDcT5iK X-Received: by 2002:aed:2984:: with SMTP id o4-v6mr3560441qtd.124.1525999632916; Thu, 10 May 2018 17:47:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525999632; cv=none; d=google.com; s=arc-20160816; b=XhpM2XEz4kqO6W+t68aIJdXP8Nz+ZMWgiKHquLxExn/YVFJ7nBE6i9Q9gjfzAhXQOi DZLdKSg1FHP0MHkH+a8U95f7yJIQqTW+zwpMaB37LjW+QUDmUdrGwaFJO6mD2RBUk57W WmRoKqUxFNiTazjWKLCTyDrRarUOVf3bQ2KZPnHoxUKOSza6jKIQfiNnDmbYvMByG0Ng /HrBaNXsYHzrTtyBae5PNzwY03Mt/rDTLzR+2rE+HCaDyOCNZ6taa+Dwv1dO24h22TEy T3/l+lz9/8xzc+cbo18lq0JZoaLHdl+IrEo1WQGqPDSBIbnj46F7baRHandlcT+k0zWM vjCQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=xs8P5M7KpsqqVNlyQrI1ugiUrrNAY5zDyuoghvVlkBg=; b=aGaNzQ3az1u9zWKJ/hzqQBAMJNAVLIMNdx6xvLfTmSImsMpsIHsrAEkP0KQ3u0nFWa fPnS6hRoNY//zV0KSYOHHdCUzwOYWX6KzU/4LOH2p5Aef8XPGJFf8vv1xjQoUdG2VjQ/ L8lrsXWRl7mePNyCFRMcLmh7mZzbCQzgFEoAAEawQGE4Tv254EjGCCIOEN3sQSFGiEh6 bHaBQooJel5jeKfeixjLZZkIFU1rVL02vxUEZiJEsX6w7yC+FAb7YHd1QeGaVEeE5nUC hLTAQYHhmhpntA4TuaUPEoRJ0t2naQdD29gWRTwEuETs3p8ctGkYoeZC7gMf1oY+QZuc fxQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HhNlsV8i; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id y24-v6sm4216728pfn.23.2018.05.10.17.43.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 17:43:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 17:43:30 -0700 Message-Id: <20180511004345.26708-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511004345.26708-1-richard.henderson@linaro.org> References: <20180511004345.26708-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH 04/19] fpu/softfloat: Canonicalize NaN fraction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Shift the NaN fraction to a canonical position, much like we do for the fraction of normal numbers. Immediately, this simplifies the float-to-float conversion. Later, this will facilitate manipulation of NaNs within the shared code paths. Signed-off-by: Richard Henderson --- fpu/softfloat.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 5e4982b035..df377b6314 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -329,10 +329,11 @@ static FloatParts canonicalize(FloatParts part, const FloatFmt *parm, if (part.frac == 0) { part.cls = float_class_inf; } else { + part.frac <<= parm->frac_shift; #ifdef NO_SIGNALING_NANS part.cls = float_class_qnan; #else - int64_t msb = part.frac << (parm->frac_shift + 2); + int64_t msb = part.frac << 2; if ((msb < 0) == status->snan_bit_is_one) { part.cls = float_class_snan; } else { @@ -498,6 +499,7 @@ static FloatParts round_canonical(FloatParts p, float_status *s, case float_class_qnan: case float_class_snan: exp = exp_max; + frac >>= parm->frac_shift; break; default: @@ -1264,13 +1266,10 @@ static FloatParts float_to_float(FloatParts a, } /* - * Our only option now is to "re-pack" the NaN. As the - * canonilization process doesn't mess with fraction bits for - * NaNs we do it all here. We also reset a.exp to the - * destination format exp_max as the maybe_silence_nan code - * assumes it is correct (which is would be for non-conversions). + * Reset a.exp to the destination format exp_max as + * the maybe_silence_nan code assumes it is correct + * (which it would be for non-conversions). */ - a.frac = a.frac << (64 - srcf->frac_size) >> (64 - dstf->frac_size); a.exp = dstf->exp_max; a.cls = float_class_msnan; } From patchwork Fri May 11 00:43:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135449 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp247793lji; Thu, 10 May 2018 17:50:14 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpHP1CKJeZ2fVV7pbDu79vhgowTlf6nSfdRSlb7YdiY7X8CIEr+87F5oVJ3G7S82TwUyIOj X-Received: by 2002:aed:37a6:: with SMTP id j35-v6mr3489250qtb.323.1525999814684; Thu, 10 May 2018 17:50:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525999814; cv=none; d=google.com; s=arc-20160816; b=K22KkTgqQ01juuG8LN8sf8ipgLTDCzxz94SPxlvzLE8aawdwkjZ1QbvYmxBEXec8m8 EnmGySYW6azrOCNhn/imh5twc/ztUFXvDVC6cFCbCj7/wDf26dHsgAOvvN0Wjvh/5epr WouFOvKNHe6g8tYmNB3r6JZjC0V3fpWbS3Ywu6PFavJ9TrdWVcsra5QVLG/LWYpqONAb 5eO8oufjc5kaf6AETVvq6QDqZPpNlW3TY4iPNH4bZCx+8d1PXEnWZKVazGmMtJgd74HE ga5FFxoabH5CmGlHfg0GBsW9iVvMzlxBMpSHGTz82z9n24/amTRyCmbsSIE8MFRjVdFJ HF5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=lRf4yJ1cSXJuJwZa6kKK3WAqrniWqnrrAqqQnzy7Auw=; b=t5otgPpHEqkpGst5fb8ahknFj3IEnIGvEJ7ZvpqdrwZzMAK+sVt0wpDIwqsY/zyAQL ET3wZr1L4C3w8r84c8BegN84cHreRSO6YO0BM0JtRahz13QHgBZvBJ0U/IVHoA+usnLF ZZAulRzbxdMIxXAbp3W1UwA5F/j08iisyWlOk5vdfeAd4I6znEMJ8pRv3FZgb0ONb7n6 WyKqgyAXQKHdrGFCYZhebde46iLpZ1Zo6nJ3gRR1NxN55wT3WxX6Q7Gt5MilHJSh2uRo 8jiIkN0jvjopO/fHX3lp4nMDegP/S5PNwWgMxe1KMZ2A4mtUytvABOebdjzQHyvy5JdE VipA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Fprt7CFH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id y24-v6sm4216728pfn.23.2018.05.10.17.43.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 17:43:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 17:43:31 -0700 Message-Id: <20180511004345.26708-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511004345.26708-1-richard.henderson@linaro.org> References: <20180511004345.26708-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH 05/19] fpu/softfloat: Introduce parts_is_snan_frac X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 15 +++++++++++++++ fpu/softfloat.c | 12 ++---------- 2 files changed, 17 insertions(+), 10 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index b59356f6a5..82d7a030e7 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -86,6 +86,21 @@ this code that are retained. #define NO_SIGNALING_NANS 1 #endif +/*---------------------------------------------------------------------------- +| For the deconstructed floating-point with fraction FRAC, return true +| if the fraction represents a signalling NaN; otherwise false. +*----------------------------------------------------------------------------*/ + +static bool parts_is_snan_frac(uint64_t frac, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + return false; +#else + flag msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1); + return msb == status->snan_bit_is_one; +#endif +} + /*---------------------------------------------------------------------------- | The pattern for a default generated half-precision NaN. *----------------------------------------------------------------------------*/ diff --git a/fpu/softfloat.c b/fpu/softfloat.c index df377b6314..6dfc992a7f 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -330,16 +330,8 @@ static FloatParts canonicalize(FloatParts part, const FloatFmt *parm, part.cls = float_class_inf; } else { part.frac <<= parm->frac_shift; -#ifdef NO_SIGNALING_NANS - part.cls = float_class_qnan; -#else - int64_t msb = part.frac << 2; - if ((msb < 0) == status->snan_bit_is_one) { - part.cls = float_class_snan; - } else { - part.cls = float_class_qnan; - } -#endif + part.cls = (parts_is_snan_frac(part.frac, status) + ? float_class_snan : float_class_qnan); } } else if (part.exp == 0) { if (likely(part.frac == 0)) { From patchwork Fri May 11 00:43:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135451 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp248125lji; Thu, 10 May 2018 17:50:47 -0700 (PDT) X-Google-Smtp-Source: AB8JxZryZF/l6Ay6nyjfvmVuLBSxYYBXgo8mh2+9cnPJ4nOiaNyOF3LeIq75KzmLafm1dBe4OOIC X-Received: by 2002:a37:4f10:: with SMTP id d16-v6mr3139345qkb.50.1525999847407; Thu, 10 May 2018 17:50:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525999847; cv=none; d=google.com; s=arc-20160816; b=iuK7AqpcpAkcTuqULxt9l1zKaJ+oTNEjf2A9H9hP1IB9R40n1eCvonEi9ARjsizHVu o/tqSM4bAjrr+Cw5QUtEKS2niCr8155qjFcp15oNnOs/8aeoYu8VftP+vj6R/GIsItKs kKjYfckDNXGN78ihd9E3ME0aTizaf949O9Inx4s/Wl5AOtbxcvUr3Wa/HN8cw84S8B+8 G1ExKqgR+epZJlvO/ztPvV65ewXE1nfSkRxWua6PGuwgIIAFe3zMtDz678mdLDrNg2rd c3+ru1LWT8O5SDtjGHJCd3PQ7kMtcZV8qzqYdixXjCaNMk9/O30g8yBstpa7uSl8UOdd Itmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=tFLJR1pEbvSdgTdtmGzVTsnU5+kht680tv9A+aKFDJs=; b=VrzJztPCX14WeE+ao8MdWLbYDcDzJQltQJhP8nSfqbWOjr+O7U0X4Gy+fB1REPP8Kt ce+L/z/P8VbaIBh7v7G44eX3oAZqfYfHgbcjwuQBJRQj4Dg/CKMp9G1iIvd1YOwSr48E 4FMr427rC795wm09ZNriw5RGNBE1TmAlzXatQUIGegTS1QnXT+6V17iW2x6CwEcts74w Mnd4d3vQ3zKzPZO2+mtGCTtTEs2Sw2nw555AHbu62h9LzaMWia/cJYRyF5JJUtFBVB+5 lI624EuI47aXK5GG5GXalbqKO/djnx+9pwk3Oh2Dn6RQkV1a5IhhTlLRULyUbkTcK0nL VuNg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=g9rLRavy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id y24-v6sm4216728pfn.23.2018.05.10.17.43.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 17:43:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 17:43:32 -0700 Message-Id: <20180511004345.26708-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511004345.26708-1-richard.henderson@linaro.org> References: <20180511004345.26708-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH 06/19] fpu/softfloat: Replace float_class_dnan with parts_default_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" With a canonical representation of NaNs, we can return the default nan directly rather than delay the expansion until the final format is known. Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 37 +++++++++++++++++++++++++++++++++++++ fpu/softfloat.c | 38 ++++++++++++-------------------------- 2 files changed, 49 insertions(+), 26 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 82d7a030e7..2ad524b11e 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -101,6 +101,43 @@ static bool parts_is_snan_frac(uint64_t frac, float_status *status) #endif } +/*---------------------------------------------------------------------------- +| The pattern for a default generated deconstructed floating-point NaN. +*----------------------------------------------------------------------------*/ + +static FloatParts parts_default_nan(float_status *status) +{ + bool sign = 0; + uint64_t frac; + +#if defined(TARGET_SPARC) || defined(TARGET_M68K) + frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1; +#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \ + defined(TARGET_S390X) || defined(TARGET_RISCV) + frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); +#elif defined(TARGET_HPPA) + frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); +#else + if (status->snan_bit_is_one) { + frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; + } else { +#if defined(TARGET_MIPS) + frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); +#else + frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1); + sign = 1; +#endif + } +#endif + + return (FloatParts) { + .cls = float_class_qnan, + .sign = sign, + .exp = INT_MAX, + .frac = frac + }; +} + /*---------------------------------------------------------------------------- | The pattern for a default generated half-precision NaN. *----------------------------------------------------------------------------*/ diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 6dfc992a7f..01036b158e 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -179,7 +179,6 @@ typedef enum __attribute__ ((__packed__)) { float_class_inf, float_class_qnan, /* all NaNs from here */ float_class_snan, - float_class_dnan, float_class_msnan, /* maybe silenced */ } FloatClass; @@ -521,8 +520,6 @@ static float16 float16a_round_pack_canonical(const FloatFmt *params, FloatParts p, float_status *s) { switch (p.cls) { - case float_class_dnan: - return float16_default_nan(s); case float_class_msnan: return float16_maybe_silence_nan(float16_pack_raw(p), s); default: @@ -544,8 +541,6 @@ static FloatParts float32_unpack_canonical(float32 f, float_status *s) static float32 float32_round_pack_canonical(FloatParts p, float_status *s) { switch (p.cls) { - case float_class_dnan: - return float32_default_nan(s); case float_class_msnan: return float32_maybe_silence_nan(float32_pack_raw(p), s); default: @@ -562,8 +557,6 @@ static FloatParts float64_unpack_canonical(float64 f, float_status *s) static float64 float64_round_pack_canonical(FloatParts p, float_status *s) { switch (p.cls) { - case float_class_dnan: - return float64_default_nan(s); case float_class_msnan: return float64_maybe_silence_nan(float64_pack_raw(p), s); default: @@ -595,7 +588,7 @@ static FloatParts return_nan(FloatParts a, float_status *s) /* fall through */ case float_class_qnan: if (s->default_nan_mode) { - a.cls = float_class_dnan; + return parts_default_nan(s); } break; @@ -612,7 +605,7 @@ static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s) } if (s->default_nan_mode) { - a.cls = float_class_dnan; + return parts_default_nan(s); } else { if (pickNaN(is_qnan(a.cls), is_snan(a.cls), is_qnan(b.cls), is_snan(b.cls), @@ -633,7 +626,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatParts b, FloatParts c, } if (s->default_nan_mode) { - a.cls = float_class_dnan; + return parts_default_nan(s); } else { switch (pickNaNMulAdd(is_qnan(a.cls), is_snan(a.cls), is_qnan(b.cls), is_snan(b.cls), @@ -648,8 +641,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatParts b, FloatParts c, a = c; break; case 3: - a.cls = float_class_dnan; - return a; + return parts_default_nan(s); default: g_assert_not_reached(); } @@ -703,7 +695,7 @@ static FloatParts addsub_floats(FloatParts a, FloatParts b, bool subtract, if (a.cls == float_class_inf) { if (b.cls == float_class_inf) { float_raise(float_flag_invalid, s); - a.cls = float_class_dnan; + return parts_default_nan(s); } return a; } @@ -849,7 +841,7 @@ static FloatParts mul_floats(FloatParts a, FloatParts b, float_status *s) if ((a.cls == float_class_inf && b.cls == float_class_zero) || (a.cls == float_class_zero && b.cls == float_class_inf)) { s->float_exception_flags |= float_flag_invalid; - a.cls = float_class_dnan; + a = parts_default_nan(s); a.sign = sign; return a; } @@ -929,8 +921,7 @@ static FloatParts muladd_floats(FloatParts a, FloatParts b, FloatParts c, if (inf_zero) { s->float_exception_flags |= float_flag_invalid; - a.cls = float_class_dnan; - return a; + return parts_default_nan(s); } if (flags & float_muladd_negate_c) { @@ -954,12 +945,12 @@ static FloatParts muladd_floats(FloatParts a, FloatParts b, FloatParts c, if (c.cls == float_class_inf) { if (p_class == float_class_inf && p_sign != c.sign) { s->float_exception_flags |= float_flag_invalid; - a.cls = float_class_dnan; + return parts_default_nan(s); } else { a.cls = float_class_inf; a.sign = c.sign ^ sign_flip; + return a; } - return a; } if (p_class == float_class_inf) { @@ -1169,8 +1160,7 @@ static FloatParts div_floats(FloatParts a, FloatParts b, float_status *s) && (a.cls == float_class_inf || a.cls == float_class_zero)) { s->float_exception_flags |= float_flag_invalid; - a.cls = float_class_dnan; - return a; + return parts_default_nan(s); } /* Inf / x or 0 / x */ if (a.cls == float_class_inf || a.cls == float_class_zero) { @@ -1253,8 +1243,7 @@ static FloatParts float_to_float(FloatParts a, } if (s->default_nan_mode) { - a.cls = float_class_dnan; - return a; + return parts_default_nan(s); } /* @@ -1470,7 +1459,6 @@ static int64_t round_to_int_and_pack(FloatParts in, int rmode, switch (p.cls) { case float_class_snan: case float_class_qnan: - case float_class_dnan: case float_class_msnan: s->float_exception_flags = orig_flags | float_flag_invalid; return max; @@ -1562,7 +1550,6 @@ static uint64_t round_to_uint_and_pack(FloatParts in, int rmode, uint64_t max, switch (p.cls) { case float_class_snan: case float_class_qnan: - case float_class_dnan: case float_class_msnan: s->float_exception_flags = orig_flags | float_flag_invalid; return max; @@ -2063,8 +2050,7 @@ static FloatParts sqrt_float(FloatParts a, float_status *s, const FloatFmt *p) } if (a.sign) { s->float_exception_flags |= float_flag_invalid; - a.cls = float_class_dnan; - return a; + return parts_default_nan(s); } if (a.cls == float_class_inf) { return a; /* sqrt(+inf) = +inf */ From patchwork Fri May 11 00:43:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135453 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp249668lji; Thu, 10 May 2018 17:53:11 -0700 (PDT) X-Google-Smtp-Source: AB8JxZoPyEhnVMyO/6EF3U4TRnkpX2ZRVKYtMSPXmw8VBqqLyOCowvda3qMZ/BSLnpMDeiCWUUxf X-Received: by 2002:a0c:d207:: with SMTP id m7-v6mr3416170qvh.179.1525999991423; Thu, 10 May 2018 17:53:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525999991; cv=none; d=google.com; s=arc-20160816; b=gpEqVqgb3scAtwDsE+yO56eH919Wm8P0Cz8xGnJlVvoI9YmS52UtCW9HIYxiBqRj1Q /gZKwiQoHbGRNIA9h2WdZS+VA76qEWO/OJLpNUVsdoSz5+qiNOpdLcaXlZ7Zqen1i7Cw q8fEpHG7eMiX8VvQnN2JDI/2v63HvbQS5c4KAfAVf+XXtubqIpQhv5G/ujnTmO3GfWjX ZrI64avMrO8k6hvB+TpY4HpdaKo2j6OKeno0SbHm2tqoTrOCq60F7K1MDRya2dJDE1to 07mbNOatSYwvnLnrpKmZAgD6zE91OR/olxuljzlbYfPMBujGryn7ixd65Zb18oZ249A1 b5wQ== ARC-Message-Signature: i=1; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id y24-v6sm4216728pfn.23.2018.05.10.17.43.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 17:43:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 17:43:33 -0700 Message-Id: <20180511004345.26708-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511004345.26708-1-richard.henderson@linaro.org> References: <20180511004345.26708-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::243 Subject: [Qemu-devel] [PATCH 07/19] fpu/softfloat: Replace float_class_msnan with parts_silence_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" With a canonical representation of NaNs, we can silence an SNaN immediately rather than delay until the final format is known. Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 23 +++++++++++++++++ fpu/softfloat.c | 51 +++++++++++--------------------------- 2 files changed, 38 insertions(+), 36 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 2ad524b11e..53a4f45a8c 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -138,6 +138,29 @@ static FloatParts parts_default_nan(float_status *status) }; } +/*---------------------------------------------------------------------------- +| Returns a quiet NaN from a signalling NaN for the deconstructed +| floating-point parts. +*----------------------------------------------------------------------------*/ + +static FloatParts parts_silence_nan(FloatParts a, float_status *status) +{ +#ifdef NO_SIGNALING_NANS + g_assert_not_reached(); +#elif defined(TARGET_HPPA) + a.frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); + a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2); +#else + if (status->snan_bit_is_one) { + return parts_default_nan(status); + } else { + a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1); + } +#endif + a.cls = float_class_qnan; + return a; +} + /*---------------------------------------------------------------------------- | The pattern for a default generated half-precision NaN. *----------------------------------------------------------------------------*/ diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 01036b158e..cce94136d4 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -179,7 +179,6 @@ typedef enum __attribute__ ((__packed__)) { float_class_inf, float_class_qnan, /* all NaNs from here */ float_class_snan, - float_class_msnan, /* maybe silenced */ } FloatClass; /* @@ -519,13 +518,7 @@ static FloatParts float16_unpack_canonical(float16 f, float_status *s) static float16 float16a_round_pack_canonical(const FloatFmt *params, FloatParts p, float_status *s) { - switch (p.cls) { - case float_class_msnan: - return float16_maybe_silence_nan(float16_pack_raw(p), s); - default: - p = round_canonical(p, s, params); - return float16_pack_raw(p); - } + return float16_pack_raw(round_canonical(p, s, params)); } static float16 float16_round_pack_canonical(FloatParts p, float_status *s) @@ -540,13 +533,7 @@ static FloatParts float32_unpack_canonical(float32 f, float_status *s) static float32 float32_round_pack_canonical(FloatParts p, float_status *s) { - switch (p.cls) { - case float_class_msnan: - return float32_maybe_silence_nan(float32_pack_raw(p), s); - default: - p = round_canonical(p, s, &float32_params); - return float32_pack_raw(p); - } + return float32_pack_raw(round_canonical(p, s, &float32_params)); } static FloatParts float64_unpack_canonical(float64 f, float_status *s) @@ -556,13 +543,7 @@ static FloatParts float64_unpack_canonical(float64 f, float_status *s) static float64 float64_round_pack_canonical(FloatParts p, float_status *s) { - switch (p.cls) { - case float_class_msnan: - return float64_maybe_silence_nan(float64_pack_raw(p), s); - default: - p = round_canonical(p, s, &float64_params); - return float64_pack_raw(p); - } + return float64_pack_raw(round_canonical(p, s, &float64_params)); } /* Simple helpers for checking if what NaN we have */ @@ -570,10 +551,12 @@ static bool is_nan(FloatClass c) { return unlikely(c >= float_class_qnan); } + static bool is_snan(FloatClass c) { return c == float_class_snan; } + static bool is_qnan(FloatClass c) { return c == float_class_qnan; @@ -584,7 +567,7 @@ static FloatParts return_nan(FloatParts a, float_status *s) switch (a.cls) { case float_class_snan: s->float_exception_flags |= float_flag_invalid; - a.cls = float_class_msnan; + a = parts_silence_nan(a, s); /* fall through */ case float_class_qnan: if (s->default_nan_mode) { @@ -613,7 +596,9 @@ static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s) (a.frac == b.frac && a.sign < b.sign))) { a = b; } - a.cls = float_class_msnan; + if (is_snan(a.cls)) { + return parts_silence_nan(a, s); + } } return a; } @@ -645,8 +630,9 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatParts b, FloatParts c, default: g_assert_not_reached(); } - - a.cls = float_class_msnan; + if (is_snan(a.cls)) { + return parts_silence_nan(a, s); + } } return a; } @@ -1245,14 +1231,9 @@ static FloatParts float_to_float(FloatParts a, if (s->default_nan_mode) { return parts_default_nan(s); } - - /* - * Reset a.exp to the destination format exp_max as - * the maybe_silence_nan code assumes it is correct - * (which it would be for non-conversions). - */ - a.exp = dstf->exp_max; - a.cls = float_class_msnan; + if (is_snan(a.cls)) { + return parts_silence_nan(a, s); + } } return a; @@ -1459,7 +1440,6 @@ static int64_t round_to_int_and_pack(FloatParts in, int rmode, switch (p.cls) { case float_class_snan: case float_class_qnan: - case float_class_msnan: s->float_exception_flags = orig_flags | float_flag_invalid; return max; case float_class_inf: @@ -1550,7 +1530,6 @@ static uint64_t round_to_uint_and_pack(FloatParts in, int rmode, uint64_t max, switch (p.cls) { case float_class_snan: case float_class_qnan: - case float_class_msnan: s->float_exception_flags = orig_flags | float_flag_invalid; return max; case float_class_inf: From patchwork Fri May 11 00:43:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135452 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp249669lji; Thu, 10 May 2018 17:53:11 -0700 (PDT) X-Google-Smtp-Source: AB8JxZom8a3UivsNWnWC4hAFXESFaNG3ZKFx8pHuJq0CB3Bl3m6R//vDge+Bep/9HHXFZf8QkyHS X-Received: by 2002:a37:8d01:: with SMTP id p1-v6mr3267990qkd.268.1525999991466; Thu, 10 May 2018 17:53:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525999991; cv=none; d=google.com; s=arc-20160816; b=drpVmCoPDYaSWDaNsOujAkBwkDyxDxpVnqVuvD5vQ1/VLikEGG9stWJ4M3WSu67CuR MsWhCAGIjfufkf5/R6JSqx5wv0CQ9DWXg4zLbgIxWAbwD8eQYWb7Dbmp5dIT6Q87z0CH HQvQpWtAHtO7AX2K441OUGMkdYa/7j7gT6ymF+IUTU/HKaeSQblqM7MZm4ZH8Dfx1Nf0 WHi/cAv2QBTpXYc3NgKAkLRoT7uI3y0XZ5UlJjGWfTezVSbCYp5iNrU9q8b5uWsRPY3v 1NX3geX35KbVctERwpitdulWd3TleP+9c4Cm+TXS59y0jKXLy9HUrhiju4wDhlzuP5mJ LK7g== ARC-Message-Signature: i=1; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id y24-v6sm4216728pfn.23.2018.05.10.17.43.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 17:43:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 17:43:34 -0700 Message-Id: <20180511004345.26708-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511004345.26708-1-richard.henderson@linaro.org> References: <20180511004345.26708-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH 08/19] target/arm: Use floatX_silence_nan when we have already checked for SNaN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 6 +++--- target/arm/helper.c | 12 ++++++------ 2 files changed, 9 insertions(+), 9 deletions(-) -- 2.17.0 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index afb25ad20c..976eaba37a 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -366,7 +366,7 @@ float16 HELPER(frecpx_f16)(float16 a, void *fpstp) float16 nan = a; if (float16_is_signaling_nan(a, fpst)) { float_raise(float_flag_invalid, fpst); - nan = float16_maybe_silence_nan(a, fpst); + nan = float16_silence_nan(a, fpst); } if (fpst->default_nan_mode) { nan = float16_default_nan(fpst); @@ -395,7 +395,7 @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp) float32 nan = a; if (float32_is_signaling_nan(a, fpst)) { float_raise(float_flag_invalid, fpst); - nan = float32_maybe_silence_nan(a, fpst); + nan = float32_silence_nan(a, fpst); } if (fpst->default_nan_mode) { nan = float32_default_nan(fpst); @@ -424,7 +424,7 @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp) float64 nan = a; if (float64_is_signaling_nan(a, fpst)) { float_raise(float_flag_invalid, fpst); - nan = float64_maybe_silence_nan(a, fpst); + nan = float64_silence_nan(a, fpst); } if (fpst->default_nan_mode) { nan = float64_default_nan(fpst); diff --git a/target/arm/helper.c b/target/arm/helper.c index a5f3d3b7e5..3065045e0c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11679,7 +11679,7 @@ float16 HELPER(recpe_f16)(float16 input, void *fpstp) float16 nan = f16; if (float16_is_signaling_nan(f16, fpst)) { float_raise(float_flag_invalid, fpst); - nan = float16_maybe_silence_nan(f16, fpst); + nan = float16_silence_nan(f16, fpst); } if (fpst->default_nan_mode) { nan = float16_default_nan(fpst); @@ -11727,7 +11727,7 @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp) float32 nan = f32; if (float32_is_signaling_nan(f32, fpst)) { float_raise(float_flag_invalid, fpst); - nan = float32_maybe_silence_nan(f32, fpst); + nan = float32_silence_nan(f32, fpst); } if (fpst->default_nan_mode) { nan = float32_default_nan(fpst); @@ -11775,7 +11775,7 @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp) float64 nan = f64; if (float64_is_signaling_nan(f64, fpst)) { float_raise(float_flag_invalid, fpst); - nan = float64_maybe_silence_nan(f64, fpst); + nan = float64_silence_nan(f64, fpst); } if (fpst->default_nan_mode) { nan = float64_default_nan(fpst); @@ -11874,7 +11874,7 @@ float16 HELPER(rsqrte_f16)(float16 input, void *fpstp) float16 nan = f16; if (float16_is_signaling_nan(f16, s)) { float_raise(float_flag_invalid, s); - nan = float16_maybe_silence_nan(f16, s); + nan = float16_silence_nan(f16, s); } if (s->default_nan_mode) { nan = float16_default_nan(s); @@ -11918,7 +11918,7 @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp) float32 nan = f32; if (float32_is_signaling_nan(f32, s)) { float_raise(float_flag_invalid, s); - nan = float32_maybe_silence_nan(f32, s); + nan = float32_silence_nan(f32, s); } if (s->default_nan_mode) { nan = float32_default_nan(s); @@ -11961,7 +11961,7 @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp) float64 nan = f64; if (float64_is_signaling_nan(f64, s)) { float_raise(float_flag_invalid, s); - nan = float64_maybe_silence_nan(f64, s); + nan = float64_silence_nan(f64, s); } if (s->default_nan_mode) { nan = float64_default_nan(s); From patchwork Fri May 11 00:43:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135455 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp249984lji; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id y24-v6sm4216728pfn.23.2018.05.10.17.43.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 17:43:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 17:43:35 -0700 Message-Id: <20180511004345.26708-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511004345.26708-1-richard.henderson@linaro.org> References: <20180511004345.26708-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH 09/19] target/arm: Remove floatX_maybe_silence_nan from conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is now handled properly by the generic softfloat code. Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 1 - target/arm/helper.c | 12 ++---------- 2 files changed, 2 insertions(+), 11 deletions(-) -- 2.17.0 diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 976eaba37a..5e51d1be9d 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -456,7 +456,6 @@ float32 HELPER(fcvtx_f64_to_f32)(float64 a, CPUARMState *env) set_float_rounding_mode(float_round_to_zero, &tstat); set_float_exception_flags(0, &tstat); r = float64_to_float32(a, &tstat); - r = float32_maybe_silence_nan(r, &tstat); exflags = get_float_exception_flags(&tstat); if (exflags & float_flag_inexact) { r = make_float32(float32_val(r) | 1); diff --git a/target/arm/helper.c b/target/arm/helper.c index 3065045e0c..61f8820487 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11369,20 +11369,12 @@ FLOAT_CONVS(ui, d, 64, u) /* floating point conversion */ float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env) { - float64 r = float32_to_float64(x, &env->vfp.fp_status); - /* ARM requires that S<->D conversion of any kind of NaN generates - * a quiet NaN by forcing the most significant frac bit to 1. - */ - return float64_maybe_silence_nan(r, &env->vfp.fp_status); + return float32_to_float64(x, &env->vfp.fp_status); } float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env) { - float32 r = float64_to_float32(x, &env->vfp.fp_status); - /* ARM requires that S<->D conversion of any kind of NaN generates - * a quiet NaN by forcing the most significant frac bit to 1. - */ - return float32_maybe_silence_nan(r, &env->vfp.fp_status); + return float64_to_float32(x, &env->vfp.fp_status); } /* VFP3 fixed point conversion. */ From patchwork Fri May 11 00:43:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135456 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp250030lji; Thu, 10 May 2018 17:53:39 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrpuEAB8O5W/g8ZidR9SeYL5pzC5NzA2SNBsxQhElgXgKq1HdR7PyBac0RdaOgbGpTTZTSf X-Received: by 2002:a37:a412:: with SMTP id n18-v6mr3294547qke.100.1526000019796; Thu, 10 May 2018 17:53:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526000019; cv=none; d=google.com; s=arc-20160816; b=bo/MmHxFvrj0s52+ycCUgw4qjZcJ39TJvFuxZnBBGo2tRnznVPDmSe5/9GXGbhmT+z JYYpbKEBEHzgvQmGboyNwuOjtK85uLZDSXpvE8fBzCCKGDnNQ84IDSeseG8N6iLiuMMZ /nEFsL+hUIn+UmyQjOaAIKLxE+6gzweeMqNs4a/y3k3mGHJmnbqhRG7zLnC/2Qf7ctan b2W+begRzrxYG2o/KjPKvlrVMjIwVuqLn5UpMXUIrD0RKTWYH5zPxw0ezZXa6qRM4esV a6OYUhiOCC+lntktbLdk/2UPD76HZbKsKOzcR9z0AJ4urFSB1NCTEHWz3fKJBT6Qukrn 64UQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=yyAYGNdO4kkJBfymYFw36wtSVFsJ2je7s9XYrOFvLZ0=; b=YWAaPyvY6HsQ34WGCM/0xknjG3TJW862mwzW7CnVV4MrVwm9YGlc958wGPmggiWBBA oB2yDDUcl3pjFWinxO4zQOY/7kzMF4QqUsJI7rBlBZ119Sz3JDLpZDRY9bDi+GeH7YIT +W8a9LOWm4oOsxcceBdk3c5nSaMy/GhBVIlQbQpXSk5deesZbqCdlMIvNX9YlPvGzA4t ZVX6f7yn5N9/lX7/3uPTwzHb0eTrU75p3BzxRuBr1gVRJmXCBJJkNAgNhJH0juKgS4Ti 5TJ0q4QMBunYPNaJRz+Lk2OIcH8bw3nCk0tX+38/6gjtGiji+opqVdD9I2e+up0SJGcR toBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kC/b2zQw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id y24-v6sm4216728pfn.23.2018.05.10.17.44.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 17:44:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 17:43:36 -0700 Message-Id: <20180511004345.26708-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511004345.26708-1-richard.henderson@linaro.org> References: <20180511004345.26708-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH 10/19] target/hppa: Remove floatX_maybe_silence_nan from conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is now handled properly by the generic softfloat code. Signed-off-by: Richard Henderson --- target/hppa/op_helper.c | 2 -- 1 file changed, 2 deletions(-) -- 2.17.0 diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index a3af62daf7..912e8d5be4 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -341,7 +341,6 @@ float64 HELPER(fdiv_d)(CPUHPPAState *env, float64 a, float64 b) float64 HELPER(fcnv_s_d)(CPUHPPAState *env, float32 arg) { float64 ret = float32_to_float64(arg, &env->fp_status); - ret = float64_maybe_silence_nan(ret, &env->fp_status); update_fr0_op(env, GETPC()); return ret; } @@ -349,7 +348,6 @@ float64 HELPER(fcnv_s_d)(CPUHPPAState *env, float32 arg) float32 HELPER(fcnv_d_s)(CPUHPPAState *env, float64 arg) { float32 ret = float64_to_float32(arg, &env->fp_status); - ret = float32_maybe_silence_nan(ret, &env->fp_status); update_fr0_op(env, GETPC()); return ret; } From patchwork Fri May 11 00:43:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135457 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp251533lji; Thu, 10 May 2018 17:55:57 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqWOoUVNszhRGuceV33kyjDswaoiHP/q70fkD1gjbO2105lokdXytlnO54REzq1hevPfkZx X-Received: by 2002:a37:3889:: with SMTP id f131-v6mr3117302qka.12.1526000157203; Thu, 10 May 2018 17:55:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526000157; cv=none; d=google.com; s=arc-20160816; b=UKFVcu8dw7EUZCWTPYA5kqorLJO9oNxxdKJf/EMTKnknDGpjpKFeZzQO8LUslgR7yB G1l000jW/c/vxiWlg+tclpAqpcfPm4jh7AO2wIyja4JKcVPgB3xZU/PjOoYwSlXF/gkZ FxoJFC2QM1QuBnEWX20/jwjZRIRlw6CeqhGiSgFi/bc4/Av8xRxmNP84NPqtgQ705Eof wdPEElUgdLnqqvXYP5Bj1nE+rf4oTmnI7C1IJkAux+T6BbDp6IVi2mSUz54VJ1IgOaNx Pb7Auiw8pJr3N2SyNBZ/D1kweEN+21YSRjxOpgaed0qPg4N02T18YZDtQoJy9oYIo2u+ Ok8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=MO0MpJeL1UwzyiS4i/686Xk7sWO20/M2TQYrWFKjaEs=; b=G7UIZjffYrdFK8lbQB1Rsz4odqI4Sj8XwGaTlT5h6OyjQw1E7dic9ywsbnZG1N2CcJ mXDaF0vl4+R4dYMJlIY62iN5JUW6zYmy8+LwVAAaAElpnbaKz61rNRY2slJVQBqk8E5r 4omnG2dKpwR3ofz3ERB3teKotgrFBmSbxx3FeA6xep/s4R/1t3z8o8rpatVcxvoKkdAc AjsIBgryFbnGf8i8AUXI7fyxx3SqaeUnbyOHwDdTujHy9JyQWe1DjrsEMhbzXtmOmzXw W8RJKqYA0Ne1Bu4Yf6kCaFvDraN+t83k2hQgRuoJouP21GIFHVvimCxnyjFSSyrbvH1Y eFHQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Lg63w6oD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id y24-v6sm4216728pfn.23.2018.05.10.17.44.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 17:44:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 17:43:37 -0700 Message-Id: <20180511004345.26708-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511004345.26708-1-richard.henderson@linaro.org> References: <20180511004345.26708-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH 11/19] target/m68k: Use floatX_silence_nan when we have already checked for SNaN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/softfloat.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.17.0 Reviewed-by: Laurent Vivier diff --git a/target/m68k/softfloat.c b/target/m68k/softfloat.c index e41b07d042..6ec227e20f 100644 --- a/target/m68k/softfloat.c +++ b/target/m68k/softfloat.c @@ -31,13 +31,14 @@ static floatx80 propagateFloatx80NaNOneArg(floatx80 a, float_status *status) { if (floatx80_is_signaling_nan(a, status)) { float_raise(float_flag_invalid, status); + a = floatx80_silence_nan(a, status); } if (status->default_nan_mode) { return floatx80_default_nan(status); } - return floatx80_maybe_silence_nan(a, status); + return a; } /*---------------------------------------------------------------------------- From patchwork Fri May 11 00:43:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135446 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp245980lji; Thu, 10 May 2018 17:47:25 -0700 (PDT) X-Google-Smtp-Source: AB8JxZognkVaXskf1r2I4Gs8KX7z9pAJ4NxyDQ2+Ppak3Ti0GlOCTbXpYCmNUsm2CivaIvEqqGJ4 X-Received: by 2002:a37:80c4:: with SMTP id b187-v6mr3186926qkd.47.1525999645054; Thu, 10 May 2018 17:47:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525999645; cv=none; d=google.com; s=arc-20160816; b=ZnIWlqbykMwNAX/kViF3ucGabf7k3d/CC6NSaSSJiO46P6ModlpY8f7P7hC9ibcWVP QR2xanUGm3k2dzwNLACPi47sN4O3jvNoJCg56bZyDO7dsS1IfTlTWTR/UHjkIrGRI30W 4pXpevD05+f1KPy9yT3PUgy1S2Am6QGPDhbnSejb0C0yR4v28BbTxv6+WAUjMvOG5E7e NfqsnPzkRnquLZ2CW2G1hU7lynuqPulQTTjTR+XzHgo8kgDofCr0Nj3heLKJzHy5hNI1 KGOBxlW9b5rftUFu3NZbmaDBFG+vWnRsg+atFAUVS09plzSNbAY++JAK4z05SX7g46l+ p0qw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=+6dmYgNBq5ftwjyPS2WMF6O8R65wvbccZZc/fwe9HEo=; b=MN8en15ZVkddFeX5qWLyLFbOxOtddKyzymmt5vpqwQyyYMvaF3pOgFHe+IBaHPnNTq KYTKt2CGCFOXdqzqo3lC7Y3Y7nIbYt6pUn04JDgVqHPafRMru8lzG1l61RS+cJC4zyvP hbBUZl8gupESmLtIUKOhuxVwhzMRjBvC/9AfPK7aBqxow/F0vQ/m7omGopoWuXBT0JAP E0KsrRW/3CEGrvI8IjTEa2lzIgPugrYT6e+MEKpYU/0d3gHjtHK2ya0tHii3WOEZCF/j BpL+jtmQYMCbfGrJ9/CFLXH26F7kyP4lzBZnvfCRC+mSqvVzQNWWoLDCCi/JZbuxKb5R G7Xg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fzQkSLQG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id y24-v6sm4216728pfn.23.2018.05.10.17.44.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 17:44:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 17:43:38 -0700 Message-Id: <20180511004345.26708-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511004345.26708-1-richard.henderson@linaro.org> References: <20180511004345.26708-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH 12/19] target/mips: Remove floatX_maybe_silence_nan from conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Yongbok Kim , alex.bennee@linaro.org, Aurelien Jarno Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is now handled properly by the generic softfloat code. Cc: Aurelien Jarno Cc: Yongbok Kim Signed-off-by: Richard Henderson --- target/mips/msa_helper.c | 4 ---- target/mips/op_helper.c | 2 -- 2 files changed, 6 deletions(-) -- 2.17.0 diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 8fb7a369ca..c74e3cdc65 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1615,7 +1615,6 @@ static inline float16 float16_from_float32(int32_t a, flag ieee, float16 f_val; f_val = float32_to_float16((float32)a, ieee, status); - f_val = float16_maybe_silence_nan(f_val, status); return a < 0 ? (f_val | (1 << 15)) : f_val; } @@ -1625,7 +1624,6 @@ static inline float32 float32_from_float64(int64_t a, float_status *status) float32 f_val; f_val = float64_to_float32((float64)a, status); - f_val = float32_maybe_silence_nan(f_val, status); return a < 0 ? (f_val | (1 << 31)) : f_val; } @@ -1636,7 +1634,6 @@ static inline float32 float32_from_float16(int16_t a, flag ieee, float32 f_val; f_val = float16_to_float32((float16)a, ieee, status); - f_val = float32_maybe_silence_nan(f_val, status); return a < 0 ? (f_val | (1 << 31)) : f_val; } @@ -1646,7 +1643,6 @@ static inline float64 float64_from_float32(int32_t a, float_status *status) float64 f_val; f_val = float32_to_float64((float64)a, status); - f_val = float64_maybe_silence_nan(f_val, status); return a < 0 ? (f_val | (1ULL << 63)) : f_val; } diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 798cdad030..9025f42366 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -2700,7 +2700,6 @@ uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0) uint64_t fdt2; fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status); - fdt2 = float64_maybe_silence_nan(fdt2, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); return fdt2; } @@ -2790,7 +2789,6 @@ uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0) uint32_t fst2; fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status); - fst2 = float32_maybe_silence_nan(fst2, &env->active_fpu.fp_status); update_fcr31(env, GETPC()); return fst2; } From patchwork Fri May 11 00:43:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135459 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp251799lji; Thu, 10 May 2018 17:56:24 -0700 (PDT) X-Google-Smtp-Source: AB8JxZoy5cZCDfCNEpovci32uLdrL4Nc3bW2BkPs4ofWKqSH7mwPbwAUNykVTDFpAq794TM8aTkb X-Received: by 2002:a0c:ba97:: with SMTP id x23-v6mr3354369qvf.112.1526000184006; Thu, 10 May 2018 17:56:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526000183; cv=none; d=google.com; s=arc-20160816; b=G3Xz6WqWlSGK6k6Oe/Z8mz4UnokSXk8vjM7Q9e67MJs/PtS9MDMGX8RDRykD6hZ+Tm bmlg9GS1kEa2vkMs5ZTVmIH5Eg7pIv0pseBlPGqQ28ak76TYZAyU8flGWaJ2/GpTR1EF F0O/yu0qrrq/JrF4UraeWhEEUhSkcCb56452MCCqsCntTnANCNrrFHckCaWf+DhSoWve DGUz+/MAuwUFPUkmqx2Yehjxf1oevuvRc+mVVpyXTZpbMZE0FVGyK8R+ovLdtskUch/Z JC8M2bYKMOX+2CO8LBISE2+AX18sqlG/SDTO/4+mmLF8UVHpoRND9JVnslsBM5eI11cS YP2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Sl9puNuuuPbRgCmqDxPltmj/Vyt5J5Mk/0va5RwJCSQ=; b=1BvGq635rJsZ0KlQ8FOeyp3MxqcjWX6W1Zvz0etrkM2al/O2odfpY35hwZ2YM25IbE 0sGmEtRmZTLmknR92/t5HWhRD4o4eYwS5Et0zm9xr20Z+O7ojad2xHclurN0xKfSt3fI uyh3759NMy9IOGDm81p1dRpVzGj0leMKmAYo9OTC2g2kpuiBlpd0ncTKeDK19I+W7JlU AD4zIjzObrmdkeKsj/p0jHwqTuTczQo7FiaDCB64nzBw3ZtnW7rczxt142pQfNKH0XQ3 qwezjgr8jZh4bxGWRY5PkkCKVRYLuBUsd70EyNRLhQ9bpi7LPn5eqU4zvGTxfPLPzTXQ gQ0w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cgwbjKgI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id y24-v6sm4216728pfn.23.2018.05.10.17.44.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 17:44:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 17:43:39 -0700 Message-Id: <20180511004345.26708-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511004345.26708-1-richard.henderson@linaro.org> References: <20180511004345.26708-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH 13/19] target/riscv: Remove floatX_maybe_silence_nan from conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Sagar Karandikar , Bastian Koppelmann , Palmer Dabbelt , Michael Clark , alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is now handled properly by the generic softfloat code. Cc: Michael Clark Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Richard Henderson --- target/riscv/fpu_helper.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) -- 2.17.0 diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index abbadead5c..fdb87d8d82 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -279,14 +279,12 @@ uint64_t helper_fmax_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1) { - rs1 = float64_to_float32(rs1, &env->fp_status); - return float32_maybe_silence_nan(rs1, &env->fp_status); + return float64_to_float32(rs1, &env->fp_status); } uint64_t helper_fcvt_d_s(CPURISCVState *env, uint64_t rs1) { - rs1 = float32_to_float64(rs1, &env->fp_status); - return float64_maybe_silence_nan(rs1, &env->fp_status); + return float32_to_float64(rs1, &env->fp_status); } uint64_t helper_fsqrt_d(CPURISCVState *env, uint64_t frs1) From patchwork Fri May 11 00:43:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135461 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp253318lji; Thu, 10 May 2018 17:58:51 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrGEJPBiiQrhj6m7DiaXZKzkHn7zpzMUo+14u8TZVx5X+5e2lR9oA4LgLIc7Qh+yHgeBHgl X-Received: by 2002:aed:2605:: with SMTP id z5-v6mr3725890qtc.72.1526000331298; Thu, 10 May 2018 17:58:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526000331; cv=none; d=google.com; s=arc-20160816; b=cwEi8phUY9xwqUBv9Q9ZfrjEtLE9a6MJqKYU+oJNlokIsCgM2fOKtKUC43nxwnCNFH yS8es5Q06HUZLTp+U42W8Tdx+H20VGR0hwxKyUxYbWyAKOvK7HFeHg1In9mKLyRlPO2G Z/WS92tar/bESPsgLiHzrG1B4S9f7dVpm31tDlCXTE9T4kffwRxtd+o+z+IwxLmoruKT 25IyFXYM7WqzXtMNdo1qCFDS3d0VH8B4JOLXm87RSaSs9fOHseqtfvXkUuVt913pJTyY Ot7RgVGdPiDU2cwvJQV19KEsviS42LrogWsgoaVQNuL01tIkIpTX4qrlXMroEJgoM5wJ /GIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=6z5jX9TCxKiZSZHZWyKzIG2jpQGZx1m9dxkm709/st0=; b=KuDah/pJNSkvketEpTkSzbfBPw7dM3Zj9/QgBpZRJqfj2DvJbRCxkWKuCKX7nIP5fC 4aKc4iBS7UVfipznS9hTEhfkJUvzQDUKj8RF5ldbOXC785n0J5hF+5OwAtccCDqXcrji nmZPUpIFfWVeZBy3nKdhrYyPoVAj/5Nx/sNIUUxrtPr5lBJuLUFKHCFWwjZDrlpXoioI KWDTRMqWxpXbtfXM56oXpcP4lhUWvDwh5609F1oEiB6NiZXm/Cvnfv0Zcm/Prhu5SPPl bKTeeCkwLRPWxU6sTeqeWgazkK5yoPfmb7g1Y8LlRgfYUo2w/6o8TV6+1eXUvidX8NXo bwOw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=L5uqh3c3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id y24-v6sm4216728pfn.23.2018.05.10.17.44.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 17:44:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 17:43:40 -0700 Message-Id: <20180511004345.26708-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511004345.26708-1-richard.henderson@linaro.org> References: <20180511004345.26708-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH 14/19] target/s390x: Remove floatX_maybe_silence_nan from conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org, Alexander Graf , David Hildenbrand Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is now handled properly by the generic softfloat code. Cc: Alexander Graf Cc: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/fpu_helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) -- 2.17.0 Reviewed-by: David Hildenbrand diff --git a/target/s390x/fpu_helper.c b/target/s390x/fpu_helper.c index 43f8bf1c94..5c5b451b3b 100644 --- a/target/s390x/fpu_helper.c +++ b/target/s390x/fpu_helper.c @@ -269,7 +269,7 @@ uint64_t HELPER(ldeb)(CPUS390XState *env, uint64_t f2) { float64 ret = float32_to_float64(f2, &env->fpu_status); handle_exceptions(env, GETPC()); - return float64_maybe_silence_nan(ret, &env->fpu_status); + return ret; } /* convert 128-bit float to 64-bit float */ @@ -277,7 +277,7 @@ uint64_t HELPER(ldxb)(CPUS390XState *env, uint64_t ah, uint64_t al) { float64 ret = float128_to_float64(make_float128(ah, al), &env->fpu_status); handle_exceptions(env, GETPC()); - return float64_maybe_silence_nan(ret, &env->fpu_status); + return ret; } /* convert 64-bit float to 128-bit float */ @@ -285,7 +285,7 @@ uint64_t HELPER(lxdb)(CPUS390XState *env, uint64_t f2) { float128 ret = float64_to_float128(f2, &env->fpu_status); handle_exceptions(env, GETPC()); - return RET128(float128_maybe_silence_nan(ret, &env->fpu_status)); + return RET128(ret); } /* convert 32-bit float to 128-bit float */ @@ -293,7 +293,7 @@ uint64_t HELPER(lxeb)(CPUS390XState *env, uint64_t f2) { float128 ret = float32_to_float128(f2, &env->fpu_status); handle_exceptions(env, GETPC()); - return RET128(float128_maybe_silence_nan(ret, &env->fpu_status)); + return RET128(ret); } /* convert 64-bit float to 32-bit float */ @@ -301,7 +301,7 @@ uint64_t HELPER(ledb)(CPUS390XState *env, uint64_t f2) { float32 ret = float64_to_float32(f2, &env->fpu_status); handle_exceptions(env, GETPC()); - return float32_maybe_silence_nan(ret, &env->fpu_status); + return ret; } /* convert 128-bit float to 32-bit float */ @@ -309,7 +309,7 @@ uint64_t HELPER(lexb)(CPUS390XState *env, uint64_t ah, uint64_t al) { float32 ret = float128_to_float32(make_float128(ah, al), &env->fpu_status); handle_exceptions(env, GETPC()); - return float32_maybe_silence_nan(ret, &env->fpu_status); + return ret; } /* 32-bit FP compare */ From patchwork Fri May 11 00:43:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135450 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp247917lji; Thu, 10 May 2018 17:50:27 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpsJDDCvwMd/DxWRWeXJRp7XvMrUstGv3exzgr7PG2XY5n+F2HhqPGwukQ0zekX7lELbfzU X-Received: by 2002:ac8:266f:: with SMTP id v44-v6mr3669182qtv.354.1525999827239; Thu, 10 May 2018 17:50:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525999827; cv=none; d=google.com; s=arc-20160816; b=UZM9s6XWBwqDEMdiG3bMZz64qszTrJ1Skfbas+in3h/lk73A85pNa3ykhz4g7U41AJ WpuQ95W2Cwm79VMhC/p48klp80V6TmfuWkt7PtWuNYoaCSUMkgLPG1w7TxB4yiYfhUMz TWxON28+u8SsHPHmEjyjrxwwYXMv1GVi6bxDHxuYCGUKUzITQd4bRqvE23Ryc1KUdqTQ Q1Awy5idhn5/Gc8n0g4HIzQT4GMTv7pQG7iyb6VxmkdmK6wneN3H7IdDJUD7f2oMZ3RE 3zBQm2PbmPGmr2Kvf8Iz56868KSXFVYzer7Ivgs1S8ep3UdzIYML0aq0GCvkrA6U/oJo nlsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=xAOPy8F+Mz2BqbptFVIU6iCHdlg7tOjKkktWd84cltQ=; b=hWacnYyJjsPFMAouuEb9Of7a25KLVRKCb4RKEMThLexCI1LHYdp0yu48VU5aa8xzF5 eY0vKAOaoxuWqo4WjNhiYgDPdigg8kIykcek0TtR5rPuhWtxo2UxQ2P0bPFzr70ectL+ iibjB8wjAqNOnJnRhBnnbvpCpog71G+M9xEdJj0Ke53eLSBoQJyGuBLRw0VrHxMYkrmr LAPztsLtL3xsxWR7446hFe6ENMXB2OgK0i+jflcPmv8QSK1tnXEQ4YbNRaBaTPVi/0Yz FjaPpbdaIT2qEI320yOWJmoDwb//V8G4bGdfhsBAde+ZNX9HHg+bRmgiU9Wxv2hEKjCD ecbQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jP1ylhX7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id y24-v6sm4216728pfn.23.2018.05.10.17.44.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 17:44:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 17:43:41 -0700 Message-Id: <20180511004345.26708-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511004345.26708-1-richard.henderson@linaro.org> References: <20180511004345.26708-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::244 Subject: [Qemu-devel] [PATCH 15/19] fpu/softfloat: Use float*_silence_nan in propagateFloat*NaN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We have already checked the arguments for SNaN; we don't need to do it again. Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 44 +++++++++++++++++++++++++++++--------- 1 file changed, 34 insertions(+), 10 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 53a4f45a8c..08ab8181d5 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -498,7 +498,7 @@ static float32 commonNaNToFloat32(commonNaNT a, float_status *status) | The routine is passed various bits of information about the | two NaNs and should return 0 to select NaN a and 1 for NaN b. | Note that signalling NaNs are always squashed to quiet NaNs -| by the caller, by calling floatXX_maybe_silence_nan() before +| by the caller, by calling floatXX_silence_nan() before | returning them. | | aIsLargerSignificand is only valid if both a and b are NaNs @@ -536,7 +536,7 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, { /* According to MIPS specifications, if one of the two operands is * a sNaN, a new qNaN has to be generated. This is done in - * floatXX_maybe_silence_nan(). For qNaN inputs the specifications + * floatXX_silence_nan(). For qNaN inputs the specifications * says: "When possible, this QNaN result is one of the operand QNaN * values." In practice it seems that most implementations choose * the first operand if both operands are qNaN. In short this gives @@ -788,9 +788,15 @@ static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status) if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, aIsLargerSignificand)) { - return float32_maybe_silence_nan(b, status); + if (bIsSignalingNaN) { + return float32_silence_nan(b, status); + } + return b; } else { - return float32_maybe_silence_nan(a, status); + if (aIsSignalingNaN) { + return float32_silence_nan(a, status); + } + return a; } } @@ -950,9 +956,15 @@ static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status) if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, aIsLargerSignificand)) { - return float64_maybe_silence_nan(b, status); + if (bIsSignalingNaN) { + return float64_silence_nan(b, status); + } + return b; } else { - return float64_maybe_silence_nan(a, status); + if (aIsSignalingNaN) { + return float64_silence_nan(a, status); + } + return a; } } @@ -1121,9 +1133,15 @@ floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, aIsLargerSignificand)) { - return floatx80_maybe_silence_nan(b, status); + if (bIsSignalingNaN) { + return floatx80_silence_nan(b, status); + } + return b; } else { - return floatx80_maybe_silence_nan(a, status); + if (aIsSignalingNaN) { + return floatx80_silence_nan(a, status); + } + return a; } } @@ -1270,8 +1288,14 @@ static float128 propagateFloat128NaN(float128 a, float128 b, if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, aIsLargerSignificand)) { - return float128_maybe_silence_nan(b, status); + if (bIsSignalingNaN) { + return float128_silence_nan(b, status); + } + return b; } else { - return float128_maybe_silence_nan(a, status); + if (aIsSignalingNaN) { + return float128_silence_nan(a, status); + } + return a; } } From patchwork Fri May 11 00:43:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135454 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp249785lji; Thu, 10 May 2018 17:53:21 -0700 (PDT) X-Google-Smtp-Source: AB8JxZoISmkd7OzhascBn1TgPlXKCuC9uEVeTi2tfWoEG1GhU7QOLmw6blu0neMEv8Cp/eQqsUZC X-Received: by 2002:a37:9342:: with SMTP id v63-v6mr3440016qkd.40.1526000001778; Thu, 10 May 2018 17:53:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526000001; cv=none; d=google.com; s=arc-20160816; b=SRvVFxojK2280ByBlYfk6kYsAPUMvxFm8I1ZXVgjTFt9vyrRUk4BTlGAbktU5TCOXT 6Rrfl8KY13rax21fvG1qGTp+uL/0t0EN0h084INsCWR8+j2RJ135q88TzGH/BURqK0Ka af+11Sa1c48TNy7lJbV94kkPWwiXjHu4dQCT6VnXDhq+RRLsyzmI5YykV24srXr77kGe QwCbIC2/Nt2vmNuR7GhH4I83tfgUtlDzR2GptWu7Gifa8uDD0qSW8ntiF4M9eUDa55xS Jeg0PLPphaiTGuKlYCRIO5kROxaGuOi5jZcicTWPwwjCwYL7564tsoBbZm0cdC2vdIpR nTyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=oJWsgaqKrV22gmzFsZC0W5+oSo6K4eM7iZrE9Cwz8bQ=; b=acppNCm8hJjPCFQYmFMJW9ejhiw3Q+LgJ+AacUjJMh2yqgTl1J3Ln82Ws/00U4VAli XOUY3rfos4qyF52v5YQ83BqtCtvVW8UPZFOo5XwylsVug6tt+TNKdiJBRpuOruqi4ved elGzB0e262OetV7F6fsulxCfUFJ2cps3FK14lfhLrU9L088wTV869So1gsO78gudyEik ivUY0Tk4lkWUo+wi6NzdaBJlQQFNsdH8Larviag7266yC6qdZfgUBGPit3F+LjsI6+Gw HRp3N6YG723F0xN3LpUwZlsKVWE/jXtSYbIUfTgt72aDoi/2tsSPZZU6aB7+GXBKbgY8 k2Og== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ccIchCYk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id y24-v6sm4216728pfn.23.2018.05.10.17.44.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 17:44:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 17:43:42 -0700 Message-Id: <20180511004345.26708-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511004345.26708-1-richard.henderson@linaro.org> References: <20180511004345.26708-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH 16/19] fpu/softfloat: Remove floatX_maybe_silence_nan X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These functions are now unused. Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 63 -------------------------------------- include/fpu/softfloat.h | 5 --- 2 files changed, 68 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 08ab8181d5..d7033b7757 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -364,19 +364,6 @@ float16 float16_silence_nan(float16 a, float_status *status) #endif } -/*---------------------------------------------------------------------------- -| Returns a quiet NaN if the half-precision floating point value `a' is a -| signaling NaN; otherwise returns `a'. -*----------------------------------------------------------------------------*/ - -float16 float16_maybe_silence_nan(float16 a, float_status *status) -{ - if (float16_is_signaling_nan(a, status)) { - float16_silence_nan(a, status); - } - return a; -} - /*---------------------------------------------------------------------------- | Returns 1 if the single-precision floating-point value `a' is a quiet | NaN; otherwise returns 0. @@ -438,18 +425,6 @@ float32 float32_silence_nan(float32 a, float_status *status) } #endif } -/*---------------------------------------------------------------------------- -| Returns a quiet NaN if the single-precision floating point value `a' is a -| signaling NaN; otherwise returns `a'. -*----------------------------------------------------------------------------*/ - -float32 float32_maybe_silence_nan(float32 a, float_status *status) -{ - if (float32_is_signaling_nan(a, status)) { - float32_silence_nan(a, status); - } - return a; -} /*---------------------------------------------------------------------------- | Returns the result of converting the single-precision floating-point NaN @@ -864,18 +839,6 @@ float64 float64_silence_nan(float64 a, float_status *status) #endif } -/*---------------------------------------------------------------------------- -| Returns a quiet NaN if the double-precision floating point value `a' is a -| signaling NaN; otherwise returns `a'. -*----------------------------------------------------------------------------*/ - -float64 float64_maybe_silence_nan(float64 a, float_status *status) -{ - if (float64_is_signaling_nan(a, status)) { - return float64_silence_nan(a, status); - } - return a; -} /*---------------------------------------------------------------------------- | Returns the result of converting the double-precision floating-point NaN @@ -1037,19 +1000,6 @@ floatx80 floatx80_silence_nan(floatx80 a, float_status *status) #endif } -/*---------------------------------------------------------------------------- -| Returns a quiet NaN if the extended double-precision floating point value -| `a' is a signaling NaN; otherwise returns `a'. -*----------------------------------------------------------------------------*/ - -floatx80 floatx80_maybe_silence_nan(floatx80 a, float_status *status) -{ - if (floatx80_is_signaling_nan(a, status)) { - return floatx80_silence_nan(a, status); - } - return a; -} - /*---------------------------------------------------------------------------- | Returns the result of converting the extended double-precision floating- | point NaN `a' to the canonical NaN format. If `a' is a signaling NaN, the @@ -1204,19 +1154,6 @@ float128 float128_silence_nan(float128 a, float_status *status) #endif } -/*---------------------------------------------------------------------------- -| Returns a quiet NaN if the quadruple-precision floating point value `a' is -| a signaling NaN; otherwise returns `a'. -*----------------------------------------------------------------------------*/ - -float128 float128_maybe_silence_nan(float128 a, float_status *status) -{ - if (float128_is_signaling_nan(a, status)) { - return float128_silence_nan(a, status); - } - return a; -} - /*---------------------------------------------------------------------------- | Returns the result of converting the quadruple-precision floating-point NaN | `a' to the canonical NaN format. If `a' is a signaling NaN, the invalid diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index a6860e858d..69f4dbc4db 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -258,7 +258,6 @@ int float16_compare_quiet(float16, float16, float_status *status); int float16_is_quiet_nan(float16, float_status *status); int float16_is_signaling_nan(float16, float_status *status); float16 float16_silence_nan(float16, float_status *status); -float16 float16_maybe_silence_nan(float16, float_status *status); static inline int float16_is_any_nan(float16 a) { @@ -370,7 +369,6 @@ float32 float32_maxnummag(float32, float32, float_status *status); int float32_is_quiet_nan(float32, float_status *status); int float32_is_signaling_nan(float32, float_status *status); float32 float32_silence_nan(float32, float_status *status); -float32 float32_maybe_silence_nan(float32, float_status *status); float32 float32_scalbn(float32, int, float_status *status); static inline float32 float32_abs(float32 a) @@ -500,7 +498,6 @@ float64 float64_maxnummag(float64, float64, float_status *status); int float64_is_quiet_nan(float64 a, float_status *status); int float64_is_signaling_nan(float64, float_status *status); float64 float64_silence_nan(float64, float_status *status); -float64 float64_maybe_silence_nan(float64, float_status *status); float64 float64_scalbn(float64, int, float_status *status); static inline float64 float64_abs(float64 a) @@ -604,7 +601,6 @@ int floatx80_compare_quiet(floatx80, floatx80, float_status *status); int floatx80_is_quiet_nan(floatx80, float_status *status); int floatx80_is_signaling_nan(floatx80, float_status *status); floatx80 floatx80_silence_nan(floatx80, float_status *status); -floatx80 floatx80_maybe_silence_nan(floatx80, float_status *status); floatx80 floatx80_scalbn(floatx80, int, float_status *status); static inline floatx80 floatx80_abs(floatx80 a) @@ -816,7 +812,6 @@ int float128_compare_quiet(float128, float128, float_status *status); int float128_is_quiet_nan(float128, float_status *status); int float128_is_signaling_nan(float128, float_status *status); float128 float128_silence_nan(float128, float_status *status); -float128 float128_maybe_silence_nan(float128, float_status *status); float128 float128_scalbn(float128, int, float_status *status); static inline float128 float128_abs(float128 a) From patchwork Fri May 11 00:43:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135458 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp251689lji; Thu, 10 May 2018 17:56:14 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpuFaBAilgbah+uLRIdkCehIv2vWBgYemR/47FmrmPqODrM/nqUnGU5RlbUUUWwCQ1uhdsY X-Received: by 2002:ae9:dc81:: with SMTP id q123-v6mr3410820qkf.318.1526000174078; Thu, 10 May 2018 17:56:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526000174; cv=none; d=google.com; s=arc-20160816; b=M2tVUAXC3G8DNexygKk7AXKOeypoCbgs2PfWXeKKYcpyuCdCWlrr0ALM4rNgVeMM57 9CpOKZd12uBDWgS4tX7YP93r2M8Q7NF97bxFK3BCMozkzHdAc+Ikia+JgvrUVpSY4ok1 vM8bGGl8vdGY+Xul8h3F86eH7LR7Bzef+Q01uj/wX7Jk2FeMPzeNPCZPOoAzpRyZBF0z Taikk5sIQIDCZMqSZdOXj5vn86U+8RaGlS4cUOQlzMOGoFI7oicVT9sEf8al7xAahZ6y hwP8oLXTBuf1Da8ESybgDmWe9kOY13A7F63oNx+xGQ6/6afgKnvoJ3TmmNbfbjqXb+qm r+mQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=oesny4QuXbveDP/wFoUMc4hNdwl6Bna3gbCe86Nls80=; b=Qy/SEg3s/tQMwgkLccKd+dtVrhY0yR2qYMh9T8+k5fz02B4jJnPR4xqa0d8H7ssBz0 1YBexkdtwn2RLTQbW/AP0JfSpQ8e/qoPjZwkW4f56byEPuYzExWaOtSSUWuoXk46Md0D yn0m6FXlgi/TnhPnwzlBPJc5cDs2gn0SRiueZu9t0CGs+sXC1omh/oPB9OULimbHzHK/ F27ynxNlTLPZV5xRRE5CtY4yqK+NNx0XJba7U1oEM3BQYzHM4g+NTIBoTbLQtj+0IB9S ZE+P/+CQSod7NMOAmsOtlbPWUX/l3gwvCtVtEb1SfgaSeLKNQRuvGdt2ZW0QniJiQ9gi orrA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=KGbtytY0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id y24-v6sm4216728pfn.23.2018.05.10.17.44.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 17:44:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 17:43:43 -0700 Message-Id: <20180511004345.26708-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511004345.26708-1-richard.henderson@linaro.org> References: <20180511004345.26708-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH 17/19] fpu/softfloat: Introduce SNAN_BIT_IS_ONE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Only MIPS requires snan_bit_is_one to be variable. While we are specializing softfloat behaviour, allow other targets to eliminate this runtime check. Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 57 ++++++++++++++++++++--------------- include/fpu/softfloat-types.h | 1 + include/fpu/softfloat.h | 4 --- target/mips/cpu.h | 4 +-- target/hppa/cpu.c | 1 - target/mips/translate_init.c | 4 +-- target/ppc/fpu_helper.c | 1 - target/sh4/cpu.c | 1 - target/unicore32/cpu.c | 2 -- 9 files changed, 37 insertions(+), 38 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index d7033b7757..e7b4544e48 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -83,7 +83,14 @@ this code that are retained. /* Define for architectures which deviate from IEEE in not supporting * signaling NaNs (so all NaNs are treated as quiet). */ -#define NO_SIGNALING_NANS 1 +# define NO_SIGNALING_NANS 1 +# define SNAN_BIT_IS_ONE(S) 0 +#elif defined(TARGET_MIPS) +# define SNAN_BIT_IS_ONE(S) ((S)->snan_bit_is_one) +#elif defined(TARGET_HPPA) || defined(TARGET_UNICORE32) || defined(TARGET_SH4) +# define SNAN_BIT_IS_ONE(S) 1 +#else +# define SNAN_BIT_IS_ONE(S) 0 #endif /*---------------------------------------------------------------------------- @@ -97,7 +104,7 @@ static bool parts_is_snan_frac(uint64_t frac, float_status *status) return false; #else flag msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1); - return msb == status->snan_bit_is_one; + return msb == SNAN_BIT_IS_ONE(status); #endif } @@ -118,7 +125,7 @@ static FloatParts parts_default_nan(float_status *status) #elif defined(TARGET_HPPA) frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2); #else - if (status->snan_bit_is_one) { + if (SNAN_BIT_IS_ONE(status)) { frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1; } else { #if defined(TARGET_MIPS) @@ -151,7 +158,7 @@ static FloatParts parts_silence_nan(FloatParts a, float_status *status) a.frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2); #else - if (status->snan_bit_is_one) { + if (SNAN_BIT_IS_ONE(status)) { return parts_default_nan(status); } else { a.frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1); @@ -169,7 +176,7 @@ float16 float16_default_nan(float_status *status) #if defined(TARGET_ARM) return const_float16(0x7E00); #else - if (status->snan_bit_is_one) { + if (SNAN_BIT_IS_ONE(status)) { return const_float16(0x7DFF); } else { #if defined(TARGET_MIPS) @@ -195,7 +202,7 @@ float32 float32_default_nan(float_status *status) #elif defined(TARGET_HPPA) return const_float32(0x7FA00000); #else - if (status->snan_bit_is_one) { + if (SNAN_BIT_IS_ONE(status)) { return const_float32(0x7FBFFFFF); } else { #if defined(TARGET_MIPS) @@ -220,7 +227,7 @@ float64 float64_default_nan(float_status *status) #elif defined(TARGET_HPPA) return const_float64(LIT64(0x7FF4000000000000)); #else - if (status->snan_bit_is_one) { + if (SNAN_BIT_IS_ONE(status)) { return const_float64(LIT64(0x7FF7FFFFFFFFFFFF)); } else { #if defined(TARGET_MIPS) @@ -242,7 +249,7 @@ floatx80 floatx80_default_nan(float_status *status) r.low = LIT64(0xFFFFFFFFFFFFFFFF); r.high = 0x7FFF; #else - if (status->snan_bit_is_one) { + if (SNAN_BIT_IS_ONE(status)) { r.low = LIT64(0xBFFFFFFFFFFFFFFF); r.high = 0x7FFF; } else { @@ -274,7 +281,7 @@ float128 float128_default_nan(float_status *status) { float128 r; - if (status->snan_bit_is_one) { + if (SNAN_BIT_IS_ONE(status)) { r.low = LIT64(0xFFFFFFFFFFFFFFFF); r.high = LIT64(0x7FFF7FFFFFFFFFFF); } else { @@ -319,7 +326,7 @@ int float16_is_quiet_nan(float16 a_, float_status *status) return float16_is_any_nan(a_); #else uint16_t a = float16_val(a_); - if (status->snan_bit_is_one) { + if (SNAN_BIT_IS_ONE(status)) { return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); } else { return ((a & ~0x8000) >= 0x7C80); @@ -338,7 +345,7 @@ int float16_is_signaling_nan(float16 a_, float_status *status) return 0; #else uint16_t a = float16_val(a_); - if (status->snan_bit_is_one) { + if (SNAN_BIT_IS_ONE(status)) { return ((a & ~0x8000) >= 0x7C80); } else { return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF); @@ -356,7 +363,7 @@ float16 float16_silence_nan(float16 a, float_status *status) #ifdef NO_SIGNALING_NANS g_assert_not_reached(); #else - if (status->snan_bit_is_one) { + if (SNAN_BIT_IS_ONE(status)) { return float16_default_nan(status); } else { return a | (1 << 9); @@ -375,7 +382,7 @@ int float32_is_quiet_nan(float32 a_, float_status *status) return float32_is_any_nan(a_); #else uint32_t a = float32_val(a_); - if (status->snan_bit_is_one) { + if (SNAN_BIT_IS_ONE(status)) { return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); } else { return ((uint32_t)(a << 1) >= 0xFF800000); @@ -394,7 +401,7 @@ int float32_is_signaling_nan(float32 a_, float_status *status) return 0; #else uint32_t a = float32_val(a_); - if (status->snan_bit_is_one) { + if (SNAN_BIT_IS_ONE(status)) { return ((uint32_t)(a << 1) >= 0xFF800000); } else { return (((a >> 22) & 0x1FF) == 0x1FE) && (a & 0x003FFFFF); @@ -412,7 +419,7 @@ float32 float32_silence_nan(float32 a, float_status *status) #ifdef NO_SIGNALING_NANS g_assert_not_reached(); #else - if (status->snan_bit_is_one) { + if (SNAN_BIT_IS_ONE(status)) { # ifdef TARGET_HPPA a &= ~0x00400000; a |= 0x00200000; @@ -651,7 +658,7 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, return 3; } - if (status->snan_bit_is_one) { + if (SNAN_BIT_IS_ONE(status)) { /* Prefer sNaN over qNaN, in the a, b, c order. */ if (aIsSNaN) { return 0; @@ -786,7 +793,7 @@ int float64_is_quiet_nan(float64 a_, float_status *status) return float64_is_any_nan(a_); #else uint64_t a = float64_val(a_); - if (status->snan_bit_is_one) { + if (SNAN_BIT_IS_ONE(status)) { return (((a >> 51) & 0xFFF) == 0xFFE) && (a & 0x0007FFFFFFFFFFFFULL); } else { @@ -806,7 +813,7 @@ int float64_is_signaling_nan(float64 a_, float_status *status) return 0; #else uint64_t a = float64_val(a_); - if (status->snan_bit_is_one) { + if (SNAN_BIT_IS_ONE(status)) { return ((a << 1) >= 0xFFF0000000000000ULL); } else { return (((a >> 51) & 0xFFF) == 0xFFE) @@ -825,7 +832,7 @@ float64 float64_silence_nan(float64 a, float_status *status) #ifdef NO_SIGNALING_NANS g_assert_not_reached(); #else - if (status->snan_bit_is_one) { + if (SNAN_BIT_IS_ONE(status)) { # ifdef TARGET_HPPA a &= ~0x0008000000000000ULL; a |= 0x0004000000000000ULL; @@ -942,7 +949,7 @@ int floatx80_is_quiet_nan(floatx80 a, float_status *status) #ifdef NO_SIGNALING_NANS return floatx80_is_any_nan(a); #else - if (status->snan_bit_is_one) { + if (SNAN_BIT_IS_ONE(status)) { uint64_t aLow; aLow = a.low & ~0x4000000000000000ULL; @@ -967,7 +974,7 @@ int floatx80_is_signaling_nan(floatx80 a, float_status *status) #ifdef NO_SIGNALING_NANS return 0; #else - if (status->snan_bit_is_one) { + if (SNAN_BIT_IS_ONE(status)) { return ((a.high & 0x7FFF) == 0x7FFF) && ((a.low << 1) >= 0x8000000000000000ULL); } else { @@ -991,7 +998,7 @@ floatx80 floatx80_silence_nan(floatx80 a, float_status *status) #ifdef NO_SIGNALING_NANS g_assert_not_reached(); #else - if (status->snan_bit_is_one) { + if (SNAN_BIT_IS_ONE(status)) { return floatx80_default_nan(status); } else { a.low |= LIT64(0xC000000000000000); @@ -1105,7 +1112,7 @@ int float128_is_quiet_nan(float128 a, float_status *status) #ifdef NO_SIGNALING_NANS return float128_is_any_nan(a); #else - if (status->snan_bit_is_one) { + if (SNAN_BIT_IS_ONE(status)) { return (((a.high >> 47) & 0xFFFF) == 0xFFFE) && (a.low || (a.high & 0x00007FFFFFFFFFFFULL)); } else { @@ -1125,7 +1132,7 @@ int float128_is_signaling_nan(float128 a, float_status *status) #ifdef NO_SIGNALING_NANS return 0; #else - if (status->snan_bit_is_one) { + if (SNAN_BIT_IS_ONE(status)) { return ((a.high << 1) >= 0xFFFF000000000000ULL) && (a.low || (a.high & 0x0000FFFFFFFFFFFFULL)); } else { @@ -1145,7 +1152,7 @@ float128 float128_silence_nan(float128 a, float_status *status) #ifdef NO_SIGNALING_NANS g_assert_not_reached(); #else - if (status->snan_bit_is_one) { + if (SNAN_BIT_IS_ONE(status)) { return float128_default_nan(status); } else { a.high |= LIT64(0x0000800000000000); diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 4e378cb612..b5207d4537 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -173,6 +173,7 @@ typedef struct float_status { /* should denormalised inputs go to zero and set the input_denormal flag? */ flag flush_inputs_to_zero; flag default_nan_mode; + /* not always used -- see SNAN_BIT_IS_ONE in softfloat-specialize.h */ flag snan_bit_is_one; } float_status; diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h index 69f4dbc4db..e72cc9525d 100644 --- a/include/fpu/softfloat.h +++ b/include/fpu/softfloat.h @@ -125,10 +125,6 @@ static inline void set_default_nan_mode(flag val, float_status *status) { status->default_nan_mode = val; } -static inline void set_snan_bit_is_one(flag val, float_status *status) -{ - status->snan_bit_is_one = val; -} static inline int get_float_detect_tininess(float_status *status) { return status->float_detect_tininess; diff --git a/target/mips/cpu.h b/target/mips/cpu.h index cfe1735e0e..2abce47ea3 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -755,8 +755,8 @@ target_ulong exception_resume_pc (CPUMIPSState *env); static inline void restore_snan_bit_mode(CPUMIPSState *env) { - set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0, - &env->active_fpu.fp_status); + env->active_fpu.fp_status.snan_bit_is_one + = (env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0; } static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index c261b6b090..00bf444620 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -141,7 +141,6 @@ static void hppa_cpu_initfn(Object *obj) cs->env_ptr = env; cs->exception_index = -1; cpu_hppa_loaded_fr0(env); - set_snan_bit_is_one(true, &env->fp_status); cpu_hppa_put_psw(env, PSW_W); } diff --git a/target/mips/translate_init.c b/target/mips/translate_init.c index c7ba6ee5f9..5e40d6a198 100644 --- a/target/mips/translate_init.c +++ b/target/mips/translate_init.c @@ -878,6 +878,6 @@ static void msa_reset(CPUMIPSState *env) /* clear float_status nan mode */ set_default_nan_mode(0, &env->active_tc.msa_fp_status); - /* set proper signanling bit meaning ("1" means "quiet") */ - set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); + /* set proper signaling bit meaning ("1" means "quiet") */ + env->active_tc.msa_fp_status.snan_bit_is_one = 0; } diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 9ae418a577..d31a933cbb 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -3382,7 +3382,6 @@ void helper_xssqrtqp(CPUPPCState *env, uint32_t opcode) xt.f128 = xb.f128; } else if (float128_is_neg(xb.f128) && !float128_is_zero(xb.f128)) { float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1); - set_snan_bit_is_one(0, &env->fp_status); xt.f128 = float128_default_nan(&env->fp_status); } } diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 541ffc2d97..b9f393b7c7 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -71,7 +71,6 @@ static void superh_cpu_reset(CPUState *s) set_flush_to_zero(1, &env->fp_status); #endif set_default_nan_mode(1, &env->fp_status); - set_snan_bit_is_one(1, &env->fp_status); } static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 29d160a88d..68f978d80b 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -70,7 +70,6 @@ static void unicore_ii_cpu_initfn(Object *obj) set_feature(env, UC32_HWCAP_CMOV); set_feature(env, UC32_HWCAP_UCF64); - set_snan_bit_is_one(1, &env->ucf64.fp_status); } static void uc32_any_cpu_initfn(Object *obj) @@ -83,7 +82,6 @@ static void uc32_any_cpu_initfn(Object *obj) set_feature(env, UC32_HWCAP_CMOV); set_feature(env, UC32_HWCAP_UCF64); - set_snan_bit_is_one(1, &env->ucf64.fp_status); } static void uc32_cpu_realizefn(DeviceState *dev, Error **errp) From patchwork Fri May 11 00:43:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135460 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp252901lji; Thu, 10 May 2018 17:58:11 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpFWh5IYeMznawhIdMyFUGyyrO2RQDfwHTou0+JZplei5qn5mc9Kmhp9/S2VP01noDsFdUH X-Received: by 2002:a0c:87b4:: with SMTP id 49-v6mr3414760qvj.217.1526000291748; Thu, 10 May 2018 17:58:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526000291; cv=none; d=google.com; s=arc-20160816; b=0aJyL9LJyxuiU4TUlXCRoZnV2YpU5urCWup9HYvhcXxlO7lMc9oUt1YBkwoDP5Brdj Jd4Uan+ti7LgdWvQlZ2pfV001XPHpUvQbTdLXY0ZVqsZY76TdlxhOjtTZoEcYB63t6nx wmNpRQmxC7Hrhh4XW9QYQSWEmFCj/nPPhNlHfyS99qxTwNb5XOc5vVnq3a+egpCikM/7 XBl9tIrRAOeXr/FwPLvBDzAwTZXMKeYq1nhoV9sSXiPj6e7sJ/5u8a0NIMbz4hTRYM/c 4uF+tk1nUjL6p7zw8nrZNOm26/KHoGXqbQ0MALvJPEWUL2BlG+MEDJVkYIBswmkXJc4F r0CQ== ARC-Message-Signature: i=1; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id y24-v6sm4216728pfn.23.2018.05.10.17.44.11 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 17:44:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 17:43:44 -0700 Message-Id: <20180511004345.26708-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511004345.26708-1-richard.henderson@linaro.org> References: <20180511004345.26708-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::241 Subject: [Qemu-devel] [PATCH 18/19] fpu/softfloat: Pass FloatClass to pickNaN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For each operand, pass a single enumeration instead of a pair of booleans. Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 168 ++++++++++++++++++------------------- fpu/softfloat.c | 35 ++++---- 2 files changed, 98 insertions(+), 105 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index e7b4544e48..83e5bf83b9 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -490,10 +490,10 @@ static float32 commonNaNToFloat32(commonNaNT a, float_status *status) | tie-break rule. *----------------------------------------------------------------------------*/ -#if defined(TARGET_ARM) -static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, +static int pickNaN(FloatClass a_cls, FloatClass b_cls, flag aIsLargerSignificand) { +#if defined(TARGET_ARM) || defined(TARGET_MIPS) || defined(TARGET_HPPA) /* ARM mandated NaN propagation rules (see FPProcessNaNs()), take * the first of: * 1. A if it is signaling @@ -502,20 +502,6 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, * 4. B (quiet) * A signaling NaN is always quietened before returning it. */ - if (aIsSNaN) { - return 0; - } else if (bIsSNaN) { - return 1; - } else if (aIsQNaN) { - return 0; - } else { - return 1; - } -} -#elif defined(TARGET_MIPS) || defined(TARGET_HPPA) -static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag aIsLargerSignificand) -{ /* According to MIPS specifications, if one of the two operands is * a sNaN, a new qNaN has to be generated. This is done in * floatXX_silence_nan(). For qNaN inputs the specifications @@ -529,35 +515,21 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, * 4. B (quiet) * A signaling NaN is always silenced before returning it. */ - if (aIsSNaN) { + if (is_snan(a_cls)) { return 0; - } else if (bIsSNaN) { + } else if (is_snan(b_cls)) { return 1; - } else if (aIsQNaN) { + } else if (is_qnan(a_cls)) { return 0; } else { return 1; } -} -#elif defined(TARGET_PPC) || defined(TARGET_XTENSA) -static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag aIsLargerSignificand) -{ +#elif defined(TARGET_PPC) || defined(TARGET_XTENSA) || defined(TARGET_M68K) /* PowerPC propagation rules: * 1. A if it sNaN or qNaN * 2. B if it sNaN or qNaN * A signaling NaN is always silenced before returning it. */ - if (aIsSNaN || aIsQNaN) { - return 0; - } else { - return 1; - } -} -#elif defined(TARGET_M68K) -static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag aIsLargerSignificand) -{ /* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL * 3.4 FLOATING-POINT INSTRUCTION DETAILS * If either operand, but not both operands, of an operation is a @@ -572,16 +544,12 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, * a nonsignaling NaN. The operation then continues as described in the * preceding paragraph for nonsignaling NaNs. */ - if (aIsQNaN || aIsSNaN) { /* a is the destination operand */ - return 0; /* return the destination operand */ + if (is_nan(a_cls)) { + return 0; } else { - return 1; /* return b */ + return 1; } -} #else -static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag aIsLargerSignificand) -{ /* This implements x87 NaN propagation rules: * SNaN + QNaN => return the QNaN * two SNaNs => return the one with the larger significand, silenced @@ -592,13 +560,13 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, * If we get down to comparing significands and they are the same, * return the NaN with the positive sign bit (if any). */ - if (aIsSNaN) { - if (bIsSNaN) { + if (is_snan(a_cls)) { + if (is_snan(b_cls)) { return aIsLargerSignificand ? 0 : 1; } - return bIsQNaN ? 1 : 0; - } else if (aIsQNaN) { - if (bIsSNaN || !bIsQNaN) { + return is_qnan(b_cls) ? 1 : 0; + } else if (is_qnan(a_cls)) { + if (is_snan(b_cls) || !is_qnan(b_cls)) { return 0; } else { return aIsLargerSignificand ? 0 : 1; @@ -606,8 +574,8 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, } else { return 1; } -} #endif +} /*---------------------------------------------------------------------------- | Select which NaN to propagate for a three-input operation. @@ -741,18 +709,26 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status) { - flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN; flag aIsLargerSignificand; uint32_t av, bv; + FloatClass a_cls, b_cls; + + /* This is not complete, but is good enough for pickNaN. */ + a_cls = (!float32_is_any_nan(a) + ? float_class_normal + : float32_is_signaling_nan(a, status) + ? float_class_snan + : float_class_qnan); + b_cls = (!float32_is_any_nan(b) + ? float_class_normal + : float32_is_signaling_nan(b, status) + ? float_class_snan + : float_class_qnan); - aIsQuietNaN = float32_is_quiet_nan(a, status); - aIsSignalingNaN = float32_is_signaling_nan(a, status); - bIsQuietNaN = float32_is_quiet_nan(b, status); - bIsSignalingNaN = float32_is_signaling_nan(b, status); av = float32_val(a); bv = float32_val(b); - if (aIsSignalingNaN | bIsSignalingNaN) { + if (is_snan(a_cls) || is_snan(b_cls)) { float_raise(float_flag_invalid, status); } @@ -768,14 +744,13 @@ static float32 propagateFloat32NaN(float32 a, float32 b, float_status *status) aIsLargerSignificand = (av < bv) ? 1 : 0; } - if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, - aIsLargerSignificand)) { - if (bIsSignalingNaN) { + if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { + if (is_snan(b_cls)) { return float32_silence_nan(b, status); } return b; } else { - if (aIsSignalingNaN) { + if (is_snan(a_cls)) { return float32_silence_nan(a, status); } return a; @@ -897,18 +872,26 @@ static float64 commonNaNToFloat64(commonNaNT a, float_status *status) static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status) { - flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN; flag aIsLargerSignificand; uint64_t av, bv; + FloatClass a_cls, b_cls; + + /* This is not complete, but is good enough for pickNaN. */ + a_cls = (!float64_is_any_nan(a) + ? float_class_normal + : float64_is_signaling_nan(a, status) + ? float_class_snan + : float_class_qnan); + b_cls = (!float64_is_any_nan(b) + ? float_class_normal + : float64_is_signaling_nan(b, status) + ? float_class_snan + : float_class_qnan); - aIsQuietNaN = float64_is_quiet_nan(a, status); - aIsSignalingNaN = float64_is_signaling_nan(a, status); - bIsQuietNaN = float64_is_quiet_nan(b, status); - bIsSignalingNaN = float64_is_signaling_nan(b, status); av = float64_val(a); bv = float64_val(b); - if (aIsSignalingNaN | bIsSignalingNaN) { + if (is_snan(a_cls) || is_snan(b_cls)) { float_raise(float_flag_invalid, status); } @@ -924,14 +907,13 @@ static float64 propagateFloat64NaN(float64 a, float64 b, float_status *status) aIsLargerSignificand = (av < bv) ? 1 : 0; } - if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, - aIsLargerSignificand)) { - if (bIsSignalingNaN) { + if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { + if (is_snan(b_cls)) { return float64_silence_nan(b, status); } return b; } else { - if (aIsSignalingNaN) { + if (is_snan(a_cls)) { return float64_silence_nan(a, status); } return a; @@ -1064,15 +1046,22 @@ static floatx80 commonNaNToFloatx80(commonNaNT a, float_status *status) floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) { - flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN; flag aIsLargerSignificand; + FloatClass a_cls, b_cls; - aIsQuietNaN = floatx80_is_quiet_nan(a, status); - aIsSignalingNaN = floatx80_is_signaling_nan(a, status); - bIsQuietNaN = floatx80_is_quiet_nan(b, status); - bIsSignalingNaN = floatx80_is_signaling_nan(b, status); + /* This is not complete, but is good enough for pickNaN. */ + a_cls = (!floatx80_is_any_nan(a) + ? float_class_normal + : floatx80_is_signaling_nan(a, status) + ? float_class_snan + : float_class_qnan); + b_cls = (!floatx80_is_any_nan(b) + ? float_class_normal + : floatx80_is_signaling_nan(b, status) + ? float_class_snan + : float_class_qnan); - if (aIsSignalingNaN | bIsSignalingNaN) { + if (is_snan(a_cls) || is_snan(b_cls)) { float_raise(float_flag_invalid, status); } @@ -1088,14 +1077,13 @@ floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status) aIsLargerSignificand = (a.high < b.high) ? 1 : 0; } - if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, - aIsLargerSignificand)) { - if (bIsSignalingNaN) { + if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { + if (is_snan(b_cls)) { return floatx80_silence_nan(b, status); } return b; } else { - if (aIsSignalingNaN) { + if (is_snan(a_cls)) { return floatx80_silence_nan(a, status); } return a; @@ -1206,15 +1194,22 @@ static float128 commonNaNToFloat128(commonNaNT a, float_status *status) static float128 propagateFloat128NaN(float128 a, float128 b, float_status *status) { - flag aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN; flag aIsLargerSignificand; + FloatClass a_cls, b_cls; - aIsQuietNaN = float128_is_quiet_nan(a, status); - aIsSignalingNaN = float128_is_signaling_nan(a, status); - bIsQuietNaN = float128_is_quiet_nan(b, status); - bIsSignalingNaN = float128_is_signaling_nan(b, status); + /* This is not complete, but is good enough for pickNaN. */ + a_cls = (!float128_is_any_nan(a) + ? float_class_normal + : float128_is_signaling_nan(a, status) + ? float_class_snan + : float_class_qnan); + b_cls = (!float128_is_any_nan(b) + ? float_class_normal + : float128_is_signaling_nan(b, status) + ? float_class_snan + : float_class_qnan); - if (aIsSignalingNaN | bIsSignalingNaN) { + if (is_snan(a_cls) || is_snan(b_cls)) { float_raise(float_flag_invalid, status); } @@ -1230,14 +1225,13 @@ static float128 propagateFloat128NaN(float128 a, float128 b, aIsLargerSignificand = (a.high < b.high) ? 1 : 0; } - if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN, - aIsLargerSignificand)) { - if (bIsSignalingNaN) { + if (pickNaN(a_cls, b_cls, aIsLargerSignificand)) { + if (is_snan(b_cls)) { return float128_silence_nan(b, status); } return b; } else { - if (aIsSignalingNaN) { + if (is_snan(a_cls)) { return float128_silence_nan(a, status); } return a; diff --git a/fpu/softfloat.c b/fpu/softfloat.c index cce94136d4..cd56beb277 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -181,6 +181,22 @@ typedef enum __attribute__ ((__packed__)) { float_class_snan, } FloatClass; +/* Simple helpers for checking if what NaN we have */ +static bool is_nan(FloatClass c) +{ + return unlikely(c >= float_class_qnan); +} + +static bool is_snan(FloatClass c) +{ + return c == float_class_snan; +} + +static bool is_qnan(FloatClass c) +{ + return c == float_class_qnan; +} + /* * Structure holding all of the decomposed parts of a float. The * exponent is unbiased and the fraction is normalized. All @@ -546,22 +562,6 @@ static float64 float64_round_pack_canonical(FloatParts p, float_status *s) return float64_pack_raw(round_canonical(p, s, &float64_params)); } -/* Simple helpers for checking if what NaN we have */ -static bool is_nan(FloatClass c) -{ - return unlikely(c >= float_class_qnan); -} - -static bool is_snan(FloatClass c) -{ - return c == float_class_snan; -} - -static bool is_qnan(FloatClass c) -{ - return c == float_class_qnan; -} - static FloatParts return_nan(FloatParts a, float_status *s) { switch (a.cls) { @@ -590,8 +590,7 @@ static FloatParts pick_nan(FloatParts a, FloatParts b, float_status *s) if (s->default_nan_mode) { return parts_default_nan(s); } else { - if (pickNaN(is_qnan(a.cls), is_snan(a.cls), - is_qnan(b.cls), is_snan(b.cls), + if (pickNaN(a.cls, b.cls, a.frac > b.frac || (a.frac == b.frac && a.sign < b.sign))) { a = b; From patchwork Fri May 11 00:43:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135462 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp253800lji; Thu, 10 May 2018 17:59:38 -0700 (PDT) X-Google-Smtp-Source: AB8JxZry0b3At64pOufH4R7mDGyKKZ+sMDiULicsvRH4Zg+b6q8o7/Fepz3Tizm2no72fTmz+45f X-Received: by 2002:a37:be86:: with SMTP id o128-v6mr3159096qkf.141.1526000378610; Thu, 10 May 2018 17:59:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526000378; cv=none; d=google.com; s=arc-20160816; b=I/DJDyGs04m2ZlOsZ7tEmBSHVr/mxXxrjAFmVIm9bSvXhPRHagsyB1s/SjjHVBgemV OOHHo0igaX0tS/FcW0OCx2njvi2wKcnj3Sr2+GfsFMQp4rThvfbdgrfvg560BEa++GFY Nxg5zSW04LdoQN6OwF1YCv1/557OPx60xzPOlBz6tsnhcGEQ814QA47M3a6NK2kMBkqt 1iKds0OaBY7VUmpdgCXzzlYFRmGQhTYL5jyE3eFDs/60hIeu7h7wXDGjALjNhffD6YR6 5KtPWGT87duofF0I5P5/p9I9E/MCm+yWNrVFzH2wuX/QPk8G54fR6MekKjf14bNuMjrx lG3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=MS+jabeFcvUCqsXLya/uB7mpbDAjQtdDouXTp4BblTw=; b=WVp7FrZIjJtZzX2rlqMntdSiNcXFeFjM343KlkG+gY9CGLb4BcDtRkP2HBb6kfXSvm wvWpcjU1WIwpWdStX3vj5CZx3AkMJYmEC38SK5ftDD7F2YoCocnQTA+fucInjrmYTTEH ZB0/g9frgsKFBafezcwv5wDn+c6xFnnauvihlKx+Cd4W+kN2rWtYc1yBh8i+PaUX/75w zvQ35XlO1VcGWUdEcbp9bm8BOcDFJsRvCSRbdz9eIPgORn+ErnOfACT03tFbpVzVfnRn 6ax0cQ4oJumEMVt4YsYLeBidoPVaYdyzspeX+Mbn1RVulgd0SGfctznyWjXv8zVD8J+B JW5g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cNa6kqeU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id y24-v6sm4216728pfn.23.2018.05.10.17.44.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 17:44:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 17:43:45 -0700 Message-Id: <20180511004345.26708-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511004345.26708-1-richard.henderson@linaro.org> References: <20180511004345.26708-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH 19/19] fpu/softfloat: Pass FloatClass to pickNaNMulAdd X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For each operand, pass a single enumeration instead of a pair of booleans. Signed-off-by: Richard Henderson --- fpu/softfloat-specialize.h | 70 +++++++++++++++----------------------- fpu/softfloat.c | 11 +++--- 2 files changed, 31 insertions(+), 50 deletions(-) -- 2.17.0 diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index 83e5bf83b9..637f1ea1be 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -583,15 +583,14 @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls, | information. | Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN *----------------------------------------------------------------------------*/ -#if defined(TARGET_ARM) -static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag cIsQNaN, flag cIsSNaN, flag infzero, - float_status *status) +static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls, + bool infzero, float_status *status) { +#if defined(TARGET_ARM) /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns * the default NaN */ - if (infzero && cIsQNaN) { + if (infzero && is_qnan(c_cls)) { float_raise(float_flag_invalid, status); return 3; } @@ -599,25 +598,20 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, /* This looks different from the ARM ARM pseudocode, because the ARM ARM * puts the operands to a fused mac operation (a*b)+c in the order c,a,b. */ - if (cIsSNaN) { + if (is_snan(c_cls)) { return 2; - } else if (aIsSNaN) { + } else if (is_snan(a_cls)) { return 0; - } else if (bIsSNaN) { + } else if (is_snan(b_cls)) { return 1; - } else if (cIsQNaN) { + } else if (is_qnan(c_cls)) { return 2; - } else if (aIsQNaN) { + } else if (is_qnan(a_cls)) { return 0; } else { return 1; } -} #elif defined(TARGET_MIPS) -static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag cIsQNaN, flag cIsSNaN, flag infzero, - float_status *status) -{ /* For MIPS, the (inf,zero,qnan) case sets InvalidOp and returns * the default NaN */ @@ -628,41 +622,36 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, if (SNAN_BIT_IS_ONE(status)) { /* Prefer sNaN over qNaN, in the a, b, c order. */ - if (aIsSNaN) { + if (is_snan(a_cls)) { return 0; - } else if (bIsSNaN) { + } else if (is_snan(b_cls)) { return 1; - } else if (cIsSNaN) { + } else if (is_snan(c_cls)) { return 2; - } else if (aIsQNaN) { + } else if (is_qnan(a_cls)) { return 0; - } else if (bIsQNaN) { + } else if (is_qnan(b_cls)) { return 1; } else { return 2; } } else { /* Prefer sNaN over qNaN, in the c, a, b order. */ - if (cIsSNaN) { + if (is_snan(c_cls)) { return 2; - } else if (aIsSNaN) { + } else if (is_snan(a_cls)) { return 0; - } else if (bIsSNaN) { + } else if (is_snan(b_cls)) { return 1; - } else if (cIsQNaN) { + } else if (is_qnan(c_cls)) { return 2; - } else if (aIsQNaN) { + } else if (is_qnan(a_cls)) { return 0; } else { return 1; } } -} #elif defined(TARGET_PPC) -static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag cIsQNaN, flag cIsSNaN, flag infzero, - float_status *status) -{ /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer * to return an input NaN if we have one (ie c) rather than generating * a default NaN @@ -675,31 +664,26 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, /* If fRA is a NaN return it; otherwise if fRB is a NaN return it; * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB */ - if (aIsSNaN || aIsQNaN) { + if (is_nan(a_cls)) { return 0; - } else if (cIsSNaN || cIsQNaN) { + } else if (is_nan(c_cls)) { return 2; } else { return 1; } -} #else -/* A default implementation: prefer a to b to c. - * This is unlikely to actually match any real implementation. - */ -static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, - flag cIsQNaN, flag cIsSNaN, flag infzero, - float_status *status) -{ - if (aIsSNaN || aIsQNaN) { + /* A default implementation: prefer a to b to c. + * This is unlikely to actually match any real implementation. + */ + if (is_nan(a_cls)) { return 0; - } else if (bIsSNaN || bIsQNaN) { + } else if (is_nan(b_cls)) { return 1; } else { return 2; } -} #endif +} /*---------------------------------------------------------------------------- | Takes two single-precision floating-point values `a' and `b', one of which diff --git a/fpu/softfloat.c b/fpu/softfloat.c index cd56beb277..4e957a5d6f 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -182,17 +182,17 @@ typedef enum __attribute__ ((__packed__)) { } FloatClass; /* Simple helpers for checking if what NaN we have */ -static bool is_nan(FloatClass c) +static inline __attribute__((unused)) bool is_nan(FloatClass c) { return unlikely(c >= float_class_qnan); } -static bool is_snan(FloatClass c) +static inline __attribute__((unused)) bool is_snan(FloatClass c) { return c == float_class_snan; } -static bool is_qnan(FloatClass c) +static inline __attribute__((unused)) bool is_qnan(FloatClass c) { return c == float_class_qnan; } @@ -612,10 +612,7 @@ static FloatParts pick_nan_muladd(FloatParts a, FloatParts b, FloatParts c, if (s->default_nan_mode) { return parts_default_nan(s); } else { - switch (pickNaNMulAdd(is_qnan(a.cls), is_snan(a.cls), - is_qnan(b.cls), is_snan(b.cls), - is_qnan(c.cls), is_snan(c.cls), - inf_zero, s)) { + switch (pickNaNMulAdd(a.cls, b.cls, c.cls, inf_zero, s)) { case 0: break; case 1: