From patchwork Fri May 11 02:03:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 135463 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp297739lji; Thu, 10 May 2018 19:04:23 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpBcoXKSSaoM/ePoFimmUyMOMCf1AdNw7Kt+7oxaMGOBzscnq22KRH4DxgZBTa9CIny2x7Y X-Received: by 2002:a63:7f07:: with SMTP id a7-v6mr2887267pgd.173.1526004263385; Thu, 10 May 2018 19:04:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526004263; cv=none; d=google.com; s=arc-20160816; b=Dfo2WLYj/H5q1SfBBSfZVv0OCjDe7FYwyT6szI6zg7u9UV4xxw1XZLgTKVD41pd0Jp NBAIuekJ8d2JLKtP0MjQ7jPcB++bzC2DmeNYbyLWP8am+N23Cfg7CQEv7+0Ji1lPf/pO suDwmlq/rMEEiFGkNc+X2W4YxRIjmR1xz+QnpIgkIoB15rdpq1UoAi66fggr3c1kJDmC GvyPdqBwuHuFqt0RyS75f0HRRfYl6qa7U/a54zAcd9dmwRE3dtXIHa4U3ypQHA2DnTHi mmFeEEqK23VEOArOHLGIxgGgQqHMjHUca/AE6YDPhdnrG4BDL5lrgxxWiwq/TVtUoZZN I+UA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=oLY9f8ekmL//C6gdaNKhXDNnwSW7gd5XZVqsz6lNt0Y=; b=mRQHdU8RhrpD3shhTsq0CZKwUoLV2edQmutp+mvuM5Geu94ULfYJAVWz6n6Y3XQ6Rd yBeXi21RpqkDcYyz/IRAxG/FXqJ+9yCLG0eQXi3KxDntDUWU+98nVbbUZIkW7aJVnWSb iX1Il7LTL8dN7AhMcLKBdvufy8EztAeyLn3CTZbDNc3dicjIz9AVq+BZ1ZA2cK0tPKAm hPYDAldULRariuoInCE5+Wf2WJpXCd9F3TvYCcRP/2Iv1g3poVD2EP98EnxFw8mjeMqU liUpE5YpUx8uuj1jOrzlJRS3OksQhh3eH14bH083qvop6LmsXxAXYtLJAsMGL1qih7+7 /ZFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=O55ZvRBg; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k7-v6si2186867pls.368.2018.05.10.19.04.22; Thu, 10 May 2018 19:04:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=O55ZvRBg; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750937AbeEKCEV (ORCPT + 6 others); Thu, 10 May 2018 22:04:21 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:34789 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750798AbeEKCEV (ORCPT ); Thu, 10 May 2018 22:04:21 -0400 Received: by mail-pf0-f195.google.com with SMTP id a14-v6so1955359pfi.1 for ; Thu, 10 May 2018 19:04:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=ZOe5xm/kAn1ifE+NyKuVnvTnIf3aOMXUUFkL1Xm4QrM=; b=O55ZvRBggwewY8KXlO3QctXQgwYJJJxGu9ZUg8n3bF4KdTOfvKVqlUI9IJ/bUoEMO/ xbDEbkt2N3bvFfWzshoWUudLhdZ2kZtHGteOGV1NkfRW9QxUACqU5hRioNqN1R6AAC1N 2LFdmjAV6dMpCZtQesVmAHDFfY4jX4+2teB7I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=ZOe5xm/kAn1ifE+NyKuVnvTnIf3aOMXUUFkL1Xm4QrM=; b=MzMQ6ZLI7IFvNwMHIj2YNwoetBPArHH9qeGpHasGTJFRi54354S+JLF8VpWU9O3fPF bPHmjGNFKlyH+83LkSSMFYAblXla27uEWSIjUbk5sRgrbXs/adLZjFk7YETIUgKT2Lad /XR5K9htIk8uiEofMp8iJ58SHrT7jLAZ2FmF+0hygYggZ7l1LY2tQ57pTEbgfPiNKhBn DKBNwcbiIH3xUYxXUy2aaU4HmeAKFtdh96oMRdxXFJvO+tCZ3xVw9esBMemjLSY7AvvE lpHP2nKPvuHodi38HVbotIUIccE3hZ/CHG/xFRTAipwd3Q0I3NIDlsUMWdyMdP6OnnkB L53A== X-Gm-Message-State: ALKqPwdUGyt4vXSbtDr38VNWO7vljwMlvXPJ2TBtQwoi+Qcalp8fJcqR bkOO6t3m/lkd38dZsOpLqiECPg== X-Received: by 2002:a65:4d0b:: with SMTP id i11-v6mr1192149pgt.51.1526004260298; Thu, 10 May 2018 19:04:20 -0700 (PDT) Received: from localhost.localdomain ([45.56.152.100]) by smtp.gmail.com with ESMTPSA id x5-v6sm2955254pgv.15.2018.05.10.19.04.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 10 May 2018 19:04:18 -0700 (PDT) From: Shawn Guo To: Wei Xu Cc: Jianguo Sun , Jiancheng Xue , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Shawn Guo Subject: [PATCH 1/3] arm64: dts: hi3798cv200: enable PCIe support for poplar board Date: Fri, 11 May 2018 10:03:38 +0800 Message-Id: <1526004220-17030-1-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org It adds combophy devices under peripheral controller and enables PCIe support for Hi3798CV200 Poplar board. Signed-off-by: Shawn Guo --- .../boot/dts/hisilicon/hi3798cv200-poplar.dts | 15 ++++++ arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 63 ++++++++++++++++++++++ 2 files changed, 78 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts index 4d5d644abb12..c4382e1f3c92 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts @@ -61,6 +61,15 @@ default-state = "off"; }; }; + + reg_pcie: regulator-pcie { + compatible = "regulator-fixed"; + regulator-name = "3V3_PCIE0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio6 7 0>; + enable-active-high; + }; }; &gmac1 { @@ -146,6 +155,12 @@ status = "okay"; }; +&pcie { + reset-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; + vpcie-supply = <®_pcie>; + status = "okay"; +}; + &sd0 { bus-width = <4>; cap-sd-highspeed; diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index 962bd79139e4..5b73403551e6 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -8,7 +8,9 @@ */ #include +#include #include +#include #include / { @@ -106,6 +108,37 @@ #reset-cells = <2>; }; + perictrl: peripheral-controller@8a20000 { + compatible = "hisilicon,hi3798cv200-perictrl", "syscon", + "simple-mfd"; + reg = <0x8a20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8a20000 0x1000>; + + combphy0: phy@850 { + compatible = "hisilicon,hi3798cv200-combphy"; + reg = <0x850 0x8>; + #phy-cells = <1>; + clocks = <&crg HISTB_COMBPHY0_CLK>; + resets = <&crg 0x188 4>; + assigned-clocks = <&crg HISTB_COMBPHY0_CLK>; + assigned-clock-rates = <100000000>; + hisilicon,fixed-mode = ; + }; + + combphy1: phy@858 { + compatible = "hisilicon,hi3798cv200-combphy"; + reg = <0x858 0x8>; + #phy-cells = <1>; + clocks = <&crg HISTB_COMBPHY1_CLK>; + resets = <&crg 0x188 12>; + assigned-clocks = <&crg HISTB_COMBPHY1_CLK>; + assigned-clock-rates = <100000000>; + hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>; + }; + }; + uart0: serial@8b00000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x8b00000 0x1000>; @@ -419,5 +452,35 @@ clocks = <&sysctrl HISTB_IR_CLK>; status = "disabled"; }; + + pcie: pcie@9860000 { + compatible = "hisilicon,hi3798cv200-pcie"; + reg = <0x9860000 0x1000>, + <0x0 0x2000>, + <0x2000000 0x01000000>; + reg-names = "control", "rc-dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0 15>; + num-lanes = <1>; + ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000 + 0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_PCIE_AUX_CLK>, + <&crg HISTB_PCIE_PIPE_CLK>, + <&crg HISTB_PCIE_SYS_CLK>, + <&crg HISTB_PCIE_BUS_CLK>; + clock-names = "aux", "pipe", "sys", "bus"; + resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>; + reset-names = "soft", "sys", "bus"; + phys = <&combphy1 PHY_TYPE_PCIE>; + phy-names = "phy"; + status = "disabled"; + }; }; }; From patchwork Fri May 11 02:03:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 135464 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp297817lji; Thu, 10 May 2018 19:04:30 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpxsSLZj0PbOZY40lI/dVgT/S1nNJimvuSupuZ9cTF7NhaWxonubnwiVMPOftA4OFEH+k6k X-Received: by 2002:a62:32c6:: with SMTP id y189-v6mr3506978pfy.241.1526004270735; Thu, 10 May 2018 19:04:30 -0700 (PDT) ARC-Seal: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id s12-v6si1826064pgn.194.2018.05.10.19.04.30; Thu, 10 May 2018 19:04:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Y9c3nN3C; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751168AbeEKCE3 (ORCPT + 6 others); Thu, 10 May 2018 22:04:29 -0400 Received: from mail-pf0-f193.google.com ([209.85.192.193]:40210 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751345AbeEKCE2 (ORCPT ); Thu, 10 May 2018 22:04:28 -0400 Received: by mail-pf0-f193.google.com with SMTP id f189-v6so1949437pfa.7 for ; Thu, 10 May 2018 19:04:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HHYmCJ6DQqNeKa4Aixp/iPqCwVOL9Rw83wrdq3fOQwY=; b=Y9c3nN3CLm9i2piWJzBDHpuQSkhHYeZqZpMrZPFG6uKc7pcnY/gWrW44gUlyfSidnz mY/MMKW5VWsi5OOYMaKmuElyPo5WoTKjq5LKXsQ+tWuNp1lDfdkt+Nm4ykbA/CsWuFVG 838Mnh7sCwqmin658eTEDR/W+26mI8/m+QMq4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HHYmCJ6DQqNeKa4Aixp/iPqCwVOL9Rw83wrdq3fOQwY=; b=YsTt1q3tzuFYsq5ytBRVSl91ABaUu5J22BCiw9Mbtq9OnqhaiJPO299hNqNsWKcSs8 Ck6WzlHhJOv4JSgPloKDseq97IuibqWKCdo5ZZO/NHA2DnSRb6YNWSsNH0W/0bYevpUT IO5GDI4M9h2bsmUWJMuggeaoMAFyo6YeU9IZamDGOYm/ylz1bxU1m9MfRRmA5z1QLg7T hGlTMwFyAw0plEvscXqNRULJzugALvrCHoHIvMuZLBBJ+a5AdajznaquQ+i4ut9ZLpqp ewMLMVY9lasWrwc45OuwDhvd/4B4MqgvjZUb1U7TJk6p3MQ/ibyw0ImTXKo7v7Q2hopi B6+g== X-Gm-Message-State: ALKqPwfu0KMHLbtx0X7j4z7K03NpQbH0hbsRLB/85Ht/R3hw9b8kaIMd I/pALgf5NH74GoZDgiuEMqNvBQ== X-Received: by 2002:a62:ce4e:: with SMTP id y75-v6mr3464476pfg.175.1526004268264; Thu, 10 May 2018 19:04:28 -0700 (PDT) Received: from localhost.localdomain ([45.56.152.100]) by smtp.gmail.com with ESMTPSA id x5-v6sm2955254pgv.15.2018.05.10.19.04.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 10 May 2018 19:04:26 -0700 (PDT) From: Shawn Guo To: Wei Xu Cc: Jianguo Sun , Jiancheng Xue , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Shawn Guo Subject: [PATCH 2/3] arm64: dts: hi3798cv200: enable usb2 support for poplar board Date: Fri, 11 May 2018 10:03:39 +0800 Message-Id: <1526004220-17030-2-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1526004220-17030-1-git-send-email-shawn.guo@linaro.org> References: <1526004220-17030-1-git-send-email-shawn.guo@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org It adds usb2 phy devices, and enables ehci/ohci support for Hi3798CV200 Poplar board. Signed-off-by: Shawn Guo --- .../boot/dts/hisilicon/hi3798cv200-poplar.dts | 8 +++ arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 68 ++++++++++++++++++++++ 2 files changed, 76 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts index c4382e1f3c92..b0b790a5aa8d 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts @@ -72,6 +72,10 @@ }; }; +&ehci { + status = "okay"; +}; + &gmac1 { status = "okay"; #address-cells = <1>; @@ -155,6 +159,10 @@ status = "okay"; }; +&ohci { + status = "okay"; +}; + &pcie { reset-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; vpcie-supply = <®_pcie>; diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index 5b73403551e6..c1723ef01cac 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -116,6 +116,42 @@ #size-cells = <1>; ranges = <0x0 0x8a20000 0x1000>; + usb2_phy1: usb2-phy@120 { + compatible = "hisilicon,hi3798cv200-usb2-phy"; + reg = <0x120 0x4>; + clocks = <&crg HISTB_USB2_PHY1_REF_CLK>; + resets = <&crg 0xbc 4>; + #address-cells = <1>; + #size-cells = <0>; + + usb2_phy1_port0: phy@0 { + reg = <0>; + #phy-cells = <0>; + resets = <&crg 0xbc 8>; + }; + + usb2_phy1_port1: phy@1 { + reg = <1>; + #phy-cells = <0>; + resets = <&crg 0xbc 9>; + }; + }; + + usb2_phy2: usb2-phy@124 { + compatible = "hisilicon,hi3798cv200-usb2-phy"; + reg = <0x124 0x4>; + clocks = <&crg HISTB_USB2_PHY2_REF_CLK>; + resets = <&crg 0xbc 6>; + #address-cells = <1>; + #size-cells = <0>; + + usb2_phy2_port0: phy@0 { + reg = <0>; + #phy-cells = <0>; + resets = <&crg 0xbc 10>; + }; + }; + combphy0: phy@850 { compatible = "hisilicon,hi3798cv200-combphy"; reg = <0x850 0x8>; @@ -482,5 +518,37 @@ phy-names = "phy"; status = "disabled"; }; + + ohci: ohci@9880000 { + compatible = "generic-ohci"; + reg = <0x9880000 0x10000>; + interrupts = ; + clocks = <&crg HISTB_USB2_BUS_CLK>, + <&crg HISTB_USB2_12M_CLK>, + <&crg HISTB_USB2_48M_CLK>; + clock-names = "bus", "clk12", "clk48"; + resets = <&crg 0xb8 12>; + reset-names = "bus"; + phys = <&usb2_phy1_port0>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci: ehci@9890000 { + compatible = "generic-ehci"; + reg = <0x9890000 0x10000>; + interrupts = ; + clocks = <&crg HISTB_USB2_BUS_CLK>, + <&crg HISTB_USB2_PHY_CLK>, + <&crg HISTB_USB2_UTMI_CLK>; + clock-names = "bus", "phy", "utmi"; + resets = <&crg 0xb8 12>, + <&crg 0xb8 16>, + <&crg 0xb8 13>; + reset-names = "bus", "phy", "utmi"; + phys = <&usb2_phy1_port0>; + phy-names = "usb"; + status = "disabled"; + }; }; }; From patchwork Fri May 11 02:03:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 135465 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp297873lji; Thu, 10 May 2018 19:04:37 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpDTA6DTPK1QSjstmukPhDtLJYPiK8uwTxIICKZGq1cjl3imVNsRzefDGo/WrTrZktr4zxY X-Received: by 2002:a62:981d:: with SMTP id q29-v6mr3540977pfd.65.1526004276906; Thu, 10 May 2018 19:04:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526004276; cv=none; d=google.com; s=arc-20160816; b=DerEzsx+eHO4n8Ut/SurZkzXu2KeI7bVn72Kj4/FbL2M/uuWYlp2nIXMHOrdfOB1w4 MagE4XMKJnqaOhua7EWEBfcQ/dk1ow07xN5gkNrwnFbxrOQVETlxeGZnCSkR6QpISUN8 MzcgcG/FM5gbx2EffMwsj7lCkK/T08Ql1RRUhpsOegODrPBKFQUQ9t2kwCGmfkX3/4Ga JoyvM4VyqSFtZ+2NFBycYabsq/MbrcXHl1qdP4alg88+PnVmx+asyyCZaQqs9a4VtDG7 UeHkqPC81k7P63VPOeoRGYPAhOgf8p5F/pzNtaeVpWNEHKtDVh9wbCKbkCn6G+9hQKqv wJwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=htaHVxkYH39bacc4sIILQ3ZS7Yq/eljZ2y1VVJlifnI=; b=AV4mxeXUQBp702MPq4chLG0VqzZHgYd+IFfe3SVz5h+Qphpl+ELj3xxs+JgX5ODlTp 8hzw8lO/y5ttbF7TUmM8AUOBSwBsFbmJ9rBZdJo9NNWdgzrBelOVjETFGmjl5XgDU4xZ +p7tbPlCfoG+nbdrsorlkYYqK8MogG0OyuZP+VlIUeSBJZ25io9mEDxpGHYfPuh1gbaI 5Yil+OMf9IdYAM33zg9frZNw1uyP379KtFPbXCMW9qBau/p8SlXBfJQ9WZlEMZ/1VDjg z5REM8WN/JExWdMEkS2q0Ci7AgaJsy3TqeHKA1uA2C2hc+1xkwTFZLd6U18ok87YifTf ACxg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Ovj7UsDn; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s12-v6si1826064pgn.194.2018.05.10.19.04.36; Thu, 10 May 2018 19:04:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Ovj7UsDn; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751462AbeEKCEg (ORCPT + 6 others); Thu, 10 May 2018 22:04:36 -0400 Received: from mail-pl0-f66.google.com ([209.85.160.66]:34060 "EHLO mail-pl0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751345AbeEKCEf (ORCPT ); Thu, 10 May 2018 22:04:35 -0400 Received: by mail-pl0-f66.google.com with SMTP id ay10-v6so2367848plb.1 for ; Thu, 10 May 2018 19:04:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3BFTN3Jt0pZlZ2FctEDh45Uk4/bDwK/w+XReCM/J1yQ=; b=Ovj7UsDnVoQUELdaDHSJ2uN9EjrGAf3nPCgqIvGB0PZFJRaZXUMuo9ojWnY0LieeIp d0/K5wm3hZxj3l7sUgxMpo0Dm3YgwAxVFZE5or57SLDwiIvf9AhKiA8jO++pcTO2v6jd WPSfvOvG4zuQ6JoWA9l52GQp9/XTMFP8R5BBc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3BFTN3Jt0pZlZ2FctEDh45Uk4/bDwK/w+XReCM/J1yQ=; b=gL83GS5h4fiywBTXoygQUby0Ioe+oXADJrVC9zkXZkao6d2sUKpbJMXuciX7mIVClT wg4GZA1+WdIRxQxmXx8hzvyD0HsqpTy/w7FH56IKZJ20nd2j+RGx2jtAS448o8bIcvzM YeFEYb7NJ9RCJhrHJmo5vEbwYYwzIcNOyoUzLuC4TSzKcAJ1jmtfYRtlXX2NzFgdVTP2 ZK7Y8OzJNIxT/XTOH0pnTw4mmO3TBdVDARx0/NqkyjDfrSLf1Xy2C2h3uyJFfpO+BSoK jB46eFVkk4l3WemZ0zN2oKdN0m22eNtJXUNfgFIIbfwVR/3qHs7LNiOtlyuNC2m2pFQY T7LA== X-Gm-Message-State: ALKqPwdRdpYnblAghbAQb/cuzfvB/FyMHkTFAva9dNSSMp8FQ5xgcF92 SG/heygAp1tLekMxxTMhKXvVZw== X-Received: by 2002:a17:902:33a5:: with SMTP id b34-v6mr3565749plc.232.1526004274662; Thu, 10 May 2018 19:04:34 -0700 (PDT) Received: from localhost.localdomain ([45.56.152.100]) by smtp.gmail.com with ESMTPSA id x5-v6sm2955254pgv.15.2018.05.10.19.04.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 10 May 2018 19:04:33 -0700 (PDT) From: Shawn Guo To: Wei Xu Cc: Jianguo Sun , Jiancheng Xue , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Shawn Guo Subject: [PATCH 3/3] arm64: dts: hi3798cv200: enable emmc support for poplar board Date: Fri, 11 May 2018 10:03:40 +0800 Message-Id: <1526004220-17030-3-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1526004220-17030-1-git-send-email-shawn.guo@linaro.org> References: <1526004220-17030-1-git-send-email-shawn.guo@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org It adds pinctrl device pinconf@8a21000, gpio-ranges for GPIO devices, and then enables eMMC support for Hi3798CV200 Poplar board. Signed-off-by: Shawn Guo --- .../boot/dts/hisilicon/hi3798cv200-poplar.dts | 15 ++++ arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi | 74 +++++++++++++++- arch/arm64/boot/dts/hisilicon/poplar-pinctrl.dtsi | 98 ++++++++++++++++++++++ 3 files changed, 184 insertions(+), 3 deletions(-) create mode 100644 arch/arm64/boot/dts/hisilicon/poplar-pinctrl.dtsi -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts index b0b790a5aa8d..d30f6eb8a5ee 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts @@ -11,6 +11,7 @@ #include #include "hi3798cv200.dtsi" +#include "poplar-pinctrl.dtsi" / { model = "HiSilicon Poplar Development Board"; @@ -76,6 +77,20 @@ status = "okay"; }; +&emmc { + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins_1 &emmc_pins_2 + &emmc_pins_3 &emmc_pins_4>; + fifo-depth = <256>; + clock-frequency = <200000000>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + bus-width = <8>; + status = "okay"; +}; + &gmac1 { status = "okay"; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index c1723ef01cac..7c0fddd7c8cf 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -175,6 +175,46 @@ }; }; + pmx0: pinconf@8a21000 { + compatible = "pinconf-single"; + reg = <0x8a21000 0x180>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <7>; + pinctrl-single,gpio-range = < + &range 0 8 2 /* GPIO 0 */ + &range 8 1 0 /* GPIO 1 */ + &range 9 4 2 + &range 13 1 0 + &range 14 1 1 + &range 15 1 0 + &range 16 5 0 /* GPIO 2 */ + &range 21 3 1 + &range 24 4 1 /* GPIO 3 */ + &range 28 2 2 + &range 86 1 1 + &range 87 1 0 + &range 30 4 2 /* GPIO 4 */ + &range 34 3 0 + &range 37 1 2 + &range 38 3 2 /* GPIO 6 */ + &range 41 5 0 + &range 46 8 1 /* GPIO 7 */ + &range 54 8 1 /* GPIO 8 */ + &range 64 7 1 /* GPIO 9 */ + &range 71 1 0 + &range 72 6 1 /* GPIO 10 */ + &range 78 1 0 + &range 79 1 1 + &range 80 6 1 /* GPIO 11 */ + &range 70 2 1 + &range 88 8 0 /* GPIO 12 */ + >; + + range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; + }; + uart0: serial@8b00000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x8b00000 0x1000>; @@ -274,12 +314,17 @@ }; emmc: mmc@9830000 { - compatible = "snps,dw-mshc"; + compatible = "hisilicon,hi3798cv200-dw-mshc"; reg = <0x9830000 0x10000>; interrupts = ; clocks = <&crg HISTB_MMC_CIU_CLK>, - <&crg HISTB_MMC_BIU_CLK>; - clock-names = "ciu", "biu"; + <&crg HISTB_MMC_BIU_CLK>, + <&crg HISTB_MMC_SAMPLE_CLK>, + <&crg HISTB_MMC_DRV_CLK>; + clock-names = "ciu", "biu", "ciu-sample", "ciu-drive"; + resets = <&crg 0xa0 4>; + reset-names = "reset"; + status = "disabled"; }; gpio0: gpio@8b20000 { @@ -290,6 +335,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&pmx0 0 0 8>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; @@ -303,6 +349,13 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = < + &pmx0 0 8 1 + &pmx0 1 9 4 + &pmx0 5 13 1 + &pmx0 6 14 1 + &pmx0 7 15 1 + >; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; @@ -316,6 +369,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&pmx0 0 16 5 &pmx0 5 21 3>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; @@ -329,6 +383,12 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = < + &pmx0 0 24 4 + &pmx0 4 28 2 + &pmx0 6 86 1 + &pmx0 7 87 1 + >; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; @@ -342,6 +402,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; @@ -368,6 +429,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&pmx0 0 38 3 &pmx0 0 41 5>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; @@ -381,6 +443,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&pmx0 0 46 8>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; @@ -394,6 +457,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&pmx0 0 54 8>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; @@ -407,6 +471,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; @@ -420,6 +485,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; @@ -433,6 +499,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&pmx0 0 80 6 &pmx0 6 70 2>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; @@ -446,6 +513,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&pmx0 0 88 8>; clocks = <&crg HISTB_APB_CLK>; clock-names = "apb_pclk"; status = "disabled"; diff --git a/arch/arm64/boot/dts/hisilicon/poplar-pinctrl.dtsi b/arch/arm64/boot/dts/hisilicon/poplar-pinctrl.dtsi new file mode 100644 index 000000000000..7bb19e4b084a --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/poplar-pinctrl.dtsi @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Pinctrl dts file for HiSilicon Poplar board + * + * Copyright (c) 2016-2018 HiSilicon Technologies Co., Ltd. + */ + +#include + +/* value, enable bits, disable bits, mask */ +#define PINCTRL_PULLDOWN(value, enable, disable, mask) \ + (value << 13) (enable << 13) (disable << 13) (mask << 13) +#define PINCTRL_PULLUP(value, enable, disable, mask) \ + (value << 12) (enable << 12) (disable << 12) (mask << 12) +#define PINCTRL_SLEW_RATE(value, mask) (value << 8) (mask << 8) +#define PINCTRL_DRV_STRENGTH(value, mask) (value << 4) (mask << 4) + +&pmx0 { + emmc_pins_1: emmc-pins-1 { + pinctrl-single,pins = < + 0x000 MUX_M2 + 0x004 MUX_M2 + 0x008 MUX_M2 + 0x00c MUX_M2 + 0x010 MUX_M2 + 0x014 MUX_M2 + 0x018 MUX_M2 + 0x01c MUX_M2 + 0x024 MUX_M2 + >; + pinctrl-single,bias-pulldown = < + PINCTRL_PULLDOWN(0, 1, 0, 1) + >; + pinctrl-single,bias-pullup = < + PINCTRL_PULLUP(0, 1, 0, 1) + >; + pinctrl-single,slew-rate = < + PINCTRL_SLEW_RATE(1, 1) + >; + pinctrl-single,drive-strength = < + PINCTRL_DRV_STRENGTH(0xb, 0xf) + >; + }; + + emmc_pins_2: emmc-pins-2 { + pinctrl-single,pins = < + 0x028 MUX_M2 + >; + pinctrl-single,bias-pulldown = < + PINCTRL_PULLDOWN(0, 1, 0, 1) + >; + pinctrl-single,bias-pullup = < + PINCTRL_PULLUP(0, 1, 0, 1) + >; + pinctrl-single,slew-rate = < + PINCTRL_SLEW_RATE(1, 1) + >; + pinctrl-single,drive-strength = < + PINCTRL_DRV_STRENGTH(0x9, 0xf) + >; + }; + + emmc_pins_3: emmc-pins-3 { + pinctrl-single,pins = < + 0x02c MUX_M2 + >; + pinctrl-single,bias-pulldown = < + PINCTRL_PULLDOWN(0, 1, 0, 1) + >; + pinctrl-single,bias-pullup = < + PINCTRL_PULLUP(0, 1, 0, 1) + >; + pinctrl-single,slew-rate = < + PINCTRL_SLEW_RATE(1, 1) + >; + pinctrl-single,drive-strength = < + PINCTRL_DRV_STRENGTH(3, 3) + >; + }; + + emmc_pins_4: emmc-pins-4 { + pinctrl-single,pins = < + 0x030 MUX_M2 + >; + pinctrl-single,bias-pulldown = < + PINCTRL_PULLDOWN(1, 1, 0, 1) + >; + pinctrl-single,bias-pullup = < + PINCTRL_PULLUP(0, 1, 0, 1) + >; + pinctrl-single,slew-rate = < + PINCTRL_SLEW_RATE(1, 1) + >; + pinctrl-single,drive-strength = < + PINCTRL_DRV_STRENGTH(3, 3) + >; + }; +};