From patchwork Tue Mar 23 12:06:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suzuki K Poulose X-Patchwork-Id: 406836 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4392394jai; Tue, 23 Mar 2021 05:08:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxijMcRWTmMZNN0nh42Wb0WgqSXjZ5GC/QwIPYQnDQVAa1PdDej8ImRhmpVO2wmvJkbSB8m X-Received: by 2002:a05:6402:51cd:: with SMTP id r13mr4325653edd.116.1616501312841; Tue, 23 Mar 2021 05:08:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616501312; cv=none; d=google.com; s=arc-20160816; b=KhnF4mG80qepkgYREqiqkZz5k+hNBnT9dnt5rjVG630uLp1I6UhXTHA0jkCxbUu0/p skAU7FOQjE1xjgRb6pI4NTtdFegdLA8ryNqCg1HUsFnjggDCaInlb8hqHALbHS/t/+dz PLSoau0xTIu+gdLTsj4w41N8yxzzD/9b1CjyP0OW8VjPQCdzZ6Rrx9j0oMLkhz6C4eqT hFxrxxyoueqKkVXhxe1c1yPBUJFXaMfE4suibDTtO2nmetsOg1iMzDslGcuPe8NwoLev fpbNk4RV1qoZdKFQvrk+HteH5yw9XGqs0kd0ZTAaHHQfguPpr+1dpt88CXbAUaQQXyim hYbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=+uCRT3i/6xyZXD5oSQhL7U6PcvD901hYoeNEG1I6q0g=; b=WOlRX130dj4xml/Nkd6DUrjgUtjCyZEEgIMLvgv1Zh8YTxo+N545sISmuD6eQXLo8j J4hwzapmJ49w5h2AAin8dYVjarEgVASiP1gdFpmjN2Wh0ydfmHKeHNR8zOjRG0b9gvH2 rtCTGkPYH0qjKrZvYptgU0Mj0RFNWVoA9mHwRFqBFa27KjP2wvA0mKgShLYYGLgv5U8l MT1RO7j4jZ3TwlfMwnwUBcCiuT8h/lsIbC097cm22Dgksy973OymiAsPe8qglpXSKiuY i4GTwWRUukX2+cou1Ph1xkQWyH/5zA1UoKhTU+BEkatzryTdZDUzrNICZHewLl1+7LDP StcA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id 11si13539829ejz.523.2021.03.23.05.08.32; Tue, 23 Mar 2021 05:08:32 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230494AbhCWMIA (ORCPT + 6 others); Tue, 23 Mar 2021 08:08:00 -0400 Received: from foss.arm.com ([217.140.110.172]:45178 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230259AbhCWMHc (ORCPT ); Tue, 23 Mar 2021 08:07:32 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 102D911B3; Tue, 23 Mar 2021 05:07:32 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.1.197.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7D8DF3F719; Tue, 23 Mar 2021 05:07:30 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, coresight@lists.linaro.org, mathieu.poirier@linaro.org, mike.leach@linaro.org, leo.yan@linaro.org, anshuman.khandual@arm.com, maz@kernel.org, catalin.marinas@arm.com, Suzuki K Poulose , devicetree@vger.kernel.org, Rob Herring Subject: [PATCH v5 13/19] dts: bindings: Document device tree bindings for ETE Date: Tue, 23 Mar 2021 12:06:41 +0000 Message-Id: <20210323120647.454211-14-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20210323120647.454211-1-suzuki.poulose@arm.com> References: <20210323120647.454211-1-suzuki.poulose@arm.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the device tree bindings for Embedded Trace Extensions. ETE can be connected to legacy coresight components and thus could optionally contain a connection graph as described by the CoreSight bindings. Cc: devicetree@vger.kernel.org Cc: Mathieu Poirier Cc: Mike Leach Cc: Rob Herring Signed-off-by: Suzuki K Poulose --- Changes since v4: - Fix the out-ports definition (Rob Herring) --- .../devicetree/bindings/arm/ete.yaml | 75 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/ete.yaml -- 2.24.1 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/arm/ete.yaml b/Documentation/devicetree/bindings/arm/ete.yaml new file mode 100644 index 000000000000..7f9b2d1e1147 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ete.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# Copyright 2021, Arm Ltd +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/ete.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: ARM Embedded Trace Extensions + +maintainers: + - Suzuki K Poulose + - Mathieu Poirier + +description: | + Arm Embedded Trace Extension(ETE) is a per CPU trace component that + allows tracing the CPU execution. It overlaps with the CoreSight ETMv4 + architecture and has extended support for future architecture changes. + The trace generated by the ETE could be stored via legacy CoreSight + components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer + Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to + legacy CoreSight components, a node must be listed per instance, along + with any optional connection graph as per the coresight bindings. + See bindings/arm/coresight.txt. + +properties: + $nodename: + pattern: "^ete([0-9a-f]+)$" + compatible: + items: + - const: arm,embedded-trace-extension + + cpu: + description: | + Handle to the cpu this ETE is bound to. + $ref: /schemas/types.yaml#/definitions/phandle + + out-ports: + description: | + Output connections from the ETE to legacy CoreSight trace bus. + $ref: /schemas/graph.yaml#/properties/ports + properties: + port: + description: Output connection from the ETE to legacy CoreSight Trace bus. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - cpu + +additionalProperties: false + +examples: + +# An ETE node without legacy CoreSight connections + - | + ete0 { + compatible = "arm,embedded-trace-extension"; + cpu = <&cpu_0>; + }; +# An ETE node with legacy CoreSight connections + - | + ete1 { + compatible = "arm,embedded-trace-extension"; + cpu = <&cpu_1>; + + out-ports { /* legacy coresight connection */ + port { + ete1_out_port: endpoint { + remote-endpoint = <&funnel_in_port0>; + }; + }; + }; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 9e876927c60d..3454ed1011c8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1761,6 +1761,7 @@ F: Documentation/ABI/testing/sysfs-bus-coresight-devices-* F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt F: Documentation/devicetree/bindings/arm/coresight-cti.yaml F: Documentation/devicetree/bindings/arm/coresight.txt +F: Documentation/devicetree/bindings/arm/ete.yaml F: Documentation/trace/coresight/* F: drivers/hwtracing/coresight/* F: include/dt-bindings/arm/coresight-cti-dt.h From patchwork Tue Mar 23 12:06:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suzuki K Poulose X-Patchwork-Id: 406837 Delivered-To: patch@linaro.org Received: by 2002:a02:8562:0:0:0:0:0 with SMTP id g89csp4392406jai; Tue, 23 Mar 2021 05:08:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxoLOQXbiAb9U/DjJ1deovxF/IY+jovfMBXRMDWRx250GtF9bklfB+ggKHl2FJiFr3cuIl7 X-Received: by 2002:a17:906:2e45:: with SMTP id r5mr4464536eji.380.1616501313488; Tue, 23 Mar 2021 05:08:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1616501313; cv=none; d=google.com; s=arc-20160816; b=LpyZBRppnbsSI3TkaLxOfYpe189qR7Jf3IyKc/Nj3oUlvMLv6LA/aF/tUHELSKqx2i QAxVoq2urNnt0ysSHYO9m78eIzh4VH2KnUGGzPBTRYZwT5r1ti/XpHi3ny85p3WOnsou laS7wacQmMezAn1xK1eZqFcr3k0oPtvy0K/h1vNh9m+n8B9VeD27aokxPDaAdHyvV6jI JcjSecoIMm+KpDJ56ezprsXy94petIMGywcCjgBbdVQJtDlTIHArj0lLuuq0SNFcmaVz hDB97f+w4wcvoUc0+EjAFRKraEmAdDbNZWeglkKmKV+ZnUMD6rk+lzMviEQCnY53R+rR 5uqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=HbUEme8B/nFpTU3Df5tcX4mXrB08yWfDi6cRJ+XQlXY=; b=Eu7cWnggMOYK/6bHf+Qp2Pk4I9Nl0NetLInz/sR9RuhCgAK9SruL7ML5tob8HcNQkO DJCKwmrDgKQMHXy1N12rXgrEWlD3mk9YgGVRGrXBZAl/ruIFlSxn3ndaivXPHaXl4fhn afXzDhZH/S95PXAYBf2HyGvS73LWNnacQhVnV6Ky9eVQg1pL98sCg7cFE6S60Nxki8oR rd49C97nps7DCYdi8DmyQmMbVR6yjc8phYiJACvRyI03N5VN03DOSBksfmzeDlKaB7mo AujIpj2YCVfB3Tza7LYgopXnS8wN546mE4PA0AKaKemwYLDYdVFNRYByJfKi4stpYJfD tR1A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id 11si13539829ejz.523.2021.03.23.05.08.33; Tue, 23 Mar 2021 05:08:33 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230516AbhCWMIE (ORCPT + 6 others); Tue, 23 Mar 2021 08:08:04 -0400 Received: from foss.arm.com ([217.140.110.172]:45242 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230385AbhCWMHm (ORCPT ); Tue, 23 Mar 2021 08:07:42 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0B75E106F; Tue, 23 Mar 2021 05:07:42 -0700 (PDT) Received: from ewhatever.cambridge.arm.com (ewhatever.cambridge.arm.com [10.1.197.1]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 795323F719; Tue, 23 Mar 2021 05:07:40 -0700 (PDT) From: Suzuki K Poulose To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, coresight@lists.linaro.org, mathieu.poirier@linaro.org, mike.leach@linaro.org, leo.yan@linaro.org, anshuman.khandual@arm.com, maz@kernel.org, catalin.marinas@arm.com, Suzuki K Poulose , Rob Herring , devicetree@vger.kernel.org Subject: [PATCH v5 19/19] dts: bindings: Document device tree bindings for Arm TRBE Date: Tue, 23 Mar 2021 12:06:47 +0000 Message-Id: <20210323120647.454211-20-suzuki.poulose@arm.com> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20210323120647.454211-1-suzuki.poulose@arm.com> References: <20210323120647.454211-1-suzuki.poulose@arm.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the device tree bindings for Trace Buffer Extension (TRBE). Cc: Anshuman Khandual Cc: Mathieu Poirier Cc: Rob Herring Cc: devicetree@vger.kernel.org Reviewed-by: Rob Herring Signed-off-by: Suzuki K Poulose --- .../devicetree/bindings/arm/trbe.yaml | 49 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/trbe.yaml -- 2.24.1 diff --git a/Documentation/devicetree/bindings/arm/trbe.yaml b/Documentation/devicetree/bindings/arm/trbe.yaml new file mode 100644 index 000000000000..4402d7bfd1fc --- /dev/null +++ b/Documentation/devicetree/bindings/arm/trbe.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# Copyright 2021, Arm Ltd +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/trbe.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: ARM Trace Buffer Extensions + +maintainers: + - Anshuman Khandual + +description: | + Arm Trace Buffer Extension (TRBE) is a per CPU component + for storing trace generated on the CPU to memory. It is + accessed via CPU system registers. The software can verify + if it is permitted to use the component by checking the + TRBIDR register. + +properties: + $nodename: + const: "trbe" + compatible: + items: + - const: arm,trace-buffer-extension + + interrupts: + description: | + Exactly 1 PPI must be listed. For heterogeneous systems where + TRBE is only supported on a subset of the CPUs, please consult + the arm,gic-v3 binding for details on describing a PPI partition. + maxItems: 1 + +required: + - compatible + - interrupts + +additionalProperties: false + +examples: + + - | + #include + + trbe { + compatible = "arm,trace-buffer-extension"; + interrupts = ; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index 3454ed1011c8..fbe863456ed1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1762,6 +1762,7 @@ F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt F: Documentation/devicetree/bindings/arm/coresight-cti.yaml F: Documentation/devicetree/bindings/arm/coresight.txt F: Documentation/devicetree/bindings/arm/ete.yaml +F: Documentation/devicetree/bindings/arm/trbe.yaml F: Documentation/trace/coresight/* F: drivers/hwtracing/coresight/* F: include/dt-bindings/arm/coresight-cti-dt.h