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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id t1-v6sm8695688pgu.41.2018.05.12.10.57.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 12 May 2018 10:57:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 12 May 2018 10:57:21 -0700 Message-Id: <20180512175724.5923-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512175724.5923-1-richard.henderson@linaro.org> References: <20180512175724.5923-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::241 Subject: [Qemu-devel] [PATCH 1/4] target/xtensa: Replace DISAS_UPDATE with DISAS_NORETURN X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jcmvbkbc@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The usage of DISAS_UPDATE is after noreturn helpers. It is thus indistinguishable from DISAS_NORETURN. Signed-off-by: Richard Henderson --- target/xtensa/translate.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) -- 2.17.0 diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index aad496347d..a1e63f9661 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -47,9 +47,6 @@ #include "exec/log.h" -/* is_jmp field values */ -#define DISAS_UPDATE DISAS_TARGET_0 /* cpu state was modified dynamically */ - struct DisasContext { const XtensaConfig *config; TranslationBlock *tb; @@ -317,7 +314,7 @@ static void gen_exception_cause(DisasContext *dc, uint32_t cause) tcg_temp_free(tcause); if (cause == ILLEGAL_INSTRUCTION_CAUSE || cause == SYSCALL_CAUSE) { - dc->is_jmp = DISAS_UPDATE; + dc->is_jmp = DISAS_NORETURN; } } @@ -339,7 +336,7 @@ static void gen_debug_exception(DisasContext *dc, uint32_t cause) tcg_temp_free(tpc); tcg_temp_free(tcause); if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) { - dc->is_jmp = DISAS_UPDATE; + dc->is_jmp = DISAS_NORETURN; } } @@ -351,7 +348,7 @@ static bool gen_check_privilege(DisasContext *dc) } #endif gen_exception_cause(dc, PRIVILEGED_CAUSE); - dc->is_jmp = DISAS_UPDATE; + dc->is_jmp = DISAS_NORETURN; return false; } @@ -360,7 +357,7 @@ static bool gen_check_cpenable(DisasContext *dc, unsigned cp) if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) && !(dc->cpenable & (1 << cp))) { gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp); - dc->is_jmp = DISAS_UPDATE; + dc->is_jmp = DISAS_NORETURN; return false; } return true; @@ -382,7 +379,7 @@ static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot) tcg_gen_exit_tb(0); } } - dc->is_jmp = DISAS_UPDATE; + dc->is_jmp = DISAS_NORETURN; } static void gen_jump(DisasContext *dc, TCGv dest) @@ -918,7 +915,7 @@ static bool gen_window_check1(DisasContext *dc, unsigned r1) TCGv_i32 w = tcg_const_i32(r1 / 4); gen_helper_window_check(cpu_env, pc, w); - dc->is_jmp = DISAS_UPDATE; + dc->is_jmp = DISAS_NORETURN; return false; } return true; @@ -1103,14 +1100,14 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) tcg_gen_insn_start(dc.pc); ++insn_count; gen_exception(&dc, EXCP_YIELD); - dc.is_jmp = DISAS_UPDATE; + dc.is_jmp = DISAS_NORETURN; goto done; } if (tb->flags & XTENSA_TBFLAG_EXCEPTION) { tcg_gen_insn_start(dc.pc); ++insn_count; gen_exception(&dc, EXCP_DEBUG); - dc.is_jmp = DISAS_UPDATE; + dc.is_jmp = DISAS_NORETURN; goto done; } @@ -1121,7 +1118,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) { tcg_gen_movi_i32(cpu_pc, dc.pc); gen_exception(&dc, EXCP_DEBUG); - dc.is_jmp = DISAS_UPDATE; + dc.is_jmp = DISAS_NORETURN; /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that From patchwork Sat May 12 17:57:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135651 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp2450568lji; Sat, 12 May 2018 10:58:08 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrmMmXoh+fZaVtMHucW2TcaF5TALItzVYeN09ed3smP1+vbjNHVnfP6z1RfJ2Ca6g7WJ267 X-Received: by 2002:ac8:1b17:: with SMTP id y23-v6mr2677556qtj.397.1526147888244; Sat, 12 May 2018 10:58:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526147888; cv=none; d=google.com; s=arc-20160816; b=l/A45ZgPYLSgIBj6aM870qNTPEsMverxbITotoaYocR0BajCNh4RtBDcMGS46czxtD 3/KylyjunsEu00psUC7rzTFSrdv8Fr78CruP/+/ErUcLUIjYw7j8z17uK7Fv6xJcThUN xMXxN9owE+Hha4DsC/tRb7BCszlk/fDtg+b1/SsOJMbFEX+C55rT+oV/PhOmiyLOgbyF R3+ncxX656Hbnvh1LCypTgAUnLjDOhReG3IPe/FsY7n+38L+4/IRQ8rNKetqEB3LJupr kEIXKsR1zWLEV+5Q1wm7WwUvXgNg4g0Osx/2ixSFJhRQcmJ+GAEfR2lXY27NCGg56UMl GqkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=2FxGm2PJnXeuNxcy5BLNHKtTBffRiMXv6b1ptlzADis=; b=iuLIt0cn7tlNHHy+NTlkDYTnbSP7fNS9R8AFViyPBocL3utxDfSm81wbKtn8ZKwptg vUvO5+a9nHHCcODw49IDDCk8ZBhtsnE+QgOvRFkFB4rlgYBAKRh+0KXjdMV1g5Psr4hm fMlSxNZ8SHuTyrAhHliwU1TEJ9JDQCUNvlKKe+Cr7MJC6Lc1/MJUl1B5F0EfnYUProio zeAqQx2pV+qcY77SABZlgFwYn/LMQvKWntpLIIBotebuIOdKRtA3eHdHGTbY6jpSeizX Qnlrht9ObU1vjF1IBuq7bVePd/1LWbJ+bswNf+fcg/bWu3JygYodx/Rgs71piirmLkWI M0Og== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=U3qipdr3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id t1-v6sm8695688pgu.41.2018.05.12.10.57.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 12 May 2018 10:57:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 12 May 2018 10:57:22 -0700 Message-Id: <20180512175724.5923-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512175724.5923-1-richard.henderson@linaro.org> References: <20180512175724.5923-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH 2/4] target/xtensa: Convert to DisasContextBase X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jcmvbkbc@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/xtensa/translate.c | 89 +++++++++++++++++++-------------------- 1 file changed, 43 insertions(+), 46 deletions(-) -- 2.17.0 diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index a1e63f9661..cc48d105e9 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -48,16 +48,13 @@ struct DisasContext { + DisasContextBase base; const XtensaConfig *config; - TranslationBlock *tb; uint32_t pc; - uint32_t next_pc; int cring; int ring; uint32_t lbeg; uint32_t lend; - int is_jmp; - int singlestep_enabled; bool sar_5bit; bool sar_m32_5bit; @@ -314,7 +311,7 @@ static void gen_exception_cause(DisasContext *dc, uint32_t cause) tcg_temp_free(tcause); if (cause == ILLEGAL_INSTRUCTION_CAUSE || cause == SYSCALL_CAUSE) { - dc->is_jmp = DISAS_NORETURN; + dc->base.is_jmp = DISAS_NORETURN; } } @@ -336,7 +333,7 @@ static void gen_debug_exception(DisasContext *dc, uint32_t cause) tcg_temp_free(tpc); tcg_temp_free(tcause); if (cause & (DEBUGCAUSE_IB | DEBUGCAUSE_BI | DEBUGCAUSE_BN)) { - dc->is_jmp = DISAS_NORETURN; + dc->base.is_jmp = DISAS_NORETURN; } } @@ -348,7 +345,7 @@ static bool gen_check_privilege(DisasContext *dc) } #endif gen_exception_cause(dc, PRIVILEGED_CAUSE); - dc->is_jmp = DISAS_NORETURN; + dc->base.is_jmp = DISAS_NORETURN; return false; } @@ -357,7 +354,7 @@ static bool gen_check_cpenable(DisasContext *dc, unsigned cp) if (option_enabled(dc, XTENSA_OPTION_COPROCESSOR) && !(dc->cpenable & (1 << cp))) { gen_exception_cause(dc, COPROCESSOR0_DISABLED + cp); - dc->is_jmp = DISAS_NORETURN; + dc->base.is_jmp = DISAS_NORETURN; return false; } return true; @@ -369,17 +366,17 @@ static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot) if (dc->icount) { tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount); } - if (dc->singlestep_enabled) { + if (dc->base.singlestep_enabled) { gen_exception(dc, EXCP_DEBUG); } else { if (slot >= 0) { tcg_gen_goto_tb(slot); - tcg_gen_exit_tb((uintptr_t)dc->tb + slot); + tcg_gen_exit_tb((uintptr_t)dc->base.tb + slot); } else { tcg_gen_exit_tb(0); } } - dc->is_jmp = DISAS_NORETURN; + dc->base.is_jmp = DISAS_NORETURN; } static void gen_jump(DisasContext *dc, TCGv dest) @@ -391,7 +388,7 @@ static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot) { TCGv_i32 tmp = tcg_const_i32(dest); #ifndef CONFIG_USER_ONLY - if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) { + if (((dc->base.pc_first ^ dest) & TARGET_PAGE_MASK) != 0) { slot = -1; } #endif @@ -408,7 +405,7 @@ static void gen_callw_slot(DisasContext *dc, int callinc, TCGv_i32 dest, tcallinc, PS_CALLINC_SHIFT, PS_CALLINC_LEN); tcg_temp_free(tcallinc); tcg_gen_movi_i32(cpu_R[callinc << 2], - (callinc << 30) | (dc->next_pc & 0x3fffffff)); + (callinc << 30) | (dc->base.pc_next & 0x3fffffff)); gen_jump_slot(dc, dest, slot); } @@ -421,7 +418,7 @@ static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot) { TCGv_i32 tmp = tcg_const_i32(dest); #ifndef CONFIG_USER_ONLY - if (((dc->tb->pc ^ dest) & TARGET_PAGE_MASK) != 0) { + if (((dc->base.pc_first ^ dest) & TARGET_PAGE_MASK) != 0) { slot = -1; } #endif @@ -432,15 +429,15 @@ static void gen_callwi(DisasContext *dc, int callinc, uint32_t dest, int slot) static bool gen_check_loop_end(DisasContext *dc, int slot) { if (option_enabled(dc, XTENSA_OPTION_LOOP) && - !(dc->tb->flags & XTENSA_TBFLAG_EXCM) && - dc->next_pc == dc->lend) { + !(dc->base.tb->flags & XTENSA_TBFLAG_EXCM) && + dc->base.pc_next == dc->lend) { TCGLabel *label = gen_new_label(); tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_SR[LCOUNT], 0, label); tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1); gen_jumpi(dc, dc->lbeg, slot); gen_set_label(label); - gen_jumpi(dc, dc->next_pc, -1); + gen_jumpi(dc, dc->base.pc_next, -1); return true; } return false; @@ -449,7 +446,7 @@ static bool gen_check_loop_end(DisasContext *dc, int slot) static void gen_jumpi_check_loop_end(DisasContext *dc, int slot) { if (!gen_check_loop_end(dc, slot)) { - gen_jumpi(dc, dc->next_pc, slot); + gen_jumpi(dc, dc->base.pc_next, slot); } } @@ -500,12 +497,12 @@ static bool gen_check_sr(DisasContext *dc, uint32_t sr, unsigned access) #ifndef CONFIG_USER_ONLY static bool gen_rsr_ccount(DisasContext *dc, TCGv_i32 d, uint32_t sr) { - if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_update_ccount(cpu_env); tcg_gen_mov_i32(d, cpu_SR[sr]); - if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { gen_io_end(); return true; } @@ -689,11 +686,11 @@ static bool gen_wsr_cpenable(DisasContext *dc, uint32_t sr, TCGv_i32 v) static void gen_check_interrupts(DisasContext *dc) { - if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_check_interrupts(cpu_env); - if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { gen_io_end(); } } @@ -747,11 +744,11 @@ static bool gen_wsr_ps(DisasContext *dc, uint32_t sr, TCGv_i32 v) static bool gen_wsr_ccount(DisasContext *dc, uint32_t sr, TCGv_i32 v) { - if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_wsr_ccount(cpu_env, v); - if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { gen_io_end(); gen_jumpi_check_loop_end(dc, 0); return true; @@ -788,11 +785,11 @@ static bool gen_wsr_ccompare(DisasContext *dc, uint32_t sr, TCGv_i32 v) tcg_gen_mov_i32(cpu_SR[sr], v); tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit); - if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_update_ccompare(cpu_env, tmp); - if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { gen_io_end(); gen_jumpi_check_loop_end(dc, 0); ret = true; @@ -892,14 +889,14 @@ static void gen_load_store_alignment(DisasContext *dc, int shift, #ifndef CONFIG_USER_ONLY static void gen_waiti(DisasContext *dc, uint32_t imm4) { - TCGv_i32 pc = tcg_const_i32(dc->next_pc); + TCGv_i32 pc = tcg_const_i32(dc->base.pc_next); TCGv_i32 intlevel = tcg_const_i32(imm4); - if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_waiti(cpu_env, pc, intlevel); - if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { gen_io_end(); } tcg_temp_free(pc); @@ -915,7 +912,7 @@ static bool gen_window_check1(DisasContext *dc, unsigned r1) TCGv_i32 w = tcg_const_i32(r1 / 4); gen_helper_window_check(cpu_env, pc, w); - dc->is_jmp = DISAS_NORETURN; + dc->base.is_jmp = DISAS_NORETURN; return false; } return true; @@ -966,7 +963,7 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) return; } - dc->next_pc = dc->pc + len; + dc->base.pc_next = dc->pc + len; for (i = 1; i < len; ++i) { b[i] = cpu_ldub_code(env, dc->pc + i); } @@ -1026,10 +1023,10 @@ static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) return; } } - if (dc->is_jmp == DISAS_NEXT) { + if (dc->base.is_jmp == DISAS_NEXT) { gen_check_loop_end(dc, 0); } - dc->pc = dc->next_pc; + dc->pc = dc->base.pc_next; } static inline unsigned xtensa_insn_len(CPUXtensaState *env, DisasContext *dc) @@ -1068,14 +1065,14 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) } dc.config = env->config; - dc.singlestep_enabled = cs->singlestep_enabled; - dc.tb = tb; + dc.base.singlestep_enabled = cs->singlestep_enabled; + dc.base.tb = tb; dc.pc = pc_start; dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK; dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring; dc.lbeg = env->sregs[LBEG]; dc.lend = env->sregs[LEND]; - dc.is_jmp = DISAS_NEXT; + dc.base.is_jmp = DISAS_NEXT; dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG; dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT; dc.cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >> @@ -1100,14 +1097,14 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) tcg_gen_insn_start(dc.pc); ++insn_count; gen_exception(&dc, EXCP_YIELD); - dc.is_jmp = DISAS_NORETURN; + dc.base.is_jmp = DISAS_NORETURN; goto done; } if (tb->flags & XTENSA_TBFLAG_EXCEPTION) { tcg_gen_insn_start(dc.pc); ++insn_count; gen_exception(&dc, EXCP_DEBUG); - dc.is_jmp = DISAS_NORETURN; + dc.base.is_jmp = DISAS_NORETURN; goto done; } @@ -1118,7 +1115,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) { tcg_gen_movi_i32(cpu_pc, dc.pc); gen_exception(&dc, EXCP_DEBUG); - dc.is_jmp = DISAS_NORETURN; + dc.base.is_jmp = DISAS_NORETURN; /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that @@ -1156,7 +1153,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) gen_exception(&dc, EXCP_DEBUG); break; } - } while (dc.is_jmp == DISAS_NEXT && + } while (dc.base.is_jmp == DISAS_NEXT && insn_count < max_insns && dc.pc - page_start < TARGET_PAGE_SIZE && dc.pc - page_start + xtensa_insn_len(env, &dc) <= TARGET_PAGE_SIZE @@ -1175,7 +1172,7 @@ done: gen_io_end(); } - if (dc.is_jmp == DISAS_NEXT) { + if (dc.base.is_jmp == DISAS_NEXT) { gen_jumpi(&dc, dc.pc, 0); } gen_tb_end(tb, insn_count); @@ -1480,7 +1477,7 @@ static void translate_break(DisasContext *dc, const uint32_t arg[], static void translate_call0(DisasContext *dc, const uint32_t arg[], const uint32_t par[]) { - tcg_gen_movi_i32(cpu_R[0], dc->next_pc); + tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next); gen_jumpi(dc, arg[0], 0); } @@ -1498,7 +1495,7 @@ static void translate_callx0(DisasContext *dc, const uint32_t arg[], if (gen_window_check1(dc, arg[0])) { TCGv_i32 tmp = tcg_temp_new_i32(); tcg_gen_mov_i32(tmp, cpu_R[arg[0]]); - tcg_gen_movi_i32(cpu_R[0], dc->next_pc); + tcg_gen_movi_i32(cpu_R[0], dc->base.pc_next); gen_jump(dc, tmp); tcg_temp_free(tmp); } @@ -1700,7 +1697,7 @@ static void translate_l32r(DisasContext *dc, const uint32_t arg[], if (gen_window_check1(dc, arg[0])) { TCGv_i32 tmp; - if (dc->tb->flags & XTENSA_TBFLAG_LITBASE) { + if (dc->base.tb->flags & XTENSA_TBFLAG_LITBASE) { tmp = tcg_const_i32(dc->raw_arg[1] - 1); tcg_gen_add_i32(tmp, cpu_SR[LITBASE], tmp); } else { @@ -1719,7 +1716,7 @@ static void translate_loop(DisasContext *dc, const uint32_t arg[], TCGv_i32 tmp = tcg_const_i32(lend); tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_R[arg[0]], 1); - tcg_gen_movi_i32(cpu_SR[LBEG], dc->next_pc); + tcg_gen_movi_i32(cpu_SR[LBEG], dc->base.pc_next); gen_helper_wsr_lend(cpu_env, tmp); tcg_temp_free(tmp); @@ -1730,7 +1727,7 @@ static void translate_loop(DisasContext *dc, const uint32_t arg[], gen_set_label(label); } - gen_jumpi(dc, dc->next_pc, 0); + gen_jumpi(dc, dc->base.pc_next, 0); } } From patchwork Sat May 12 17:57:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135653 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp2452425lji; Sat, 12 May 2018 11:00:44 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqlbfmVJKYyYhBru8hdxXvcLBYQGkEBnt3MYRr6N1yBSVEk63qplU4AidH77uZ0N5jx5lO+ X-Received: by 2002:a0c:bd0d:: with SMTP id m13-v6mr2983604qvg.233.1526148044873; Sat, 12 May 2018 11:00:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526148044; cv=none; d=google.com; s=arc-20160816; b=DS9exWW7/wLVRSGDqhO7W8U8Fn6U8I/uBCTAQMHgtS3iDhtQVH/XIOA53V1m/Cmx4y SlzGtkz1tQtDeY7iemNQx9s5Z6+gmO4qlUdjZIJRV7pZoiWCJACkq/uJYRh5+Kjj5yoh 47Op/gP86zZmAMYyJkfezA6pawir4SwZK1wlc0I8tPEM+nxvxUf5zKt2J96yM5MHPrt7 eOU22yIvs5S0PaJQEPajcgx7Ztbggmi1g3YesRjFFyLRO0a7nqFcbKBykvPXVeiHtSTD r+YKXhRaSPP3c0Zi3P/gCndqM0en9bQEkZ6X51NTuQ78JhxBaftptdxOZ3PCq0M2Ng/G 0mFA== ARC-Message-Signature: i=1; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id t1-v6sm8695688pgu.41.2018.05.12.10.57.30 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 12 May 2018 10:57:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 12 May 2018 10:57:23 -0700 Message-Id: <20180512175724.5923-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512175724.5923-1-richard.henderson@linaro.org> References: <20180512175724.5923-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH 3/4] target/xtensa: Change gen_intermediate_code dc to pointer X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jcmvbkbc@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This will reduce the size of the patch in the next patch, where the context will have to be a pointer. Signed-off-by: Richard Henderson --- target/xtensa/translate.c | 122 +++++++++++++++++++------------------- 1 file changed, 61 insertions(+), 61 deletions(-) -- 2.17.0 diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index cc48d105e9..45f32dc71f 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1051,7 +1051,7 @@ static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc) void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { CPUXtensaState *env = cs->env_ptr; - DisasContext dc; + DisasContext dc1, *dc = &dc1; int insn_count = 0; int max_insns = tb_cflags(tb) & CF_COUNT_MASK; uint32_t pc_start = tb->pc; @@ -1064,63 +1064,63 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) max_insns = TCG_MAX_INSNS; } - dc.config = env->config; - dc.base.singlestep_enabled = cs->singlestep_enabled; - dc.base.tb = tb; - dc.pc = pc_start; - dc.ring = tb->flags & XTENSA_TBFLAG_RING_MASK; - dc.cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc.ring; - dc.lbeg = env->sregs[LBEG]; - dc.lend = env->sregs[LEND]; - dc.base.is_jmp = DISAS_NEXT; - dc.debug = tb->flags & XTENSA_TBFLAG_DEBUG; - dc.icount = tb->flags & XTENSA_TBFLAG_ICOUNT; - dc.cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >> + dc->config = env->config; + dc->base.singlestep_enabled = cs->singlestep_enabled; + dc->base.tb = tb; + dc->pc = pc_start; + dc->ring = tb->flags & XTENSA_TBFLAG_RING_MASK; + dc->cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc->ring; + dc->lbeg = env->sregs[LBEG]; + dc->lend = env->sregs[LEND]; + dc->base.is_jmp = DISAS_NEXT; + dc->debug = tb->flags & XTENSA_TBFLAG_DEBUG; + dc->icount = tb->flags & XTENSA_TBFLAG_ICOUNT; + dc->cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >> XTENSA_TBFLAG_CPENABLE_SHIFT; - dc.window = ((tb->flags & XTENSA_TBFLAG_WINDOW_MASK) >> + dc->window = ((tb->flags & XTENSA_TBFLAG_WINDOW_MASK) >> XTENSA_TBFLAG_WINDOW_SHIFT); - if (dc.config->isa) { - dc.insnbuf = xtensa_insnbuf_alloc(dc.config->isa); - dc.slotbuf = xtensa_insnbuf_alloc(dc.config->isa); + if (dc->config->isa) { + dc->insnbuf = xtensa_insnbuf_alloc(dc->config->isa); + dc->slotbuf = xtensa_insnbuf_alloc(dc->config->isa); } - init_sar_tracker(&dc); - if (dc.icount) { - dc.next_icount = tcg_temp_local_new_i32(); + init_sar_tracker(dc); + if (dc->icount) { + dc->next_icount = tcg_temp_local_new_i32(); } gen_tb_start(tb); if ((tb_cflags(tb) & CF_USE_ICOUNT) && (tb->flags & XTENSA_TBFLAG_YIELD)) { - tcg_gen_insn_start(dc.pc); + tcg_gen_insn_start(dc->pc); ++insn_count; - gen_exception(&dc, EXCP_YIELD); - dc.base.is_jmp = DISAS_NORETURN; + gen_exception(dc, EXCP_YIELD); + dc->base.is_jmp = DISAS_NORETURN; goto done; } if (tb->flags & XTENSA_TBFLAG_EXCEPTION) { - tcg_gen_insn_start(dc.pc); + tcg_gen_insn_start(dc->pc); ++insn_count; - gen_exception(&dc, EXCP_DEBUG); - dc.base.is_jmp = DISAS_NORETURN; + gen_exception(dc, EXCP_DEBUG); + dc->base.is_jmp = DISAS_NORETURN; goto done; } do { - tcg_gen_insn_start(dc.pc); + tcg_gen_insn_start(dc->pc); ++insn_count; - if (unlikely(cpu_breakpoint_test(cs, dc.pc, BP_ANY))) { - tcg_gen_movi_i32(cpu_pc, dc.pc); - gen_exception(&dc, EXCP_DEBUG); - dc.base.is_jmp = DISAS_NORETURN; + if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { + tcg_gen_movi_i32(cpu_pc, dc->pc); + gen_exception(dc, EXCP_DEBUG); + dc->base.is_jmp = DISAS_NORETURN; /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we increment the PC here so that the logic setting tb->size below does the right thing. */ - dc.pc += 2; + dc->pc += 2; break; } @@ -1128,52 +1128,52 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) gen_io_start(); } - if (dc.icount) { + if (dc->icount) { TCGLabel *label = gen_new_label(); - tcg_gen_addi_i32(dc.next_icount, cpu_SR[ICOUNT], 1); - tcg_gen_brcondi_i32(TCG_COND_NE, dc.next_icount, 0, label); - tcg_gen_mov_i32(dc.next_icount, cpu_SR[ICOUNT]); - if (dc.debug) { - gen_debug_exception(&dc, DEBUGCAUSE_IC); + tcg_gen_addi_i32(dc->next_icount, cpu_SR[ICOUNT], 1); + tcg_gen_brcondi_i32(TCG_COND_NE, dc->next_icount, 0, label); + tcg_gen_mov_i32(dc->next_icount, cpu_SR[ICOUNT]); + if (dc->debug) { + gen_debug_exception(dc, DEBUGCAUSE_IC); } gen_set_label(label); } - if (dc.debug) { - gen_ibreak_check(env, &dc); + if (dc->debug) { + gen_ibreak_check(env, dc); } - disas_xtensa_insn(env, &dc); - if (dc.icount) { - tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount); + disas_xtensa_insn(env, dc); + if (dc->icount) { + tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount); } - if (cs->singlestep_enabled) { - tcg_gen_movi_i32(cpu_pc, dc.pc); - gen_exception(&dc, EXCP_DEBUG); + if (dc->base.singlestep_enabled) { + tcg_gen_movi_i32(cpu_pc, dc->pc); + gen_exception(dc, EXCP_DEBUG); break; } - } while (dc.base.is_jmp == DISAS_NEXT && - insn_count < max_insns && - dc.pc - page_start < TARGET_PAGE_SIZE && - dc.pc - page_start + xtensa_insn_len(env, &dc) <= TARGET_PAGE_SIZE - && !tcg_op_buf_full()); + } while (dc->base.is_jmp == DISAS_NEXT && + insn_count < max_insns && + dc->pc - page_start < TARGET_PAGE_SIZE && + dc->pc - page_start + xtensa_insn_len(env, dc) <= TARGET_PAGE_SIZE + && !tcg_op_buf_full()); done: - reset_sar_tracker(&dc); - if (dc.icount) { - tcg_temp_free(dc.next_icount); + reset_sar_tracker(dc); + if (dc->icount) { + tcg_temp_free(dc->next_icount); } - if (dc.config->isa) { - xtensa_insnbuf_free(dc.config->isa, dc.insnbuf); - xtensa_insnbuf_free(dc.config->isa, dc.slotbuf); + if (dc->config->isa) { + xtensa_insnbuf_free(dc->config->isa, dc->insnbuf); + xtensa_insnbuf_free(dc->config->isa, dc->slotbuf); } if (tb_cflags(tb) & CF_LAST_IO) { gen_io_end(); } - if (dc.base.is_jmp == DISAS_NEXT) { - gen_jumpi(&dc, dc.pc, 0); + if (dc->base.is_jmp == DISAS_NEXT) { + gen_jumpi(dc, dc->pc, 0); } gen_tb_end(tb, insn_count); @@ -1183,12 +1183,12 @@ done: qemu_log_lock(); qemu_log("----------------\n"); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc.pc - pc_start); + log_target_disas(cs, pc_start, dc->pc - pc_start); qemu_log("\n"); qemu_log_unlock(); } #endif - tb->size = dc.pc - pc_start; + tb->size = dc->pc - pc_start; tb->icount = insn_count; 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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id t1-v6sm8695688pgu.41.2018.05.12.10.57.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 12 May 2018 10:57:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 12 May 2018 10:57:24 -0700 Message-Id: <20180512175724.5923-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180512175724.5923-1-richard.henderson@linaro.org> References: <20180512175724.5923-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH 4/4] target/xtensa: Convert to TranslatorOps X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jcmvbkbc@gmail.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/xtensa/translate.c | 229 ++++++++++++++++++++------------------ 1 file changed, 122 insertions(+), 107 deletions(-) -- 2.17.0 diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 45f32dc71f..9de45e4be4 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1048,148 +1048,163 @@ static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc) } } -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +static void xtensa_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cpu) { - CPUXtensaState *env = cs->env_ptr; - DisasContext dc1, *dc = &dc1; - int insn_count = 0; - int max_insns = tb_cflags(tb) & CF_COUNT_MASK; - uint32_t pc_start = tb->pc; - uint32_t page_start = pc_start & TARGET_PAGE_MASK; - - if (max_insns == 0) { - max_insns = CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns = TCG_MAX_INSNS; - } + DisasContext *dc = container_of(dcbase, DisasContext, base); + CPUXtensaState *env = cpu->env_ptr; + uint32_t tb_flags = dc->base.tb->flags; dc->config = env->config; - dc->base.singlestep_enabled = cs->singlestep_enabled; - dc->base.tb = tb; - dc->pc = pc_start; - dc->ring = tb->flags & XTENSA_TBFLAG_RING_MASK; - dc->cring = (tb->flags & XTENSA_TBFLAG_EXCM) ? 0 : dc->ring; + dc->pc = dc->base.pc_first; + dc->ring = tb_flags & XTENSA_TBFLAG_RING_MASK; + dc->cring = (tb_flags & XTENSA_TBFLAG_EXCM) ? 0 : dc->ring; dc->lbeg = env->sregs[LBEG]; dc->lend = env->sregs[LEND]; - dc->base.is_jmp = DISAS_NEXT; - dc->debug = tb->flags & XTENSA_TBFLAG_DEBUG; - dc->icount = tb->flags & XTENSA_TBFLAG_ICOUNT; - dc->cpenable = (tb->flags & XTENSA_TBFLAG_CPENABLE_MASK) >> + dc->debug = tb_flags & XTENSA_TBFLAG_DEBUG; + dc->icount = tb_flags & XTENSA_TBFLAG_ICOUNT; + dc->cpenable = (tb_flags & XTENSA_TBFLAG_CPENABLE_MASK) >> XTENSA_TBFLAG_CPENABLE_SHIFT; - dc->window = ((tb->flags & XTENSA_TBFLAG_WINDOW_MASK) >> + dc->window = ((tb_flags & XTENSA_TBFLAG_WINDOW_MASK) >> XTENSA_TBFLAG_WINDOW_SHIFT); if (dc->config->isa) { dc->insnbuf = xtensa_insnbuf_alloc(dc->config->isa); dc->slotbuf = xtensa_insnbuf_alloc(dc->config->isa); } - init_sar_tracker(dc); +} + +static void xtensa_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + if (dc->icount) { dc->next_icount = tcg_temp_local_new_i32(); } +} - gen_tb_start(tb); +static void xtensa_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + tcg_gen_insn_start(dcbase->pc_next); +} - if ((tb_cflags(tb) & CF_USE_ICOUNT) && - (tb->flags & XTENSA_TBFLAG_YIELD)) { - tcg_gen_insn_start(dc->pc); - ++insn_count; +static bool xtensa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, + const CPUBreakpoint *bp) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); + gen_exception(dc, EXCP_DEBUG); + dc->base.is_jmp = DISAS_NORETURN; + /* The address covered by the breakpoint must be included in + [tb->pc, tb->pc + tb->size) in order to for it to be + properly cleared -- thus we increment the PC here so that + the logic setting tb->size below does the right thing. */ + dc->base.pc_next += 2; + return true; +} + +static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + CPUXtensaState *env = cpu->env_ptr; + target_ulong page_start; + + /* These two conditions only apply to the first insn in the TB, + but this is the first TranslateOps hook that allows exiting. */ + if ((tb_cflags(dc->base.tb) & CF_USE_ICOUNT) + && (dc->base.tb->flags & XTENSA_TBFLAG_YIELD)) { gen_exception(dc, EXCP_YIELD); dc->base.is_jmp = DISAS_NORETURN; - goto done; + return; } - if (tb->flags & XTENSA_TBFLAG_EXCEPTION) { - tcg_gen_insn_start(dc->pc); - ++insn_count; + if (dc->base.tb->flags & XTENSA_TBFLAG_EXCEPTION) { gen_exception(dc, EXCP_DEBUG); dc->base.is_jmp = DISAS_NORETURN; - goto done; + return; } - do { - tcg_gen_insn_start(dc->pc); - ++insn_count; - - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { - tcg_gen_movi_i32(cpu_pc, dc->pc); - gen_exception(dc, EXCP_DEBUG); - dc->base.is_jmp = DISAS_NORETURN; - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - dc->pc += 2; - break; - } - - if (insn_count == max_insns && (tb_cflags(tb) & CF_LAST_IO)) { - gen_io_start(); - } - - if (dc->icount) { - TCGLabel *label = gen_new_label(); - - tcg_gen_addi_i32(dc->next_icount, cpu_SR[ICOUNT], 1); - tcg_gen_brcondi_i32(TCG_COND_NE, dc->next_icount, 0, label); - tcg_gen_mov_i32(dc->next_icount, cpu_SR[ICOUNT]); - if (dc->debug) { - gen_debug_exception(dc, DEBUGCAUSE_IC); - } - gen_set_label(label); - } - - if (dc->debug) { - gen_ibreak_check(env, dc); - } - - disas_xtensa_insn(env, dc); - if (dc->icount) { - tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount); - } - if (dc->base.singlestep_enabled) { - tcg_gen_movi_i32(cpu_pc, dc->pc); - gen_exception(dc, EXCP_DEBUG); - break; - } - } while (dc->base.is_jmp == DISAS_NEXT && - insn_count < max_insns && - dc->pc - page_start < TARGET_PAGE_SIZE && - dc->pc - page_start + xtensa_insn_len(env, dc) <= TARGET_PAGE_SIZE - && !tcg_op_buf_full()); -done: - reset_sar_tracker(dc); if (dc->icount) { - tcg_temp_free(dc->next_icount); + TCGLabel *label = gen_new_label(); + + tcg_gen_addi_i32(dc->next_icount, cpu_SR[ICOUNT], 1); + tcg_gen_brcondi_i32(TCG_COND_NE, dc->next_icount, 0, label); + tcg_gen_mov_i32(dc->next_icount, cpu_SR[ICOUNT]); + if (dc->debug) { + gen_debug_exception(dc, DEBUGCAUSE_IC); + } + gen_set_label(label); } + + if (dc->debug) { + gen_ibreak_check(env, dc); + } + + disas_xtensa_insn(env, dc); + + if (dc->icount) { + tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount); + } + + /* End the TB if the next insn will cross into the next page. */ + page_start = dc->base.pc_first & TARGET_PAGE_MASK; + if (dc->base.is_jmp == DISAS_NEXT && + dc->pc - page_start < TARGET_PAGE_SIZE && + dc->pc - page_start + xtensa_insn_len(env, dc) <= TARGET_PAGE_SIZE) { + dc->base.is_jmp = DISAS_TOO_MANY; + } +} + +static void xtensa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + reset_sar_tracker(dc); if (dc->config->isa) { xtensa_insnbuf_free(dc->config->isa, dc->insnbuf); xtensa_insnbuf_free(dc->config->isa, dc->slotbuf); } - - if (tb_cflags(tb) & CF_LAST_IO) { - gen_io_end(); + if (dc->icount) { + tcg_temp_free(dc->next_icount); } - if (dc->base.is_jmp == DISAS_NEXT) { - gen_jumpi(dc, dc->pc, 0); + switch (dc->base.is_jmp) { + case DISAS_NORETURN: + break; + case DISAS_TOO_MANY: + if (dc->base.singlestep_enabled) { + tcg_gen_movi_i32(cpu_pc, dc->pc); + gen_exception(dc, EXCP_DEBUG); + } else { + gen_jumpi(dc, dc->pc, 0); + } + break; + default: + g_assert_not_reached(); } - gen_tb_end(tb, insn_count); +} -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(pc_start)) { - qemu_log_lock(); - qemu_log("----------------\n"); - qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(cs, pc_start, dc->pc - pc_start); - qemu_log("\n"); - qemu_log_unlock(); - } -#endif - tb->size = dc->pc - pc_start; - tb->icount = insn_count; +static void xtensa_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) +{ + qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); + log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); +} + +static const TranslatorOps xtensa_translator_ops = { + .init_disas_context = xtensa_tr_init_disas_context, + .tb_start = xtensa_tr_tb_start, + .insn_start = xtensa_tr_insn_start, + .breakpoint_check = xtensa_tr_breakpoint_check, + .translate_insn = xtensa_tr_translate_insn, + .tb_stop = xtensa_tr_tb_stop, + .disas_log = xtensa_tr_disas_log, +}; + +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) +{ + DisasContext dc = {}; + translator_loop(&xtensa_translator_ops, &dc.base, cpu, tb); } void xtensa_cpu_dump_state(CPUState *cs, FILE *f,