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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id h62-v6si9257749pfg.308.2018.05.13.21.34.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 13 May 2018 21:34:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=gkcRCQms; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id C1EFA207E53EC; Sun, 13 May 2018 21:34:47 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::244; helo=mail-pf0-x244.google.com; envelope-from=haojian.zhuang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf0-x244.google.com (mail-pf0-x244.google.com [IPv6:2607:f8b0:400e:c00::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id EEFB0207E4E0E for ; Sun, 13 May 2018 21:34:46 -0700 (PDT) Received: by mail-pf0-x244.google.com with SMTP id c10-v6so5375857pfi.12 for ; Sun, 13 May 2018 21:34:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5e+Csw/uplXo5HqQlitiGbhzAIyVsDYoSOr3hiIh2yE=; b=gkcRCQmsxM74/awThlzLX39LMwTgxiwoXrU7tJDpzTcwpsyjEN3wC6GmtJu0kALoVa lRBhlltl3Bf6Xp/aX+WtCadvURnzG3QXVxqGM/hOdHdAgaf6rAw5zqd8cTKCZ3V5CPl2 97s/bZYFa6Tx1QuxTOmAgHfHyNGi/pa6TFTQw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5e+Csw/uplXo5HqQlitiGbhzAIyVsDYoSOr3hiIh2yE=; b=Zw3icnpYkF14HxWFGVzkYFiIiSDBs6yjjERCLVuBFhoE477mf1Igap/zbK/8Gfd28g EJsI4ckJ80zpBpLySQE+L2Ahn2H/rINdhtWc4Abz/k9ItieWvWq1oCxFjNiKQVNI1RNS 48Lzqq57z6AiJAn3ytXG/tEK+Di04RILZT3eSl6amkYzS2Q95H+1VQchFE3+Ee20Bqnn OwlYNhdtNIamX4mgA2PmCRoAL4uHPSTQyMQsfyKAPc5bfNPtRy0p3wgyw8dZ/2GdHjag M7loYVKic6z+RO/MjVWihy698aE8BrRWcrWq6D4xiVd+5aEjpyvk6s8iCBtdRr6yLz8S 45sA== X-Gm-Message-State: ALKqPwdq7HJ6q3IvKQotsU+6kul6lD7Kosra+pCGZPaXypU2CRcQipOw 0S9aLS2XQFlah6L9351DM6FqwfH0HUQ= X-Received: by 2002:a62:e903:: with SMTP id j3-v6mr8855540pfh.196.1526272486156; Sun, 13 May 2018 21:34:46 -0700 (PDT) Received: from localhost.localdomain ([64.64.108.93]) by smtp.gmail.com with ESMTPSA id c11-v6sm15125613pfh.15.2018.05.13.21.34.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 13 May 2018 21:34:45 -0700 (PDT) From: Haojian Zhuang To: edk2-devel@lists.01.org Date: Mon, 14 May 2018 12:34:28 +0800 Message-Id: <1526272473-25565-2-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1526272473-25565-1-git-send-email-haojian.zhuang@linaro.org> References: <1526272473-25565-1-git-send-email-haojian.zhuang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v4 1/6] Platform/Hisilicon/HiKey960: add gpio platform driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Haojian Zhuang , Leif Lindholm , Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Add gpio platform driver to enable GPIO in HiKey960 platform. Cc: Leif Lindholm Cc: Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Haojian Zhuang --- Platform/Hisilicon/HiKey960/HiKey960.dsc | 1 + Platform/Hisilicon/HiKey960/HiKey960.fdf | 1 + .../HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.c | 83 ++++++++++++++++++++++ .../HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf | 35 +++++++++ 4 files changed, 120 insertions(+) create mode 100644 Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.c create mode 100644 Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Platform/Hisilicon/HiKey960/HiKey960.dsc b/Platform/Hisilicon/HiKey960/HiKey960.dsc index 36f43956ab40..3da1b8556321 100644 --- a/Platform/Hisilicon/HiKey960/HiKey960.dsc +++ b/Platform/Hisilicon/HiKey960/HiKey960.dsc @@ -179,6 +179,7 @@ [Components.common] # # GPIO # + Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf # diff --git a/Platform/Hisilicon/HiKey960/HiKey960.fdf b/Platform/Hisilicon/HiKey960/HiKey960.fdf index 655032a36c53..162dbaaf2646 100644 --- a/Platform/Hisilicon/HiKey960/HiKey960.fdf +++ b/Platform/Hisilicon/HiKey960/HiKey960.fdf @@ -120,6 +120,7 @@ [FV.FvMain] # # GPIO # + INF Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf # diff --git a/Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.c b/Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.c new file mode 100644 index 000000000000..b196455072cc --- /dev/null +++ b/Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.c @@ -0,0 +1,83 @@ +/** @file +* +* Copyright (c) 2018, Linaro. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include + +#include + +GPIO_CONTROLLER gGpioDevice[] = { + // + // { base address, gpio index, gpio count } + // + { 0xe8a0b000, 0, 8 }, // GPIO0 + { 0xe8a0c000, 8, 8 }, // GPIO1 + { 0xe8a0d000, 16, 8 }, // GPIO2 + { 0xe8a0e000, 24, 8 }, // GPIO3 + { 0xe8a0f000, 32, 8 }, // GPIO4 + { 0xe8a10000, 40, 8 }, // GPIO5 + { 0xe8a11000, 48, 8 }, // GPIO6 + { 0xe8a12000, 56, 8 }, // GPIO7 + { 0xe8a13000, 64, 8 }, // GPIO8 + { 0xe8a14000, 72, 8 }, // GPIO9 + { 0xe8a15000, 80, 8 }, // GPIO10 + { 0xe8a16000, 88, 8 }, // GPIO11 + { 0xe8a17000, 96, 8 }, // GPIO12 + { 0xe8a18000, 104, 8 }, // GPIO13 + { 0xe8a19000, 112, 8 }, // GPIO14 + { 0xe8a1a000, 120, 8 }, // GPIO15 + { 0xe8a1b000, 128, 8 }, // GPIO16 + { 0xe8a1c000, 136, 8 }, // GPIO17 + { 0xff3b4000, 144, 8 }, // GPIO18 + { 0xff3b5000, 152, 8 }, // GPIO19 + { 0xe8a1f000, 160, 8 }, // GPIO20 + { 0xe8a20000, 168, 8 }, // GPIO21 + { 0xfff0b000, 176, 8 }, // GPIO22 + { 0xfff0c000, 184, 8 }, // GPIO23 + { 0xfff0d000, 192, 8 }, // GPIO24 + { 0xfff0e000, 200, 8 }, // GPIO25 + { 0xfff0f000, 208, 8 }, // GPIO26 + { 0xfff10000, 216, 8 }, // GPIO27 + { 0xfff1d000, 224, 8 }, // GPIO28 +}; + +PLATFORM_GPIO_CONTROLLER gPlatformGpioDevice = { + // + // { global gpio count, gpio controller count, GPIO_CONTROLLER } + // + 232, 29, gGpioDevice +}; + +EFI_STATUS +EFIAPI +HiKey960GpioEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + + // Install the Embedded Platform GPIO Protocol onto a new handle + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces( + &Handle, + &gPlatformGpioProtocolGuid, &gPlatformGpioDevice, + NULL + ); + if (EFI_ERROR(Status)) { + Status = EFI_OUT_OF_RESOURCES; + } + + return Status; +} diff --git a/Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf b/Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf new file mode 100644 index 000000000000..5ea3747321d8 --- /dev/null +++ b/Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf @@ -0,0 +1,35 @@ +# +# Copyright (c) 2018, Linaro. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[Defines] + INF_VERSION = 0x0001001a + BASE_NAME = HiKey960GpioDxe + FILE_GUID = 6aa12592-7e36-4aec-acf8-2ac2fd13815c + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = HiKey960GpioEntryPoint + +[Sources] + HiKey960GpioDxe.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + +[Protocols] + gPlatformGpioProtocolGuid + +[Depex] + TRUE From patchwork Mon May 14 04:34:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 135661 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1253390lji; Sun, 13 May 2018 21:34:52 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrkkgsnQeNoNiTfu0vg0wZStUADEyteElAqIyUP/Q/O80BSxfEvW5wnUzPTQSPOjVdwQEIp X-Received: by 2002:a62:b509:: with SMTP id y9-v6mr8740908pfe.121.1526272492440; Sun, 13 May 2018 21:34:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526272492; cv=none; d=google.com; s=arc-20160816; b=w2o2Af5tSLbe4Qno8md4FaVHE9dtdM+xwyvS8pReIGKNyA7m5uYwzUS34DjUBjSfpp QqszzRaXSTOYQnh/VC6GpDXZ42AoR5hCu10iipaLgOOeaPn+xLOFKqKv2t0SDiyq5kGu B3psJ6kOEOPCInNhjLYPleDV7X2kXgySqJXShqvcTIBwTfPzcia5jmWnsEDl/6K6aINt V1gBSb35L8ASvOqusnX1Tb85U1195tpoNmd/u2RnttQScFk38MjmFNaIwquoGB4gVgsr nPfyPG/vuz4Hz/YPzgW1Wqiqd+pluGrHYjsqSZbOe+l/DThGGG6a/godmFXAx2pxR56q ra2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=ft6Ffg6NFgk94V9NKJPe6IZJofTEdxEAs56v1PJDKR8=; b=lyIMMCagr+BNVFdwr38GxpuSCBC3cirlaQYSxMfSoXugaZ3iiqkbjppzwd+lXzoMnJ Sa33n/kmiCeMjOQ/phaCErq+KuSyKIn8CTqc/Ew2tZZjezi+ggxVxZsiYJfoBaqUf+J/ qTaw9m/3QVTyD8i5fE/UNZ/9BasYEHMF9t6SUYZFbnM3f5Eh0gkc8rbgS1O2r8fDWYH2 r4IAgD8IJZIIA/as/fPBxfItmVSnSVF5FtF45XmgzQix24ZI6e8LhIeazyAbLVfWST/K OrXGGf6AQVGwa6kWWRzq8eaBTaJjZ+3837s5GiPgtX4qTGY3VM4mWsOhs/8ZGTyBQ8zl Szrg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Y0zZnBuv; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id l33-v6si8314241pld.440.2018.05.13.21.34.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 13 May 2018 21:34:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Y0zZnBuv; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id EE565207E53EB; Sun, 13 May 2018 21:34:51 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::242; helo=mail-pf0-x242.google.com; envelope-from=haojian.zhuang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf0-x242.google.com (mail-pf0-x242.google.com [IPv6:2607:f8b0:400e:c00::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3F482207E4E0E for ; Sun, 13 May 2018 21:34:51 -0700 (PDT) Received: by mail-pf0-x242.google.com with SMTP id x9-v6so5385267pfm.2 for ; Sun, 13 May 2018 21:34:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QW8ilxZlJjLsHEOkv5xMYcx02pvrQWVshgonUqqXdio=; b=Y0zZnBuviym7zggum/zA0IMmv+ATYAhJy+yOUWg/NsnmYqqoe1k7HBAr7K5Pgcmtkr 87lK9pTZw9Zi95AwVJwas4o+oQUBCkfnIOYGLeb4ra7GGdk2DiTJqtobDtv21pHOeJkN gYkJs3irg+wGq0BDQDJJ+E9vHgZDFWtTktNSM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QW8ilxZlJjLsHEOkv5xMYcx02pvrQWVshgonUqqXdio=; b=sRC0V8gnzkscysAH8iVXy5MWppupSzcOl7+Fa9dtdkYl7E++3bMfxZ3823XHNDMb3B rnHSpDtMsodsv43w6j3FuZEMuEagNFBdAuP3ahzZywQfYfltkALth1xGWY47yYM6FSAH 90CuavbOSAukReqrfSwj2aUICHilhhL5u7IH4+aoiuDmaVvV5xTxYeHY35wQoC3C2L/W 8Jm6Jy86C57GtR6ObLmZB4ewi9Wzx3njq95gH5i6cVreMN+jlvuZQIxa1cDU/1B4kGVn a6vS5wYZY1LTxVB+It4RmQAZShQ4X6U0g05EejcGje/6HFdkW85PE1bbA+lafeAs6D4J 4W/w== X-Gm-Message-State: ALKqPwdzi5U6oR9NF6MicMhhu0XksrCF+40/ojBK0nElDMg3JN0bHg/s gJQnVMJQw5Y67+WPCnQAO2hY0uJa9r4= X-Received: by 2002:a63:2407:: with SMTP id k7-v6mr7227493pgk.63.1526272489893; Sun, 13 May 2018 21:34:49 -0700 (PDT) Received: from localhost.localdomain ([64.64.108.93]) by smtp.gmail.com with ESMTPSA id c11-v6sm15125613pfh.15.2018.05.13.21.34.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 13 May 2018 21:34:48 -0700 (PDT) From: Haojian Zhuang To: edk2-devel@lists.01.org Date: Mon, 14 May 2018 12:34:29 +0800 Message-Id: <1526272473-25565-3-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1526272473-25565-1-git-send-email-haojian.zhuang@linaro.org> References: <1526272473-25565-1-git-send-email-haojian.zhuang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v4 2/6] Platform/HiKey960: do basic initialization X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Haojian Zhuang , Leif Lindholm , Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Do some basic initliazation on peripherals, such as pins and regulators. Cc: Leif Lindholm Cc: Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Haojian Zhuang --- Platform/Hisilicon/HiKey960/HiKey960.dsc | 2 + Platform/Hisilicon/HiKey960/HiKey960.fdf | 2 + .../Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c | 186 ++++++++++++++++++++ .../Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.h | 91 ++++++++++ .../Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf | 47 +++++ Silicon/Hisilicon/Hi3660/Hi3660.dec | 32 ++++ Silicon/Hisilicon/Hi3660/Include/Hi3660.h | 194 +++++++++++++++++++++ Silicon/Hisilicon/Hi3660/Include/Hkadc.h | 68 ++++++++ 8 files changed, 622 insertions(+) create mode 100644 Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c create mode 100644 Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.h create mode 100644 Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf create mode 100644 Silicon/Hisilicon/Hi3660/Hi3660.dec create mode 100644 Silicon/Hisilicon/Hi3660/Include/Hi3660.h create mode 100644 Silicon/Hisilicon/Hi3660/Include/Hkadc.h -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/HiKey960/HiKey960.dsc b/Platform/Hisilicon/HiKey960/HiKey960.dsc index 3da1b8556321..6cc1c1edf453 100644 --- a/Platform/Hisilicon/HiKey960/HiKey960.dsc +++ b/Platform/Hisilicon/HiKey960/HiKey960.dsc @@ -182,6 +182,8 @@ [Components.common] Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf + Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf + # # USB Host Support # diff --git a/Platform/Hisilicon/HiKey960/HiKey960.fdf b/Platform/Hisilicon/HiKey960/HiKey960.fdf index 162dbaaf2646..b7d70b010598 100644 --- a/Platform/Hisilicon/HiKey960/HiKey960.fdf +++ b/Platform/Hisilicon/HiKey960/HiKey960.fdf @@ -123,6 +123,8 @@ [FV.FvMain] INF Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf + INF Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf + # # USB Host Support # diff --git a/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c new file mode 100644 index 000000000000..fae68feca89d --- /dev/null +++ b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c @@ -0,0 +1,186 @@ +/** @file +* +* Copyright (c) 2018, Linaro Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include "HiKey960Dxe.h" + +STATIC +VOID +InitSdCard ( + IN VOID + ) +{ + UINT32 Data; + + // + // LDO16 + // 000: 1.75V, 001: 1.8V, 010: 2.4V, 011: 2.6V, 100: 2.7V, + // 101: 2.85V, 110: 2.95V, 111: 3.0V. + // + Data = MmioRead32 (PMIC_LDO16_VSET_REG) & LDO16_VSET_MASK; + Data |= 6; + MmioWrite32 (PMIC_LDO16_VSET_REG, Data); + MmioOr32 (PMIC_LDO16_ONOFF_ECO_REG, LDO16_ONOFF_ECO_LDO16_ENABLE); + // + // wait regulator stable + // + MicroSecondDelay (100); + + // + // LDO9 + // 000: 1.75V, 001: 1.8V, 010: 1.825V, 011: 2.8V, 100: 2.85V, + // 101: 2.95V, 110: 3.0V, 111: 3.3V. + // + Data = MmioRead32 (PMIC_LDO9_VSET_REG) & LDO9_VSET_MASK; + Data |= 5; + MmioWrite32 (PMIC_LDO9_VSET_REG, Data); + MmioOr32 (PMU_REG_BASE + (0x6a << 2), 2); + // + // wait regulator stable + // + MicroSecondDelay (100); + + // + // GPIO203 + // + MmioWrite32 (IOMG_AO_REG_BASE + (24 << 2), 0); // GPIO function + + // + // SD pinmux + // + MmioWrite32 (IOMG_MMC0_000_REG, IOMG_FUNC1); // SD_CLK + MmioWrite32 (IOMG_MMC0_001_REG, IOMG_FUNC1); // SD_CMD + MmioWrite32 (IOMG_MMC0_002_REG, IOMG_FUNC1); // SD_DATA0 + MmioWrite32 (IOMG_MMC0_003_REG, IOMG_FUNC1); // SD_DATA1 + MmioWrite32 (IOMG_MMC0_004_REG, IOMG_FUNC1); // SD_DATA2 + MmioWrite32 (IOMG_MMC0_005_REG, IOMG_FUNC1); // SD_DATA3 + MmioWrite32 (IOCG_MMC0_000_REG, IOCG_DRIVE (15)); // SD_CLK float with 32mA + MmioWrite32 (IOCG_MMC0_001_REG, IOCG_PULLUP | IOCG_DRIVE (8)); // SD_CMD + MmioWrite32 (IOCG_MMC0_002_REG, IOCG_PULLUP | IOCG_DRIVE (8)); // SD_DATA0 + MmioWrite32 (IOCG_MMC0_003_REG, IOCG_PULLUP | IOCG_DRIVE (8)); // SD_DATA1 + MmioWrite32 (IOCG_MMC0_004_REG, IOCG_PULLUP | IOCG_DRIVE (8)); // SD_DATA2 + MmioWrite32 (IOCG_MMC0_005_REG, IOCG_PULLUP | IOCG_DRIVE (8)); // SD_DATA3 + + // + // SC_SEL_SD: + // 0xx: 3.2MHz, 100: PPLL0, 101: PPLL1, 11x: PPLL2. + // SC_DIV_SD: + // divider = value + 1 + // + do { + MmioOr32 ( + CRG_CLKDIV4, CLKDIV4_SC_SEL_SD (4) | CLKDIV4_SC_SEL_SD_MASK | + CLKDIV4_SC_DIV_SD (0) | CLKDIV4_SC_DIV_SD_MASK + ); + Data = MmioRead32 (CRG_CLKDIV4) & + (CLKDIV4_SC_SEL_SD_MASK | CLKDIV4_SC_DIV_SD_MASK); + } while (Data != (CLKDIV4_SC_SEL_SD (4) | CLKDIV4_SC_DIV_SD (0))); + + // + // Unreset SD controller + // + MmioWrite32 (CRG_PERRSTDIS4, PERRSTEN4_SD); + do { + Data = MmioRead32 (CRG_PERRSTSTAT4); + } while ((Data & PERRSTEN4_SD) == PERRSTEN4_SD); + // + // Enable SD controller clock + // + MmioOr32 (CRG_PEREN0, PEREN0_GT_HCLK_SD); + MmioOr32 (CRG_PEREN4, PEREN4_GT_CLK_SD); + do { + Data = MmioRead32 (CRG_PERCLKEN4); + } while ((Data & PEREN4_GT_CLK_SD) != PEREN4_GT_CLK_SD); +} + +VOID +InitPeripherals ( + IN VOID + ) +{ + // + // Enable FPLL0 + // + MmioOr32 (SCTRL_SCFPLLCTRL0, SCTRL_SCFPLLCTRL0_FPLL0_EN); + + InitSdCard (); + + // + // Enable wifi clock + // + MmioOr32 (PMIC_HARDWARE_CTRL0, PMIC_HARDWARE_CTRL0_WIFI_CLK); + MmioOr32 (PMIC_OSC32K_ONOFF_CTRL, PMIC_OSC32K_ONOFF_CTRL_EN_32K); +} + +/** + Notification function of the event defined as belonging to the + EFI_END_OF_DXE_EVENT_GROUP_GUID event group that was created in + the entry point of the driver. + + This function is called when an event belonging to the + EFI_END_OF_DXE_EVENT_GROUP_GUID event group is signalled. Such an + event is signalled once at the end of the dispatching of all + drivers (end of the so called DXE phase). + + @param[in] Event Event declared in the entry point of the driver whose + notification function is being invoked. + @param[in] Context NULL +**/ +STATIC +VOID +OnEndOfDxe ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + UINT32 BootMode; + + BootMode = MmioRead32 (SCTRL_BAK_DATA0) & BOOT_MODE_MASK; + if (BootMode == BOOT_MODE_RECOVERY) { + SerialPortWrite ((UINT8 *)"WARNING: CAN NOT BOOT KERNEL IN RECOVERY MODE!\r\n", 48); + SerialPortWrite ((UINT8 *)"Switch to normal boot mode, then reboot to boot kernel.\r\n", 57); + } +} + +EFI_STATUS +EFIAPI +HiKey960EntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_EVENT EndOfDxeEvent; + + InitPeripherals (); + + // + // Create an event belonging to the "gEfiEndOfDxeEventGroupGuid" group. + // The "OnEndOfDxe()" function is declared as the call back function. + // It will be called at the end of the DXE phase when an event of the + // same group is signalled to inform about the end of the DXE phase. + // Install the INSTALL_FDT_PROTOCOL protocol. + // + Status = gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + OnEndOfDxe, + NULL, + &gEfiEndOfDxeEventGroupGuid, + &EndOfDxeEvent + ); + if (EFI_ERROR (Status)) { + return Status; + } + return Status; +} diff --git a/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.h b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.h new file mode 100644 index 000000000000..2e89d10e2723 --- /dev/null +++ b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.h @@ -0,0 +1,91 @@ +/** @file +* +* Copyright (c) 2018, Linaro Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __HIKEY960DXE_H__ +#define __HIKEY960DXE_H__ + +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ADC_ADCIN0 0 +#define ADC_ADCIN1 1 +#define ADC_ADCIN2 2 + +#define HKADC_DATA_GRADE0 0 +#define HKADC_DATA_GRADE1 100 +#define HKADC_DATA_GRADE2 300 +#define HKADC_DATA_GRADE3 500 +#define HKADC_DATA_GRADE4 700 +#define HKADC_DATA_GRADE5 900 +#define HKADC_DATA_GRADE6 1100 +#define HKADC_DATA_GRADE7 1300 +#define HKADC_DATA_GRADE8 1500 +#define HKADC_DATA_GRADE9 1700 +#define HKADC_DATA_GRADE10 1800 + +#define BOARDID_VALUE0 0 +#define BOARDID_VALUE1 1 +#define BOARDID_VALUE2 2 +#define BOARDID_VALUE3 3 +#define BOARDID_VALUE4 4 +#define BOARDID_VALUE5 5 +#define BOARDID_VALUE6 6 +#define BOARDID_VALUE7 7 +#define BOARDID_VALUE8 8 +#define BOARDID_VALUE9 9 +#define BOARDID_UNKNOWN 0xF + +#define BOARDID3_BASE 5 + +#define HIKEY960_BOARDID_V1 5300 +#define HIKEY960_BOARDID_V2 5301 + +#define HIKEY960_COMPATIBLE_LEDS_V1 "gpio-leds_v1" +#define HIKEY960_COMPATIBLE_LEDS_V2 "gpio-leds_v2" +#define HIKEY960_COMPATIBLE_HUB_V1 "hisilicon,gpio_hubv1" +#define HIKEY960_COMPATIBLE_HUB_V2 "hisilicon,gpio_hubv2" + +#define ADB_REBOOT_ADDRESS 0x32100000 +#define ADB_REBOOT_BOOTLOADER 0x77665500 +#define ADB_REBOOT_NONE 0x77665501 + +#define DETECT_SW_FASTBOOT 68 // GPIO8_4 + +enum { + BOOT_MODE_RECOVERY = 0, + BOOT_MODE_NORMAL, + BOOT_MODE_MASK = 1, +}; + +typedef struct { + UINTN DataGrade; + UINTN BoardidValue; +} HKADC_DATA; + +#endif /* __HIKEY960DXE_H__ */ diff --git a/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf new file mode 100644 index 000000000000..a1a7d005ce8b --- /dev/null +++ b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf @@ -0,0 +1,47 @@ +# +# Copyright (c) 2018, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[Defines] + INF_VERSION = 0x0001001a + BASE_NAME = HiKey960Dxe + FILE_GUID = 6d824b2c-640e-4643-b9f2-9c09e8bff429 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = HiKey960EntryPoint + +[Sources.common] + HiKey960Dxe.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Hisilicon/Hi3660/Hi3660.dec + +[LibraryClasses] + BaseMemoryLib + CacheMaintenanceLib + DxeServicesTableLib + IoLib + PcdLib + TimerLib + UefiDriverEntryPoint + UefiLib + +[Protocols] + gEmbeddedGpioProtocolGuid + +[Guids] + gEfiEndOfDxeEventGroupGuid + +[Depex] + TRUE diff --git a/Silicon/Hisilicon/Hi3660/Hi3660.dec b/Silicon/Hisilicon/Hi3660/Hi3660.dec new file mode 100644 index 000000000000..5c69ac4f19b8 --- /dev/null +++ b/Silicon/Hisilicon/Hi3660/Hi3660.dec @@ -0,0 +1,32 @@ +# +# Copyright (c) 2018, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[Defines] + DEC_SPECIFICATION = 0x0001001a + PACKAGE_NAME = Hi3660 + PACKAGE_GUID = e457ba7c-faba-4dea-b274-f5962d016c79 + PACKAGE_VERSION = 0.1 + +################################################################################ +# +# Include Section - list of Include Paths that are provided by this package. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION +# +################################################################################ +[Includes.common] + Include # Root include for the package + +[Guids.common] + gHi3660TokenSpaceGuid = { 0x4abc73fa, 0x8a49, 0x4d2c, { 0x95, 0x44, 0x17, 0x87, 0x29, 0x06, 0x20, 0xb4 } } diff --git a/Silicon/Hisilicon/Hi3660/Include/Hi3660.h b/Silicon/Hisilicon/Hi3660/Include/Hi3660.h new file mode 100644 index 000000000000..ca07a4dd1b81 --- /dev/null +++ b/Silicon/Hisilicon/Hi3660/Include/Hi3660.h @@ -0,0 +1,194 @@ +/** @file +* +* Copyright (c) 2018, Linaro Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __HI3660_H__ +#define __HI3660_H__ + +#define HKADC_SSI_REG_BASE 0xE82B8000 + +#define PCTRL_REG_BASE 0xE8A09000 + +#define PCTRL_CTRL3 (PCTRL_REG_BASE + 0x010) +#define PCTRL_CTRL24 (PCTRL_REG_BASE + 0x064) + +#define PCTRL_CTRL3_USB_TXCO_EN (1 << 1) +#define PCTRL_CTRL24_USB3PHY_3MUX1_SEL (1 << 25) + +#define SCTRL_REG_BASE 0xFFF0A000 + +#define SCTRL_SCFPLLCTRL0 (SCTRL_REG_BASE + 0x120) +#define SCTRL_SCFPLLCTRL0_FPLL0_EN (1 << 0) + +#define SCTRL_BAK_DATA0 (SCTRL_REG_BASE + 0x40C) + +#define USB3OTG_BC_REG_BASE 0xFF200000 + +#define USB3OTG_CTRL0 (USB3OTG_BC_REG_BASE + 0x000) +#define USB3OTG_CTRL2 (USB3OTG_BC_REG_BASE + 0x008) +#define USB3OTG_CTRL3 (USB3OTG_BC_REG_BASE + 0x00C) +#define USB3OTG_CTRL4 (USB3OTG_BC_REG_BASE + 0x010) +#define USB3OTG_CTRL6 (USB3OTG_BC_REG_BASE + 0x018) +#define USB3OTG_CTRL7 (USB3OTG_BC_REG_BASE + 0x01C) +#define USB3OTG_PHY_CR_STS (USB3OTG_BC_REG_BASE + 0x050) +#define USB3OTG_PHY_CR_CTRL (USB3OTG_BC_REG_BASE + 0x054) + +#define USB3OTG_CTRL0_SC_USB3PHY_ABB_GT_EN (1 << 15) +#define USB3OTG_CTRL2_TEST_POWERDOWN_SSP (1 << 1) +#define USB3OTG_CTRL2_TEST_POWERDOWN_HSP (1 << 0) +#define USB3OTG_CTRL3_VBUSVLDEXT (1 << 6) +#define USB3OTG_CTRL3_VBUSVLDEXTSEL (1 << 5) +#define USB3OTG_CTRL7_REF_SSP_EN (1 << 16) +#define USB3OTG_PHY_CR_DATA_OUT(x) (((x) & 0xFFFF) << 1) +#define USB3OTG_PHY_CR_ACK (1 << 0) +#define USB3OTG_PHY_CR_DATA_IN(x) (((x) & 0xFFFF) << 4) +#define USB3OTG_PHY_CR_WRITE (1 << 3) +#define USB3OTG_PHY_CR_READ (1 << 2) +#define USB3OTG_PHY_CR_CAP_DATA (1 << 1) +#define USB3OTG_PHY_CR_CAP_ADDR (1 << 0) + +#define PMU_REG_BASE 0xFFF34000 +#define PMIC_LDO9_VSET_REG (PMU_REG_BASE + (0x068 << 2)) +#define LDO9_VSET_MASK (7 << 0) + +#define PMIC_LDO16_ONOFF_ECO_REG (PMU_REG_BASE + (0x078 << 2)) +#define LDO16_ONOFF_ECO_LDO16_ENABLE BIT1 +#define LDO16_ONOFF_ECO_ECO_ENABLE BIT0 + +#define PMIC_LDO16_VSET_REG (PMU_REG_BASE + (0x079 << 2)) +#define LDO16_VSET_MASK (7 << 0) + +#define PMIC_HARDWARE_CTRL0 (PMU_REG_BASE + (0x0C5 << 2)) +#define PMIC_OSC32K_ONOFF_CTRL (PMU_REG_BASE + (0x0CC << 2)) + +#define PMIC_HARDWARE_CTRL0_WIFI_CLK (1 << 5) +#define PMIC_OSC32K_ONOFF_CTRL_EN_32K (1 << 1) + + +#define CRG_REG_BASE 0xFFF35000 + +#define CRG_PEREN0 (CRG_REG_BASE + 0x000) +#define CRG_PEREN2 (CRG_REG_BASE + 0x020) +#define CRG_PERDIS2 (CRG_REG_BASE + 0x024) +#define CRG_PERCLKEN2 (CRG_REG_BASE + 0x028) +#define CRG_PERSTAT2 (CRG_REG_BASE + 0x02C) +#define CRG_PEREN4 (CRG_REG_BASE + 0x040) +#define CRG_PERDIS4 (CRG_REG_BASE + 0x044) +#define CRG_PERCLKEN4 (CRG_REG_BASE + 0x048) +#define CRG_PERSTAT4 (CRG_REG_BASE + 0x04C) +#define CRG_PERRSTEN2 (CRG_REG_BASE + 0x078) +#define CRG_PERRSTDIS2 (CRG_REG_BASE + 0x07C) +#define CRG_PERRSTSTAT2 (CRG_REG_BASE + 0x080) +#define CRG_PERRSTEN3 (CRG_REG_BASE + 0x084) +#define CRG_PERRSTDIS3 (CRG_REG_BASE + 0x088) +#define CRG_PERRSTSTAT3 (CRG_REG_BASE + 0x08C) +#define CRG_PERRSTEN4 (CRG_REG_BASE + 0x090) +#define CRG_PERRSTDIS4 (CRG_REG_BASE + 0x094) +#define CRG_PERRSTSTAT4 (CRG_REG_BASE + 0x098) +#define CRG_CLKDIV4 (CRG_REG_BASE + 0x0B8) +#define CRG_ISOEN (CRG_REG_BASE + 0x144) +#define CRG_ISODIS (CRG_REG_BASE + 0x148) +#define CRG_ISOSTAT (CRG_REG_BASE + 0x14C) + +#define PERI_UFS_BIT (1 << 12) +#define PERI_ARST_UFS_BIT (1 << 7) + +#define PEREN0_GT_HCLK_SD BIT30 + +#define PEREN2_HKADCSSI BIT24 + +#define PEREN4_GT_CLK_SD BIT17 +#define PEREN4_GT_ACLK_USB3OTG (1 << 1) +#define PEREN4_GT_CLK_USB3OTG_REF (1 << 0) + +#define PERRSTEN2_HKADCSSI BIT24 + +#define PERRSTEN4_SD BIT18 + +#define PERRSTEN4_USB3OTG_MUX (1 << 8) +#define PERRSTEN4_USB3OTG_AHBIF (1 << 7) +#define PERRSTEN4_USB3OTG_32K (1 << 6) +#define PERRSTEN4_USB3OTG (1 << 5) +#define PERRSTEN4_USB3OTGPHY_POR (1 << 3) + +#define PERISOEN_USB_REFCLK_ISO_EN (1 << 25) + +#define CLKDIV4_SC_SEL_SD_MASK ((7 << 4) << 16) +#define CLKDIV4_SC_DIV_SD_MASK (0xf << 16) +#define CLKDIV4_SC_SEL_SD(x) (((x) & 0x7) << 4) +#define CLKDIV4_SC_DIV_SD(x) ((x) & 0xf) + +#define CRG_CLKDIV16_OFFSET 0x0E8 +#define SC_DIV_UFSPHY_CFG_MASK (0x3 << 9) +#define SC_DIV_UFSPHY_CFG(x) (((x) & 0x3) << 9) + +#define CRG_CLKDIV17_OFFSET 0x0EC +#define SC_DIV_UFS_PERIBUS (1 << 14) + +#define IOMG_MMC0_REG_BASE 0xFF37E000 +#define IOMG_MMC0_000_REG (IOMG_MMC0_REG_BASE + 0x000) +#define IOMG_MMC0_001_REG (IOMG_MMC0_REG_BASE + 0x004) +#define IOMG_MMC0_002_REG (IOMG_MMC0_REG_BASE + 0x008) +#define IOMG_MMC0_003_REG (IOMG_MMC0_REG_BASE + 0x00C) +#define IOMG_MMC0_004_REG (IOMG_MMC0_REG_BASE + 0x010) +#define IOMG_MMC0_005_REG (IOMG_MMC0_REG_BASE + 0x014) + +#define IOCG_MMC0_REG_BASE 0xFF37E800 +#define IOCG_MMC0_000_REG (IOCG_MMC0_REG_BASE + 0x000) +#define IOCG_MMC0_001_REG (IOCG_MMC0_REG_BASE + 0x004) +#define IOCG_MMC0_002_REG (IOCG_MMC0_REG_BASE + 0x008) +#define IOCG_MMC0_003_REG (IOCG_MMC0_REG_BASE + 0x00C) +#define IOCG_MMC0_004_REG (IOCG_MMC0_REG_BASE + 0x010) +#define IOCG_MMC0_005_REG (IOCG_MMC0_REG_BASE + 0x014) + +#define IOMG_AO_REG_BASE 0xFFF11000 +#define IOMG_AO_006_REG (IOMG_AO_REG_BASE + 0x018) + +#define IOMG_FUNC0 0 +#define IOMG_FUNC1 1 +#define IOCG_PULLUP BIT0 +#define IOCG_PULLDOWN BIT1 +#define IOCG_DRIVE(x) ((x) << 4) + +#define UFS_SYS_REG_BASE 0xFF3B1000 + +#define UFS_SYS_PSW_POWER_CTRL_OFFSET 0x004 +#define UFS_SYS_PHY_ISO_EN_OFFSET 0x008 +#define UFS_SYS_HC_LP_CTRL_OFFSET 0x00C +#define UFS_SYS_PHY_CLK_CTRL_OFFSET 0x010 +#define UFS_SYS_PSW_CLK_CTRL_OFFSET 0x014 +#define UFS_SYS_CLOCK_GATE_BYPASS_OFFSET 0x018 +#define UFS_SYS_RESET_CTRL_EN_OFFSET 0x01C +#define UFS_SYS_MONITOR_HH_OFFSET 0x03C +#define UFS_SYS_UFS_SYSCTRL_OFFSET 0x05C +#define UFS_SYS_UFS_DEVICE_RESET_CTRL_OFFSET 0x060 +#define UFS_SYS_UFS_APB_ADDR_MASK_OFFSET 0x064 + +#define BIT_UFS_PSW_ISO_CTRL (1 << 16) +#define BIT_UFS_PSW_MTCMOS_EN (1 << 0) +#define BIT_UFS_REFCLK_ISO_EN (1 << 16) +#define BIT_UFS_PHY_ISO_CTRL (1 << 0) +#define BIT_SYSCTRL_LP_ISOL_EN (1 << 16) +#define BIT_SYSCTRL_PWR_READY (1 << 8) +#define BIT_SYSCTRL_REF_CLOCK_EN (1 << 24) +#define MASK_SYSCTRL_REF_CLOCK_SEL (3 << 8) +#define MASK_SYSCTRL_CFG_CLOCK_FREQ (0xFF) +#define BIT_SYSCTRL_PSW_CLK_EN (1 << 4) +#define MASK_UFS_CLK_GATE_BYPASS (0x3F) +#define BIT_SYSCTRL_LP_RESET_N (1 << 0) +#define BIT_UFS_REFCLK_SRC_SE1 (1 << 0) +#define MASK_UFS_SYSCTRL_BYPASS (0x3F << 16) +#define MASK_UFS_DEVICE_RESET (1 << 16) +#define BIT_UFS_DEVICE_RESET (1 << 0) + +#endif /* __HI3660_H__ */ diff --git a/Silicon/Hisilicon/Hi3660/Include/Hkadc.h b/Silicon/Hisilicon/Hi3660/Include/Hkadc.h new file mode 100644 index 000000000000..990c0928eaab --- /dev/null +++ b/Silicon/Hisilicon/Hi3660/Include/Hkadc.h @@ -0,0 +1,68 @@ +/** @file +* +* Copyright (c) 2018, Linaro Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __HKADC_H__ +#define __HKADC_H__ + +#include + +#define HKADC_DSP_START (HKADC_SSI_REG_BASE + 0x000) +#define DSP_START_BIT BIT0 + +#define HKADC_WR_NUM (HKADC_SSI_REG_BASE + 0x008) +#define HKADC_DSP_START_CLR (HKADC_SSI_REG_BASE + 0x01C) +#define HKADC_WR01_DATA (HKADC_SSI_REG_BASE + 0x020) + +#define WR1_WRITE_MODE BIT31 +#define WR1_READ_MODE (0 << 31) +#define WR1_ADDR(x) (((x) & 0x7F) << 24) +#define WR1_DATA(x) (((x) & 0xFF) << 16) +#define WR0_WRITE_MODE BIT15 +#define WR0_READ_MODE (0 << 15) +#define WR0_ADDR(x) (((x) & 0x7F) << 8) +#define WR0_DATA(x) ((x) & 0xFF) + +#define HKADC_WR23_DATA (HKADC_SSI_REG_BASE + 0x024) +#define HKADC_WR45_DATA (HKADC_SSI_REG_BASE + 0x028) +#define HKADC_DELAY01 (HKADC_SSI_REG_BASE + 0x030) +#define HKADC_DELAY23 (HKADC_SSI_REG_BASE + 0x034) +#define HKADC_DELAY45 (HKADC_SSI_REG_BASE + 0x038) +#define HKADC_DSP_RD2_DATA (HKADC_SSI_REG_BASE + 0x048) +#define HKADC_DSP_RD3_DATA (HKADC_SSI_REG_BASE + 0x04C) + +// HKADC Internal Registers +#define HKADC_CTRL_ADDR 0x00 +#define HKADC_START_ADDR 0x01 +#define HKADC_DATA1_ADDR 0x03 // high 8 bits +#define HKADC_DATA0_ADDR 0x04 // low 8 bits +#define HKADC_MODE_CFG 0x0A + +#define HKADC_VALUE_HIGH 0x0FF0 +#define HKADC_VALUE_LOW 0x000F +#define HKADC_VALID_VALUE 0x0FFF + +#define HKADC_CHANNEL_MAX 15 +#define HKADC_VREF_1V8 1800 +#define HKADC_ACCURACY 0x0FFF + +#define HKADC_WR01_VALUE ((HKADC_START_ADDR << 24) | (0x1 << 16)) +#define HKADC_WR23_VALUE ((0x1 << 31) | (HKADC_DATA0_ADDR << 24) | (1 << 15) | (HKADC_DATA1_ADDR << 8)) +#define HKADC_WR45_VALUE (0x80) +#define HKADC_CHANNEL0_DELAY01_VALUE ((0x0700 << 16) | 0xFFFF) +#define HKADC_DELAY01_VALUE ((0x0700 << 16) | 0x0200) +#define HKADC_DELAY23_VALUE ((0x00C8 << 16) | 0x00C8) +#define START_DELAY_TIMEOUT 2000 +#define HKADC_WR_NUM_VALUE 4 + +#endif /* __HKADC_H__ */ From patchwork Mon May 14 04:34:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 135662 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1253429lji; Sun, 13 May 2018 21:34:55 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqMrukGYlqxNhywcoCUr6SyPYeTGveFom2l8lyrHhCucOfsjZ8F6MBhVRghRk26nt7wFtYq X-Received: by 2002:a17:902:a718:: with SMTP id w24-v6mr8342155plq.45.1526272495524; Sun, 13 May 2018 21:34:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526272495; cv=none; d=google.com; s=arc-20160816; b=qS5IifpCZTP46psNeqQSvYzQmb02epFBQV7Ll5/P28KXDHH3LEjelPMQxdiF59K3bF Ft5Na5gmKhRLGqjEcbE8nIDljAswGgzB5kU382MriT6Yj+6jdQTGqtGPfMqCBWN656tg 3vgJjIrlELbqgC/LCRNKBUYubC5XXFVSZYm9S3PoJnO7IO8iFjiM6+LVbGHfxSsYIfOu 3szx1KFRilaTs7UFqveUzOhX03MLiuuYtGgdsgymwC055qh74FNUW8Uge/FiQlJ7kq0A iO/SqH7vpSGv6O9arjyvy7jJzUUvHp9F6OMN7i2/4U1hO7oWXixU0uAq3LpZEw1xwUaR IBJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=g/e5rbUr2As4bwGdsCynBGLSFOqeP5YI15aVzVesk4Y=; b=OdCf/QzcAZ/o7TQRWhLrdKsJxUu66cc2d1ELHoG/18wB+sCTbY4U01VS8eKxQcUQrn oLxvMyWpzhPG/knvTDZeCqy9C9bTBqfKYqmuJEw142lTwBSH1+Yio31pxyZfLFd6Fhc8 3dUyIzvoH8XWArmFUy8NLMz0c3QX0aCvShQq1Vg1E5N0LtQaQi/6hKfv0rJ/ajP0pikd oWK6b079RTQhmfgRQ+qjVRqcaJVGt7p4mKBZngavapoEtd/xUpVIVsaX8YrpWuvOFVta qTEer/d2sjTVfwUdAfjNI7TO0kG3AjVJxHYTB6lVEg22FfzfPdsdqmeV74y2mHEp/n8J K6pQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=SGxrWbkQ; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id b8-v6si1711271ple.469.2018.05.13.21.34.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 13 May 2018 21:34:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=SGxrWbkQ; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 25D63207E53F8; Sun, 13 May 2018 21:34:55 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::242; helo=mail-pl0-x242.google.com; envelope-from=haojian.zhuang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x242.google.com (mail-pl0-x242.google.com [IPv6:2607:f8b0:400e:c01::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 059F4207E4E0E for ; Sun, 13 May 2018 21:34:53 -0700 (PDT) Received: by mail-pl0-x242.google.com with SMTP id ay10-v6so6593633plb.1 for ; Sun, 13 May 2018 21:34:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=P+RIyl5pmXjxK6t6jTFSZ8I1qCTo9ZxnEB+XF6o+mNs=; b=SGxrWbkQqUevQBSTf/OLBCkJ/ELiJrifXsiqtxCOUGd14PsgWYk/D2lPXfKN6Pe2aq LURP1+znlTk5CqnfHq+EUre98MWVzUj4tknRy8c/WaaeWoJ/DK2xdt6teA6jfK9l5+gl rGPAZH/8JZBpdmgeZ3OUTt9ksxN0zKYCIOsGI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=P+RIyl5pmXjxK6t6jTFSZ8I1qCTo9ZxnEB+XF6o+mNs=; b=nAZKKAdZuP/+nV0Uw5lG7kI1Q4OqTxHSiS6G1Krc8oac1JbuHj+m719irA7+5IU+cv je81m8wRrbAWvoj0c8Wk78qizgj619C5f5k2Y+NudEjCbgCbcuyYc+x8eB/f/WWHouDo Q4r2dIytWmacW+ikyw6mVQmThLnnuPSvIbM47bjhsjCNC2Uak+MM3f4PoMUWa94NGce9 QME3JD5teySRTJtSYP+s3Nbug+MRW86LhKUVlpVukyGHe7ELvcVrKRC847P0QhBWKZj3 gBpGRsreBheA1UOESakRFaEKBzytuNEE83LhndbcI2JJGdJmL331F4L8mm+SZXWC+wPr nLKw== X-Gm-Message-State: ALKqPwet6RJJuP3MvH+OEPtE33xIMcBpNgiWZmVgsLSE6xQ5SNg1BWbl CsY2hBbM/+Si7/47+3CPy9uEiHYYBsM= X-Received: by 2002:a17:902:6e4:: with SMTP id 91-v6mr2803060plh.63.1526272493322; Sun, 13 May 2018 21:34:53 -0700 (PDT) Received: from localhost.localdomain ([64.64.108.93]) by smtp.gmail.com with ESMTPSA id c11-v6sm15125613pfh.15.2018.05.13.21.34.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 13 May 2018 21:34:52 -0700 (PDT) From: Haojian Zhuang To: edk2-devel@lists.01.org Date: Mon, 14 May 2018 12:34:30 +0800 Message-Id: <1526272473-25565-4-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1526272473-25565-1-git-send-email-haojian.zhuang@linaro.org> References: <1526272473-25565-1-git-send-email-haojian.zhuang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v4 3/6] Platform/HiKey960: enable virtual keyboard X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Haojian Zhuang , Leif Lindholm , Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Enable virtual keyboard on HiKey960 platform. It checks two conditions, such as pattern in memory and GPIO pin setting. Cc: Leif Lindholm Cc: Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Haojian Zhuang --- Platform/Hisilicon/HiKey960/HiKey960.dsc | 5 ++ Platform/Hisilicon/HiKey960/HiKey960.fdf | 5 ++ .../Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c | 97 ++++++++++++++++++++++ .../Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.h | 3 + .../Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf | 1 + 5 files changed, 111 insertions(+) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/HiKey960/HiKey960.dsc b/Platform/Hisilicon/HiKey960/HiKey960.dsc index 6cc1c1edf453..79e68754976d 100644 --- a/Platform/Hisilicon/HiKey960/HiKey960.dsc +++ b/Platform/Hisilicon/HiKey960/HiKey960.dsc @@ -182,6 +182,11 @@ [Components.common] Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf + # + # Virtual Keyboard + # + EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf + Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf # diff --git a/Platform/Hisilicon/HiKey960/HiKey960.fdf b/Platform/Hisilicon/HiKey960/HiKey960.fdf index b7d70b010598..d65f77878575 100644 --- a/Platform/Hisilicon/HiKey960/HiKey960.fdf +++ b/Platform/Hisilicon/HiKey960/HiKey960.fdf @@ -123,6 +123,11 @@ [FV.FvMain] INF Platform/Hisilicon/HiKey960/HiKey960GpioDxe/HiKey960GpioDxe.inf INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf + # + # Virtual Keyboard + # + INF EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf + INF Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf # diff --git a/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c index fae68feca89d..60d0e380e0b1 100644 --- a/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c +++ b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.c @@ -14,6 +14,8 @@ #include "HiKey960Dxe.h" +STATIC EMBEDDED_GPIO *mGpio; + STATIC VOID InitSdCard ( @@ -154,6 +156,94 @@ OnEndOfDxe ( EFI_STATUS EFIAPI +VirtualKeyboardRegister ( + IN VOID + ) +{ + EFI_STATUS Status; + + Status = gBS->LocateProtocol ( + &gEmbeddedGpioProtocolGuid, + NULL, + (VOID **) &mGpio + ); + if (EFI_ERROR (Status)) { + return Status; + } + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +VirtualKeyboardReset ( + IN VOID + ) +{ + EFI_STATUS Status; + + if (mGpio == NULL) { + return EFI_INVALID_PARAMETER; + } + // + // Configure GPIO68 as GPIO function + // + MmioWrite32 (0xe896c108, 0); + Status = mGpio->Set (mGpio, DETECT_SW_FASTBOOT, GPIO_MODE_INPUT); + return Status; +} + +BOOLEAN +EFIAPI +VirtualKeyboardQuery ( + IN VIRTUAL_KBD_KEY *VirtualKey + ) +{ + EFI_STATUS Status; + UINTN Value = 0; + + if ((VirtualKey == NULL) || (mGpio == NULL)) { + return FALSE; + } + if (MmioRead32 (ADB_REBOOT_ADDRESS) == ADB_REBOOT_BOOTLOADER) { + goto Done; + } else { + Status = mGpio->Get (mGpio, DETECT_SW_FASTBOOT, &Value); + if (EFI_ERROR (Status) || (Value != 0)) { + return FALSE; + } + } +Done: + VirtualKey->Signature = VIRTUAL_KEYBOARD_KEY_SIGNATURE; + VirtualKey->Key.ScanCode = SCAN_NULL; + VirtualKey->Key.UnicodeChar = L'f'; + return TRUE; +} + +EFI_STATUS +EFIAPI +VirtualKeyboardClear ( + IN VIRTUAL_KBD_KEY *VirtualKey + ) +{ + if (VirtualKey == NULL) { + return EFI_INVALID_PARAMETER; + } + if (MmioRead32 (ADB_REBOOT_ADDRESS) == ADB_REBOOT_BOOTLOADER) { + MmioWrite32 (ADB_REBOOT_ADDRESS, ADB_REBOOT_NONE); + WriteBackInvalidateDataCacheRange ((VOID *)ADB_REBOOT_ADDRESS, 4); + } + return EFI_SUCCESS; +} + +PLATFORM_VIRTUAL_KBD_PROTOCOL mVirtualKeyboard = { + VirtualKeyboardRegister, + VirtualKeyboardReset, + VirtualKeyboardQuery, + VirtualKeyboardClear +}; + +EFI_STATUS +EFIAPI HiKey960EntryPoint ( IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable @@ -182,5 +272,12 @@ HiKey960EntryPoint ( if (EFI_ERROR (Status)) { return Status; } + + Status = gBS->InstallProtocolInterface ( + &ImageHandle, + &gPlatformVirtualKeyboardProtocolGuid, + EFI_NATIVE_INTERFACE, + &mVirtualKeyboard + ); return Status; } diff --git a/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.h b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.h index 2e89d10e2723..2d5349888ed5 100644 --- a/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.h +++ b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.h @@ -33,6 +33,9 @@ #include #include +#include +#include + #define ADC_ADCIN0 0 #define ADC_ADCIN1 1 #define ADC_ADCIN2 2 diff --git a/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf index a1a7d005ce8b..46a9a5803e3d 100644 --- a/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf +++ b/Platform/Hisilicon/HiKey960/HiKey960Dxe/HiKey960Dxe.inf @@ -39,6 +39,7 @@ [LibraryClasses] [Protocols] gEmbeddedGpioProtocolGuid + gPlatformVirtualKeyboardProtocolGuid [Guids] gEfiEndOfDxeEventGroupGuid From patchwork Mon May 14 04:34:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 135663 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1253466lji; 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[198.145.21.10]) by mx.google.com with ESMTPS id u69-v6si7018190pgd.467.2018.05.13.21.34.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 13 May 2018 21:34:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=jgtCswx9; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 57DEF207E5401; Sun, 13 May 2018 21:34:58 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::242; helo=mail-pl0-x242.google.com; envelope-from=haojian.zhuang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x242.google.com (mail-pl0-x242.google.com [IPv6:2607:f8b0:400e:c01::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E88E3207E53FF for ; Sun, 13 May 2018 21:34:56 -0700 (PDT) Received: by mail-pl0-x242.google.com with SMTP id n10-v6so6597206plp.0 for ; Sun, 13 May 2018 21:34:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dbY0NfGtfkBljvjtMfvF23F9ZO7VhqTv0js7eRmakPk=; b=jgtCswx9/BumQVelYM9D2HyFtIvecc4rV/gzz0FOem7NFgmC4PY1pyTDUYBcpCCXw7 1rYGZ4RtugTCy5n/fUUe6JNxAzsenIvyMu9Y4MpFQmuRPzmSxacIlAJ5NthiHoj/R0T3 +ytKBkDdwTpgiZg5paDuSy05467wYGvEBP7As= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dbY0NfGtfkBljvjtMfvF23F9ZO7VhqTv0js7eRmakPk=; b=Epcusrq2TY4oPQEy4TWxk27A+GZEZRUmqWYJtbSjUxlNEOW4NV18z0hevrJVxRy1bq wka4y2I/645THbo6a7nLndBe6oqw3Lsanr61MIBX8kSrSu+u/YadkKhsODtTc5dYKiFD 0x76Gl8E4YaqREera2NkkcGSdGUfd++J63P1WAPx7mKOIbv9VXN3vtu+mA58pGRy3t+V ReiLWzz1bTTOdAGEFj4pEfcN4Qb6oOkxB0BDwxtThA0wBvaar1w7QV/XIDz58h38QZCG wlO6eSIWC0IFcAUGEESIoxSeCOyBY8ssNZD28kyGK05hTlZ52xastgA176iFY4GiVzy9 lN0Q== X-Gm-Message-State: ALKqPwdwYWTbIzM4064Az2nMjbgiDoYxMZumvCRhRrISEWLCYDvbUd8B ayYo0HiyaKxvRCUs20VRnx5HGnTuOWU= X-Received: by 2002:a17:902:848b:: with SMTP id c11-v6mr8179371plo.132.1526272496208; Sun, 13 May 2018 21:34:56 -0700 (PDT) Received: from localhost.localdomain ([64.64.108.93]) by smtp.gmail.com with ESMTPSA id c11-v6sm15125613pfh.15.2018.05.13.21.34.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 13 May 2018 21:34:55 -0700 (PDT) From: Haojian Zhuang To: edk2-devel@lists.01.org Date: Mon, 14 May 2018 12:34:31 +0800 Message-Id: <1526272473-25565-5-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1526272473-25565-1-git-send-email-haojian.zhuang@linaro.org> References: <1526272473-25565-1-git-send-email-haojian.zhuang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v4 4/6] Platform/Hisilicon/HiKey: add gpio platform driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Haojian Zhuang , Leif Lindholm , Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Add gpio platform driver to enable GPIO in HiKey platform. Cc: Leif Lindholm Cc: Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Haojian Zhuang --- .../Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.c | 74 ++++++++++++++++++++++ .../Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf | 36 +++++++++++ 2 files changed, 110 insertions(+) create mode 100644 Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.c create mode 100644 Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.c b/Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.c new file mode 100644 index 000000000000..be535f8f1903 --- /dev/null +++ b/Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.c @@ -0,0 +1,74 @@ +/** @file +* +* Copyright (c) 2018, Linaro. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include + +#include + +GPIO_CONTROLLER gGpioDevice[] = { + // + // { base address, gpio index, gpio count } + // + { 0xf8011000, 0, 8 }, // GPIO0 + { 0xf8012000, 8, 8 }, // GPIO1 + { 0xf8013000, 16, 8 }, // GPIO2 + { 0xf8014000, 24, 8 }, // GPIO3 + { 0xf7020000, 32, 8 }, // GPIO4 + { 0xf7021000, 40, 8 }, // GPIO5 + { 0xf7022000, 48, 8 }, // GPIO6 + { 0xf7023000, 56, 8 }, // GPIO7 + { 0xf7024000, 64, 8 }, // GPIO8 + { 0xf7025000, 72, 8 }, // GPIO9 + { 0xf7026000, 80, 8 }, // GPIO10 + { 0xf7027000, 88, 8 }, // GPIO11 + { 0xf7028000, 96, 8 }, // GPIO12 + { 0xf7029000, 104, 8 }, // GPIO13 + { 0xf702a000, 112, 8 }, // GPIO14 + { 0xf702b000, 120, 8 }, // GPIO15 + { 0xf702c000, 128, 8 }, // GPIO16 + { 0xf702d000, 136, 8 }, // GPIO17 + { 0xf702e000, 144, 8 }, // GPIO18 + { 0xf702f000, 152, 8 } // GPIO19 +}; + +PLATFORM_GPIO_CONTROLLER gPlatformGpioDevice = { + // + // { global gpio count, gpio controller counter, GPIO_CONTROLLER } + // + 160, 20, gGpioDevice +}; + +EFI_STATUS +EFIAPI +HiKeyGpioEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + + // Install the Embedded Platform GPIO Protocol onto a new handle + Handle = NULL; + Status = gBS->InstallMultipleProtocolInterfaces( + &Handle, + &gPlatformGpioProtocolGuid, &gPlatformGpioDevice, + NULL + ); + if (EFI_ERROR(Status)) { + Status = EFI_OUT_OF_RESOURCES; + } + + return Status; +} diff --git a/Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf b/Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf new file mode 100644 index 000000000000..2791b9f44cad --- /dev/null +++ b/Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf @@ -0,0 +1,36 @@ +# +# Copyright (c) 2018, Linaro. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[Defines] + INF_VERSION = 0x0001001a + BASE_NAME = HiKeyGpio + FILE_GUID = b51a851c-7bf7-463f-b261-cfb158b7f699 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = HiKeyGpioEntryPoint + +[Sources.common] + HiKeyGpioDxe.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + DebugLib + UefiDriverEntryPoint + +[Protocols] + gPlatformGpioProtocolGuid + +[Depex] + TRUE From patchwork Mon May 14 04:34:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 135664 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1253520lji; Sun, 13 May 2018 21:35:02 -0700 (PDT) X-Google-Smtp-Source: AB8JxZr0VhP9ykhKPf3DOJsgzFo6hyzllDnFgtwrf64wNLHIMtQpW0FKDksmfx4lripNTW4YUngY X-Received: by 2002:a17:902:1aa:: with SMTP id b39-v6mr8216740plb.120.1526272501939; Sun, 13 May 2018 21:35:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526272501; cv=none; d=google.com; s=arc-20160816; b=aMisCPRnDVvd4nyDlr9pTCQwqol7N0MX+J8Y/oeBFQTcEMzEjJUvGVwD9bVMWiAZAM iPpsbBxui6egXvBRHVqTL+qBZa5LbviKtzHzc1QB3jhZrhJGbulij8pi/67W9FSRHDLf EHGenfzRugJuDhSerRUps+99qNDXifb2GMYbyuK5bkPLUW+B8xfRM5F0l46d0LQ7+RD/ 2+A5DIP8Nx/ScmVIYCqQrowAhn0Oic1T+LFhak3D+onOSoH6qsnYQJ0ImCPX6kGCGQPs JSlmH5aYLbPhaSTuio4mY6ZcgSBSiel+D08YmostvPrUk/CV+36nm7OTNnCFpKoQWNfF odVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=IWsPjvqE16N42U8xs3fghS7KjZWDrD4h4kHcWy0ET4M=; b=bI/KhqiwSiC5Wn5v1kc5nrtSi3IzgAx8BWHXHaf+DOdkznBlupffCcCXalDNTW6ujA MPppy1xUqpOqUW7ivttmVqtidWZYaVZnHoKT2cJj5ws6U88zxrqi/cfpEJfVi7A5kNwU ErSaDRnkzY4zU0ycxKmgAvx3GKm+abrtADcSJqbQ0YxhtC0bp0c4PCwah7Uwtk85sTUs oWIKbZwt6NjrK144B87FBe+dS4WMl5KENWoiGETlXSw4eKB0oWdC4CWioBamlhzblSlz wf8yB5FzHM7pCP0qk1x3+yi2QCadEdtVd2HJ/GGNBpBdl8vTEw0kNH5gMgXddc+gysu8 Q9mA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=LpaTzqKZ; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id q2-v6si6817522pgc.567.2018.05.13.21.35.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 13 May 2018 21:35:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=LpaTzqKZ; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 8980A207E5400; Sun, 13 May 2018 21:35:01 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c05::241; helo=mail-pg0-x241.google.com; envelope-from=haojian.zhuang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg0-x241.google.com (mail-pg0-x241.google.com [IPv6:2607:f8b0:400e:c05::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2F56C207E53E5 for ; Sun, 13 May 2018 21:35:00 -0700 (PDT) Received: by mail-pg0-x241.google.com with SMTP id l2-v6so4914905pgc.7 for ; Sun, 13 May 2018 21:35:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=HUM4tYWvPF8UrBIJYcVYn7pEx7S92RcD5KljCX3CcS0=; b=LpaTzqKZJMz55U7CKC2NVcmlVenlIOPA0Q/4dvg5k585KBgycrYZCpY/zav0leMTUY YnMUZAS/yalP4+RMU9mnA4g+ISAdYnHBrJF/2S9Qos2RpLtivr3Cs/nCJHpcRgLjlTcR GviW2GU6dFtrgyFrav6bsP2HMATF7A8kIWsTk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=HUM4tYWvPF8UrBIJYcVYn7pEx7S92RcD5KljCX3CcS0=; b=c+cKEsDNb7vD9HYgsxOtWEN5R0aaaXSi+HKEz3XCJvHW3A3l/Q8/N5lZlYCSUlUd1d pySsEOva1qWRIS9vs9OkU56vEJIVdOzmd9MCx3B06+5v71GyFmjyKXL3pBpnuVx53SIf YXeugOalXtR/EuP69z7gCZgmzGA/uZHwDzRgOSeNULBwxcb6unvREdKYwb28D4hXFdZN 9UAjLCGi5LcoNKesfS0BN3zHQMdmasqsuty9xbRJ3yIFRQwtXui341ZlzmBo1ViFh4RB P1vgRybTCrImwdjtbGexr8EcO4lp9tu8+JT15cT+/KA628OkjenJvJ9iJIbt9KMYe++G Mg5Q== X-Gm-Message-State: ALKqPwdzdlv1PqLr3Jd0KNgHGdyi6uJ5HUUQpSVOJmE7J8nyYQZ8ShX/ j6h5UKk2ADDgOMj7M7HZj4OrBbUzawE= X-Received: by 2002:a65:4d0b:: with SMTP id i11-v6mr7096486pgt.51.1526272499342; Sun, 13 May 2018 21:34:59 -0700 (PDT) Received: from localhost.localdomain ([64.64.108.93]) by smtp.gmail.com with ESMTPSA id c11-v6sm15125613pfh.15.2018.05.13.21.34.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 13 May 2018 21:34:58 -0700 (PDT) From: Haojian Zhuang To: edk2-devel@lists.01.org Date: Mon, 14 May 2018 12:34:32 +0800 Message-Id: <1526272473-25565-6-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1526272473-25565-1-git-send-email-haojian.zhuang@linaro.org> References: <1526272473-25565-1-git-send-email-haojian.zhuang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v4 5/6] Platform/HiKey: do basic initialization on hikey X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Haojian Zhuang , Leif Lindholm , Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Do some basic initialization on HiKey platform, such as pin setting, regulators and making peripherals out of reset mode. Cc: Leif Lindholm Cc: Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Haojian Zhuang --- Platform/Hisilicon/HiKey/HiKey.dsc | 3 + Platform/Hisilicon/HiKey/HiKey.fdf | 3 + Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.c | 119 ++++++++++++++++++++++ Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf | 40 ++++++++ Silicon/Hisilicon/Hi6220/Include/Hi6220.h | 6 ++ Silicon/Hisilicon/Hi6220/Include/Hi6220RegsPeri.h | 50 +++++++++ 6 files changed, 221 insertions(+) create mode 100644 Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.c create mode 100644 Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf create mode 100644 Silicon/Hisilicon/Hi6220/Include/Hi6220RegsPeri.h -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Platform/Hisilicon/HiKey/HiKey.dsc b/Platform/Hisilicon/HiKey/HiKey.dsc index 5c1604d7f689..5cc4ff27f01b 100644 --- a/Platform/Hisilicon/HiKey/HiKey.dsc +++ b/Platform/Hisilicon/HiKey/HiKey.dsc @@ -189,8 +189,11 @@ [Components.common] # # GPIO # + Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf + Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf + # # MMC/SD # diff --git a/Platform/Hisilicon/HiKey/HiKey.fdf b/Platform/Hisilicon/HiKey/HiKey.fdf index 2a5c5a4d6e79..39020d27dbcd 100644 --- a/Platform/Hisilicon/HiKey/HiKey.fdf +++ b/Platform/Hisilicon/HiKey/HiKey.fdf @@ -120,8 +120,11 @@ [FV.FvMain] # # GPIO # + INF Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf + INF Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf + # # Multimedia Card Interface # diff --git a/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.c b/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.c new file mode 100644 index 000000000000..19987e0b29c3 --- /dev/null +++ b/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.c @@ -0,0 +1,119 @@ +/** @file +* +* Copyright (c) 2018, Linaro Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include + +#include +#include + +#define SERIAL_NUMBER_SIZE 17 +#define SERIAL_NUMBER_BLOCK_SIZE EFI_PAGE_SIZE +#define SERIAL_NUMBER_LBA 1024 +#define RANDOM_MAX 0x7FFFFFFFFFFFFFFF +#define RANDOM_MAGIC 0x9A4DBEAF + +#define DETECT_J15_FASTBOOT 24 // GPIO3_0 + +#define ADB_REBOOT_ADDRESS 0x05F01000 +#define ADB_REBOOT_BOOTLOADER 0x77665500 +#define ADB_REBOOT_NONE 0x77665501 + +STATIC +VOID +UartInit ( + IN VOID + ) +{ + UINT32 Val; + + /* make UART1 out of reset */ + MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART1); + MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART1); + /* make UART2 out of reset */ + MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART2); + MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART2); + /* make UART3 out of reset */ + MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART3); + MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART3); + /* make UART4 out of reset */ + MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, PERIPH_RST3_UART4); + MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_CLKEN3, PERIPH_RST3_UART4); + + /* make DW_MMC2 out of reset */ + MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS0, PERIPH_RST0_MMC2); + + /* enable clock for BT/WIFI */ + Val = MmioRead32 (PMUSSI_ONOFF8_REG) | PMUSSI_ONOFF8_EN_32KB; + MmioWrite32 (PMUSSI_ONOFF8_REG, Val); +} + +STATIC +VOID +MtcmosInit ( + IN VOID + ) +{ + UINT32 Data; + + /* enable MTCMOS for GPU */ + MmioWrite32 (AO_CTRL_BASE + SC_PW_MTCMOS_EN0, PW_EN0_G3D); + do { + Data = MmioRead32 (AO_CTRL_BASE + SC_PW_MTCMOS_ACK_STAT0); + } while ((Data & PW_EN0_G3D) == 0); +} + +EFI_STATUS +HiKeyInitPeripherals ( + IN VOID + ) +{ + UINT32 Data, Bits; + + /* make I2C0/I2C1/I2C2/SPI0 out of reset */ + Bits = PERIPH_RST3_I2C0 | PERIPH_RST3_I2C1 | PERIPH_RST3_I2C2 | \ + PERIPH_RST3_SSP; + MmioWrite32 (PERI_CTRL_BASE + SC_PERIPH_RSTDIS3, Bits); + + do { + Data = MmioRead32 (PERI_CTRL_BASE + SC_PERIPH_RSTSTAT3); + } while (Data & Bits); + + UartInit (); + /* MTCMOS -- Multi-threshold CMOS */ + MtcmosInit (); + + /* Set DETECT_J15_FASTBOOT (GPIO24) pin as GPIO function */ + MmioWrite32 (IOCG_084_REG, 0); /* configure GPIO24 as nopull */ + MmioWrite32 (IOMG_080_REG, 0); /* configure GPIO24 as GPIO */ + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +HiKeyEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status = HiKeyInitPeripherals (); + if (EFI_ERROR (Status)) { + return Status; + } + return Status; +} diff --git a/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf b/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf new file mode 100644 index 000000000000..34734391b45a --- /dev/null +++ b/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf @@ -0,0 +1,40 @@ +# +# Copyright (c) 2013 - 2014, ARM Ltd. All rights reserved. +# Copyright (c) 2018, Linaro Ltd. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +[Defines] + INF_VERSION = 0x0001001a + BASE_NAME = HiKeyDxe + FILE_GUID = f567684b-1089-4214-8881-d64b20cbda2f + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = HiKeyEntryPoint + +[Sources.common] + HiKeyDxe.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + DebugLib + IoLib + UefiLib + UefiDriverEntryPoint + +[Guids] + gEfiEndOfDxeEventGroupGuid + +[Depex] + TRUE diff --git a/Silicon/Hisilicon/Hi6220/Include/Hi6220.h b/Silicon/Hisilicon/Hi6220/Include/Hi6220.h index 203424adfc8b..9b2508955772 100644 --- a/Silicon/Hisilicon/Hi6220/Include/Hi6220.h +++ b/Silicon/Hisilicon/Hi6220/Include/Hi6220.h @@ -23,6 +23,12 @@ #define HI6220_PERIPH_BASE 0xF4000000 #define HI6220_PERIPH_SZ 0x05800000 +#define IOMG_BASE 0xF7010000 +#define IOMG_080_REG (IOMG_BASE + 0x140) + +#define IOCG_BASE 0xF7010800 +#define IOCG_084_REG (IOCG_BASE + 0x150) + #define PERI_CTRL_BASE 0xF7030000 #define SC_PERIPH_CTRL4 0x00C #define CTRL4_FPGA_EXT_PHY_SEL BIT3 diff --git a/Silicon/Hisilicon/Hi6220/Include/Hi6220RegsPeri.h b/Silicon/Hisilicon/Hi6220/Include/Hi6220RegsPeri.h new file mode 100644 index 000000000000..0db8af37d2d0 --- /dev/null +++ b/Silicon/Hisilicon/Hi6220/Include/Hi6220RegsPeri.h @@ -0,0 +1,50 @@ +/** @file +* +* Copyright (c) 2018, Linaro Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#ifndef __HI6220_REGS_PERI_H__ +#define __HI6220_REGS_PERI_H__ + +#define SC_PERIPH_CLKEN3 0x230 +#define SC_PERIPH_RSTEN3 0x330 +#define SC_PERIPH_RSTDIS0 0x304 +#define SC_PERIPH_RSTDIS3 0x334 +#define SC_PERIPH_RSTSTAT3 0x338 + +/* SC_PERIPH_RSTEN0/RSTDIS0/RSTSTAT0 */ +#define PERIPH_RST0_MMC2 (1 << 2) + +/* SC_PERIPH_RSTEN3/RSTDIS3/RSTSTAT3 */ +#define PERIPH_RST3_CSSYS (1 << 0) +#define PERIPH_RST3_I2C0 (1 << 1) +#define PERIPH_RST3_I2C1 (1 << 2) +#define PERIPH_RST3_I2C2 (1 << 3) +#define PERIPH_RST3_I2C3 (1 << 4) +#define PERIPH_RST3_UART1 (1 << 5) +#define PERIPH_RST3_UART2 (1 << 6) +#define PERIPH_RST3_UART3 (1 << 7) +#define PERIPH_RST3_UART4 (1 << 8) +#define PERIPH_RST3_SSP (1 << 9) +#define PERIPH_RST3_PWM (1 << 10) +#define PERIPH_RST3_BLPWM (1 << 11) +#define PERIPH_RST3_TSENSOR (1 << 12) +#define PERIPH_RST3_DAPB (1 << 18) +#define PERIPH_RST3_HKADC (1 << 19) +#define PERIPH_RST3_CODEC_SSI (1 << 20) +#define PERIPH_RST3_PMUSSI1 (1 << 22) + +#define PMUSSI_REG(x) (PMUSSI_BASE + ((x) << 2)) +#define PMUSSI_ONOFF8_REG (PMUSSI_BASE + (0x1c << 2)) +#define PMUSSI_ONOFF8_EN_32KB BIT6 + +#endif /* __HI6220_REGS_PERI_H__ */ From patchwork Mon May 14 04:34:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 135665 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1253559lji; Sun, 13 May 2018 21:35:05 -0700 (PDT) X-Google-Smtp-Source: AB8JxZor13QuPFuwOzJvn8LQaCJ9A4CYMNbvWbrib6t7dxmuYVgL0LRydZOgl5batp1bLLXJdW9+ X-Received: by 2002:a65:49c3:: with SMTP id t3-v6mr7041083pgs.65.1526272504926; Sun, 13 May 2018 21:35:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526272504; cv=none; d=google.com; s=arc-20160816; b=d1ko8SOPEHr395ky0s/CRjq2vAWX2zPX7F8PS6U/JvyKLcokwOpzitgZit6szyPB5Q d5h7OzghTyheJkQsWjUKv3QnvvVkEpGncB5gKcGXKasAmAA81l9g0OtP8/HYKI26lr7F eVjim2b17DB58A7QHgeEnDqCjJvFc/et/UJjGfv4PMKmVukCfNJBaBghKiVTcv983wzd cMenelLu0yopTlL+QaGTIc+rEbZWqXYf31z3heMpZdL4AjIGrIMSEF434EVvyCffXHVo W7On9K78Ao+uTsw/y/TvG17Bzd/rSz21rf8rkPkA7zRdFbi9XcqLsWZ3DAFWW1BAn/qw jMoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:delivered-to:arc-authentication-results; bh=pkeicgX2Fu+wHSCQBTs/PLx/CytkRwRJkRHV7M6XDoE=; b=h4xkUbFm0aFd2kMNSO21J3WrGc4wfaPCfpc2ipSKoIr4AkvOFkeX9NY6eaIA1uWlwT /mWzUlCiBiQDys+wKnDcOgvPb2wjTcYGVnryVPbUVy7cvBdgdAoPRaM2ORRyzciCmaJd FldAfzESqU6d7n+GYUZk3GJNcYpOMyZy5TWNSdAN4d0T5Wz5cr/E9FCz1+L/pxEAyiZP BjCW5f3BcoBo+it7ivja2DOdpMtwpAdfnwpeefa5m39gUjJ42mNnZ4CaCC2KdF0ulAEV IYAQoIqYsiaTyI2Lv+s1MBGrYTL7mhrGKS4yqjxhkKWu9bUrXCbNT7iMcZwphXjhAxXx hVWQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=RSHL+W2b; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org. [198.145.21.10]) by mx.google.com with ESMTPS id 77-v6si8411717pfz.334.2018.05.13.21.35.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 13 May 2018 21:35:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=RSHL+W2b; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id BA202207E5413; Sun, 13 May 2018 21:35:03 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::241; helo=mail-pf0-x241.google.com; envelope-from=haojian.zhuang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf0-x241.google.com (mail-pf0-x241.google.com [IPv6:2607:f8b0:400e:c00::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 07E14207E540E for ; Sun, 13 May 2018 21:35:03 -0700 (PDT) Received: by mail-pf0-x241.google.com with SMTP id v63-v6so5379723pfk.8 for ; Sun, 13 May 2018 21:35:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BJmZc//LTMfHCTOFvQUYc0FfOBsdXwz3aMX/66wkoEM=; b=RSHL+W2bqsnCfGh5oRBpTP+s90u1MTFDAM1Uae7fuq5dcUaXvHkKC4DMrLoNDGWQ3r 3lQo6QZ4pa7p9fVP0tIpL+otcwSRuOjeLNZ9iT2C5N6Kr/ygl9I/cjiF/1SDH2W0hsdZ 0W4P3eDBFmGMlTTqQ9UGrniA/Qts/BfY46zy4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BJmZc//LTMfHCTOFvQUYc0FfOBsdXwz3aMX/66wkoEM=; b=rQX/BYlqiCYVE0jjOkpPcT4fqGPQQWeF6YapAbcS8tJhXaEpgpbxiFYLH634JIGqkp L3QgfwADxyKkibeFGS1aWxCo5w26Q1vCvu9qk/ve6UjW7Wj51h2b40uODUcXLuTWWj3E xFJkc06kCW8Tw9rLtS4aDZ7vD9mBxM7REs5v/v7oLfJYbBlqIbSrbumcqvju5o9miK5m XcmEJEa6dKjO0yek8vFEHdm3/Lz5tPCbr/TayPFwS9CldhjFKXGHcZUXN0Ue5k0+Srva FFakWIzZIkzHN8RwtXGoVmiOuab5FRutxm2TMg+cxtQnybs0cLk3vGhvVgQowzBmcOmx aJ2w== X-Gm-Message-State: ALKqPweyaHYiYJVD19D+QrfuYst/nBhDbb7Bf9QmKHtXOVn8XHGG91bo L7MTfp3JCEPW3QVKSJ9qXDFUucn8jyg= X-Received: by 2002:a62:990f:: with SMTP id d15-v6mr8755126pfe.115.1526272502419; Sun, 13 May 2018 21:35:02 -0700 (PDT) Received: from localhost.localdomain ([64.64.108.93]) by smtp.gmail.com with ESMTPSA id c11-v6sm15125613pfh.15.2018.05.13.21.34.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 13 May 2018 21:35:01 -0700 (PDT) From: Haojian Zhuang To: edk2-devel@lists.01.org Date: Mon, 14 May 2018 12:34:33 +0800 Message-Id: <1526272473-25565-7-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1526272473-25565-1-git-send-email-haojian.zhuang@linaro.org> References: <1526272473-25565-1-git-send-email-haojian.zhuang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v4 6/6] Platform/HiKey: enable virtual keyboard X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Haojian Zhuang , Leif Lindholm , Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Enable virtual keyboard on HiKey platform. It detects the pattern in memory and GPIO pin setting, and simulates them into virtual key. Cc: Leif Lindholm Cc: Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Haojian Zhuang --- Platform/Hisilicon/HiKey/HiKey.dsc | 5 ++ Platform/Hisilicon/HiKey/HiKey.fdf | 5 ++ Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.c | 98 ++++++++++++++++++++++++++ Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf | 5 ++ 4 files changed, 113 insertions(+) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm diff --git a/Platform/Hisilicon/HiKey/HiKey.dsc b/Platform/Hisilicon/HiKey/HiKey.dsc index 5cc4ff27f01b..83dd68a820b1 100644 --- a/Platform/Hisilicon/HiKey/HiKey.dsc +++ b/Platform/Hisilicon/HiKey/HiKey.dsc @@ -192,6 +192,11 @@ [Components.common] Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf + # + # Virtual Keyboard + # + EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf + Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf # diff --git a/Platform/Hisilicon/HiKey/HiKey.fdf b/Platform/Hisilicon/HiKey/HiKey.fdf index 39020d27dbcd..2bca7232b6e5 100644 --- a/Platform/Hisilicon/HiKey/HiKey.fdf +++ b/Platform/Hisilicon/HiKey/HiKey.fdf @@ -123,6 +123,11 @@ [FV.FvMain] INF Platform/Hisilicon/HiKey/HiKeyGpioDxe/HiKeyGpioDxe.inf INF ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf + # + # Virtual Keyboard + # + INF EmbeddedPkg/Drivers/VirtualKeyboardDxe/VirtualKeyboardDxe.inf + INF Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf # diff --git a/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.c b/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.c index 19987e0b29c3..8f4f9157835c 100644 --- a/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.c +++ b/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.c @@ -12,10 +12,15 @@ * **/ +#include #include #include +#include #include +#include +#include + #include #include @@ -31,6 +36,8 @@ #define ADB_REBOOT_BOOTLOADER 0x77665500 #define ADB_REBOOT_NONE 0x77665501 +STATIC EMBEDDED_GPIO *mGpio; + STATIC VOID UartInit ( @@ -104,6 +111,90 @@ HiKeyInitPeripherals ( EFI_STATUS EFIAPI +VirtualKeyboardRegister ( + IN VOID + ) +{ + EFI_STATUS Status; + + Status = gBS->LocateProtocol ( + &gEmbeddedGpioProtocolGuid, + NULL, + (VOID **) &mGpio + ); + if (EFI_ERROR (Status)) { + return Status; + } + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +VirtualKeyboardReset ( + IN VOID + ) +{ + EFI_STATUS Status; + + if (mGpio == NULL) { + return EFI_INVALID_PARAMETER; + } + Status = mGpio->Set (mGpio, DETECT_J15_FASTBOOT, GPIO_MODE_INPUT); + return Status; +} + +BOOLEAN +EFIAPI +VirtualKeyboardQuery ( + IN VIRTUAL_KBD_KEY *VirtualKey + ) +{ + EFI_STATUS Status; + UINTN Value = 0; + + if ((VirtualKey == NULL) || (mGpio == NULL)) { + return FALSE; + } + if (MmioRead32 (ADB_REBOOT_ADDRESS) == ADB_REBOOT_BOOTLOADER) { + goto Done; + } else { + Status = mGpio->Get (mGpio, DETECT_J15_FASTBOOT, &Value); + if (EFI_ERROR (Status) || (Value != 0)) { + return FALSE; + } + } +Done: + VirtualKey->Signature = VIRTUAL_KEYBOARD_KEY_SIGNATURE; + VirtualKey->Key.ScanCode = SCAN_NULL; + VirtualKey->Key.UnicodeChar = L'f'; + return TRUE; +} + +EFI_STATUS +EFIAPI +VirtualKeyboardClear ( + IN VIRTUAL_KBD_KEY *VirtualKey + ) +{ + if (VirtualKey == NULL) { + return EFI_INVALID_PARAMETER; + } + if (MmioRead32 (ADB_REBOOT_ADDRESS) == ADB_REBOOT_BOOTLOADER) { + MmioWrite32 (ADB_REBOOT_ADDRESS, ADB_REBOOT_NONE); + WriteBackInvalidateDataCacheRange ((VOID *)ADB_REBOOT_ADDRESS, 4); + } + return EFI_SUCCESS; +} + +PLATFORM_VIRTUAL_KBD_PROTOCOL mVirtualKeyboard = { + VirtualKeyboardRegister, + VirtualKeyboardReset, + VirtualKeyboardQuery, + VirtualKeyboardClear +}; + +EFI_STATUS +EFIAPI HiKeyEntryPoint ( IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable @@ -115,5 +206,12 @@ HiKeyEntryPoint ( if (EFI_ERROR (Status)) { return Status; } + + Status = gBS->InstallProtocolInterface ( + &ImageHandle, + &gPlatformVirtualKeyboardProtocolGuid, + EFI_NATIVE_INTERFACE, + &mVirtualKeyboard + ); return Status; } diff --git a/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf b/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf index 34734391b45a..41aa7f8081ed 100644 --- a/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf +++ b/Platform/Hisilicon/HiKey/HiKeyDxe/HiKeyDxe.inf @@ -28,11 +28,16 @@ [Packages] MdePkg/MdePkg.dec [LibraryClasses] + CacheMaintenanceLib DebugLib IoLib UefiLib UefiDriverEntryPoint +[Protocols] + gEmbeddedGpioProtocolGuid + gPlatformVirtualKeyboardProtocolGuid + [Guids] gEfiEndOfDxeEventGroupGuid