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[80.251.214.228]) by smtp.gmail.com with ESMTPSA id i13sm8092521pgi.3.2021.03.26.04.02.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Mar 2021 04:02:24 -0700 (PDT) From: Shawn Guo To: Adrian Hunter , Ulf Hansson Cc: Haibo Chen , Dong Aisheng , Pengutronix Kernel Team , NXP Linux Team , linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Shawn Guo Subject: [PATCH] mmc: sdhci-esdhc-imx: separate 100/200 MHz pinctrl states check Date: Fri, 26 Mar 2021 19:02:14 +0800 Message-Id: <20210326110214.28416-1-shawnguo@kernel.org> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Shawn Guo As indicated by function esdhc_change_pinstate(), SDR50 and DDR50 require pins_100mhz, while SDR104 and HS400 require pins_200mhz. Some system design may support SDR50 and DDR50 with 100mhz pin state only (without 200mhz one). Currently the combined 100/200 MHz pinctrl state check prevents such system from running SDR50 and DDR50. Separate the check to support such system design. Signed-off-by: Shawn Guo --- drivers/mmc/host/sdhci-esdhc-imx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.17.1 Reviewed-by: Haibo Chen diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index a20459744d21..aa45901325b9 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -434,10 +434,10 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg) * Do not advertise faster UHS modes if there are no * pinctrl states for 100MHz/200MHz. */ - if (IS_ERR_OR_NULL(imx_data->pins_100mhz) || - IS_ERR_OR_NULL(imx_data->pins_200mhz)) - val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50 - | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400); + if (IS_ERR_OR_NULL(imx_data->pins_100mhz)) + val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); + if (IS_ERR_OR_NULL(imx_data->pins_200mhz)) + val &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400); } }