From patchwork Sun May 20 05:17:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 136407 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp3093373lji; Sat, 19 May 2018 22:18:59 -0700 (PDT) X-Google-Smtp-Source: AB8JxZpwUDu4NZl7i/It0aa0lNQbjJyJ+OZyRWJfGbuS+GeQzT4tb15dcmHgT9Jg8MZGD0HrbPqk X-Received: by 2002:a62:8605:: with SMTP id x5-v6mr15330257pfd.103.1526793539652; Sat, 19 May 2018 22:18:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526793539; cv=none; d=google.com; s=arc-20160816; b=tkVYsWl4NNF/8lc4o5W9q+OgxuIgUlyY51P7uIY1HcGv0t1DV7Rh1NoygwuWObfQVK jOCwVsFCNOWX++PRCqHNlk7AGaL3XF/CBvsgipEEKVQ+OEVi2VDhnFWsncyqGyZQRPYD UXUG2E1bzm6rmXbtfg/zKrQdd9Y1eY7sZmCOroRhI9wZx5AebtLlx++CymU0yKsKkmKf v6LE6+cURt3d7sBUAk9oti103SAp3GtT1qxDz6sZ3FAnTR6f8bYwFzstnNSIrzkozNu8 Nq3TrF2XLiQl0+XFStCJbkAJLkkT5l+eN6IaA9shidmnn3+xatBRJy2mPkMqS9Mxclkp UGwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=1CTC7GdgVkQ8CpxRplqVqdZS2FtPJbd0ZXPsgf4D2DA=; b=mLhrwFdZaK8aPg/TnKm+5eB3FDSNns5goQI8k/fToho0oAEici76IYtigvn3QAe+RC dKx8vtZWIIjjgxiqEME6KYztSNwyhr30NSWTXXVjZG2dhI88g6bqYBb2leVvEJfrB7lh Pa7FnztLo5QglUlKAPjl6XHQhwJaHTMon5yRLbtUrVwnfjizDKbSnvFMOvZJOX9WM4Qa /n4u0wVWytaZduXIHDhdi+h5efG2kUB0jIbzZeCMt+GrBMKazlLsN/xSsbhNEM0QOEjo uHcgFJqc2QCCtrgHRcVarecGflrmxs83V0zT9s+/aab/LPqvIn8XYytGIfKXdj0ajkFL msoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=bsG8XnYa; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 87-v6si11285723pfo.137.2018.05.19.22.18.58; Sat, 19 May 2018 22:18:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=bsG8XnYa; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751408AbeETFS4 (ORCPT + 5 others); Sun, 20 May 2018 01:18:56 -0400 Received: from mail-pf0-f196.google.com ([209.85.192.196]:33990 "EHLO mail-pf0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751348AbeETFSw (ORCPT ); Sun, 20 May 2018 01:18:52 -0400 Received: by mail-pf0-f196.google.com with SMTP id a14-v6so5546721pfi.1 for ; Sat, 19 May 2018 22:18:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NRRET1a774IOfwV6KycY0/gxdu703500H+0h/6Ji0oc=; b=bsG8XnYaATFivCyxcJvJzHjUffyIjX+5yv+ItXW+i/JavrARlVTcGQbztGj9wn4zjC NlIIkTeZAP5/cse5Lt8Fh99gZSyhmdDpsG5j/4A9FeHwdK6T+4Z5Xu0SINv2+FLUAVqB naos1g/s1ALHHRuf2nlgRuBzYyk0mSk8J+ZQE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NRRET1a774IOfwV6KycY0/gxdu703500H+0h/6Ji0oc=; b=tsmiUb/3wIyqZcTSQ7vEf3xwLvWoUf/4Cv2rLkMBTm8UCkr+EaRnA9PVeVQVqRVVap 3SiMEIPlVdB5xcaeP4mGIyi9FmhV4P86YCLvPIpC8jvwVtmURDLCEFK0OrktrFF1s2Cc aINOn4TrW/j+pW+NJOkNmLXOJIbFmXvREammCTl6GdlbGNSHZNEEfQO8QS4bo2SJE5nD xftCJjc8hXyFNLa8STOUmtCcdx0hRbA9SKhM8aRtq+6XL3hQYMTG+6tYDk7pK/VqrEM+ m8O0R+NZ/JBOYuUMb7Pi5vNkvGDnquSb18OdeT0vYJiWlIpIZgN6g0Tr0rN+UttxSWOR x36g== X-Gm-Message-State: ALKqPwcA+acE0z1+vDas+gqGTMMnWib1VFVQGaih8JPamqUzzcDL/N0l o5Xjaf/6Glxl1r+WFc1WISCt X-Received: by 2002:a62:9099:: with SMTP id q25-v6mr15599153pfk.66.1526793531435; Sat, 19 May 2018 22:18:51 -0700 (PDT) Received: from localhost.localdomain ([2405:204:718a:6d36:c501:566:93b3:ade2]) by smtp.gmail.com with ESMTPSA id p6-v6sm20107670pfg.157.2018.05.19.22.18.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 19 May 2018 22:18:51 -0700 (PDT) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, robh+dt@kernel.org, afaerber@suse.de Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, andy.shevchenko@gmail.com, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, Manivannan Sadhasivam Subject: [PATCH v2 1/5] dt-bindings: pinctrl: Add gpio bindings for Actions S900 SoC Date: Sun, 20 May 2018 10:47:32 +0530 Message-Id: <20180520051736.4842-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180520051736.4842-1-manivannan.sadhasivam@linaro.org> References: <20180520051736.4842-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add gpio bindings for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam --- .../devicetree/bindings/pinctrl/actions,s900-pinctrl.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.14.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt index fb87c7d74f2e..8fb5a53775e8 100644 --- a/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt @@ -8,6 +8,17 @@ Required Properties: - reg: Should contain the register base address and size of the pin controller. - clocks: phandle of the clock feeding the pin controller +- gpio-controller: Marks the device node as a GPIO controller. +- gpio-ranges: Specifies the mapping between gpio controller and + pin-controller pins. +- #gpio-cells: Should be two. The first cell is the gpio pin number + and the second cell is used for optional parameters. +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells: Specifies the number of cells needed to encode an + interrupt. Shall be set to 2. The first cell + defines the interrupt number, the second encodes + the trigger flags described in + bindings/interrupt-controller/interrupts.txt Please refer to pinctrl-bindings.txt in this directory for details of the common pinctrl bindings used by client devices, including the meaning of the @@ -164,6 +175,11 @@ Example: compatible = "actions,s900-pinctrl"; reg = <0x0 0xe01b0000 0x0 0x1000>; clocks = <&cmu CLK_GPIO>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 146>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; uart2-default: uart2-default { pinmux { From patchwork Sun May 20 05:17:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 136410 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp3093651lji; Sat, 19 May 2018 22:19:22 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrUdZunWVJ3C6Ecara//yHcib4LIJCK+cWKjVV36O1biqda41kgLM7606xTyAlaXEvW9i/n X-Received: by 2002:a17:902:28a7:: with SMTP id f36-v6mr15685531plb.155.1526793562224; Sat, 19 May 2018 22:19:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526793562; cv=none; d=google.com; s=arc-20160816; b=NQXp6ODhpGwt9vJ9JAys8TdhW7yLfFOXtHnc6b1CEYpunHA5wumebBS9VwsnhCTXUW MQr22yJ1B21fhdyIL1wBZg1O/RbEJKdiuYWISlfjH/KkmegSgRTp6nbtBAWrO84mWOOO VrU6vBkaZ8bk3jMOXRoiYI9rHxNjkcTP8ppzjvJyQczNb6O0QJoVvHnXtJPPpg7nBJko tTeHKuPPR9omHf+4Xf3MOCRwdurjg9AoCfCfsMv7TQ14ar1piKmQjS9s0krcoOfHsKhV ks7XkOMtcFE4dJddBdvLdrHtFrQSLJ85+VF49YB2cPCdEBhbHjdhqnqsJnaMIFTqv2Z2 0kzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=MVYcw18lq9VRgaIMoGrN5D8+Povz5P6XpZjsFgeFB5k=; b=GVbiXTAzHIUr7mhk3+1zRXoWO6reUpsjqOl0o0A3zoET0MZVmVr9f3Y+nfe8CwPxLd G57etCcoM0bF5/WnpmlvIB9M8nVC6Q5jWXx4WQHCNK9DacraUUVdt/9g9g6CLBK3e6GG Bzu6E+Y4JCX/PnG3xDsZgk2anFydwoLHr+nH2x+8mLSkJUjg3ZvvBFnESf48rZW+vZGG N39mMV5kG1xD6LPGDbrOqGzvOQewCP5ZWFlh/uMT7AO7X7Xg/fBDc32JwqF9c9WDJK0/ g9IvyDtfYbDZ4jpB7+tlVFHiyRvuNnIxtTc53khn2dZ2mEZajY35nuGz7jEQuuAv98Pd Yy3g== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=hPWiT+hw; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x12-v6si10968150pln.97.2018.05.19.22.19.21; Sat, 19 May 2018 22:19:22 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=hPWiT+hw; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751773AbeETFTT (ORCPT + 5 others); Sun, 20 May 2018 01:19:19 -0400 Received: from mail-pl0-f68.google.com ([209.85.160.68]:45122 "EHLO mail-pl0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751707AbeETFTP (ORCPT ); Sun, 20 May 2018 01:19:15 -0400 Received: by mail-pl0-f68.google.com with SMTP id bi12-v6so6853435plb.12 for ; Sat, 19 May 2018 22:19:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=A/ccYhyG5w8wrBatfl34N3OJJCxtcKcUeeIH1bl07do=; b=hPWiT+hw6Nhs2DL+rKk3Gp7Gon4YI5nEhHbjRdEeVRA3HtrLTIvQkzTUH4W2yBvThZ OZlrnDrluGYqdZcQraJ+ECqxo79teyO0oAsZQj/PocZVC3JmrikU9KwiGa2fcMpJCKBe ennk3YjeaRdgKK3KayRDmbfVAfr5GDGP5JIzg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=A/ccYhyG5w8wrBatfl34N3OJJCxtcKcUeeIH1bl07do=; b=WXUdkrEs6SY2XugEhQ/MzN0tng5hz42rdZU/GtmPFfhY8qmlFICEbV62+kE+E6dMCy bGxlOU1Ys4nXg96a7ceFYRneEV0OgKgEL3jhtenrtcbCbgKNCdW6g4qZMu2N8n0wKyAa MvxKDMhJl1I6y4KL1CwTQqJHTqQzM06Sy40OFyAZjNRu8NX0ZO3fNTAVLG5p/mhDfrr+ LgAthMeDsgxSIt0zsG2E1WUWIR3PZXajMyvQti61ttbZwdtrQj4FUoList3md3ahjbNn ycBWNwqraj/hqYUKuMiJumwRsrI6BP3dSKAVMGDGhB7P7RV+oQEXjUe5BcaY1It2pAI4 I4rA== X-Gm-Message-State: ALKqPwevOExKsYES43hbTbxlH/8tEirAsHWjp57RXm1NBlq9y8A8epzY jsonmG29MyQ6ZlD583Q81VEP X-Received: by 2002:a17:902:b589:: with SMTP id a9-v6mr15256155pls.161.1526793554769; Sat, 19 May 2018 22:19:14 -0700 (PDT) Received: from localhost.localdomain ([2405:204:718a:6d36:c501:566:93b3:ade2]) by smtp.gmail.com with ESMTPSA id p6-v6sm20107670pfg.157.2018.05.19.22.19.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 19 May 2018 22:19:14 -0700 (PDT) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, robh+dt@kernel.org, afaerber@suse.de Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, andy.shevchenko@gmail.com, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, Manivannan Sadhasivam Subject: [PATCH v2 4/5] pinctrl: actions: Add gpio support for Actions S900 SoC Date: Sun, 20 May 2018 10:47:35 +0530 Message-Id: <20180520051736.4842-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180520051736.4842-1-manivannan.sadhasivam@linaro.org> References: <20180520051736.4842-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add gpio support to pinctrl driver for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Andy Shevchenko --- drivers/pinctrl/actions/Kconfig | 1 + drivers/pinctrl/actions/pinctrl-owl.c | 198 +++++++++++++++++++++++++++++++++ drivers/pinctrl/actions/pinctrl-owl.h | 20 ++++ drivers/pinctrl/actions/pinctrl-s900.c | 29 ++++- 4 files changed, 247 insertions(+), 1 deletion(-) -- 2.14.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pinctrl/actions/Kconfig b/drivers/pinctrl/actions/Kconfig index ede97cdbbc12..490927b4ea76 100644 --- a/drivers/pinctrl/actions/Kconfig +++ b/drivers/pinctrl/actions/Kconfig @@ -4,6 +4,7 @@ config PINCTRL_OWL select PINMUX select PINCONF select GENERIC_PINCONF + select GPIOLIB help Say Y here to enable Actions Semi OWL pinctrl driver diff --git a/drivers/pinctrl/actions/pinctrl-owl.c b/drivers/pinctrl/actions/pinctrl-owl.c index ee090697b1e9..76243caa08c6 100644 --- a/drivers/pinctrl/actions/pinctrl-owl.c +++ b/drivers/pinctrl/actions/pinctrl-owl.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include @@ -31,6 +32,7 @@ * struct owl_pinctrl - pinctrl state of the device * @dev: device handle * @pctrldev: pinctrl handle + * @chip: gpio chip * @lock: spinlock to protect registers * @soc: reference to soc_data * @base: pinctrl register base address @@ -38,6 +40,7 @@ struct owl_pinctrl { struct device *dev; struct pinctrl_dev *pctrldev; + struct gpio_chip chip; raw_spinlock_t lock; struct clk *clk; const struct owl_pinctrl_soc_data *soc; @@ -536,6 +539,190 @@ static struct pinctrl_desc owl_pinctrl_desc = { .owner = THIS_MODULE, }; +static const struct owl_gpio_port * +owl_gpio_get_port(struct owl_pinctrl *pctrl, unsigned int *pin) +{ + unsigned int start = 0, i; + + for (i = 0; i < pctrl->soc->nports; i++) { + const struct owl_gpio_port *port = &pctrl->soc->ports[i]; + + if (*pin >= start && *pin < start + port->pins) { + *pin -= start; + return port; + } + + start += port->pins; + } + + return NULL; +} + +static void owl_gpio_update_reg(void __iomem *base, unsigned int pin, int flag) +{ + u32 val; + + val = readl_relaxed(base); + + if (flag) + val |= BIT(pin); + else + val &= ~BIT(pin); + + writel_relaxed(val, base); +} + +static int owl_gpio_request(struct gpio_chip *chip, unsigned int offset) +{ + struct owl_pinctrl *pctrl = gpiochip_get_data(chip); + const struct owl_gpio_port *port; + void __iomem *gpio_base; + unsigned long flags; + + port = owl_gpio_get_port(pctrl, &offset); + if (WARN_ON(port == NULL)) + return -ENODEV; + + gpio_base = pctrl->base + port->offset; + + /* + * GPIOs have higher priority over other modules, so either setting + * them as OUT or IN is sufficient + */ + raw_spin_lock_irqsave(&pctrl->lock, flags); + owl_gpio_update_reg(gpio_base + port->outen, offset, true); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + +static void owl_gpio_free(struct gpio_chip *chip, unsigned int offset) +{ + struct owl_pinctrl *pctrl = gpiochip_get_data(chip); + const struct owl_gpio_port *port; + void __iomem *gpio_base; + unsigned long flags; + + port = owl_gpio_get_port(pctrl, &offset); + if (WARN_ON(port == NULL)) + return; + + gpio_base = pctrl->base + port->offset; + + raw_spin_lock_irqsave(&pctrl->lock, flags); + /* disable gpio output */ + owl_gpio_update_reg(gpio_base + port->outen, offset, false); + + /* disable gpio input */ + owl_gpio_update_reg(gpio_base + port->inen, offset, false); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static int owl_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct owl_pinctrl *pctrl = gpiochip_get_data(chip); + const struct owl_gpio_port *port; + void __iomem *gpio_base; + unsigned long flags; + u32 val; + + port = owl_gpio_get_port(pctrl, &offset); + if (WARN_ON(port == NULL)) + return -ENODEV; + + gpio_base = pctrl->base + port->offset; + + raw_spin_lock_irqsave(&pctrl->lock, flags); + val = readl_relaxed(gpio_base + port->dat); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + + return !!(val & BIT(offset)); +} + +static void owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) +{ + struct owl_pinctrl *pctrl = gpiochip_get_data(chip); + const struct owl_gpio_port *port; + void __iomem *gpio_base; + unsigned long flags; + + port = owl_gpio_get_port(pctrl, &offset); + if (WARN_ON(port == NULL)) + return; + + gpio_base = pctrl->base + port->offset; + + raw_spin_lock_irqsave(&pctrl->lock, flags); + owl_gpio_update_reg(gpio_base + port->dat, offset, value); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static int owl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + struct owl_pinctrl *pctrl = gpiochip_get_data(chip); + const struct owl_gpio_port *port; + void __iomem *gpio_base; + unsigned long flags; + + port = owl_gpio_get_port(pctrl, &offset); + if (WARN_ON(port == NULL)) + return -ENODEV; + + gpio_base = pctrl->base + port->offset; + + raw_spin_lock_irqsave(&pctrl->lock, flags); + owl_gpio_update_reg(gpio_base + port->outen, offset, false); + owl_gpio_update_reg(gpio_base + port->inen, offset, true); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + +static int owl_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct owl_pinctrl *pctrl = gpiochip_get_data(chip); + const struct owl_gpio_port *port; + void __iomem *gpio_base; + unsigned long flags; + + port = owl_gpio_get_port(pctrl, &offset); + if (WARN_ON(port == NULL)) + return -ENODEV; + + gpio_base = pctrl->base + port->offset; + + raw_spin_lock_irqsave(&pctrl->lock, flags); + owl_gpio_update_reg(gpio_base + port->inen, offset, false); + owl_gpio_update_reg(gpio_base + port->outen, offset, true); + owl_gpio_update_reg(gpio_base + port->dat, offset, value); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + + return 0; +} + +static int owl_gpio_init(struct owl_pinctrl *pctrl) +{ + struct gpio_chip *chip; + int ret; + + chip = &pctrl->chip; + chip->base = -1; + chip->ngpio = pctrl->soc->ngpios; + chip->label = dev_name(pctrl->dev); + chip->parent = pctrl->dev; + chip->owner = THIS_MODULE; + chip->of_node = pctrl->dev->of_node; + + ret = gpiochip_add_data(&pctrl->chip, pctrl); + if (ret) { + dev_err(pctrl->dev, "failed to register gpiochip\n"); + return ret; + } + + return 0; +} + int owl_pinctrl_probe(struct platform_device *pdev, struct owl_pinctrl_soc_data *soc_data) { @@ -571,6 +758,13 @@ int owl_pinctrl_probe(struct platform_device *pdev, owl_pinctrl_desc.pins = soc_data->pins; owl_pinctrl_desc.npins = soc_data->npins; + pctrl->chip.direction_input = owl_gpio_direction_input; + pctrl->chip.direction_output = owl_gpio_direction_output; + pctrl->chip.get = owl_gpio_get; + pctrl->chip.set = owl_gpio_set; + pctrl->chip.request = owl_gpio_request; + pctrl->chip.free = owl_gpio_free; + pctrl->soc = soc_data; pctrl->dev = &pdev->dev; @@ -581,6 +775,10 @@ int owl_pinctrl_probe(struct platform_device *pdev, return PTR_ERR(pctrl->pctrldev); } + ret = owl_gpio_init(pctrl); + if (ret) + return ret; + platform_set_drvdata(pdev, pctrl); return 0; diff --git a/drivers/pinctrl/actions/pinctrl-owl.h b/drivers/pinctrl/actions/pinctrl-owl.h index 448f81a6db3b..74342378937c 100644 --- a/drivers/pinctrl/actions/pinctrl-owl.h +++ b/drivers/pinctrl/actions/pinctrl-owl.h @@ -114,6 +114,22 @@ struct owl_pinmux_func { unsigned int ngroups; }; +/** + * struct owl_gpio_port - Actions GPIO port info + * @offset: offset of the GPIO port. + * @pins: number of pins belongs to the GPIO port. + * @outen: offset of the output enable register. + * @inen: offset of the input enable register. + * @dat: offset of the data register. + */ +struct owl_gpio_port { + unsigned int offset; + unsigned int pins; + unsigned int outen; + unsigned int inen; + unsigned int dat; +}; + /** * struct owl_pinctrl_soc_data - Actions pin controller driver configuration * @pins: array describing all pins of the pin controller. @@ -124,6 +140,8 @@ struct owl_pinmux_func { * @ngroups: number of entries in @groups. * @padinfo: array describing the pad info of this SoC. * @ngpios: number of pingroups the driver should expose as GPIOs. + * @port: array describing all GPIO ports of this SoC. + * @nports: number of GPIO ports in this SoC. */ struct owl_pinctrl_soc_data { const struct pinctrl_pin_desc *pins; @@ -134,6 +152,8 @@ struct owl_pinctrl_soc_data { unsigned int ngroups; const struct owl_padinfo *padinfo; unsigned int ngpios; + const struct owl_gpio_port *ports; + unsigned int nports; }; int owl_pinctrl_probe(struct platform_device *pdev, diff --git a/drivers/pinctrl/actions/pinctrl-s900.c b/drivers/pinctrl/actions/pinctrl-s900.c index 08d93f8fc086..5503c7945764 100644 --- a/drivers/pinctrl/actions/pinctrl-s900.c +++ b/drivers/pinctrl/actions/pinctrl-s900.c @@ -33,6 +33,13 @@ #define PAD_SR1 (0x0274) #define PAD_SR2 (0x0278) +#define OWL_GPIO_PORT_A 0 +#define OWL_GPIO_PORT_B 1 +#define OWL_GPIO_PORT_C 2 +#define OWL_GPIO_PORT_D 3 +#define OWL_GPIO_PORT_E 4 +#define OWL_GPIO_PORT_F 5 + #define _GPIOA(offset) (offset) #define _GPIOB(offset) (32 + (offset)) #define _GPIOC(offset) (64 + (offset)) @@ -1814,6 +1821,24 @@ static struct owl_padinfo s900_padinfo[NUM_PADS] = { [SGPIO3] = PAD_INFO_PULLCTL_ST(SGPIO3) }; +#define OWL_GPIO_PORT(port, base, count, _outen, _inen, _dat) \ + [OWL_GPIO_PORT_##port] = { \ + .offset = base, \ + .pins = count, \ + .outen = _outen, \ + .inen = _inen, \ + .dat = _dat, \ + } + +static const struct owl_gpio_port s900_gpio_ports[] = { + OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8), + OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8), + OWL_GPIO_PORT(C, 0x0018, 12, 0x0, 0x4, 0x8), + OWL_GPIO_PORT(D, 0x0024, 30, 0x0, 0x4, 0x8), + OWL_GPIO_PORT(E, 0x0030, 32, 0x0, 0x4, 0x8), + OWL_GPIO_PORT(F, 0x00F0, 8, 0x0, 0x4, 0x8) +}; + static struct owl_pinctrl_soc_data s900_pinctrl_data = { .padinfo = s900_padinfo, .pins = (const struct pinctrl_pin_desc *)s900_pads, @@ -1822,7 +1847,9 @@ static struct owl_pinctrl_soc_data s900_pinctrl_data = { .nfunctions = ARRAY_SIZE(s900_functions), .groups = s900_groups, .ngroups = ARRAY_SIZE(s900_groups), - .ngpios = NUM_GPIOS + .ngpios = NUM_GPIOS, + .ports = s900_gpio_ports, + .nports = ARRAY_SIZE(s900_gpio_ports) }; static int s900_pinctrl_probe(struct platform_device *pdev)