From patchwork Mon May 21 10:09:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 136447 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp121490lji; Mon, 21 May 2018 03:14:08 -0700 (PDT) X-Google-Smtp-Source: AB8JxZoOxaFr2MclBGlf6elv9y7Pxx7myweqBv7qnfgcfpeahhDArG2mnAI5nrPEvgLPo15BuWZr X-Received: by 2002:a63:6285:: with SMTP id w127-v6mr5935261pgb.164.1526897648334; Mon, 21 May 2018 03:14:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526897648; cv=none; d=google.com; s=arc-20160816; b=M6ty8SVGF3L5NaQTFXlca20KX2b8T+tVu7048s2hqqbwzrU6HZlSIcp9vEl407RQ/a a06MG5XaMO8jkLaer3a3G3j7ve+sJ1eXb0SJm6uoh+pkRyYFnggmTGTZvX0iTzWVujGp 4h8sH96PNUlzSlFhXdSqP+OY2xnVR/s55TupXC7saMO8byV5CLtNviuSH2zjxeyX1Ppl Q1wXX/T91RmkC77NvsnK8D/tzZqDdmI8LGIX8qmffu3NE1czGv3181BzWRTDrgkRQHIp W0V8fvVbn5sQwzU77trZkp24L+mz2B0AFA2JfaAbC7B0EesY+y3oZljrnpLS46VlcJaD sNcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=PwDu/IPK1FirmiG/ZHItUZSPdNY3lDLdMTayULtXYB8=; b=tBVJ209tZkatsUb0oYoPmLfzbEpNGMjemePNG97rikUatromDM0szj9ACWrHJSByVQ kwOxXyIRf174bOKnIrzHKaeglOOWhKxqmitJ2vKRj+UcBBqk3iQuHmPwBbObej7Vj4Nu S/4PDqkBU51hh7Vu5pgxZ9h8ADfw5YnhbaHp5bjg5yK1IKHrpSgsJE1nF8ING7/rPh6/ 8okaJURGQrnUn7lqLv+HBYOP7SIFr45ZC+09mxmY2L7Dzsv8dizhdQf1ACgsC1QuQoWk aCMUHvukaUwHxC5Po7a1Uc6twpOf3biStmf8NsgMDMV+E4I+2hMArH8ykW3FC8PNotEK 3IBA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-scsi-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c65-v6si14075311pfa.99.2018.05.21.03.14.08; Mon, 21 May 2018 03:14:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-scsi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752827AbeEUKOG (ORCPT + 1 other); Mon, 21 May 2018 06:14:06 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:55795 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752535AbeEUKLm (ORCPT ); Mon, 21 May 2018 06:11:42 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id BAAA53F79D9E0; Mon, 21 May 2018 18:11:35 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.382.0; Mon, 21 May 2018 18:11:31 +0800 From: John Garry To: , CC: , , , Xiaofei Tan , "John Garry" Subject: [PATCH 08/13] scsi: hisi_sas: Try wait commands before before controller reset Date: Mon, 21 May 2018 18:09:20 +0800 Message-ID: <1526897365-228549-9-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1526897365-228549-1-git-send-email-john.garry@huawei.com> References: <1526897365-228549-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Xiaofei Tan We may reset the controller in many scenarios, such as SCSI EH and HW errors. There should be no IO which returns from target when SCSI EH is active. But for other scenarios, there may be. It is not necessary to make such IOs failure. This patch adds an function of trying to wait for any commands, or IO, to complete before host reset. If no more CQ returned from host controller in 100ms, we assume no more IO can return, and then stop waiting. We wait 5s at most. The HW has a register CQE_SEND_CNT to indicate the total number of CQs that has been reported to driver. We can use this register and it is reliable to resd this register in such scenarios that require host reset. Signed-off-by: Xiaofei Tan Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas.h | 2 ++ drivers/scsi/hisi_sas/hisi_sas_main.c | 2 ++ drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 19 +++++++++++++++++++ drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 20 ++++++++++++++++++++ 4 files changed, 43 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index 37c9a62..8ce6abb 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -246,6 +246,8 @@ struct hisi_sas_hw { u32 (*get_phys_state)(struct hisi_hba *hisi_hba); int (*write_gpio)(struct hisi_hba *hisi_hba, u8 reg_type, u8 reg_index, u8 reg_count, u8 *write_data); + void (*wait_cmds_complete_timeout)(struct hisi_hba *hisi_hba, + int delay_ms, int timeout_ms); int max_command_entries; int complete_hdr_size; struct scsi_host_template *sht; diff --git a/drivers/scsi/hisi_sas/hisi_sas_main.c b/drivers/scsi/hisi_sas/hisi_sas_main.c index 0dfefdf..a6fcfb3 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_main.c +++ b/drivers/scsi/hisi_sas/hisi_sas_main.c @@ -1293,6 +1293,8 @@ static int hisi_sas_controller_reset(struct hisi_hba *hisi_hba) old_state = hisi_hba->hw->get_phys_state(hisi_hba); scsi_block_requests(shost); + hisi_hba->hw->wait_cmds_complete_timeout(hisi_hba, 100, 5000); + if (timer_pending(&hisi_hba->timer)) del_timer_sync(&hisi_hba->timer); diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c index 8def327..18dbaff 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c @@ -144,6 +144,7 @@ #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 19 #define SAS_ECC_INTR_MSK 0x1ec #define HGC_ERR_STAT_EN 0x238 +#define CQE_SEND_CNT 0x248 #define DLVRY_Q_0_BASE_ADDR_LO 0x260 #define DLVRY_Q_0_BASE_ADDR_HI 0x264 #define DLVRY_Q_0_DEPTH 0x268 @@ -3501,6 +3502,23 @@ static int write_gpio_v2_hw(struct hisi_hba *hisi_hba, u8 reg_type, return 0; } +static void wait_cmds_complete_timeout_v2_hw(struct hisi_hba *hisi_hba, + int delay_ms, int timeout_ms) +{ + struct device *dev = hisi_hba->dev; + int entries, entries_old = 0, time; + + for (time = 0; time < timeout_ms; time += delay_ms) { + entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT); + if (entries == entries_old) + break; + + entries_old = entries; + msleep(delay_ms); + } + + dev_dbg(dev, "wait commands complete %dms\n", time); +} static struct scsi_host_template sht_v2_hw = { .name = DRV_NAME, @@ -3552,6 +3570,7 @@ static int write_gpio_v2_hw(struct hisi_hba *hisi_hba, u8 reg_type, .soft_reset = soft_reset_v2_hw, .get_phys_state = get_phys_state_v2_hw, .write_gpio = write_gpio_v2_hw, + .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v2_hw, .sht = &sht_v2_hw, }; diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 13d2134..dd5f542 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -92,6 +92,7 @@ #define SAS_ECC_INTR 0x1e8 #define SAS_ECC_INTR_MSK 0x1ec #define HGC_ERR_STAT_EN 0x238 +#define CQE_SEND_CNT 0x248 #define DLVRY_Q_0_BASE_ADDR_LO 0x260 #define DLVRY_Q_0_BASE_ADDR_HI 0x264 #define DLVRY_Q_0_DEPTH 0x268 @@ -2015,6 +2016,24 @@ static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type, return 0; } +static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba, + int delay_ms, int timeout_ms) +{ + struct device *dev = hisi_hba->dev; + int entries, entries_old = 0, time; + + for (time = 0; time < timeout_ms; time += delay_ms) { + entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT); + if (entries == entries_old) + break; + + entries_old = entries; + msleep(delay_ms); + } + + dev_dbg(dev, "wait commands complete %dms\n", time); +} + static struct scsi_host_template sht_v3_hw = { .name = DRV_NAME, .module = THIS_MODULE, @@ -2063,6 +2082,7 @@ static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type, .get_phys_state = get_phys_state_v3_hw, .get_events = phy_get_events_v3_hw, .write_gpio = write_gpio_v3_hw, + .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw, }; static struct Scsi_Host * From patchwork Mon May 21 10:09:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 136439 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp119564lji; 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[209.132.180.67]) by mx.google.com with ESMTP id v24-v6si14404829pfj.292.2018.05.21.03.12.15; Mon, 21 May 2018 03:12:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-scsi-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-scsi-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751537AbeEUKMO (ORCPT + 1 other); Mon, 21 May 2018 06:12:14 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:55809 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752668AbeEUKLr (ORCPT ); Mon, 21 May 2018 06:11:47 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 6A38A2A25E120; Mon, 21 May 2018 18:11:40 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.382.0; Mon, 21 May 2018 18:11:32 +0800 From: John Garry To: , CC: , , , Xiaofei Tan , "John Garry" Subject: [PATCH 10/13] scsi: hisi_sas: Add v2 hw force PHY function for internal ATA command Date: Mon, 21 May 2018 18:09:22 +0800 Message-ID: <1526897365-228549-11-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1526897365-228549-1-git-send-email-john.garry@huawei.com> References: <1526897365-228549-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-scsi-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org From: Xiaofei Tan This patch adds an force PHY function for internal ATA command for v2 hw. Because there is an SoC bug of v2 hw, and need send an IO through each PHY of a port to workaround a bug which occurs after a controller reset. This force PHY function will be used in the later patch. Signed-off-by: Xiaofei Tan Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas.h | 2 ++ drivers/scsi/hisi_sas/hisi_sas_v2_hw.c | 11 +++++++++++ 2 files changed, 13 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas.h b/drivers/scsi/hisi_sas/hisi_sas.h index 60bd652..9400824 100644 --- a/drivers/scsi/hisi_sas/hisi_sas.h +++ b/drivers/scsi/hisi_sas/hisi_sas.h @@ -180,6 +180,8 @@ struct hisi_sas_device { }; struct hisi_sas_tmf_task { + int force_phy; + int phy_id; u8 tmf; u16 tag_of_task_to_be_managed; }; diff --git a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c index fafb3f1..369ef7e 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v2_hw.c @@ -296,6 +296,10 @@ #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) #define CMD_HDR_TLR_CTRL_OFF 6 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF) +#define CMD_HDR_PHY_ID_OFF 8 +#define CMD_HDR_PHY_ID_MSK (0x1ff << CMD_HDR_PHY_ID_OFF) +#define CMD_HDR_FORCE_PHY_OFF 17 +#define CMD_HDR_FORCE_PHY_MSK (0x1 << CMD_HDR_FORCE_PHY_OFF) #define CMD_HDR_PORT_OFF 18 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF) #define CMD_HDR_PRIORITY_OFF 27 @@ -2512,6 +2516,7 @@ static void prep_ata_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; struct asd_sas_port *sas_port = device->port; struct hisi_sas_port *port = to_hisi_sas_port(sas_port); + struct hisi_sas_tmf_task *tmf = slot->tmf; u8 *buf_cmd; int has_data = 0, hdr_tag = 0; u32 dw1 = 0, dw2 = 0; @@ -2524,6 +2529,12 @@ static void prep_ata_v2_hw(struct hisi_hba *hisi_hba, else hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF); + if (tmf && tmf->force_phy) { + hdr->dw0 |= CMD_HDR_FORCE_PHY_MSK; + hdr->dw0 |= cpu_to_le32((1 << tmf->phy_id) + << CMD_HDR_PHY_ID_OFF); + } + /* dw1 */ switch (task->data_dir) { case DMA_TO_DEVICE: