From patchwork Tue May 22 16:34:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 136576 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1853937lji; Tue, 22 May 2018 09:35:09 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrZE6BHr3Ji+ZGwZ3qoJYLgzWtb74+LiuzYn+TAWgcUSEIkAMgza0e/4lG17fNrs/KUCO56 X-Received: by 2002:a17:902:145:: with SMTP id 63-v6mr25620675plb.332.1527006909055; Tue, 22 May 2018 09:35:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527006909; cv=none; d=google.com; s=arc-20160816; b=fNvzvP2xe4gpK2zQZAft1/3DGHqaKQo4fFzgYTcJnz0CWXbfCSQJUv+QfFcYVguvJP IZzCz94P9fdBzG3TvPxgjp3ifqChR+hEf1EmZbvB3s2OHpTdGEv6y5gc2NCA/0He/Eww fzWZwPbn7wYDv6A0EEhw6b/FlJXIfS4NZaOxoj4nr7RCayQhCvi/6wRuHH9tOyZwuuDf 3XmrECeitmx60SgEffU+lnEAoGSuD1Pfp3RkYaJnHSSFqYPITHhL3OeHrJK4Nb0Ae+5H khdDxXoI7vZzwPxtjVdZuhtBm4PWmeEnjtlPzc0Io5NvaZJI7AwLxhPVaDaeh2KuWEFA OL1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=NPYLQfXofHaK7PFZW+1cFNnzh5u8IfS8PjyeGzazwyY=; b=xeQ1ZKjR2AKm44AuKGCAPhX6IZ4CpZTxtq3LpvwTj9ZbR7Q/hSiZuC7NOIl9utZqNE Whwz7UkCHowkQNvK4UPvRAqYFJWQvkd+wAEv7KwKVObrbzyh3P2K2q2JpyRAPMnM6GnM 66UR+99GIFSywY4JhVDwOMTzmCoZ1rFyJcDO/nHIRN4pAD/k1QuXaH4d0/PlNl5sczfw qQOOqRMYQMaoqYkCe/Klub+74IEhLoWctBdkS2aYROyBqYVyJ9tazhQzl2jRCduF9gO9 wqliPU/0ewvuXkTLzEAVT3V89/hMQXYnC7El1ppwmCZ2dvYx5UEisxVzVYa8uclE8jwl AfPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=sKYBJVpM; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b125-v6si10064652pga.536.2018.05.22.09.35.08; Tue, 22 May 2018 09:35:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=sKYBJVpM; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751629AbeEVQfG (ORCPT + 5 others); Tue, 22 May 2018 12:35:06 -0400 Received: from mail-wr0-f195.google.com ([209.85.128.195]:44976 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751278AbeEVQfD (ORCPT ); Tue, 22 May 2018 12:35:03 -0400 Received: by mail-wr0-f195.google.com with SMTP id y15-v6so21321753wrg.11 for ; Tue, 22 May 2018 09:35:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Csr+OAI9fWstE4dhd2Fjfc+mlFPfu3HUaFEpI4ql6zg=; b=sKYBJVpMyg4WYawbTs7jtAzIhHEFW3Wlpe5cOiTqOj1lJ8gXeXMHISEsjKbP50fOVA LbIbNXIxbUC4D2pl6RaUjtpKrTISa3bp49fzOYA2gI9UjCoqovyRsnTEF81YG0rYawG3 ETiJJy53fgj8imYJHyIu1RGZfJmP/ukvF/2ny3+feGcRYfo/81xsiASc8VeNx7Uxg8yR MD4SI6R/vjumUzklqNgUYpUtpxg6oA1XeaFiC+dSfl8ICb6PYRHMY37bw6N8xMEwcdEJ 6rYHO09FXvpF/ZJEJPRQJf2kEz275kL+rchjde+r1EgpoqwjUU3YalT22Xvg2FDBBx2j rzaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Csr+OAI9fWstE4dhd2Fjfc+mlFPfu3HUaFEpI4ql6zg=; b=H1uCU04Ov0zPsXa3uSYFDPWYzoc5rTWHYteMuxCQmZwSBJsznAUx2oNSr53wjgxNyS yr70BRJdRU7B3pFLLmb4kqGdhtrbTN5uxCLf41zhodqcnYRHU4k1BFBSWJGtueePMATA LgGclHQBKqzM9kG44BqBZclOCILGcuPcGHA5ftIpzabzIbYzlinyRcCpeW0A/AWwtFS7 gflFtJMCrzw4ybkKTfiSQoWpiUeeB+NJLVXegqD/3h96LVAokWc8QHx3aGVlaGPLS7zp jYLnhWYSGNas4nADP0vC6BkI7zaEyYukLpzI8obC8bI70KASFyDWd1ZUN534+PtERZfw EWNg== X-Gm-Message-State: ALKqPwfdlrgbgEYTeAkVBR8IwK561MJn1jcMt4gnda3jZE2FR3dADXbA i3KBbmZp3T1kFAEtDvr4efFeng== X-Received: by 2002:adf:dc8b:: with SMTP id r11-v6mr1993116wrj.263.1527006902818; Tue, 22 May 2018 09:35:02 -0700 (PDT) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id h8-v6sm294062wmc.16.2018.05.22.09.35.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 22 May 2018 09:35:02 -0700 (PDT) From: Jerome Brunet To: Neil Armstrong , Carlo Caione , Kevin Hilman Cc: Jerome Brunet , Michael Turquette , Stephen Boyd , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/6] clk: meson: clean-up meson clock configuration Date: Tue, 22 May 2018 18:34:52 +0200 Message-Id: <20180522163457.13834-2-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180522163457.13834-1-jbrunet@baylibre.com> References: <20180522163457.13834-1-jbrunet@baylibre.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Clean the dependencies in meson clock Kconfig. CLK_AMLOGIC should actually select CLK_REGMAP_MESON which it uses. Also, each platform should select CLK_AMLOGIC, so everything is properly turned on when the platform Kconfig enable each configuration flag Acked-by: Neil Armstrong Signed-off-by: Jerome Brunet --- drivers/clk/meson/Kconfig | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) -- 2.14.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 815659eebea3..9d00809f07fc 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -1,13 +1,14 @@ config COMMON_CLK_AMLOGIC bool - depends on OF depends on ARCH_MESON || COMPILE_TEST + select COMMON_CLK_REGMAP_MESON config COMMON_CLK_MESON_AO bool depends on OF depends on ARCH_MESON || COMPILE_TEST select COMMON_CLK_REGMAP_MESON + select RESET_CONTROLLER config COMMON_CLK_REGMAP_MESON bool @@ -15,9 +16,8 @@ config COMMON_CLK_REGMAP_MESON config COMMON_CLK_MESON8B bool - depends on COMMON_CLK_AMLOGIC + select COMMON_CLK_AMLOGIC select RESET_CONTROLLER - select COMMON_CLK_REGMAP_MESON help Support for the clock controller on AmLogic S802 (Meson8), S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you @@ -25,10 +25,8 @@ config COMMON_CLK_MESON8B config COMMON_CLK_GXBB bool - depends on COMMON_CLK_AMLOGIC - select RESET_CONTROLLER + select COMMON_CLK_AMLOGIC select COMMON_CLK_MESON_AO - select COMMON_CLK_REGMAP_MESON select MFD_SYSCON help Support for the clock controller on AmLogic S905 devices, aka gxbb. @@ -36,10 +34,8 @@ config COMMON_CLK_GXBB config COMMON_CLK_AXG bool - depends on COMMON_CLK_AMLOGIC - select RESET_CONTROLLER + select COMMON_CLK_AMLOGIC select COMMON_CLK_MESON_AO - select COMMON_CLK_REGMAP_MESON select MFD_SYSCON help Support for the clock controller on AmLogic A113D devices, aka axg. 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Tue, 22 May 2018 09:35:03 -0700 (PDT) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id h8-v6sm294062wmc.16.2018.05.22.09.35.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 22 May 2018 09:35:03 -0700 (PDT) From: Jerome Brunet To: Neil Armstrong , Carlo Caione , Kevin Hilman Cc: Jerome Brunet , Michael Turquette , Stephen Boyd , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/6] clk: meson: add clk-phase clock driver Date: Tue, 22 May 2018 18:34:53 +0200 Message-Id: <20180522163457.13834-3-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180522163457.13834-1-jbrunet@baylibre.com> References: <20180522163457.13834-1-jbrunet@baylibre.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a driver based meson clk-regmap to control clock phase on amlogic SoCs Acked-by: Neil Armstrong Signed-off-by: Jerome Brunet --- drivers/clk/meson/Makefile | 1 + drivers/clk/meson/clk-phase.c | 63 +++++++++++++++++++++++++++++++++++++++++++ drivers/clk/meson/clkc.h | 8 ++++++ 3 files changed, 72 insertions(+) create mode 100644 drivers/clk/meson/clk-phase.c -- 2.14.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index d0d13aeb369a..162e4a6f5c55 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -3,6 +3,7 @@ # obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o +obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-phase.o obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o diff --git a/drivers/clk/meson/clk-phase.c b/drivers/clk/meson/clk-phase.c new file mode 100644 index 000000000000..cba43748ce3d --- /dev/null +++ b/drivers/clk/meson/clk-phase.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2018 BayLibre, SAS. + * Author: Jerome Brunet + */ + +#include +#include "clkc.h" + +#define phase_step(_width) (360 / (1 << (_width))) + +static inline struct meson_clk_phase_data * +meson_clk_phase_data(struct clk_regmap *clk) +{ + return (struct meson_clk_phase_data *)clk->data; +} + +int meson_clk_degrees_from_val(unsigned int val, unsigned int width) +{ + return phase_step(width) * val; +} +EXPORT_SYMBOL_GPL(meson_clk_degrees_from_val); + +unsigned int meson_clk_degrees_to_val(int degrees, unsigned int width) +{ + unsigned int val = DIV_ROUND_CLOSEST(degrees, phase_step(width)); + + /* + * This last calculation is here for cases when degrees is rounded + * to 360, in which case val == (1 << width). + */ + return val % (1 << width); +} +EXPORT_SYMBOL_GPL(meson_clk_degrees_to_val); + +static int meson_clk_phase_get_phase(struct clk_hw *hw) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); + unsigned int val; + + val = meson_parm_read(clk->map, &phase->ph); + + return meson_clk_degrees_from_val(val, phase->ph.width); +} + +static int meson_clk_phase_set_phase(struct clk_hw *hw, int degrees) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_phase_data *phase = meson_clk_phase_data(clk); + unsigned int val; + + val = meson_clk_degrees_to_val(degrees, phase->ph.width); + meson_parm_write(clk->map, &phase->ph, val); + + return 0; +} + +const struct clk_ops meson_clk_phase_ops = { + .get_phase = meson_clk_phase_get_phase, + .set_phase = meson_clk_phase_set_phase, +}; +EXPORT_SYMBOL_GPL(meson_clk_phase_ops); diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index 2fb084330ee9..fd520ccdd1be 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -96,6 +96,13 @@ struct meson_clk_audio_div_data { u8 flags; }; +struct meson_clk_phase_data { + struct parm ph; +}; + +int meson_clk_degrees_from_val(unsigned int val, unsigned int width); +unsigned int meson_clk_degrees_to_val(int degrees, unsigned int width); + #define MESON_GATE(_name, _reg, _bit) \ struct clk_regmap _name = { \ .data = &(struct clk_regmap_gate_data){ \ @@ -119,5 +126,6 @@ extern const struct clk_ops meson_clk_mpll_ro_ops; extern const struct clk_ops meson_clk_mpll_ops; extern const struct clk_ops meson_clk_audio_divider_ro_ops; extern const struct clk_ops meson_clk_audio_divider_ops; +extern const struct clk_ops meson_clk_phase_ops; #endif /* __CLKC_H */ From patchwork Tue May 22 16:34:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 136578 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1854067lji; Tue, 22 May 2018 09:35:15 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrA/TCCzmOceoGRPaq4gZPa89EpLFgVexWnxUuzAGfxyh4TtK30Gyd5h8cdqbFYbZZILJB2 X-Received: by 2002:a62:3a94:: with SMTP id v20-v6mr25021303pfj.90.1527006915132; Tue, 22 May 2018 09:35:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527006915; cv=none; d=google.com; s=arc-20160816; b=tXr5ZZy3IKHvLXWd71uQGHT2DvR6ZOyn8sTNDMwuxYm862Pd96pmfWV2Do5VPRChnl cULL6zqhIQ/uFWbPcNgtQplmDiQSjuT7YOmU4MlnJ6H2TwJtFKoeDe1hcq8r+Xyab8Ja 0XcHkLVD7Ixi2O6RebZiRwOTtNREqMPwSD8n4zt1zgKg40XJH0ZGjiSYfjA509PRKohd Var/zvCj0FwLUvciFK/YWkfjEXPRPgS2osr04Vfj/a8RVnCr7dGFcq16ALhU/VCy7xTi of7+IuMe/xRxdyEiqVziCF+QUilr7bTJTRPUayiug5JdXcCoSYHGDDFsi7xr+AEWmczv XXew== ARC-Message-Signature: i=1; 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The sclk divider accumulates specific features which make the generic divider unsuitable to control it: - zero based divider (div = val + 1), but zero value gates the clock, so minimum divider value is 2. - lrclk variant may adjust the duty cycle depending the divider value and the 'hi' value. Acked-by: Neil Armstrong Signed-off-by: Jerome Brunet --- drivers/clk/meson/Makefile | 2 +- drivers/clk/meson/clkc-audio.h | 8 ++ drivers/clk/meson/sclk-div.c | 243 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 252 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/meson/sclk-div.c -- 2.14.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 74ec070b0974..1574e3f0de5c 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -4,7 +4,7 @@ obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-phase.o -obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o +obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o sclk-div.o obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o diff --git a/drivers/clk/meson/clkc-audio.h b/drivers/clk/meson/clkc-audio.h index 286ff1201258..0a7c157ebf81 100644 --- a/drivers/clk/meson/clkc-audio.h +++ b/drivers/clk/meson/clkc-audio.h @@ -15,6 +15,14 @@ struct meson_clk_triphase_data { struct parm ph2; }; +struct meson_sclk_div_data { + struct parm div; + struct parm hi; + unsigned int cached_div; + struct clk_duty cached_duty; +}; + extern const struct clk_ops meson_clk_triphase_ops; +extern const struct clk_ops meson_sclk_div_ops; #endif /* __MESON_CLKC_AUDIO_H */ diff --git a/drivers/clk/meson/sclk-div.c b/drivers/clk/meson/sclk-div.c new file mode 100644 index 000000000000..bc64019b8eeb --- /dev/null +++ b/drivers/clk/meson/sclk-div.c @@ -0,0 +1,243 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2018 BayLibre, SAS. + * Author: Jerome Brunet + * + * Sample clock generator divider: + * This HW divider gates with value 0 but is otherwise a zero based divider: + * + * val >= 1 + * divider = val + 1 + * + * The duty cycle may also be set for the LR clock variant. The duty cycle + * ratio is: + * + * hi = [0 - val] + * duty_cycle = (1 + hi) / (1 + val) + */ + +#include "clkc-audio.h" + +static inline struct meson_sclk_div_data * +meson_sclk_div_data(struct clk_regmap *clk) +{ + return (struct meson_sclk_div_data *)clk->data; +} + +static int sclk_div_maxval(struct meson_sclk_div_data *sclk) +{ + return (1 << sclk->div.width) - 1; +} + +static int sclk_div_maxdiv(struct meson_sclk_div_data *sclk) +{ + return sclk_div_maxval(sclk) + 1; +} + +static int sclk_div_getdiv(struct clk_hw *hw, unsigned long rate, + unsigned long prate, int maxdiv) +{ + int div = DIV_ROUND_CLOSEST_ULL((u64)prate, rate); + + return clamp(div, 2, maxdiv); +} + +static int sclk_div_bestdiv(struct clk_hw *hw, unsigned long rate, + unsigned long *prate, + struct meson_sclk_div_data *sclk) +{ + struct clk_hw *parent = clk_hw_get_parent(hw); + int bestdiv = 0, i; + unsigned long maxdiv, now, parent_now; + unsigned long best = 0, best_parent = 0; + + if (!rate) + rate = 1; + + maxdiv = sclk_div_maxdiv(sclk); + + if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) + return sclk_div_getdiv(hw, rate, *prate, maxdiv); + + /* + * The maximum divider we can use without overflowing + * unsigned long in rate * i below + */ + maxdiv = min(ULONG_MAX / rate, maxdiv); + + for (i = 2; i <= maxdiv; i++) { + /* + * It's the most ideal case if the requested rate can be + * divided from parent clock without needing to change + * parent rate, so return the divider immediately. + */ + if (rate * i == *prate) + return i; + + parent_now = clk_hw_round_rate(parent, rate * i); + now = DIV_ROUND_UP_ULL((u64)parent_now, i); + + if (abs(rate - now) < abs(rate - best)) { + bestdiv = i; + best = now; + best_parent = parent_now; + } + } + + if (!bestdiv) + bestdiv = sclk_div_maxdiv(sclk); + else + *prate = best_parent; + + return bestdiv; +} + +static long sclk_div_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); + int div; + + div = sclk_div_bestdiv(hw, rate, prate, sclk); + + return DIV_ROUND_UP_ULL((u64)*prate, div); +} + +static void sclk_apply_ratio(struct clk_regmap *clk, + struct meson_sclk_div_data *sclk) +{ + unsigned int hi = DIV_ROUND_CLOSEST(sclk->cached_div * + sclk->cached_duty.num, + sclk->cached_duty.den); + + if (hi) + hi -= 1; + + meson_parm_write(clk->map, &sclk->hi, hi); +} + +static int sclk_div_set_duty_cycle(struct clk_hw *hw, + struct clk_duty *duty) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); + + if (MESON_PARM_APPLICABLE(&sclk->hi)) { + memcpy(&sclk->cached_duty, duty, sizeof(*duty)); + sclk_apply_ratio(clk, sclk); + } + + return 0; +} + +static int sclk_div_get_duty_cycle(struct clk_hw *hw, + struct clk_duty *duty) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); + int hi; + + if (!MESON_PARM_APPLICABLE(&sclk->hi)) { + duty->num = 1; + duty->den = 2; + return 0; + } + + hi = meson_parm_read(clk->map, &sclk->hi); + duty->num = hi + 1; + duty->den = sclk->cached_div; + return 0; +} + +static void sclk_apply_divider(struct clk_regmap *clk, + struct meson_sclk_div_data *sclk) +{ + if (MESON_PARM_APPLICABLE(&sclk->hi)) + sclk_apply_ratio(clk, sclk); + + meson_parm_write(clk->map, &sclk->div, sclk->cached_div - 1); +} + +static int sclk_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); + unsigned long maxdiv = sclk_div_maxdiv(sclk); + + sclk->cached_div = sclk_div_getdiv(hw, rate, prate, maxdiv); + + if (clk_hw_is_enabled(hw)) + sclk_apply_divider(clk, sclk); + + return 0; +} + +static unsigned long sclk_div_recalc_rate(struct clk_hw *hw, + unsigned long prate) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); + + return DIV_ROUND_UP_ULL((u64)prate, sclk->cached_div); +} + +static int sclk_div_enable(struct clk_hw *hw) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); + + sclk_apply_divider(clk, sclk); + + return 0; +} + +static void sclk_div_disable(struct clk_hw *hw) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); + + meson_parm_write(clk->map, &sclk->div, 0); +} + +static int sclk_div_is_enabled(struct clk_hw *hw) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); + + if (meson_parm_read(clk->map, &sclk->div)) + return 1; + + return 0; +} + +static void sclk_div_init(struct clk_hw *hw) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); + unsigned int val; + + val = meson_parm_read(clk->map, &sclk->div); + + /* if the divider is initially disabled, assume max */ + if (!val) + sclk->cached_div = sclk_div_maxdiv(sclk); + else + sclk->cached_div = val + 1; + + sclk_div_get_duty_cycle(hw, &sclk->cached_duty); +} + +const struct clk_ops meson_sclk_div_ops = { + .recalc_rate = sclk_div_recalc_rate, + .round_rate = sclk_div_round_rate, + .set_rate = sclk_div_set_rate, + .enable = sclk_div_enable, + .disable = sclk_div_disable, + .is_enabled = sclk_div_is_enabled, + .get_duty_cycle = sclk_div_get_duty_cycle, + .set_duty_cycle = sclk_div_set_duty_cycle, + .init = sclk_div_init, +}; +EXPORT_SYMBOL_GPL(meson_sclk_div_ops);