From patchwork Tue May 22 17:37:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 136583 Delivered-To: patches@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp1921376lji; Tue, 22 May 2018 10:37:15 -0700 (PDT) X-Google-Smtp-Source: AB8JxZojiPfxKXSXHZxiXNdJ1PZFfSYmVxIhEv0BaRmxzBDt1Hd5SeZ91bkB/5od10Gq7+lFu9Fq X-Received: by 2002:a1c:bf52:: with SMTP id p79-v6mr1877653wmf.43.1527010635800; Tue, 22 May 2018 10:37:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527010635; cv=none; d=google.com; s=arc-20160816; b=HrGuTP6ci4bi/f6A897oogRaeZ9MiLs+4Th6HPK1klJfQ+32ycw3wMW1vo0EFXt46K ts/PHk4itb8+ykBa77HxIZWtuYwEG3rP0ceBwWyir+HPhA9QN+1QZnxWB1G9J4WyIGh/ FbQiDZv1AZLf7gGyJk1LepUlmYbyUBEsRtIoWnWD+Xt68f6KFhQ4U9ndxYYAnvuppgQa 08qEQzRlOG7wVD3WqPrE6QqG01zhYsyCUy+osv7ayUoyVk+H6KVvxVuvdq07O1f+yLxQ Sj1Tfzl4eIEaZLZVBj44ePhpHXh5hGeIpYxlgcw86r3aHrgfU1Ocn8IffUeA5DYsgQ3Q T7jw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=8JK+XveI07mK4wmG1xaMkelgEA9gBRO0WD5PtcJefr0=; b=RZpeG6yVk2oEpLoBs65ctUNlHVKAPtOgz5MUQlmleWjFQ3u+HXliZ2D4EGksSqiNdb Zs6iGRhUaR1gDcgzOH2dqchNLth4aUQbfX/wF0t3BhNeYEKVXQ4mnzvH/VVwmgF/vgTx 8z78+I34VqRHwutm4u4LpnJMe6hLHJZoSyd9UXs4amCsKCIygGsnngR0Wn98nT4yPR1M fIUu+jxy1s4MJqqi+1jsXl39wnXu81qjOvOWaR8iKcYhY7m3vgr0RB/lQMBP3uQoZiMA CI798hhn2jgfEDGmZRDpLbfCWpkuHmI4wPhwz89UFqdVtnXTJ0DfFJQD5VtHK3BdmG9f eUhw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by mx.google.com with ESMTPS id o204-v6si290900wmb.209.2018.05.22.10.37.15 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 22 May 2018 10:37:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) client-ip=2001:8b0:1d0::2; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::2 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fLBDm-00018u-Lx; Tue, 22 May 2018 18:37:14 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: patches@linaro.org, =?utf-8?q?C=C3=A9dric_Le_Goater?= Subject: [PATCH] Correct CPACR reset value for v7 cores Date: Tue, 22 May 2018 18:37:13 +0100 Message-Id: <20180522173713.26282-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.0 MIME-Version: 1.0 In commit f0aff255700 we made cpacr_write() enforce that some CPACR bits are RAZ/WI and some are RAO/WI for ARMv7 cores. Unfortunately we forgot to also update the register's reset value. The effect was that (a) a guest that read CPACR on reset would not see ones in the RAO bits, and (b) if you did a migration before the guest did a write to the CPACR then the migration would fail because the destination would enforce the RAO bits and then complain that they didn't match the zero value from the source. Implement reset for the CPACR using a custom reset function that just calls cpacr_write(), to avoid having to duplicate the logic for which bits are RAO. This bug would affect migration for TCG CPUs which are ARMv7 with VFP but without one of Neon or VFPv3. Reported-by: Cédric Le Goater Signed-off-by: Peter Maydell --- This is sufficient that a save-and-reload while the romulus-bmc machine is in the bootloader will work. On the other hand if I do a save-and-reload after the kernel has started booting then we get the classic "guest hang after reload", so some state is still not being transferred somewhere (probably in a device in the machine model?) --- target/arm/helper.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) -- 2.17.0 Tested-by: Cédric Le Goater diff --git a/target/arm/helper.c b/target/arm/helper.c index c0f739972e..6023bf6046 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -863,6 +863,14 @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, env->cp15.cpacr_el1 = value; } +static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* Call cpacr_write() so that we reset with the correct RAO bits set + * for our CPU features. + */ + cpacr_write(env, ri, 0); +} + static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { @@ -920,7 +928,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] = { { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1), - .resetvalue = 0, .writefn = cpacr_write }, + .resetfn = cpacr_reset, .writefn = cpacr_write }, REGINFO_SENTINEL };