From patchwork Thu May 24 10:59:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 136735 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp2039567lji; Thu, 24 May 2018 03:59:40 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqzAvvbII+l/m4eEVsaPlB641dIWw5nO2teuuam1zY8h92OastBzd4Fzqea+Q1Vnxzjff7P X-Received: by 2002:a63:b34e:: with SMTP id x14-v6mr5490824pgt.70.1527159579934; Thu, 24 May 2018 03:59:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527159579; cv=none; d=google.com; s=arc-20160816; b=Q3BV+F8VUQ/nAZ3E2i51UVfGs+W8hDcHqbeqrIPpPWrCNnEeaCWlCLH8Rr7NXbibKn kSYhLDju5r2zwVqiT5z5mUod4iXXbsqA689KadtUIU84JcJPOSTiyYunbuE6inUloZW1 AQgRrWP5HTKVQy8DpHJnzHI5c0GPmmYHlmACxdSp/cX2mk/dxxE33DIlPqqLKYzTYr9N l8XuFKWjDNWdWyYT8ozVWHqOjp3ftm56xel9y1U3z4HCECaocXcFiW7h27Cbzy/dEklE FtIK2umYoScSuuU5Eocs82mwFqRgk0f0fHS7n2ORVgYO9iP8pbh/dOwkV9r2TzgLSa89 wFyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=uYayreNaCexijW8oKgvS7R7gvZQf9Kw/3zESbbf2Yx0=; b=RWczJ9V2wvQO8a3R5IAPopsE0Za7jyIvZ85rbTxLhn6KhI0PdXAuotdRyICqjU+1Zd 6nRJJD+ZwkWApC4L6CE/xublMXyItkrRTCjT8oXjSWLF3uJzDKZ+4/HuOFMjKp/P5rjt vESJDU5/QiOq1jJ1V3SoYz1NjwIeDd1Omie3aksGzOYefIoTfjQfribsgMNByS5ex2+1 pQiogbI8kFg9d3xrRBe+zZHbl8O/9Yp0QPhQpE+dXyWZQdjSjMNxyvS2G5/C9b/QpYzm KJpLHsbpvGnWYOD8GZ6cJzIHMNZFQnxNtpEtns0drStN0JZQfSjqmruRM6qkXnyuN/gl u1kA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r8-v6si1537324plj.40.2018.05.24.03.59.39; Thu, 24 May 2018 03:59:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1032783AbeEXK7h (ORCPT + 30 others); Thu, 24 May 2018 06:59:37 -0400 Received: from foss.arm.com ([217.140.101.70]:40924 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030261AbeEXK7T (ORCPT ); Thu, 24 May 2018 06:59:19 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7EF3415AD; Thu, 24 May 2018 03:59:19 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 4F6B03F5C1; Thu, 24 May 2018 03:59:19 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 5374D1AE0F4E; Thu, 24 May 2018 11:59:47 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon , Yoshinori Sato Subject: [PATCH 1/9] h8300: Don't include linux/kernel.h in asm/atomic.h Date: Thu, 24 May 2018 11:59:38 +0100 Message-Id: <1527159586-8578-2-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1527159586-8578-1-git-send-email-will.deacon@arm.com> References: <1527159586-8578-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org linux/kernel.h isn't needed by asm/atomic.h and will result in circular dependencies when the asm-generic atomic bitops are built around the tomic_long_t interface. Remove the broad include and replace it with linux/compiler.h for READ_ONCE etc and asm/irqflags.h for arch_local_irq_save etc. Cc: Yoshinori Sato Signed-off-by: Will Deacon --- arch/h8300/include/asm/atomic.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.1.4 diff --git a/arch/h8300/include/asm/atomic.h b/arch/h8300/include/asm/atomic.h index 941e7554e886..b174dec099bf 100644 --- a/arch/h8300/include/asm/atomic.h +++ b/arch/h8300/include/asm/atomic.h @@ -2,8 +2,10 @@ #ifndef __ARCH_H8300_ATOMIC__ #define __ARCH_H8300_ATOMIC__ +#include #include #include +#include /* * Atomic operations that C can't guarantee us. Useful for @@ -15,8 +17,6 @@ #define atomic_read(v) READ_ONCE((v)->counter) #define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i)) -#include - #define ATOMIC_OP_RETURN(op, c_op) \ static inline int atomic_##op##_return(int i, atomic_t *v) \ { \ From patchwork Thu May 24 10:59:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 136733 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp2039482lji; Thu, 24 May 2018 03:59:34 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrdxO00hu4NBRW8aSXFmpszcu2Nd8BirLKoYs4a9kPfnklwd2H8ndyWJXnIDPYqbIBfFVsk X-Received: by 2002:a17:902:988b:: with SMTP id s11-v6mr6849419plp.304.1527159574821; Thu, 24 May 2018 03:59:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527159574; cv=none; d=google.com; s=arc-20160816; b=gGTnAeG7BohYRMelN9/9PpqMplH6inCtOPiIBv4b/NwUM33xK7gbauVHYs5g10E024 nU6AwwuRzGmZY97AyU5+knbyILs8yXqNt3gGy8EOugQxug+XimQ1Kr/vU/FjWv9uKqAf pgVTgTzOHdAcvmLAc6hiurMcPmdHltd5A9uy7SyJafE7OSwrJASm5OBFqZOzEsur3wcB 1wSMLZR6sxobhjdjlzoim5nATOSzvZc75DuD2cHn04MW3qFPrjqwZFgNHaSeoME1joTG L1DPw3lVVbi9XZJmSwyjd96ulN8rNvHfH3XZops97SjI6iBjyLfGDk4HgXUb27y0dMLb iFQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=KPoO3xkmTJNlaTbhFQlzQWdV0d+0c5MF04CUiFuVFTI=; b=YmPGieWwBVhoZsQhOnL+9Nal1nBJ+s7eR/EvCy5aYr6KPuJCPpbpjegpcTljzKXHs7 p4D0/fz8RullCGt/NE7UKoCaPnuAgBNT1sQddjKnYoMyL9ZLg+NNua5B2J96YVmMILYX dXBKuZyj2fRdGnqeqON0+6S+sGRYima0KiDJIc/uR26obZWOSIiiUpawvsvEB9o7/9QN 9kb4JGo4ue6wLZPOA8z+xPnDWD21i2vJgP0SRqpS7JjIQUF55/ne84rtWD0Ve0JyU9vl lFDMEOsPPtoBfgHnRmYzTWQbj+mjRdc2ov6Gsp5XUJbS9QILwjLmrFrtJ235d6m6i6NO ECxA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o1-v6si16338877pge.307.2018.05.24.03.59.34; Thu, 24 May 2018 03:59:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1032760AbeEXK7c (ORCPT + 30 others); Thu, 24 May 2018 06:59:32 -0400 Received: from foss.arm.com ([217.140.101.70]:40932 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030295AbeEXK7T (ORCPT ); Thu, 24 May 2018 06:59:19 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8FE8F165D; Thu, 24 May 2018 03:59:19 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 608393F762; Thu, 24 May 2018 03:59:19 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 6133C1AE372C; Thu, 24 May 2018 11:59:47 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [PATCH 2/9] m68k: Don't use asm-generic/bitops/lock.h Date: Thu, 24 May 2018 11:59:39 +0100 Message-Id: <1527159586-8578-3-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1527159586-8578-1-git-send-email-will.deacon@arm.com> References: <1527159586-8578-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org asm-generic/bitops/lock.h is shortly going to be built on top of the atomic_long_* API, which introduces a nasty circular dependency for m68k where linux/atomic.h pulls in linux/bitops.h via: linux/atomic.h asm/atomic.h linux/irqflags.h asm/irqflags.h linux/preempt.h asm/preempt.h asm-generic/preempt.h linux/thread_info.h asm/thread_info.h asm/page.h asm-generic/getorder.h linux/log2.h linux/bitops.h Since m68k isn't SMP and doesn't support ACQUIRE/RELEASE barriers, we can just define the lock bitops in terms of the atomic bitops in the asm/bitops.h header. Acked-by: Geert Uytterhoeven Signed-off-by: Will Deacon --- arch/m68k/include/asm/bitops.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- 2.1.4 diff --git a/arch/m68k/include/asm/bitops.h b/arch/m68k/include/asm/bitops.h index 93b47b1f6fb4..18193419f97d 100644 --- a/arch/m68k/include/asm/bitops.h +++ b/arch/m68k/include/asm/bitops.h @@ -515,12 +515,16 @@ static inline int __fls(int x) #endif +/* Simple test-and-set bit locks */ +#define test_and_set_bit_lock test_and_set_bit +#define clear_bit_unlock clear_bit +#define __clear_bit_unlock clear_bit_unlock + #include #include #include #include #include -#include #endif /* __KERNEL__ */ #endif /* _M68K_BITOPS_H */ From patchwork Thu May 24 10:59:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 136731 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp2039354lji; Thu, 24 May 2018 03:59:27 -0700 (PDT) X-Google-Smtp-Source: AB8JxZo0X4S0LiFg6f7VS9cKFxkJ2eHestilR52VQOjKnQWUQNKpepEnEp8WImbWJl4nv/bZ4AFY X-Received: by 2002:a17:902:aa4b:: with SMTP id c11-v6mr6873620plr.17.1527159567538; Thu, 24 May 2018 03:59:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527159567; cv=none; d=google.com; s=arc-20160816; b=qHuSj1QHRpW9m02PNM+69qWo6Cdbvv9UoPv/5pn2gygFXjug/FxONaiFto753CYRt7 7G1ynctE5r4AAw6sCLZN98dIbWGqjHW22cFJZoE4+oAmAVzciR/LPs7IDfqaHCsqQwRY begGHWLdzd1sVJ8zcNTsHKHaLGWfeojrPZMlQUHoFmI1ETh3Rqit0H0u9uhgbtExfjc2 dsFLjRvK8kvbAUXskT9H1uJThj1TYT6+gwaeg3eObnDQ1MkEa2gtMGAUa8CRArGa3n6J sCGk5h8ZpJAnmZc1lWVuwoGNrnUg3q1kq+UiukksLWLujm/0xo1CQIHKdA4hIwePZGWK ROtQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=dxsWqaY+cyvP9/Wn+QoATPyiIJKTrgv/4wVaFT6fg7E=; b=tbw5KDEBrzIk58Hj03Rwjo9YxskuCBsuXSlBAvzQFo5t7iuaHPF25EA2A7bGw7m/4l gGR6YGaEw8tlUHsPGn5CVHdzuisB98g+u/I666GJuD8VUwF9VByvQ+VxqyvUqoK7t347 aGY7sqNcyNHyrN4hbEd27C6laPaUReqKdgA5mruKxr51a90Mnrhp8k2eCOO+fO7qigwx K1bMN55/p0ByJ/Y1Cq8+zjihkc3FgOYRyfyaUBzRAYE008u1uB96fCZm8adK+FDLY0NX 4fEI17K+HkpVESRETlDf1mngztnjFecTKpwjiJ43Unu39W9pyqxQYjyd0SurW0+x4mx6 vt7w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d9-v6si16344978pga.192.2018.05.24.03.59.27; Thu, 24 May 2018 03:59:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1032738AbeEXK7Z (ORCPT + 30 others); Thu, 24 May 2018 06:59:25 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:40940 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030372AbeEXK7T (ORCPT ); Thu, 24 May 2018 06:59:19 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A15CE1688; Thu, 24 May 2018 03:59:19 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 720823F7B4; Thu, 24 May 2018 03:59:19 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 719121AE3856; Thu, 24 May 2018 11:59:47 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [PATCH 3/9] asm-generic: Move some macros from linux/bitops.h to a new bits.h file Date: Thu, 24 May 2018 11:59:40 +0100 Message-Id: <1527159586-8578-4-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1527159586-8578-1-git-send-email-will.deacon@arm.com> References: <1527159586-8578-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org In preparation for implementing the asm-generic atomic bitops in terms of atomic_long_*, we need to prevent asm/atomic.h implementations from pulling in linux/bitops.h. A common reason for this include is for the BITS_PER_BYTE definition, so move this and some other BIT and masking macros into a new header file, linux/bits.h Signed-off-by: Will Deacon --- include/linux/bitops.h | 22 +--------------------- include/linux/bits.h | 26 ++++++++++++++++++++++++++ 2 files changed, 27 insertions(+), 21 deletions(-) create mode 100644 include/linux/bits.h -- 2.1.4 diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 4cac4e1a72ff..af419012d77d 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -2,29 +2,9 @@ #ifndef _LINUX_BITOPS_H #define _LINUX_BITOPS_H #include +#include -#ifdef __KERNEL__ -#define BIT(nr) (1UL << (nr)) -#define BIT_ULL(nr) (1ULL << (nr)) -#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) -#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) -#define BIT_ULL_MASK(nr) (1ULL << ((nr) % BITS_PER_LONG_LONG)) -#define BIT_ULL_WORD(nr) ((nr) / BITS_PER_LONG_LONG) -#define BITS_PER_BYTE 8 #define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) -#endif - -/* - * Create a contiguous bitmask starting at bit position @l and ending at - * position @h. For example - * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000. - */ -#define GENMASK(h, l) \ - (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) - -#define GENMASK_ULL(h, l) \ - (((~0ULL) - (1ULL << (l)) + 1) & \ - (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) extern unsigned int __sw_hweight8(unsigned int w); extern unsigned int __sw_hweight16(unsigned int w); diff --git a/include/linux/bits.h b/include/linux/bits.h new file mode 100644 index 000000000000..2b7b532c1d51 --- /dev/null +++ b/include/linux/bits.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_BITS_H +#define __LINUX_BITS_H +#include + +#define BIT(nr) (1UL << (nr)) +#define BIT_ULL(nr) (1ULL << (nr)) +#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) +#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) +#define BIT_ULL_MASK(nr) (1ULL << ((nr) % BITS_PER_LONG_LONG)) +#define BIT_ULL_WORD(nr) ((nr) / BITS_PER_LONG_LONG) +#define BITS_PER_BYTE 8 + +/* + * Create a contiguous bitmask starting at bit position @l and ending at + * position @h. For example + * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000. + */ +#define GENMASK(h, l) \ + (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) + +#define GENMASK_ULL(h, l) \ + (((~0ULL) - (1ULL << (l)) + 1) & \ + (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) + +#endif /* __LINUX_BITS_H */ From patchwork Thu May 24 10:59:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 136732 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp2039424lji; Thu, 24 May 2018 03:59:31 -0700 (PDT) X-Google-Smtp-Source: AB8JxZplnGWksdjCZhJ7wpyPygC1bSyAbnuEzR5XYRDDDFD6qOMnrM2MqRAEOm/ZTP4f+z9XEIpQ X-Received: by 2002:a62:9c0d:: with SMTP id f13-v6mr6666781pfe.15.1527159571399; Thu, 24 May 2018 03:59:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527159571; cv=none; d=google.com; s=arc-20160816; b=OpF+5B6oEHYxg0qXSeGXEK3rUdSEx66vLzbQ18r+cQtqFizs1YCm5wYjh9gTvaw8bg Lr7mKsUc00kGuCqwjSdnZUHuCAV324RvKB6Gf7bEVqDDKGGePb+Ouza5fxCaBORxSsJD 6WLqZmqZHJC475jYxoOMOXfm9SgQ6FICR8wSoTj9vCYQa0mWUlF7P8ENlXDefcAZzp8j /A4qK+41J6x5ck2O76aZOXfLtkjR3UvhpaKqE//FzJE8nfJkb8kz7TsHhdwL4VAsljL6 3x2cFR6KgV7DcD7hl+/2P65tJcVsH5SS55yh6ZLpEJkif94pB7b27lplcwPupM2LfScW /OaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=xXZM+SI2dlCVbKrYLzQGoyA6pW2OyLL1pq3eXR+nMv8=; b=g3hqJ//Yvnt2ILTqbj1fbTJugHO9i6aPDHZOY2CeJdiWOstmLoyHtpz25qrO+RXf1p loAl8d0LFSn6ERuLPutMMvnjYpHDt3WNRF3YZc34kFNe6XKoIo16KclWNL00nMSLN7fu L4uVrSYbQ7kItJC/F0RlBl1h5HQy91uB0V8p6IXxA7mdPVgu8HABfRuUpFSYdYClvwcM hO+sHWE2fqUddF8qcllW4bs3TcL29IMJtvdyMTfaRdYJqjlhjoxC4K7rS8FFQgyUr7x2 iyYwHVCykWyB6B0N1WvC1QFKaMmOxChEro4ufJgUhw6Ms4kvBJzN1ZRtGoF+8vRRyb4J KTGQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d9-v6si16344978pga.192.2018.05.24.03.59.31; Thu, 24 May 2018 03:59:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1032748AbeEXK73 (ORCPT + 30 others); Thu, 24 May 2018 06:59:29 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:40958 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030373AbeEXK7U (ORCPT ); Thu, 24 May 2018 06:59:20 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B5AF3168F; Thu, 24 May 2018 03:59:19 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 865603F25D; Thu, 24 May 2018 03:59:19 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 83CEC1AE386A; Thu, 24 May 2018 11:59:47 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [PATCH 4/9] openrisc: Don't pull in all of linux/bitops.h in asm/cmpxchg.h Date: Thu, 24 May 2018 11:59:41 +0100 Message-Id: <1527159586-8578-5-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1527159586-8578-1-git-send-email-will.deacon@arm.com> References: <1527159586-8578-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The openrisc implementation of asm/cmpxchg.h pulls in linux/bitops.h so that it can refer to BITS_PER_BYTE. It also transitively relies on this pulling in linux/compiler.h for READ_ONCE. Replace the #include with linux/bits.h and linux/compiler.h Signed-off-by: Will Deacon --- arch/openrisc/include/asm/cmpxchg.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.1.4 diff --git a/arch/openrisc/include/asm/cmpxchg.h b/arch/openrisc/include/asm/cmpxchg.h index d29f7db53906..f9cd43a39d72 100644 --- a/arch/openrisc/include/asm/cmpxchg.h +++ b/arch/openrisc/include/asm/cmpxchg.h @@ -16,8 +16,9 @@ #ifndef __ASM_OPENRISC_CMPXCHG_H #define __ASM_OPENRISC_CMPXCHG_H +#include +#include #include -#include #define __HAVE_ARCH_CMPXCHG 1 From patchwork Thu May 24 10:59:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 136739 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp2043692lji; Thu, 24 May 2018 04:02:49 -0700 (PDT) X-Google-Smtp-Source: AB8JxZrCbFRf4MxCF4lKpGAHq2K0+wKozpUMmxmSam9Ql4KdvQB0vAGpZVI6IEKArem8ZTU6vApz X-Received: by 2002:a17:902:264:: with SMTP id 91-v6mr6803335plc.341.1527159769051; Thu, 24 May 2018 04:02:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527159769; cv=none; d=google.com; s=arc-20160816; b=rPzk+XRp3p70jJx5Fi1qYHMQ7cjza3SdjIzJht81Ps3BD76ktw3ItIacqn1G9UVAEQ coYQfT3SPWpxtk6fjA2WZdNi3SJSZyDp1JQSzGUK/+8SpiNJ/OA2nbmgPV6Vo5K4WrcD liKE3jgMuY0AnwOyKNOZwm768wCqwnQEDZRj7qnw6ZnmU7dS4qT/uP87bC05Cco+l6BL /1MeCmAR3OUxZhwndB3tB+Snw4n7ciH/0rmwtNyn3w0G/5ENMBJVwTOHfMdrJ+Xnq1VT kRPeKPdyozk3AGST8ekJnlCcMk2uSvh0Ca5zt3mcZL59cvwo6hQiE/bU7lM/9X7wtdTB /Tww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=Cc8BEwAhVFO5E0uxxh5DaP653Zwr8wKoE8TAsag6eVg=; b=CL6vYjSn62EjRuYVsEFUuvHrvTAYgBxHOLtqzin72lXY57k1F9v6ORDQC0XFN+VwxM J7LFHYxqnctXuoHXGrQkggLrQDrQNw7Xvgb6j351bLzhUuw9L6qGKaeJnMt9lIoR7nLP TUH56z5V218t/myAQTvdleLbH4kyrwHrzHexM/nXw4iYKHSv70WXcbemkwfphMgZGBrv k0ryPAiSSvIqH+IbWwmzbUTH/UbwSUY16kLxqBdvkVhmKdWJ1IQ4/uhGlbVKutkphK2f irfYEru8awx3Stae4Nkud4Ll3WC9FIb37QMZSfxiEzfsrrcd4h8pw9qUFzln6Pwy3H01 sW0A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id x32-v6si20519637pld.435.2018.05.24.04.02.48; Thu, 24 May 2018 04:02:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1032777AbeEXLCq (ORCPT + 30 others); Thu, 24 May 2018 07:02:46 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:40982 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1032476AbeEXK7V (ORCPT ); Thu, 24 May 2018 06:59:21 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 65A5B16A0; Thu, 24 May 2018 03:59:20 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 363B43F25D; Thu, 24 May 2018 03:59:20 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 982551AE38C3; Thu, 24 May 2018 11:59:47 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [PATCH 5/9] sh: Don't pull in all of linux/bitops.h in asm/cmpxchg-xchg.h Date: Thu, 24 May 2018 11:59:42 +0100 Message-Id: <1527159586-8578-6-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1527159586-8578-1-git-send-email-will.deacon@arm.com> References: <1527159586-8578-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The sh implementation of asm/cmpxchg-xchg.h pulls in linux/bitops.h so that it can refer to BITS_PER_BYTE. It also transitively relies on this pulling in linux/compiler.h for READ_ONCE. Replace the #include with linux/bits.h and linux/compiler.h Signed-off-by: Will Deacon --- arch/sh/include/asm/cmpxchg-xchg.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.1.4 diff --git a/arch/sh/include/asm/cmpxchg-xchg.h b/arch/sh/include/asm/cmpxchg-xchg.h index 1e881f5db659..593a9704782b 100644 --- a/arch/sh/include/asm/cmpxchg-xchg.h +++ b/arch/sh/include/asm/cmpxchg-xchg.h @@ -8,7 +8,8 @@ * This work is licensed under the terms of the GNU GPL, version 2. See the * file "COPYING" in the main directory of this archive for more details. */ -#include +#include +#include #include /* From patchwork Thu May 24 10:59:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 136740 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp2043755lji; Thu, 24 May 2018 04:02:52 -0700 (PDT) X-Google-Smtp-Source: AB8JxZo11CAUaTVeARu/M+nbqsGjBNEvF+8gczb24DCXh6FVTy8H/3DWH+OQ/Sz2hMfUlGxe1g/I X-Received: by 2002:a63:7904:: with SMTP id u4-v6mr5498724pgc.143.1527159771993; Thu, 24 May 2018 04:02:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527159771; cv=none; d=google.com; s=arc-20160816; b=CuRhEnIWIc0r3F3PyXJGHDoPMag30lFMFoqFWvgQZ5HheSr/QvvezEuhuVTMwadghX u03/YJchxU482hd8hxAgUoyMuWujOskJN12edZYgKXjaGzAbM4INrImUoJfIthmLozR2 tPhQJuQAAWlCrGJe1WO+5OIhMf7ibomlHAIDVHZsfjIAOf3DVKMgHX3arN3XCq6nEwzT zLWD/U58mkf9g3BpjhD7zaobNvhy60aYlaNI4b8RNi0iql/N6Tj/YckBl6yKtEda2uNj Hughfm+tvZDqIAMlATycooakfRbthGu03NZMLfg4npQ3l7yXgF/fr374PZJ3PlO+arRD 7x8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=VU+CpT7H3yMXqUbNbCnOpiD9JYKLiKAtQwnyOdZDVVg=; b=pSB5+Sl1lDSR4SxOfxh3dPCIMafFN5FhjGf3+fSt0+hoWjjUcTaKUaxZHTmdkMtWuH sh8N+S8er4XCf83T8TTkvzMLMTybxot6YFc2JxD3Yh9JGg+v7ADnqosyyrTbZ0LcDpYw NiyuzGePZw0xy2udNZZoUSHARAYCcfGbCY0NL8KNCT1VRDBEms516mL50kqgb6w3um7I 8JkHa8cUw2sWK0/0MhTVYJkZlv8VGYuWgSSgXu5PgvawzA3uvRYJ8snv2oLn+hnyvTr3 63oimuALxH+eC0bjhwQN6ixZdOkqJqU0lkDBpEvihvi7jVyOwYqw7M4xOMqFacrNBfbF lK7g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f11-v6si16691066pgr.275.2018.05.24.04.02.51; Thu, 24 May 2018 04:02:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1032694AbeEXLCu (ORCPT + 30 others); Thu, 24 May 2018 07:02:50 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:40984 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030262AbeEXK7V (ORCPT ); Thu, 24 May 2018 06:59:21 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6FF9316A3; Thu, 24 May 2018 03:59:20 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 3F4183F5C1; Thu, 24 May 2018 03:59:20 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id AC87E1AE38D9; Thu, 24 May 2018 11:59:47 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [PATCH 6/9] asm-generic/bitops/atomic.h: Rewrite using atomic_fetch_* Date: Thu, 24 May 2018 11:59:43 +0100 Message-Id: <1527159586-8578-7-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1527159586-8578-1-git-send-email-will.deacon@arm.com> References: <1527159586-8578-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The atomic bitops can actually be implemented pretty efficiently using the atomic_fetch_* ops, rather than explicit use of spinlocks. Cc: Peter Zijlstra Cc: Ingo Molnar Signed-off-by: Will Deacon --- include/asm-generic/bitops/atomic.h | 188 +++++++----------------------------- 1 file changed, 33 insertions(+), 155 deletions(-) -- 2.1.4 diff --git a/include/asm-generic/bitops/atomic.h b/include/asm-generic/bitops/atomic.h index 04deffaf5f7d..bca92586c2f6 100644 --- a/include/asm-generic/bitops/atomic.h +++ b/include/asm-generic/bitops/atomic.h @@ -2,189 +2,67 @@ #ifndef _ASM_GENERIC_BITOPS_ATOMIC_H_ #define _ASM_GENERIC_BITOPS_ATOMIC_H_ -#include -#include - -#ifdef CONFIG_SMP -#include -#include /* we use L1_CACHE_BYTES */ - -/* Use an array of spinlocks for our atomic_ts. - * Hash function to index into a different SPINLOCK. - * Since "a" is usually an address, use one spinlock per cacheline. - */ -# define ATOMIC_HASH_SIZE 4 -# define ATOMIC_HASH(a) (&(__atomic_hash[ (((unsigned long) a)/L1_CACHE_BYTES) & (ATOMIC_HASH_SIZE-1) ])) - -extern arch_spinlock_t __atomic_hash[ATOMIC_HASH_SIZE] __lock_aligned; - -/* Can't use raw_spin_lock_irq because of #include problems, so - * this is the substitute */ -#define _atomic_spin_lock_irqsave(l,f) do { \ - arch_spinlock_t *s = ATOMIC_HASH(l); \ - local_irq_save(f); \ - arch_spin_lock(s); \ -} while(0) - -#define _atomic_spin_unlock_irqrestore(l,f) do { \ - arch_spinlock_t *s = ATOMIC_HASH(l); \ - arch_spin_unlock(s); \ - local_irq_restore(f); \ -} while(0) - - -#else -# define _atomic_spin_lock_irqsave(l,f) do { local_irq_save(f); } while (0) -# define _atomic_spin_unlock_irqrestore(l,f) do { local_irq_restore(f); } while (0) -#endif +#include +#include +#include /* - * NMI events can occur at any time, including when interrupts have been - * disabled by *_irqsave(). So you can get NMI events occurring while a - * *_bit function is holding a spin lock. If the NMI handler also wants - * to do bit manipulation (and they do) then you can get a deadlock - * between the original caller of *_bit() and the NMI handler. - * - * by Keith Owens + * Implementation of atomic bitops using atomic-fetch ops. + * See Documentation/atomic_bitops.txt for details. */ -/** - * set_bit - Atomically set a bit in memory - * @nr: the bit to set - * @addr: the address to start counting from - * - * This function is atomic and may not be reordered. See __set_bit() - * if you do not require the atomic guarantees. - * - * Note: there are no guarantees that this function will not be reordered - * on non x86 architectures, so if you are writing portable code, - * make sure not to rely on its reordering guarantees. - * - * Note that @nr may be almost arbitrarily large; this function is not - * restricted to acting on a single-word quantity. - */ -static inline void set_bit(int nr, volatile unsigned long *addr) +static inline void set_bit(unsigned int nr, volatile unsigned long *p) { - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long flags; - - _atomic_spin_lock_irqsave(p, flags); - *p |= mask; - _atomic_spin_unlock_irqrestore(p, flags); + p += BIT_WORD(nr); + atomic_long_fetch_or_relaxed(BIT_MASK(nr), (atomic_long_t *)p); } -/** - * clear_bit - Clears a bit in memory - * @nr: Bit to clear - * @addr: Address to start counting from - * - * clear_bit() is atomic and may not be reordered. However, it does - * not contain a memory barrier, so if it is used for locking purposes, - * you should call smp_mb__before_atomic() and/or smp_mb__after_atomic() - * in order to ensure changes are visible on other processors. - */ -static inline void clear_bit(int nr, volatile unsigned long *addr) +static inline void clear_bit(unsigned int nr, volatile unsigned long *p) { - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long flags; - - _atomic_spin_lock_irqsave(p, flags); - *p &= ~mask; - _atomic_spin_unlock_irqrestore(p, flags); + p += BIT_WORD(nr); + atomic_long_fetch_andnot_relaxed(BIT_MASK(nr), (atomic_long_t *)p); } -/** - * change_bit - Toggle a bit in memory - * @nr: Bit to change - * @addr: Address to start counting from - * - * change_bit() is atomic and may not be reordered. It may be - * reordered on other architectures than x86. - * Note that @nr may be almost arbitrarily large; this function is not - * restricted to acting on a single-word quantity. - */ -static inline void change_bit(int nr, volatile unsigned long *addr) +static inline void change_bit(unsigned int nr, volatile unsigned long *p) { - unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long flags; - - _atomic_spin_lock_irqsave(p, flags); - *p ^= mask; - _atomic_spin_unlock_irqrestore(p, flags); + p += BIT_WORD(nr); + atomic_long_fetch_xor_relaxed(BIT_MASK(nr), (atomic_long_t *)p); } -/** - * test_and_set_bit - Set a bit and return its old value - * @nr: Bit to set - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It may be reordered on other architectures than x86. - * It also implies a memory barrier. - */ -static inline int test_and_set_bit(int nr, volatile unsigned long *addr) +static inline int test_and_set_bit(unsigned int nr, volatile unsigned long *p) { + long old; unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long old; - unsigned long flags; - _atomic_spin_lock_irqsave(p, flags); - old = *p; - *p = old | mask; - _atomic_spin_unlock_irqrestore(p, flags); + p += BIT_WORD(nr); + if (READ_ONCE(*p) & mask) + return 1; - return (old & mask) != 0; + old = atomic_long_fetch_or(mask, (atomic_long_t *)p); + return !!(old & mask); } -/** - * test_and_clear_bit - Clear a bit and return its old value - * @nr: Bit to clear - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It can be reorderdered on other architectures other than x86. - * It also implies a memory barrier. - */ -static inline int test_and_clear_bit(int nr, volatile unsigned long *addr) +static inline int test_and_clear_bit(unsigned int nr, volatile unsigned long *p) { + long old; unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long old; - unsigned long flags; - _atomic_spin_lock_irqsave(p, flags); - old = *p; - *p = old & ~mask; - _atomic_spin_unlock_irqrestore(p, flags); + p += BIT_WORD(nr); + if (!(READ_ONCE(*p) & mask)) + return 0; - return (old & mask) != 0; + old = atomic_long_fetch_andnot(mask, (atomic_long_t *)p); + return !!(old & mask); } -/** - * test_and_change_bit - Change a bit and return its old value - * @nr: Bit to change - * @addr: Address to count from - * - * This operation is atomic and cannot be reordered. - * It also implies a memory barrier. - */ -static inline int test_and_change_bit(int nr, volatile unsigned long *addr) +static inline int test_and_change_bit(unsigned int nr, volatile unsigned long *p) { + long old; unsigned long mask = BIT_MASK(nr); - unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); - unsigned long old; - unsigned long flags; - - _atomic_spin_lock_irqsave(p, flags); - old = *p; - *p = old ^ mask; - _atomic_spin_unlock_irqrestore(p, flags); - return (old & mask) != 0; + p += BIT_WORD(nr); + old = atomic_long_fetch_xor(mask, (atomic_long_t *)p); + return !!(old & mask); } #endif /* _ASM_GENERIC_BITOPS_ATOMIC_H */ From patchwork Thu May 24 10:59:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 136738 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp2043564lji; Thu, 24 May 2018 04:02:43 -0700 (PDT) X-Google-Smtp-Source: AB8JxZq9TU9QhPbV8smSOb9YrE0e6yJ0yltmeAQMVtoq/iP+aBW7HgX0FXb/tU5bzXow8xoogBPX X-Received: by 2002:a63:7d43:: with SMTP id m3-v6mr5526876pgn.117.1527159763800; Thu, 24 May 2018 04:02:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527159763; cv=none; d=google.com; s=arc-20160816; b=xUngUJBlUk0jjbKfkMPZG5vACVbQqeg003XV/oiJJ8QXi+zIecqRWSE+p6+xTUjPZo AVA9CbhJVvM+//Zf8SY88cuvf20bOuItggOORBZjNDHWSczhAQFA891pVXPlQuFs/6eC FNMQ6dGTsdL576SXGpxpLMmEGqgNXXYC684PFSHnFHF3BhxhZ5CpZD+hOo9PAG+XEwPV fKjMDvgdktO6PVMTD0wkh+OWdHl1zGK927IZOltSlJuVM1yeRJQfgCeTUqCB5VLRs4WM RSZSBSExzU7PyVpnYdEQVFk7YL9f4As/xGEZtZXeQG1fRgLzutot+Cdi6reUKSTVzxf6 FU2A== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id x32-v6si20519637pld.435.2018.05.24.04.02.43; Thu, 24 May 2018 04:02:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1032419AbeEXLCl (ORCPT + 30 others); Thu, 24 May 2018 07:02:41 -0400 Received: from foss.arm.com ([217.140.101.70]:40986 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1032596AbeEXK7V (ORCPT ); Thu, 24 May 2018 06:59:21 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 77EF916EA; Thu, 24 May 2018 03:59:20 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 484023F762; Thu, 24 May 2018 03:59:20 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id BEDB71AE38E7; Thu, 24 May 2018 11:59:47 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [PATCH 7/9] asm-generic/bitops/lock.h: Rewrite using atomic_fetch_* Date: Thu, 24 May 2018 11:59:44 +0100 Message-Id: <1527159586-8578-8-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1527159586-8578-1-git-send-email-will.deacon@arm.com> References: <1527159586-8578-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The lock bitops can be implemented more efficiently using the atomic_fetch_* ops, which provide finer-grained control over the memory ordering semantics than the bitops. Cc: Peter Zijlstra Cc: Ingo Molnar Signed-off-by: Will Deacon --- include/asm-generic/bitops/lock.h | 68 ++++++++++++++++++++++++++++++++------- 1 file changed, 56 insertions(+), 12 deletions(-) -- 2.1.4 diff --git a/include/asm-generic/bitops/lock.h b/include/asm-generic/bitops/lock.h index 67ab280ad134..3ae021368f48 100644 --- a/include/asm-generic/bitops/lock.h +++ b/include/asm-generic/bitops/lock.h @@ -2,6 +2,10 @@ #ifndef _ASM_GENERIC_BITOPS_LOCK_H_ #define _ASM_GENERIC_BITOPS_LOCK_H_ +#include +#include +#include + /** * test_and_set_bit_lock - Set a bit and return its old value, for lock * @nr: Bit to set @@ -11,7 +15,20 @@ * the returned value is 0. * It can be used to implement bit locks. */ -#define test_and_set_bit_lock(nr, addr) test_and_set_bit(nr, addr) +static inline int test_and_set_bit_lock(unsigned int nr, + volatile unsigned long *p) +{ + long old; + unsigned long mask = BIT_MASK(nr); + + p += BIT_WORD(nr); + if (READ_ONCE(*p) & mask) + return 1; + + old = atomic_long_fetch_or_acquire(mask, (atomic_long_t *)p); + return !!(old & mask); +} + /** * clear_bit_unlock - Clear a bit in memory, for unlock @@ -20,11 +37,11 @@ * * This operation is atomic and provides release barrier semantics. */ -#define clear_bit_unlock(nr, addr) \ -do { \ - smp_mb__before_atomic(); \ - clear_bit(nr, addr); \ -} while (0) +static inline void clear_bit_unlock(unsigned int nr, volatile unsigned long *p) +{ + p += BIT_WORD(nr); + atomic_long_fetch_andnot_release(BIT_MASK(nr), (atomic_long_t *)p); +} /** * __clear_bit_unlock - Clear a bit in memory, for unlock @@ -37,11 +54,38 @@ do { \ * * See for example x86's implementation. */ -#define __clear_bit_unlock(nr, addr) \ -do { \ - smp_mb__before_atomic(); \ - clear_bit(nr, addr); \ -} while (0) +static inline void __clear_bit_unlock(unsigned int nr, + volatile unsigned long *p) +{ + unsigned long old; -#endif /* _ASM_GENERIC_BITOPS_LOCK_H_ */ + p += BIT_WORD(nr); + old = READ_ONCE(*p); + old &= ~BIT_MASK(nr); + atomic_long_set_release((atomic_long_t *)p, old); +} + +/** + * clear_bit_unlock_is_negative_byte - Clear a bit in memory and test if bottom + * byte is negative, for unlock. + * @nr: the bit to clear + * @addr: the address to start counting from + * + * This is a bit of a one-trick-pony for the filemap code, which clears + * PG_locked and tests PG_waiters, + */ +#ifndef clear_bit_unlock_is_negative_byte +static inline bool clear_bit_unlock_is_negative_byte(unsigned int nr, + volatile unsigned long *p) +{ + long old; + unsigned long mask = BIT_MASK(nr); + + p += BIT_WORD(nr); + old = atomic_long_fetch_andnot_release(mask, (atomic_long_t *)p); + return !!(old & BIT(7)); +} +#define clear_bit_unlock_is_negative_byte clear_bit_unlock_is_negative_byte +#endif +#endif /* _ASM_GENERIC_BITOPS_LOCK_H_ */ From patchwork Thu May 24 10:59:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 136737 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp2043492lji; Thu, 24 May 2018 04:02:40 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqvwNrNrrXgGiQ6X2b2XWS2sIjq68qjReg2v27pBADETsebd6frmPLUzGXmTwZDvcyR5sKx X-Received: by 2002:a63:b213:: with SMTP id x19-v6mr5465434pge.393.1527159760737; Thu, 24 May 2018 04:02:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527159760; cv=none; d=google.com; s=arc-20160816; b=mkhzIrtbApN2aRO7XNRFEIkgE+Gzzphl7B2B0pSLHFsfoX0RlXqzvs5HE13EaeHqRJ bDZshrtZw/2x7VcFlwIOEKEaG2kgdR9hPmC5SOgZMPqlPPFUDVrMLqqm27ut+9VqZkPB v6+C1U/Aab+dOA8C5IBqT22gjhTxn/KtmwyiFTNTm/bjEJEx/OjNguxWFKBKOnNxRfss UsOzXUTKCBAgx6FQCCCWUgjfhD3Q27HBnz7aCDt71eTitNHMgeDZdcBIC1jKF/0hrE5I XWJzsplSRFeyUY3M8pjV5XqVBXF9us99w5ArEaZQ0EqLqlnPWlKn/WrFUX5nFOc4dFeW jwhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=88Np3PUNTEYxNN1Z+7fZ0C9DrRKS+lculQW06jbIgMw=; b=laejzOFJbMPELzVfvaZwPetqpPaT8Wh0odO1V5EIxbIi+suhhV7FTTC+5nf7UDpjQU gBTTVO4wtUARO/myU0A6sx/lI54eGT6cJiqpKLPq410S8M6yVHHN5YTBHNFySKnELaT0 o6KENFm+DfXCOGux2zrY33/G94sM8MSx6Ob8uFNfhXh6afILa38ktdmxBzTPX6LleWVi 8pR1+xSm+dvlma/lHpp+iAmxnDBoxsCl+Tc635hpB5RYJh8jBS0XPzfnfYJ3fb50G5is oyDfn7f7X1MTtwVXpNvLyJINxF2XGFhTFKbJfGAZSH69GIr3Age/NGGrQMNOP1gcTMVY Nq3g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s194-v6si1113823pgc.602.2018.05.24.04.02.40; Thu, 24 May 2018 04:02:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S968443AbeEXLCj (ORCPT + 30 others); Thu, 24 May 2018 07:02:39 -0400 Received: from foss.arm.com ([217.140.101.70]:40988 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1032603AbeEXK7V (ORCPT ); Thu, 24 May 2018 06:59:21 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 81F101713; Thu, 24 May 2018 03:59:20 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 51EA93F7B4; Thu, 24 May 2018 03:59:20 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id CF2C91AE3916; Thu, 24 May 2018 11:59:47 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [PATCH 8/9] arm64: Replace our atomic/lock bitop implementations with asm-generic Date: Thu, 24 May 2018 11:59:45 +0100 Message-Id: <1527159586-8578-9-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1527159586-8578-1-git-send-email-will.deacon@arm.com> References: <1527159586-8578-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The asm-generic/bitops/{atomic,lock}.h implementations are built around the atomic-fetch ops, which we implement efficiently for both LSE and LL/SC systems. Use that instead of our hand-rolled, out-of-line bitops.S. Signed-off-by: Will Deacon --- arch/arm64/include/asm/bitops.h | 14 ++------ arch/arm64/lib/Makefile | 2 +- arch/arm64/lib/bitops.S | 76 ----------------------------------------- 3 files changed, 3 insertions(+), 89 deletions(-) delete mode 100644 arch/arm64/lib/bitops.S -- 2.1.4 diff --git a/arch/arm64/include/asm/bitops.h b/arch/arm64/include/asm/bitops.h index 9c19594ce7cb..13501460be6b 100644 --- a/arch/arm64/include/asm/bitops.h +++ b/arch/arm64/include/asm/bitops.h @@ -17,22 +17,11 @@ #define __ASM_BITOPS_H #include -#include #ifndef _LINUX_BITOPS_H #error only can be included directly #endif -/* - * Little endian assembly atomic bitops. - */ -extern void set_bit(int nr, volatile unsigned long *p); -extern void clear_bit(int nr, volatile unsigned long *p); -extern void change_bit(int nr, volatile unsigned long *p); -extern int test_and_set_bit(int nr, volatile unsigned long *p); -extern int test_and_clear_bit(int nr, volatile unsigned long *p); -extern int test_and_change_bit(int nr, volatile unsigned long *p); - #include #include #include @@ -44,8 +33,9 @@ extern int test_and_change_bit(int nr, volatile unsigned long *p); #include #include -#include +#include +#include #include #include diff --git a/arch/arm64/lib/Makefile b/arch/arm64/lib/Makefile index 137710f4dac3..68755fd70dcf 100644 --- a/arch/arm64/lib/Makefile +++ b/arch/arm64/lib/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -lib-y := bitops.o clear_user.o delay.o copy_from_user.o \ +lib-y := clear_user.o delay.o copy_from_user.o \ copy_to_user.o copy_in_user.o copy_page.o \ clear_page.o memchr.o memcpy.o memmove.o memset.o \ memcmp.o strcmp.o strncmp.o strlen.o strnlen.o \ diff --git a/arch/arm64/lib/bitops.S b/arch/arm64/lib/bitops.S deleted file mode 100644 index 43ac736baa5b..000000000000 --- a/arch/arm64/lib/bitops.S +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Based on arch/arm/lib/bitops.h - * - * Copyright (C) 2013 ARM Ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include - -/* - * x0: bits 5:0 bit offset - * bits 31:6 word offset - * x1: address - */ - .macro bitop, name, llsc, lse -ENTRY( \name ) - and w3, w0, #63 // Get bit offset - eor w0, w0, w3 // Clear low bits - mov x2, #1 - add x1, x1, x0, lsr #3 // Get word offset -alt_lse " prfm pstl1strm, [x1]", "nop" - lsl x3, x2, x3 // Create mask - -alt_lse "1: ldxr x2, [x1]", "\lse x3, [x1]" -alt_lse " \llsc x2, x2, x3", "nop" -alt_lse " stxr w0, x2, [x1]", "nop" -alt_lse " cbnz w0, 1b", "nop" - - ret -ENDPROC(\name ) - .endm - - .macro testop, name, llsc, lse -ENTRY( \name ) - and w3, w0, #63 // Get bit offset - eor w0, w0, w3 // Clear low bits - mov x2, #1 - add x1, x1, x0, lsr #3 // Get word offset -alt_lse " prfm pstl1strm, [x1]", "nop" - lsl x4, x2, x3 // Create mask - -alt_lse "1: ldxr x2, [x1]", "\lse x4, x2, [x1]" - lsr x0, x2, x3 -alt_lse " \llsc x2, x2, x4", "nop" -alt_lse " stlxr w5, x2, [x1]", "nop" -alt_lse " cbnz w5, 1b", "nop" -alt_lse " dmb ish", "nop" - - and x0, x0, #1 - ret -ENDPROC(\name ) - .endm - -/* - * Atomic bit operations. - */ - bitop change_bit, eor, steor - bitop clear_bit, bic, stclr - bitop set_bit, orr, stset - - testop test_and_change_bit, eor, ldeoral - testop test_and_clear_bit, bic, ldclral - testop test_and_set_bit, orr, ldsetal From patchwork Thu May 24 10:59:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 136736 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp2042448lji; Thu, 24 May 2018 04:01:52 -0700 (PDT) X-Google-Smtp-Source: AB8JxZry5Obatn1cpxuvt7AIZshGG2pfW1uqszHT8zsSmiYoSiaHvSw9eAUwDxHYzz/kEWnPBxpt X-Received: by 2002:a62:8ac1:: with SMTP id o62-v6mr6797927pfk.141.1527159712248; Thu, 24 May 2018 04:01:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527159712; cv=none; d=google.com; s=arc-20160816; b=tvOsCwvyV/Y76MYaT/SzA9fqWkBdjeegOTNnWhkZjqI5cJMIHt/+YS/n7JBAawRyR5 YqhJrkInopnitrfz8Dcqrb49hzkDQ58K9b3guH1uEklpteg2Y760rWj0NPxbMm/Z9LKw IrkiSjgQb5qF5//cJwNZZhaQA0R+lr+r0AhwW3gvJQqKFR1MANBxa9CeQhgWSl6Y7c5r 3Ets1doAFhuhi/pcLcjRucZ2LBXnlsE0PhS32wniEFMUMFhptpkTcNDukIqEU9McdKdz p/12PQs3+jDfiXRHQoCxgZ73NyKCgaaGEyv5iXdiKUNvB6uu0tBlGa3R5n2vmyQwjbkN 1E8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=n5MGW/pfF/fJTATDJDJJ2DG14cgfSYeD3F8Z9NccPfo=; b=pxF4RS6clAZiE6MUih7D0oblbZny9+ceGY3pw0/vKolwcsgk4wfjldlf0P84bSk5M0 2QuToq8gNR2EHCfxiEhWkY+5zplU/WSe60jZ3RESXbhOabAebL/QDplugpF+4fXh9tqT ViwDqnjws3uBrVdJxVl/mAvEPMCkJf9qmn6GcGJQNKbD97eXjs+aWwirqoB5xTefGQvr ob5CtzpL4wVUNNpDMyI41daaVmBQR9F0lsG19OPyDVD0FBHvZZy1AIbD2n8tu5dB23fH pK9s9foB8LXPwDHMb6S9vLxg2hYBMy+GP33V+g2eDO2R24JBf/mWybOHD4CHy20d+GHX uA3Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i72-v6si16447133pgd.211.2018.05.24.04.01.51; Thu, 24 May 2018 04:01:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1032858AbeEXLBu (ORCPT + 30 others); Thu, 24 May 2018 07:01:50 -0400 Received: from foss.arm.com ([217.140.101.70]:41008 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030356AbeEXK7V (ORCPT ); Thu, 24 May 2018 06:59:21 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8A4AF174E; Thu, 24 May 2018 03:59:20 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5ACCB3F855; Thu, 24 May 2018 03:59:20 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id DF6641AE3ACE; Thu, 24 May 2018 11:59:47 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@kernel.org, linux-arm-kernel@lists.infradead.org, yamada.masahiro@socionext.com, Will Deacon Subject: [PATCH 9/9] arm64: bitops: Include Date: Thu, 24 May 2018 11:59:46 +0100 Message-Id: <1527159586-8578-10-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1527159586-8578-1-git-send-email-will.deacon@arm.com> References: <1527159586-8578-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org asm-generic/bitops/ext2-atomic-setbit.h provides the ext2 atomic bitop definitions, so we don't need to define our own. Signed-off-by: Will Deacon --- arch/arm64/include/asm/bitops.h | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) -- 2.1.4 diff --git a/arch/arm64/include/asm/bitops.h b/arch/arm64/include/asm/bitops.h index 13501460be6b..10d536b1af74 100644 --- a/arch/arm64/include/asm/bitops.h +++ b/arch/arm64/include/asm/bitops.h @@ -38,11 +38,6 @@ #include #include #include - -/* - * Ext2 is defined to use little-endian byte ordering. - */ -#define ext2_set_bit_atomic(lock, nr, p) test_and_set_bit_le(nr, p) -#define ext2_clear_bit_atomic(lock, nr, p) test_and_clear_bit_le(nr, p) +#include #endif /* __ASM_BITOPS_H */