From patchwork Thu May 24 14:19:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 136746 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp2271882lji; Thu, 24 May 2018 07:19:34 -0700 (PDT) X-Google-Smtp-Source: AB8JxZp2lLAcQMemnHBhiwYT/u/jHAPQMsqt8HldN2Of3joqpLQiln3fFvZTNYzR9x+3almu+uEF X-Received: by 2002:a17:902:26:: with SMTP id 35-v6mr7946366pla.104.1527171574432; Thu, 24 May 2018 07:19:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527171574; cv=none; d=google.com; s=arc-20160816; b=a/YmN8qBWW65r1zAw3gRV2Jen/QcC2DXDIr9QXMs/EjeJWYTDZL2i7bI/wxE1ykDQu JUWeB0DYahy4jV/80JFI734xd83KSjqFG2rtL/fAEZn2xdWjJjOdQA5sSmhgI0CGhtKP PASRB38TtUYYyj5PWSm7MEyEksYC4o3ygMsZkG37hKfwqWMb47wOMcm3UIlA698c5lS0 hZuDuyiqxPWLaBDXRHER+C75y+n6xYyjRgkNtpONfaw9CpfmodB6I/LQEf4mICKbMycw /81UrfP4qGwQ3H1JIRD8gBVUn1Hks7iMG6kxk5ZLVIOVTZANeLldcnjqzcNDilWaVs/B nZmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=Gg14CiDid97zwsslgVaNRijI7QD793UqV7SDQvVJoa8=; b=FhqX3W3CBJy5LNdAmrlRnjWMVF77f8T+H1pHhGRpqEoLJKla5faI7BlhD0DALqtQvq RyD1/phNwsC0w3GuvJfoMo4vj9a7d/kK9Opwo5f4ccWB9vOWR1CypsE6QlCwbapmlRQy kxi1OzPGr5mxHK5fNYZJeMiqpSpmlVsfZldHcwM/70ACexIE8bHJo/w/5oM0EjIh8wzh 9LpTZ70Vpa1EUmwnTvDDw3GkCGDRYU75IUgxLeqxxVKF3TuSOIc8C8LK39LTBQcNpJRf iXVx6lco2doh3Zw4oek8Ck2G8n4Hr9Xojdl3XCJ3mtnYn8IuBncfR1ae9Pqlgr8ZQU7O o7Qg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b9-v6si20297114pli.427.2018.05.24.07.19.34; Thu, 24 May 2018 07:19:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1031873AbeEXOTc (ORCPT + 1 other); Thu, 24 May 2018 10:19:32 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:45614 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030516AbeEXOT2 (ORCPT ); Thu, 24 May 2018 10:19:28 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8FEDB15AD; Thu, 24 May 2018 07:19:27 -0700 (PDT) Received: from sugar.kfn.arm.com (unknown [10.45.48.133]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 27E1D3F24A; Thu, 24 May 2018 07:19:22 -0700 (PDT) From: Gilad Ben-Yossef To: Simon Horman , Magnus Damm , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Herbert Xu , "David S. Miller" Cc: Ofir Drang , stable@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org Subject: [PATCH v2 1/5] crypto: ccree: correct host regs offset Date: Thu, 24 May 2018 15:19:06 +0100 Message-Id: <1527171551-21979-2-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1527171551-21979-1-git-send-email-gilad@benyossef.com> References: <1527171551-21979-1-git-send-email-gilad@benyossef.com> Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org The product signature and HW revision register have different offset on the older HW revisions. This fixes the problem of the driver failing sanity check on silicon despite working on the FPGA emulation systems. Fixes: 27b3b22dd98c ("crypto: ccree - add support for older HW revs") Cc: stable@vger.kernel.org Signed-off-by: Gilad Ben-Yossef --- drivers/crypto/ccree/cc_debugfs.c | 7 +++++-- drivers/crypto/ccree/cc_driver.c | 8 ++++++-- drivers/crypto/ccree/cc_driver.h | 2 ++ drivers/crypto/ccree/cc_host_regs.h | 6 ++++-- 4 files changed, 17 insertions(+), 6 deletions(-) -- 2.7.4 diff --git a/drivers/crypto/ccree/cc_debugfs.c b/drivers/crypto/ccree/cc_debugfs.c index 08f8db4..5ca184e 100644 --- a/drivers/crypto/ccree/cc_debugfs.c +++ b/drivers/crypto/ccree/cc_debugfs.c @@ -26,7 +26,8 @@ struct cc_debugfs_ctx { static struct dentry *cc_debugfs_dir; static struct debugfs_reg32 debug_regs[] = { - CC_DEBUG_REG(HOST_SIGNATURE), + { .name = "SIGNATURE" }, /* Must be 0th */ + { .name = "VERSION" }, /* Must be 1st */ CC_DEBUG_REG(HOST_IRR), CC_DEBUG_REG(HOST_POWER_DOWN_EN), CC_DEBUG_REG(AXIM_MON_ERR), @@ -34,7 +35,6 @@ static struct debugfs_reg32 debug_regs[] = { CC_DEBUG_REG(HOST_IMR), CC_DEBUG_REG(AXIM_CFG), CC_DEBUG_REG(AXIM_CACHE_PARAMS), - CC_DEBUG_REG(HOST_VERSION), CC_DEBUG_REG(GPR_HOST), CC_DEBUG_REG(AXIM_MON_COMP), }; @@ -58,6 +58,9 @@ int cc_debugfs_init(struct cc_drvdata *drvdata) struct debugfs_regset32 *regset; struct dentry *file; + debug_regs[0].offset = drvdata->sig_offset; + debug_regs[1].offset = drvdata->ver_offset; + ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); if (!ctx) return -ENOMEM; diff --git a/drivers/crypto/ccree/cc_driver.c b/drivers/crypto/ccree/cc_driver.c index 89ce013..6f93ce7 100644 --- a/drivers/crypto/ccree/cc_driver.c +++ b/drivers/crypto/ccree/cc_driver.c @@ -207,9 +207,13 @@ static int init_cc_resources(struct platform_device *plat_dev) if (hw_rev->rev >= CC_HW_REV_712) { new_drvdata->hash_len_sz = HASH_LEN_SIZE_712; new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP); + new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_712); + new_drvdata->ver_offset = CC_REG(HOST_VERSION_712); } else { new_drvdata->hash_len_sz = HASH_LEN_SIZE_630; new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP8); + new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_630); + new_drvdata->ver_offset = CC_REG(HOST_VERSION_630); } platform_set_drvdata(plat_dev, new_drvdata); @@ -276,7 +280,7 @@ static int init_cc_resources(struct platform_device *plat_dev) } /* Verify correct mapping */ - signature_val = cc_ioread(new_drvdata, CC_REG(HOST_SIGNATURE)); + signature_val = cc_ioread(new_drvdata, new_drvdata->sig_offset); if (signature_val != hw_rev->sig) { dev_err(dev, "Invalid CC signature: SIGNATURE=0x%08X != expected=0x%08X\n", signature_val, hw_rev->sig); @@ -287,7 +291,7 @@ static int init_cc_resources(struct platform_device *plat_dev) /* Display HW versions */ dev_info(dev, "ARM CryptoCell %s Driver: HW version 0x%08X, Driver version %s\n", - hw_rev->name, cc_ioread(new_drvdata, CC_REG(HOST_VERSION)), + hw_rev->name, cc_ioread(new_drvdata, new_drvdata->ver_offset), DRV_MODULE_VERSION); rc = init_cc_regs(new_drvdata, true); diff --git a/drivers/crypto/ccree/cc_driver.h b/drivers/crypto/ccree/cc_driver.h index 2048fde..95f82b2 100644 --- a/drivers/crypto/ccree/cc_driver.h +++ b/drivers/crypto/ccree/cc_driver.h @@ -129,6 +129,8 @@ struct cc_drvdata { enum cc_hw_rev hw_rev; u32 hash_len_sz; u32 axim_mon_offset; + u32 sig_offset; + u32 ver_offset; }; struct cc_crypto_alg { diff --git a/drivers/crypto/ccree/cc_host_regs.h b/drivers/crypto/ccree/cc_host_regs.h index f510018..616b2e1 100644 --- a/drivers/crypto/ccree/cc_host_regs.h +++ b/drivers/crypto/ccree/cc_host_regs.h @@ -45,7 +45,8 @@ #define CC_HOST_ICR_DSCRPTR_WATERMARK_QUEUE0_CLEAR_BIT_SIZE 0x1UL #define CC_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SHIFT 0x17UL #define CC_HOST_ICR_AXIM_COMP_INT_CLEAR_BIT_SIZE 0x1UL -#define CC_HOST_SIGNATURE_REG_OFFSET 0xA24UL +#define CC_HOST_SIGNATURE_712_REG_OFFSET 0xA24UL +#define CC_HOST_SIGNATURE_630_REG_OFFSET 0xAC8UL #define CC_HOST_SIGNATURE_VALUE_BIT_SHIFT 0x0UL #define CC_HOST_SIGNATURE_VALUE_BIT_SIZE 0x20UL #define CC_HOST_BOOT_REG_OFFSET 0xA28UL @@ -105,7 +106,8 @@ #define CC_HOST_BOOT_ONLY_ENCRYPT_LOCAL_BIT_SIZE 0x1UL #define CC_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SHIFT 0x1EUL #define CC_HOST_BOOT_AES_EXISTS_LOCAL_BIT_SIZE 0x1UL -#define CC_HOST_VERSION_REG_OFFSET 0xA40UL +#define CC_HOST_VERSION_712_REG_OFFSET 0xA40UL +#define CC_HOST_VERSION_630_REG_OFFSET 0xAD8UL #define CC_HOST_VERSION_VALUE_BIT_SHIFT 0x0UL #define CC_HOST_VERSION_VALUE_BIT_SIZE 0x20UL #define CC_HOST_KFDE0_VALID_REG_OFFSET 0xA60UL From patchwork Thu May 24 14:19:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gilad Ben-Yossef X-Patchwork-Id: 136750 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp2273600lji; Thu, 24 May 2018 07:20:58 -0700 (PDT) X-Google-Smtp-Source: AB8JxZoB/R/XR4S9ZGJwjtsk6k/oyh4gau/eHfrEZxYLnFhOAzVZD3gVZmnsV3Z0jmnYX6gjUVp7 X-Received: by 2002:a63:8c05:: with SMTP id m5-v6mr6080928pgd.98.1527171658609; Thu, 24 May 2018 07:20:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527171658; cv=none; d=google.com; s=arc-20160816; b=O+w7UMt1kl2PL9B7ROHYutRnYToNn2r/H54cIViUTKmNIJzgA8QoaUeVbmcNYaSTKl Lz9u9z0cnCcPQ4WuuNgg43OZVmfqf+xo51+VLfgD+VKtVuqPKvkoOHC9SJJfhYW7BbRM tGpaN1oSWBIFehIyQSslUVoXRU+oG9L81OOK8AYP8XF/C90hS2GtpoRZmKHP6v9xuvG6 u9+g1Xb1+OQZaJe7qkHqGNC1SMX1ScoPMutDh/s2TZfudvivXlvxhmHaN32aJsXb90NH pJvHgl/sEdTkGqXiUUfeBHugQucmB+M5CcxOhayy9XQE1l4AYmGP7wLsmSBPmircGniq wJXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; 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[209.132.180.67]) by mx.google.com with ESMTP id r59-v6si21086045plb.187.2018.05.24.07.20.58; Thu, 24 May 2018 07:20:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1032437AbeEXOU4 (ORCPT + 1 other); Thu, 24 May 2018 10:20:56 -0400 Received: from foss.arm.com ([217.140.101.70]:45696 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1032545AbeEXOTu (ORCPT ); Thu, 24 May 2018 10:19:50 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 329F0165D; Thu, 24 May 2018 07:19:50 -0700 (PDT) Received: from sugar.kfn.arm.com (unknown [10.45.48.133]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 163CF3F24A; Thu, 24 May 2018 07:19:45 -0700 (PDT) From: Gilad Ben-Yossef To: Simon Horman , Magnus Damm , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Herbert Xu , "David S. Miller" Cc: Ofir Drang , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-crypto@vger.kernel.org Subject: [PATCH v2 5/5] arm64: dts: renesas: r8a7795: add ccree binding Date: Thu, 24 May 2018 15:19:10 +0100 Message-Id: <1527171551-21979-6-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1527171551-21979-1-git-send-email-gilad@benyossef.com> References: <1527171551-21979-1-git-send-email-gilad@benyossef.com> Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Add bindings for CryptoCell instance in the SoC. Signed-off-by: Gilad Ben-Yossef --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.7.4 diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index d842940..3ac75db 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -528,6 +528,15 @@ status = "disabled"; }; + arm_cc630p: crypto@e6601000 { + compatible = "arm,cryptocell-630p-ree"; + interrupts = ; + reg = <0x0 0xe6601000 0 0x1000>; + clocks = <&cpg CPG_MOD 229>; + resets = <&cpg 229>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + }; + i2c3: i2c@e66d0000 { #address-cells = <1>; #size-cells = <0>;