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[209.132.180.67]) by mx.google.com with ESMTP id j2-v6si3622625pll.411.2018.05.24.22.40.41; Thu, 24 May 2018 22:40:41 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=c1TyAYId; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964925AbeEYFkj (ORCPT + 30 others); Fri, 25 May 2018 01:40:39 -0400 Received: from mail-pg0-f68.google.com ([74.125.83.68]:43761 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964843AbeEYFkg (ORCPT ); Fri, 25 May 2018 01:40:36 -0400 Received: by mail-pg0-f68.google.com with SMTP id p8-v6so1798336pgq.10 for ; Thu, 24 May 2018 22:40:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=3owkLNekyB+F51qF2xmEv7fT8CE3xQHPsbGPpJfAzZM=; b=c1TyAYIdLK96SC7lMfn+y01IAgExPuLevGOOnIWa4EcLo/368TrCNU+rX8D2CJsWQJ cVIiIpMdryPl9k1AyVRzxnmFUusN4DOgJuls0DWtnUwUMD3/3Z/MrQCjUa0ZWwoGIFLp M2CcfzTGB2ZilLmx+lUV/7S3DTkwiNFw9NrDs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=3owkLNekyB+F51qF2xmEv7fT8CE3xQHPsbGPpJfAzZM=; b=KIhdCPwxcZ5cp9KKWNZ4jcCc3YAIPWWFpeoZviKQC/PFlZRJ8c/N6xOTJFPqVJ5MHJ OLY1ua+TjaO7upHox/VTVV51jW7+d2lIEFDJMm1Phal9CjtdP0TMv31UOF7Q1UsfKBdX oH5bNSO5Qmv/OD1cdVJi6PVfm2sjfVh9sMSoLwj5gREoh1iUYbskYOYBb3fc+Pc1d/Io WUSVPbkOYVeL1ut/exCC2+Bc2ZoCKvzX2NMFS5q9LnM+2dZxJfyD4foihfSa/1vCLNQL P3QPxQfvepBwHM049Pv5IRWdLaTPw1YorQozT9p7SzM0ytyv0z65LmZyiKBJ9kF811hD TP4w== X-Gm-Message-State: ALKqPwc3oaS7E8Pnu/Fq2lN3N4IiSlIXlaiXXh9XkMoSzgFrT4p6zNMX 2jiL7bTp5iaO6cqSnDJpZW3bqFu6o6A= X-Received: by 2002:a62:9056:: with SMTP id a83-v6mr1098973pfe.186.1527226835339; Thu, 24 May 2018 22:40:35 -0700 (PDT) Received: from localhost ([122.172.112.176]) by smtp.gmail.com with ESMTPSA id a10-v6sm35398333pfo.55.2018.05.24.22.40.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 24 May 2018 22:40:34 -0700 (PDT) From: Viresh Kumar To: arm@kernel.org, Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon Cc: Viresh Kumar , Vincent Guittot , ionela.voinescu@arm.com, Daniel Lezcano , chris.redpath@arm.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/6] arm64: dts: freescale: Add missing cooling device properties for CPUs Date: Fri, 25 May 2018 11:10:02 +0530 Message-Id: X-Mailer: git-send-email 2.15.0.194.g9af6a3dea062 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Do minor rearrangement as well to keep ordering consistent. Signed-off-by: Viresh Kumar --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 5 ++++- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 3 +++ arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 4 ++++ arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 4 ++++ 5 files changed, 21 insertions(+), 1 deletion(-) -- 2.15.0.194.g9af6a3dea062 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 1109f22bda5e..630ee47441f2 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -80,8 +80,8 @@ reg = <0x0>; clocks = <&clockgen 1 0>; next-level-cache = <&l2>; - #cooling-cells = <2>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -91,6 +91,7 @@ clocks = <&clockgen 1 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -100,6 +101,7 @@ clocks = <&clockgen 1 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -109,6 +111,7 @@ clocks = <&clockgen 1 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; l2: l2-cache { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 136ebfa9b333..ee7beab8bfae 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -87,6 +87,7 @@ clocks = <&clockgen 1 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -96,6 +97,7 @@ clocks = <&clockgen 1 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -105,6 +107,7 @@ clocks = <&clockgen 1 0>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; l2: l2-cache { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 1c6556bcfddf..e64823a25158 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -76,6 +76,7 @@ reg = <0x1>; clocks = <&clockgen 1 0>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -84,6 +85,7 @@ reg = <0x2>; clocks = <&clockgen 1 0>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -92,6 +94,7 @@ reg = <0x3>; clocks = <&clockgen 1 0>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu4: cpu@100 { @@ -109,6 +112,7 @@ reg = <0x101>; clocks = <&clockgen 1 1>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu6: cpu@102 { @@ -117,6 +121,7 @@ reg = <0x102>; clocks = <&clockgen 1 1>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; cpu7: cpu@103 { @@ -125,6 +130,7 @@ reg = <0x103>; clocks = <&clockgen 1 1>; cpu-idle-states = <&CPU_PH20>; + #cooling-cells = <2>; }; CPU_PH20: cpu-ph20 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index 8d739301e7b8..c264b6d1bd7f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -65,6 +65,7 @@ clocks = <&clockgen 1 0>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster0_l2>; + #cooling-cells = <2>; }; cpu2: cpu@100 { @@ -84,6 +85,7 @@ clocks = <&clockgen 1 1>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster1_l2>; + #cooling-cells = <2>; }; cpu4: cpu@200 { @@ -103,6 +105,7 @@ clocks = <&clockgen 1 2>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster2_l2>; + #cooling-cells = <2>; }; cpu6: cpu@300 { @@ -122,6 +125,7 @@ clocks = <&clockgen 1 3>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster3_l2>; + #cooling-cells = <2>; }; cluster0_l2: l2-cache0 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi index 0884e1a77901..b6ea9e96c866 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi @@ -65,6 +65,7 @@ clocks = <&clockgen 1 0>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster0_l2>; + #cooling-cells = <2>; }; cpu2: cpu@100 { @@ -84,6 +85,7 @@ clocks = <&clockgen 1 1>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster1_l2>; + #cooling-cells = <2>; }; cpu4: cpu@200 { @@ -103,6 +105,7 @@ clocks = <&clockgen 1 2>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster2_l2>; + #cooling-cells = <2>; }; cpu6: cpu@300 { @@ -122,6 +125,7 @@ clocks = <&clockgen 1 3>; cpu-idle-states = <&CPU_PW20>; next-level-cache = <&cluster3_l2>; + #cooling-cells = <2>; }; cluster0_l2: l2-cache0 { From patchwork Fri May 25 05:40:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 136779 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp3130237lji; Thu, 24 May 2018 22:41:32 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqIjm/2afptpGFbvSIM8C57eteHbTHRTN7sG87YwQ5oZRxgaTy4dPg/xnYg9P81Aq0fVWsq X-Received: by 2002:a62:3c10:: with SMTP id j16-v6mr1086768pfa.7.1527226891863; Thu, 24 May 2018 22:41:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; 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[209.132.180.67]) by mx.google.com with ESMTP id f62-v6si15290127pgc.651.2018.05.24.22.41.31; Thu, 24 May 2018 22:41:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JdGna9Nr; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753343AbeEYFl3 (ORCPT + 30 others); Fri, 25 May 2018 01:41:29 -0400 Received: from mail-pf0-f194.google.com ([209.85.192.194]:40305 "EHLO mail-pf0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964875AbeEYFki (ORCPT ); Fri, 25 May 2018 01:40:38 -0400 Received: by mail-pf0-f194.google.com with SMTP id f189-v6so2021200pfa.7 for ; Thu, 24 May 2018 22:40:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=oRUuLH7flE4Fvg206nWF7csPgcPeAXkHjdKNYq5dMh8=; b=JdGna9NrumQ0C3jprwSOW4n+BGRLVsJM2q8xYQ+ii88CadkPC2krp2SGJz+AryW7VN dzARt55d59RtyjEmZ4AToTi3SEBg3ONe32+cZTW97hVDC3UpfLw7dr1hAUUV1VjNtjX5 nkwqCDGE0+6OVUQ7yCmzPRK7lyThPvfEBX5ZY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=oRUuLH7flE4Fvg206nWF7csPgcPeAXkHjdKNYq5dMh8=; b=ntDBO8Pwshf8AXQwRH5q4blCD1iCfnBuzhFtskdib/DKq13mgc2Zqc8i6bdZ5PpNzz un0cQbjdzQjs9TuAQ4tkqCIfQYOR123QClbU1K4GqhNSeVta6ggN52jb2ZvTwQS5z/ak hDtA0PT3hKzT8Cg5AWdr3KaWPap11832ppVb7d0lx3QvT3kf4NN7KjeB4NFlF5SpDwz5 Apj0tJl9f/Vi/1uasmYduim8z8jYUezY4xERrsdHxtPGcS5J8MxMQOsGJbyq8TFCIo61 T1P89ombFRQLwIUZXwuQZeaAzxf85jJMsNceTcNqrvnK9v5AaWojjxrVDOBSUj7V3uK4 q0vg== X-Gm-Message-State: ALKqPweWamy4M9qP2wpIHRZEhtLN1RrnBIKV2/8/GipdOtY6paqSx5Ox yNkbI/5tk5ypHC1Mv3Tm5V2aMg== X-Received: by 2002:a63:69c3:: with SMTP id e186-v6mr832546pgc.353.1527226838329; Thu, 24 May 2018 22:40:38 -0700 (PDT) Received: from localhost ([122.172.112.176]) by smtp.gmail.com with ESMTPSA id c83-v6sm45342586pfc.111.2018.05.24.22.40.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 24 May 2018 22:40:37 -0700 (PDT) From: Viresh Kumar To: arm@kernel.org, Wei Xu , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon Cc: Viresh Kumar , Vincent Guittot , ionela.voinescu@arm.com, Daniel Lezcano , chris.redpath@arm.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/6] arm64: dts: hisilicon: Add missing cooling device properties for CPUs Date: Fri, 25 May 2018 11:10:03 +0530 Message-Id: <0754957a2c3842cf4e36fa27231d327fd8d6d499.1527225682.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.15.0.194.g9af6a3dea062 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Do minor rearrangement as well to keep ordering consistent. Signed-off-by: Viresh Kumar --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) -- 2.15.0.194.g9af6a3dea062 diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 586b281cd531..247024df714f 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -88,8 +88,8 @@ next-level-cache = <&CLUSTER0_L2>; clocks = <&stub_clock 0>; operating-points-v2 = <&cpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <311>; }; @@ -101,6 +101,8 @@ next-level-cache = <&CLUSTER0_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <311>; }; cpu2: cpu@2 { @@ -111,6 +113,8 @@ next-level-cache = <&CLUSTER0_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <311>; }; cpu3: cpu@3 { @@ -121,6 +125,8 @@ next-level-cache = <&CLUSTER0_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <311>; }; cpu4: cpu@100 { @@ -131,6 +137,8 @@ next-level-cache = <&CLUSTER1_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <311>; }; cpu5: cpu@101 { @@ -141,6 +149,8 @@ next-level-cache = <&CLUSTER1_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <311>; }; cpu6: cpu@102 { @@ -151,6 +161,8 @@ next-level-cache = <&CLUSTER1_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <311>; }; cpu7: cpu@103 { @@ -161,6 +173,8 @@ next-level-cache = <&CLUSTER1_L2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <311>; }; CLUSTER0_L2: l2-cache0 { From patchwork Fri May 25 05:40:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 136776 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp3129690lji; Thu, 24 May 2018 22:40:50 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqtKZALKn7KWafOfSjB54qUBgCYTaJVna7PcesNZyjFATcH08TEIoURpNmcATJ3aBLF/Me+ X-Received: by 2002:a17:902:5851:: with SMTP id f17-v6mr1172362plj.32.1527226850356; Thu, 24 May 2018 22:40:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527226850; cv=none; d=google.com; s=arc-20160816; b=M9NT3O+heda79ckuJOJoujDeOqQI8IcvgamXL04nWYa8x8yziVTNpqGNBhpt9bq/xP udpLjIHYk8YsI3ANvQ4oguiYZM+jKZOjeBecLQkQ2t9MSsesUhRUAUQ9/zgr69gTSruD 0ilyDROAoSJ39j6DtMADOE0106wUVVxJuJhyuAG4sFOBG7TFAGtibLH8Abp5ym+mkQRB H8xt5lYmG6RhHVAJ7W9nXlXLSjD/ds4N1gBSjpw+2CYZZY2N7lsdnVJ9Xyrg6pjW6maV 97oYI4yTluemvs8fpr+WpCXFnm3NxDsrnWhJyeWpsGtKlsCIWnZ3sfuZTbX7nBjLo/Rd PZ+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=0R4yxojOPc8DMkNP+2+XwqTUa9Wws43ZzgN5jtGILvc=; b=VrEIlQt8wVhYXkiO3GsmKMwJkoBueVNXkoLrBE629lFNpCL1dMbYYcFzz1IlUYbmYl K9QU0FBbGehW9/FQTa8gOwiBSErhdPxoz9VK046zOFC4Ad4VW3hr+TvcscGGBoOMTEGG uJNbI52L9zZzZ+IoeZmrxuHDoGjN3QXNqg3hvAxUvUQdM6Ckkw94QYEdeBfW5FXT9EgG gkpx53xG5rHkhhifyNp3wZW0BDXa7jHU7Z5RjAlnQ5WTQZmndpkMIakay4GOhwRxGpAS ctcaU8lI64wVAVbMsPFvf1b8Sgcka998m3bafbmXMZMJgd68xD6lKHQywnUBtFu/Z0VN K4/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=d/zmHH+J; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y9-v6si23400629pfk.34.2018.05.24.22.40.50; Thu, 24 May 2018 22:40:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=d/zmHH+J; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935835AbeEYFkr (ORCPT + 30 others); Fri, 25 May 2018 01:40:47 -0400 Received: from mail-pl0-f67.google.com ([209.85.160.67]:45122 "EHLO mail-pl0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964947AbeEYFkl (ORCPT ); Fri, 25 May 2018 01:40:41 -0400 Received: by mail-pl0-f67.google.com with SMTP id bi12-v6so2450358plb.12 for ; Thu, 24 May 2018 22:40:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=0R4yxojOPc8DMkNP+2+XwqTUa9Wws43ZzgN5jtGILvc=; b=d/zmHH+JWhIDThSRy/cZ01hDHm5bv44LmAxGmS6gnOHSOUzJo1V2KDlPL+zj6NcreG 24bLrxc9fXqrDLbUM3thwFqOAmsRHOVrL9rHXUnBPt2HkjXTS2TjLtX/bY3/QwB43IQk Zz7asRRPp/5TUJ/trxOjyDG5eKKV2mTRwFUFc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=0R4yxojOPc8DMkNP+2+XwqTUa9Wws43ZzgN5jtGILvc=; b=cRCiAarvY8EbYrqwq1MJaHQGbGRJBtJchWLHXxM8lX7eUqY44+I8orRbzcfvcmSSly WsDlQbLXpfB6/wJ08XNYXhWThRn1JqL6yw4z9bXjp8MPo2Hu8PubN4YrAmILto9qwWNj 550lT1JnHnGgHZy4b5UF/l2jSiptK3VKk5EDyGqUxXhwwKsUY67JnCkXWCy8DW5RPhc3 ZBUOACi2khTOctBZSWPV+CDNr287MlsgA6VTTgCTLmILD+N/LNZcirggPBT0CPOhl79p ImEn7BxxAMRYaNj1BIBQ6XReHGkjE/Vchw+WuwFCO1pJXz/LK4zVMsrWIdp3Jwekx/gC MEaw== X-Gm-Message-State: ALKqPwcoEz6d9xzOrbmIKqSc8D7IGZIZJ+rmc6xI8+6RB6v7UVmjizNp zsfZT1Q7VVa+6HYEac0eia3jwQ== X-Received: by 2002:a17:902:d20c:: with SMTP id t12-v6mr1115186ply.364.1527226841306; Thu, 24 May 2018 22:40:41 -0700 (PDT) Received: from localhost ([122.172.112.176]) by smtp.gmail.com with ESMTPSA id p6-v6sm43193894pfg.157.2018.05.24.22.40.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 24 May 2018 22:40:40 -0700 (PDT) From: Viresh Kumar To: arm@kernel.org, Matthias Brugger , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon Cc: Viresh Kumar , Vincent Guittot , ionela.voinescu@arm.com, Daniel Lezcano , chris.redpath@arm.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/6] arm64: dts: mediatek: Add missing cooling device properties for CPUs Date: Fri, 25 May 2018 11:10:04 +0530 Message-Id: <49b1086c104b0ee22f6e992a0abb380de9320c09.1527225682.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.15.0.194.g9af6a3dea062 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Signed-off-by: Viresh Kumar --- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 1 + arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 ++ 2 files changed, 3 insertions(+) -- 2.15.0.194.g9af6a3dea062 diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 9213c966c224..d49fe125e770 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -89,6 +89,7 @@ <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; enable-method = "psci"; clock-frequency = <1300000000>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 94597e33c806..abd2f15a544b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -168,6 +168,7 @@ reg = <0x001>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + #cooling-cells = <2>; clocks = <&infracfg CLK_INFRA_CA53SEL>, <&apmixedsys CLK_APMIXED_MAINPLL>; clock-names = "cpu", "intermediate"; @@ -193,6 +194,7 @@ reg = <0x101>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; + #cooling-cells = <2>; clocks = <&infracfg CLK_INFRA_CA57SEL>, <&apmixedsys CLK_APMIXED_MAINPLL>; clock-names = "cpu", "intermediate"; From patchwork Fri May 25 05:40:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 136778 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp3130058lji; Thu, 24 May 2018 22:41:16 -0700 (PDT) X-Google-Smtp-Source: AB8JxZo2FR7gGwC0dEV/QcEqFFgfG8L4r4J/q0PVmo/KA+Pmhxz7p+HJxtfUhLhOYfE1veya1JHA X-Received: by 2002:a65:665a:: with SMTP id z26-v6mr831839pgv.302.1527226876670; Thu, 24 May 2018 22:41:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1527226876; cv=none; d=google.com; s=arc-20160816; b=pSx3NlQ24HUVBTgtmwU9ST8K2EHV4Xg4P1yg44Dus3dIQPoWucd3io66qdBurhtPu4 kRo5YPD9hAEuEVQj4ARSyKSDhD9R352Xq2wB0Ie5g/LSo7iTx+TE42ypLtTplUSht+pR qhdwm4kc1smUFBX9O1GYz+AEk1locF76x2AkjkTeYIUvY40Uy9Bv89OvN9jHNzX76aFH +odhaiuqChM7wTcBDi2gj4TfC5wilGLvwxV3+UKfaAmA9yadAJM9RnuwFmHOUxfDbGUL ms6pdetT3KYllPWtdAAerp1vFxhli7AqFwZSi6xSzceHT6gIIjaPPJ8pyxQb0NX7e61m vrJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=R7AXhcykQKSlSx5Ebfq4WSBNV+A2kPnqRSDfYr9KGp0=; b=bRqyEsy3z0D/iT/MIKr5ohxrSppZpQ9LgKDeChb3Z5BV9qWIOuPDF+wY5Nq9JXGhuq l2GD9rM+n4MftQOJbo5cY9VdWOlPX5k35uPbvVidEfoea+7r96AFkqf7PtPDrAHc1udG Lu2TtD7l/8q9sk4bw17Xogu4ZtUVGsAI+vwpK7+owcJkBvyXXb3/YU4cZFl4kGG/+Y99 eAuKEPP4HfBApODIIuYw1Gh+lD52Yti3vM9cwF/gjF1F4Gaiig7d8veKH9m2P/QDho5K O+aHy41Z0paDmSkKCLvLjiST744AJXGPKoYU90JAHYrKma2u0j0+HVkxs64yLjVKKk4p Xd2w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cPgiKd02; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 1-v6si22177672plz.101.2018.05.24.22.41.16; Thu, 24 May 2018 22:41:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cPgiKd02; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935872AbeEYFlO (ORCPT + 30 others); Fri, 25 May 2018 01:41:14 -0400 Received: from mail-pl0-f66.google.com ([209.85.160.66]:33012 "EHLO mail-pl0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964969AbeEYFkp (ORCPT ); Fri, 25 May 2018 01:40:45 -0400 Received: by mail-pl0-f66.google.com with SMTP id n10-v6so2465922plp.0 for ; Thu, 24 May 2018 22:40:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=R7AXhcykQKSlSx5Ebfq4WSBNV+A2kPnqRSDfYr9KGp0=; b=cPgiKd02y50IKgzkkBC0yh15c8el4N1As1RE3gi7AWPk6Tcme1ScYa5/hwjGZQJ1Md 5AL3E7OCZ08bmCCc00C7dvApnizXed5zN7StPLkUaAyotiiaU2liBFu1PR+Srjm+X56d ZvQag95ViOO/jtZ5UDZdssPrDqMG56OGdhMdM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=R7AXhcykQKSlSx5Ebfq4WSBNV+A2kPnqRSDfYr9KGp0=; b=P/NsMVK6TxTT10+nvTH/dXhzalSGF28FGWcndhyAQSaQcuUWoz3KfoeINEkcJGUkoU O91V7wdtdKLb4ZivXLuiIqn9j/ioYwa5gVR1QPLIDzGWItjqWV6vBus0pQilreqCht6f BMKCcCV9MmZAkp72t4bwhw7Au7AO0kq5uAedPKkAl2rL+CiZZ9W7taGpHAKXDjLFg7Z6 MECyOQ3NrAVBjYT//cqywGmCxsYkC2RMM4oBxiYo0CSOhK9BFhBEQ9540w6pE8QtQ+4d SOt+e5zliZP5fK7LVHAD/PwwCdjYHnGYCY9+BLDn3DY/rtiNVVQBsJM/bAxI4aRXNUgg TB4A== X-Gm-Message-State: ALKqPwegiH5QQRizXkAYcfBW1jZ024dtWZ+3ShK2lzLKXapCqHKiaM/u 4BHyDBIZqoqFaUf+Q1oqHetLNg== X-Received: by 2002:a17:902:4303:: with SMTP id i3-v6mr1147597pld.394.1527226844899; Thu, 24 May 2018 22:40:44 -0700 (PDT) Received: from localhost ([122.172.112.176]) by smtp.gmail.com with ESMTPSA id t14-v6sm49892747pfh.109.2018.05.24.22.40.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 24 May 2018 22:40:44 -0700 (PDT) From: Viresh Kumar To: arm@kernel.org, Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , Heiko Stuebner Cc: Viresh Kumar , Vincent Guittot , ionela.voinescu@arm.com, Daniel Lezcano , chris.redpath@arm.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/6] arm64: dts: rockchip: Add missing cooling device properties for CPUs Date: Fri, 25 May 2018 11:10:05 +0530 Message-Id: X-Mailer: git-send-email 2.15.0.194.g9af6a3dea062 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Do minor rearrangement as well to keep ordering consistent. Signed-off-by: Viresh Kumar --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 3 +++ arch/arm64/boot/dts/rockchip/rk3368.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/rockchip/rk3399.dtsi | 8 ++++++-- 3 files changed, 21 insertions(+), 2 deletions(-) -- 2.15.0.194.g9af6a3dea062 diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index b8e9da15e00c..902a0907ad34 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -89,6 +89,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x1>; clocks = <&cru ARMCLK>; + #cooling-cells = <2>; dynamic-power-coefficient = <120>; enable-method = "psci"; next-level-cache = <&l2>; @@ -100,6 +101,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x2>; clocks = <&cru ARMCLK>; + #cooling-cells = <2>; dynamic-power-coefficient = <120>; enable-method = "psci"; next-level-cache = <&l2>; @@ -111,6 +113,7 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x3>; clocks = <&cru ARMCLK>; + #cooling-cells = <2>; dynamic-power-coefficient = <120>; enable-method = "psci"; next-level-cache = <&l2>; diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi index ad91ced78649..c32f2a551a1f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi @@ -122,6 +122,8 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x1>; enable-method = "psci"; + + #cooling-cells = <2>; /* min followed by max */ }; cpu_l2: cpu@2 { @@ -129,6 +131,8 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x2>; enable-method = "psci"; + + #cooling-cells = <2>; /* min followed by max */ }; cpu_l3: cpu@3 { @@ -136,6 +140,8 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x3>; enable-method = "psci"; + + #cooling-cells = <2>; /* min followed by max */ }; cpu_b0: cpu@100 { @@ -152,6 +158,8 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x101>; enable-method = "psci"; + + #cooling-cells = <2>; /* min followed by max */ }; cpu_b2: cpu@102 { @@ -159,6 +167,8 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x102>; enable-method = "psci"; + + #cooling-cells = <2>; /* min followed by max */ }; cpu_b3: cpu@103 { @@ -166,6 +176,8 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x103>; enable-method = "psci"; + + #cooling-cells = <2>; /* min followed by max */ }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index e0040b648f43..da935383a8f2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -108,8 +108,8 @@ compatible = "arm,cortex-a53", "arm,armv8"; reg = <0x0 0x0>; enable-method = "psci"; - #cooling-cells = <2>; /* min followed by max */ clocks = <&cru ARMCLKL>; + #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; }; @@ -119,6 +119,7 @@ reg = <0x0 0x1>; enable-method = "psci"; clocks = <&cru ARMCLKL>; + #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; }; @@ -128,6 +129,7 @@ reg = <0x0 0x2>; enable-method = "psci"; clocks = <&cru ARMCLKL>; + #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; }; @@ -137,6 +139,7 @@ reg = <0x0 0x3>; enable-method = "psci"; clocks = <&cru ARMCLKL>; + #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <100>; }; @@ -145,8 +148,8 @@ compatible = "arm,cortex-a72", "arm,armv8"; reg = <0x0 0x100>; enable-method = "psci"; - #cooling-cells = <2>; /* min followed by max */ clocks = <&cru ARMCLKB>; + #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <436>; }; @@ -156,6 +159,7 @@ reg = <0x0 0x101>; enable-method = "psci"; clocks = <&cru ARMCLKB>; + #cooling-cells = <2>; /* min followed by max */ dynamic-power-coefficient = <436>; }; }; From patchwork Fri May 25 05:40:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 136777 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp3129762lji; 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[209.132.180.67]) by mx.google.com with ESMTP id y9-v6si23400629pfk.34.2018.05.24.22.40.54; Thu, 24 May 2018 22:40:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EwFiUJ4r; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964986AbeEYFkw (ORCPT + 30 others); Fri, 25 May 2018 01:40:52 -0400 Received: from mail-pl0-f67.google.com ([209.85.160.67]:39435 "EHLO mail-pl0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935837AbeEYFkt (ORCPT ); Fri, 25 May 2018 01:40:49 -0400 Received: by mail-pl0-f67.google.com with SMTP id f1-v6so2015694plt.6 for ; Thu, 24 May 2018 22:40:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=EY5ErDzTc6jujkgqTPyqlWRwSTcheDMa2bHxN0W1Vbo=; b=EwFiUJ4rLKrPm0vIyqaGpVP2lBVgzhBpQw0OPfVp1yOkBMb+QIzGcjeyqMH+9EiWEH tK6UxYqPbxbVt5PEvvnuLOzVoCD/XGsO/C+pzJAWVFbpR5nEmrKsSNH3oHwwuyFXs9RY zXqqIxL45pEfLaPJuBRi9AVbvgX/S4VzhZXJA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=EY5ErDzTc6jujkgqTPyqlWRwSTcheDMa2bHxN0W1Vbo=; b=qKXiLyWmYJ/f13yOvWQr4ic46IlZRphmOn0yuJgUKrSOAd5MsaDKc14sKzs30NfyI2 ZjQ2SKANs+sJ0VFJezTsiFTAqYghRx35wqeUX9fgwNbE5BnAt2a0FR+vcP8b9ylKEvk9 +WPU6L7I2qexqNvDhGFIUXC2c/rVmYI5G9/nhF3ElrF8tiwMbcxq5M54nfFiOSZZ/9PQ INSENpAMbq9VYWUP1RWl8sPCnmMp87wzsE92ACVkf15eUSaw9rhFPgCbI6XvpTigjOVP diZH7h1Bjgrx0r4XvLX2hRNCeyycUzjJlXRFR4+H5VZtk0VlVCy+1L6Llzr56sksbe6D Ssdg== X-Gm-Message-State: ALKqPwdvxtzhs2E2RUnYHsYJAEb/e8A1bb0P9fvcyxfjrAZgqsVYlKQH QVktMPdez1i7FJPkEEnQM1UY2Q== X-Received: by 2002:a17:902:6b44:: with SMTP id g4-v6mr1108688plt.390.1527226848492; Thu, 24 May 2018 22:40:48 -0700 (PDT) Received: from localhost ([122.172.112.176]) by smtp.gmail.com with ESMTPSA id w19-v6sm28253054pgv.59.2018.05.24.22.40.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 24 May 2018 22:40:47 -0700 (PDT) From: Viresh Kumar To: arm@kernel.org, Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , Masahiro Yamada Cc: Viresh Kumar , Vincent Guittot , ionela.voinescu@arm.com, Daniel Lezcano , chris.redpath@arm.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/6] arm64: dts: socionext: Add missing cooling device properties for CPUs Date: Fri, 25 May 2018 11:10:06 +0530 Message-Id: <744f4c0a9a6f0d3acfc36e49ef62f17f53831b3b.1527225682.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.15.0.194.g9af6a3dea062 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Signed-off-by: Viresh Kumar --- arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 ++ 1 file changed, 2 insertions(+) -- 2.15.0.194.g9af6a3dea062 diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index 3a5ed789c056..10ffb5019013 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -58,6 +58,7 @@ clocks = <&sys_clk 32>; enable-method = "psci"; operating-points-v2 = <&cluster0_opp>; + #cooling-cells = <2>; }; cpu2: cpu@100 { @@ -77,6 +78,7 @@ clocks = <&sys_clk 33>; enable-method = "psci"; operating-points-v2 = <&cluster1_opp>; + #cooling-cells = <2>; }; };