From patchwork Thu Apr 8 12:39:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qingfang Deng X-Patchwork-Id: 418708 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31997C433B4 for ; Thu, 8 Apr 2021 12:39:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0D24261026 for ; Thu, 8 Apr 2021 12:39:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231567AbhDHMjt (ORCPT ); Thu, 8 Apr 2021 08:39:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55854 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229741AbhDHMjt (ORCPT ); Thu, 8 Apr 2021 08:39:49 -0400 Received: from mail-pf1-x430.google.com (mail-pf1-x430.google.com [IPv6:2607:f8b0:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D5F3C061760; Thu, 8 Apr 2021 05:39:38 -0700 (PDT) Received: by mail-pf1-x430.google.com with SMTP id l123so1707395pfl.8; Thu, 08 Apr 2021 05:39:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=n4wqHMiN29lzV6muE8pN4a6Ibkd52ctj3SwR+DOuyIE=; b=myl1K0+w0+1r1+Vd8CU+eSLoUnmGJ13NizjkOwGT5McXLJp4i4biKLfToFr1efN0pS DsiErq84Yb/KLIdNKmt7+Y9knMUH2E0btjQX7AJoptL9G+jWMVwhuNZDq8ihmQjB5tY0 XddaR892sh8gUMholPbYwPsNsTwoZkkLczfxQD8TpRVqlDdzQRMlD2ilZefABrPMBB5+ 0YmHEbk2+fkfw+5hMC3Or57kBaOAvfrWTwfG2oPumWb8nmOl3tbLlgzZbsn5goipBY59 5Q04wY5HMlEUMw979yQIYEkPXH5mLJ5oUErCbP7lF0xeg364VJSxK7tthZQzfIF0ciLd QucA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=n4wqHMiN29lzV6muE8pN4a6Ibkd52ctj3SwR+DOuyIE=; b=uAMIOeBWTPxKskgnSAeRyvKPLr4LHSa7e+4+LV0kwA1d6YN+U+W9SAjDSb/48yNxTm lSjgJXk412xLUCnCYyyft1ZUcNh2Anrma4r84U6IB8S7nONJU+ajM6Xc3IsOjQiYKKz2 +lD/VoQAPbZ2343kd8AV0bzcGAv5+H5KFOVY5Q/GYvj0IhOi+0qfcZ6P/Xl5ajHA4xGI T1uWC92Re+FrSs0eGBFVbpPQ73YdOCVhSxG0hIA3vpeth7KC96kg6L+88tGsTS4GuUHn Gq7/g6xEKnCw5LoCzkC45OBThFtNOwRoMRHjUT0+tAt8rUe26wKNDdckcLJDTwd9FRwf eAXw== X-Gm-Message-State: AOAM5310rYmS0paqg3MwgqX+lJxEG5Y3m4kEdBdIsDbwgRtzT+y/sLOM Bd2gm1/pBToGauOk+wBm/CI= X-Google-Smtp-Source: ABdhPJwUcMhWWlJb1haZYAryuyyVs8e7/OQeBjb8LJ0KSxr3RO/9MqLXQ1l+Sr+8Ts2f6bVHkyDJdw== X-Received: by 2002:aa7:9804:0:b029:1f1:5340:77c1 with SMTP id e4-20020aa798040000b02901f1534077c1mr7384855pfl.72.1617885577843; Thu, 08 Apr 2021 05:39:37 -0700 (PDT) Received: from localhost.localdomain ([138.197.212.246]) by smtp.gmail.com with ESMTPSA id e65sm25831311pfe.9.2021.04.08.05.39.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Apr 2021 05:39:37 -0700 (PDT) From: DENG Qingfang To: "David S. Miller" , Andrew Lunn , Florian Fainelli , Heiner Kallweit , Jakub Kicinski , Landen Chao , Matthias Brugger , Russell King , Sean Wang , Vivien Didelot , Vladimir Oltean , Rob Herring , Linus Walleij , Greg Kroah-Hartman , Sergio Paracuellos , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-staging@lists.linux.dev, devicetree@vger.kernel.org, netdev@vger.kernel.org Cc: Weijie Gao , Chuanhong Guo , =?utf-8?q?Ren=C3=A9_van_Dorst?= , Frank Wunderlich , Thomas Gleixner , Marc Zyngier Subject: [RFC v3 net-next 1/4] net: phy: add MediaTek PHY driver Date: Thu, 8 Apr 2021 20:39:16 +0800 Message-Id: <20210408123919.2528516-2-dqfext@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210408123919.2528516-1-dqfext@gmail.com> References: <20210408123919.2528516-1-dqfext@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add support for MediaTek PHYs found in MT7530 and MT7531 switches. The initialization procedure is from the vendor driver, but due to lack of documentation, the function of some register values remains unknown. Signed-off-by: DENG Qingfang Reviewed-by: Andrew Lunn --- RFC v2 -> RFC v3: - No changes. drivers/net/phy/Kconfig | 5 ++ drivers/net/phy/Makefile | 1 + drivers/net/phy/mediatek.c | 112 +++++++++++++++++++++++++++++++++++++ 3 files changed, 118 insertions(+) create mode 100644 drivers/net/phy/mediatek.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index a615b3660b05..edd858cec9ec 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -207,6 +207,11 @@ config MARVELL_88X2222_PHY Support for the Marvell 88X2222 Dual-port Multi-speed Ethernet Transceiver. +config MEDIATEK_PHY + tristate "MediaTek PHYs" + help + Supports the MediaTek switch integrated PHYs. + config MICREL_PHY tristate "Micrel PHYs" help diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index de683e3abe63..9ed7dbab7770 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -64,6 +64,7 @@ obj-$(CONFIG_LXT_PHY) += lxt.o obj-$(CONFIG_MARVELL_10G_PHY) += marvell10g.o obj-$(CONFIG_MARVELL_PHY) += marvell.o obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o +obj-$(CONFIG_MEDIATEK_PHY) += mediatek.o obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o obj-$(CONFIG_MICREL_PHY) += micrel.o diff --git a/drivers/net/phy/mediatek.c b/drivers/net/phy/mediatek.c new file mode 100644 index 000000000000..1faed57e2ed9 --- /dev/null +++ b/drivers/net/phy/mediatek.c @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include +#include +#include + +#define MTK_EXT_PAGE_ACCESS 0x1f +#define MTK_PHY_PAGE_STANDARD 0x0000 +#define MTK_PHY_PAGE_EXTENDED 0x0001 +#define MTK_PHY_PAGE_EXTENDED_2 0x0002 +#define MTK_PHY_PAGE_EXTENDED_3 0x0003 +#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 +#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 + +static int mtk_phy_read_page(struct phy_device *phydev) +{ + return __phy_read(phydev, MTK_EXT_PAGE_ACCESS); +} + +static int mtk_phy_write_page(struct phy_device *phydev, int page) +{ + return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page); +} + +static void mtk_phy_config_init(struct phy_device *phydev) +{ + /* Disable EEE */ + phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); + + /* Enable HW auto downshift */ + phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4)); + + /* Increase SlvDPSready time */ + phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); + __phy_write(phydev, 0x10, 0xafae); + __phy_write(phydev, 0x12, 0x2f); + __phy_write(phydev, 0x10, 0x8fae); + phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); + + /* Adjust 100_mse_threshold */ + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff); + + /* Disable mcc */ + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300); +} + +static int mt7530_phy_config_init(struct phy_device *phydev) +{ + mtk_phy_config_init(phydev); + + /* Increase post_update_timer */ + phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b); + + return 0; +} + +static int mt7531_phy_config_init(struct phy_device *phydev) +{ + if (phydev->interface != PHY_INTERFACE_MODE_INTERNAL) + return -EINVAL; + + mtk_phy_config_init(phydev); + + /* PHY link down power saving enable */ + phy_set_bits(phydev, 0x17, BIT(4)); + phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300); + + /* Set TX Pair delay selection */ + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404); + phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404); + + return 0; +} + +static struct phy_driver mtk_phy_driver[] = { + { + PHY_ID_MATCH_EXACT(0x03a29412), + .name = "MediaTek MT7530 PHY", + .config_init = mt7530_phy_config_init, + /* Interrupts are handled by the switch, not the PHY + * itself. + */ + .config_intr = genphy_no_config_intr, + .handle_interrupt = genphy_handle_interrupt_no_ack, + .read_page = mtk_phy_read_page, + .write_page = mtk_phy_write_page, + }, + { + PHY_ID_MATCH_EXACT(0x03a29441), + .name = "MediaTek MT7531 PHY", + .config_init = mt7531_phy_config_init, + /* Interrupts are handled by the switch, not the PHY + * itself. + */ + .config_intr = genphy_no_config_intr, + .handle_interrupt = genphy_handle_interrupt_no_ack, + .read_page = mtk_phy_read_page, + .write_page = mtk_phy_write_page, + }, +}; + +module_phy_driver(mtk_phy_driver); + +static struct mdio_device_id __maybe_unused mtk_phy_tbl[] = { + { PHY_ID_MATCH_VENDOR(0x03a29400) }, + { } +}; + +MODULE_DESCRIPTION("MediaTek switch integrated PHY driver"); +MODULE_AUTHOR("DENG, Qingfang "); +MODULE_LICENSE("GPL"); + +MODULE_DEVICE_TABLE(mdio, mtk_phy_tbl); From patchwork Thu Apr 8 12:39:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qingfang Deng X-Patchwork-Id: 418021 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5EF38C433B4 for ; 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Thu, 08 Apr 2021 05:39:45 -0700 (PDT) Received: from localhost.localdomain ([138.197.212.246]) by smtp.gmail.com with ESMTPSA id e65sm25831311pfe.9.2021.04.08.05.39.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Apr 2021 05:39:44 -0700 (PDT) From: DENG Qingfang To: "David S. Miller" , Andrew Lunn , Florian Fainelli , Heiner Kallweit , Jakub Kicinski , Landen Chao , Matthias Brugger , Russell King , Sean Wang , Vivien Didelot , Vladimir Oltean , Rob Herring , Linus Walleij , Greg Kroah-Hartman , Sergio Paracuellos , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-staging@lists.linux.dev, devicetree@vger.kernel.org, netdev@vger.kernel.org Cc: Weijie Gao , Chuanhong Guo , =?utf-8?q?Ren=C3=A9_van_Dorst?= , Frank Wunderlich , Thomas Gleixner , Marc Zyngier Subject: [RFC v3 net-next 2/4] net: dsa: mt7530: add interrupt support Date: Thu, 8 Apr 2021 20:39:17 +0800 Message-Id: <20210408123919.2528516-3-dqfext@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210408123919.2528516-1-dqfext@gmail.com> References: <20210408123919.2528516-1-dqfext@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add support for MT7530 interrupt controller to handle internal PHYs. In order to assign an IRQ number to each PHY, the registration of MDIO bus is also done in this driver. Signed-off-by: DENG Qingfang --- RFC v2 -> RFC v3: - Rework IRQ request and free procedure. - Add irq_set_nested_thread. - Move mt753x_phy_{read,write} functions. drivers/net/dsa/Kconfig | 1 + drivers/net/dsa/mt7530.c | 266 +++++++++++++++++++++++++++++++++++---- drivers/net/dsa/mt7530.h | 20 ++- 3 files changed, 258 insertions(+), 29 deletions(-) diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig index a5f1aa911fe2..264384449f09 100644 --- a/drivers/net/dsa/Kconfig +++ b/drivers/net/dsa/Kconfig @@ -36,6 +36,7 @@ config NET_DSA_LANTIQ_GSWIP config NET_DSA_MT7530 tristate "MediaTek MT753x and MT7621 Ethernet switch support" select NET_DSA_TAG_MTK + select MEDIATEK_PHY help This enables support for the MediaTek MT7530, MT7531, and MT7621 Ethernet switch chips. diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 2bd1bab71497..da033004a74d 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -596,18 +597,14 @@ mt7530_mib_reset(struct dsa_switch *ds) mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); } -static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum) +static int mt7530_phy_read(struct mt7530_priv *priv, int port, int regnum) { - struct mt7530_priv *priv = ds->priv; - return mdiobus_read_nested(priv->bus, port, regnum); } -static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum, +static int mt7530_phy_write(struct mt7530_priv *priv, int port, int regnum, u16 val) { - struct mt7530_priv *priv = ds->priv; - return mdiobus_write_nested(priv->bus, port, regnum, val); } @@ -785,9 +782,8 @@ mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, } static int -mt7531_ind_phy_read(struct dsa_switch *ds, int port, int regnum) +mt7531_ind_phy_read(struct mt7530_priv *priv, int port, int regnum) { - struct mt7530_priv *priv = ds->priv; int devad; int ret; @@ -803,10 +799,9 @@ mt7531_ind_phy_read(struct dsa_switch *ds, int port, int regnum) } static int -mt7531_ind_phy_write(struct dsa_switch *ds, int port, int regnum, +mt7531_ind_phy_write(struct mt7530_priv *priv, int port, int regnum, u16 data) { - struct mt7530_priv *priv = ds->priv; int devad; int ret; @@ -822,6 +817,22 @@ mt7531_ind_phy_write(struct dsa_switch *ds, int port, int regnum, return ret; } +static int +mt753x_phy_read(struct mii_bus *bus, int port, int regnum) +{ + struct mt7530_priv *priv = bus->priv; + + return priv->info->phy_read(priv, port, regnum); +} + +static int +mt753x_phy_write(struct mii_bus *bus, int port, int regnum, u16 val) +{ + struct mt7530_priv *priv = bus->priv; + + return priv->info->phy_write(priv, port, regnum, val); +} + static void mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data) @@ -1828,6 +1839,211 @@ mt7530_setup_gpio(struct mt7530_priv *priv) } #endif /* CONFIG_GPIOLIB */ +static irqreturn_t +mt7530_irq_thread_fn(int irq, void *dev_id) +{ + struct mt7530_priv *priv = dev_id; + bool handled = false; + u32 val; + int p; + + mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); + val = mt7530_mii_read(priv, MT7530_SYS_INT_STS); + mt7530_mii_write(priv, MT7530_SYS_INT_STS, val); + mutex_unlock(&priv->bus->mdio_lock); + + for (p = 0; p < MT7530_NUM_PHYS; p++) { + if (BIT(p) & val) { + unsigned int irq; + + irq = irq_find_mapping(priv->irq_domain, p); + handle_nested_irq(irq); + handled = true; + } + } + + return IRQ_RETVAL(handled); +} + +static void +mt7530_irq_mask(struct irq_data *d) +{ + struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); + + priv->irq_enable &= ~BIT(d->hwirq); +} + +static void +mt7530_irq_unmask(struct irq_data *d) +{ + struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); + + priv->irq_enable |= BIT(d->hwirq); +} + +static void +mt7530_irq_bus_lock(struct irq_data *d) +{ + struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); + + mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); +} + +static void +mt7530_irq_bus_sync_unlock(struct irq_data *d) +{ + struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); + + mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); + mutex_unlock(&priv->bus->mdio_lock); +} + +static struct irq_chip mt7530_irq_chip = { + .name = KBUILD_MODNAME, + .irq_mask = mt7530_irq_mask, + .irq_unmask = mt7530_irq_unmask, + .irq_bus_lock = mt7530_irq_bus_lock, + .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock, +}; + +static int +mt7530_irq_map(struct irq_domain *domain, unsigned int irq, + irq_hw_number_t hwirq) +{ + irq_set_chip_data(irq, domain->host_data); + irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq); + irq_set_nested_thread(irq, true); + irq_set_noprobe(irq); + + return 0; +} + +static const struct irq_domain_ops mt7530_irq_domain_ops = { + .map = mt7530_irq_map, + .xlate = irq_domain_xlate_onecell, +}; + +static void +mt7530_setup_mdio_irq(struct mt7530_priv *priv) +{ + struct dsa_switch *ds = priv->ds; + int p; + + for (p = 0; p < MT7530_NUM_PHYS; p++) { + if (BIT(p) & ds->phys_mii_mask) { + unsigned int irq; + + irq = irq_create_mapping(priv->irq_domain, p); + ds->slave_mii_bus->irq[p] = irq; + } + } +} + +static int +mt7530_setup_irq(struct mt7530_priv *priv) +{ + struct device *dev = priv->dev; + struct device_node *np = dev->of_node; + int ret; + + if (!of_property_read_bool(np, "interrupt-controller")) { + dev_info(dev, "no interrupt support\n"); + return 0; + } + + priv->irq = of_irq_get(np, 0); + if (priv->irq <= 0) { + dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); + return priv->irq ? : -EINVAL; + } + + priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, + &mt7530_irq_domain_ops, priv); + if (!priv->irq_domain) { + dev_err(dev, "failed to create IRQ domain\n"); + return -ENOMEM; + } + + /* This register must be set for MT7530 to properly fire interrupts */ + if (priv->id != ID_MT7531) + mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); + + ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, + IRQF_ONESHOT, KBUILD_MODNAME, priv); + if (ret) { + irq_domain_remove(priv->irq_domain); + dev_err(dev, "failed to request IRQ: %d\n", ret); + return ret; + } + + return 0; +} + +static void +mt7530_free_mdio_irq(struct mt7530_priv *priv) +{ + int p; + + for (p = 0; p < MT7530_NUM_PHYS; p++) { + if (BIT(p) & priv->ds->phys_mii_mask) { + unsigned int irq; + + irq = irq_find_mapping(priv->irq_domain, p); + irq_dispose_mapping(irq); + } + } +} + + +static void +mt7530_free_irq_common(struct mt7530_priv *priv) +{ + free_irq(priv->irq, priv); + irq_domain_remove(priv->irq_domain); +} + +static void +mt7530_free_irq(struct mt7530_priv *priv) +{ + mt7530_free_mdio_irq(priv); + mt7530_free_irq_common(priv); +} + +static int +mt7530_setup_mdio(struct mt7530_priv *priv) +{ + struct dsa_switch *ds = priv->ds; + struct device *dev = priv->dev; + struct mii_bus *bus; + static int idx; + int ret; + + bus = devm_mdiobus_alloc(dev); + if (!bus) + return -ENOMEM; + + ds->slave_mii_bus = bus; + bus->priv = priv; + bus->name = KBUILD_MODNAME "-mii"; + snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); + bus->read = mt753x_phy_read; + bus->write = mt753x_phy_write; + bus->parent = dev; + bus->phy_mask = ~ds->phys_mii_mask; + + if (priv->irq) + mt7530_setup_mdio_irq(priv); + + ret = mdiobus_register(bus); + if (ret) { + dev_err(dev, "failed to register MDIO bus: %d\n", ret); + if (priv->irq) + mt7530_free_mdio_irq(priv); + } + + return ret; +} + static int mt7530_setup(struct dsa_switch *ds) { @@ -2780,32 +2996,25 @@ static int mt753x_setup(struct dsa_switch *ds) { struct mt7530_priv *priv = ds->priv; + int ret = priv->info->sw_setup(ds); + if (ret) + return ret; - return priv->info->sw_setup(ds); -} - -static int -mt753x_phy_read(struct dsa_switch *ds, int port, int regnum) -{ - struct mt7530_priv *priv = ds->priv; - - return priv->info->phy_read(ds, port, regnum); -} + ret = mt7530_setup_irq(priv); + if (ret) + return ret; -static int -mt753x_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) -{ - struct mt7530_priv *priv = ds->priv; + ret = mt7530_setup_mdio(priv); + if (ret && priv->irq) + mt7530_free_irq_common(priv); - return priv->info->phy_write(ds, port, regnum, val); + return ret; } static const struct dsa_switch_ops mt7530_switch_ops = { .get_tag_protocol = mtk_get_tag_protocol, .setup = mt753x_setup, .get_strings = mt7530_get_strings, - .phy_read = mt753x_phy_read, - .phy_write = mt753x_phy_write, .get_ethtool_stats = mt7530_get_ethtool_stats, .get_sset_count = mt7530_get_sset_count, .set_ageing_time = mt7530_set_ageing_time, @@ -2986,6 +3195,9 @@ mt7530_remove(struct mdio_device *mdiodev) dev_err(priv->dev, "Failed to disable io pwr: %d\n", ret); + if (priv->irq) + mt7530_free_irq(priv); + dsa_unregister_switch(priv->ds); mutex_destroy(&priv->reg_mutex); } diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index ec36ea5dfd57..62fcaabefba1 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -7,6 +7,7 @@ #define __MT7530_H #define MT7530_NUM_PORTS 7 +#define MT7530_NUM_PHYS 5 #define MT7530_CPU_PORT 6 #define MT7530_NUM_FDB_RECORDS 2048 #define MT7530_ALL_MEMBERS 0xff @@ -381,6 +382,12 @@ enum mt7531_sgmii_force_duplex { #define SYS_CTRL_SW_RST BIT(1) #define SYS_CTRL_REG_RST BIT(0) +/* Register for system interrupt */ +#define MT7530_SYS_INT_EN 0x7008 + +/* Register for system interrupt status */ +#define MT7530_SYS_INT_STS 0x700c + /* Register for PHY Indirect Access Control */ #define MT7531_PHY_IAC 0x701C #define MT7531_PHY_ACS_ST BIT(31) @@ -702,6 +709,8 @@ static const char *p5_intf_modes(unsigned int p5_interface) } } +struct mt7530_priv; + /* struct mt753x_info - This is the main data structure for holding the specific * part for each supported device * @sw_setup: Holding the handler to a device initialization @@ -726,8 +735,8 @@ struct mt753x_info { enum mt753x_id id; int (*sw_setup)(struct dsa_switch *ds); - int (*phy_read)(struct dsa_switch *ds, int port, int regnum); - int (*phy_write)(struct dsa_switch *ds, int port, int regnum, u16 val); + int (*phy_read)(struct mt7530_priv *priv, int port, int regnum); + int (*phy_write)(struct mt7530_priv *priv, int port, int regnum, u16 val); int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface); int (*cpu_port_config)(struct dsa_switch *ds, int port); bool (*phy_mode_supported)(struct dsa_switch *ds, int port, @@ -761,6 +770,10 @@ struct mt753x_info { * registers * @p6_interface Holding the current port 6 interface * @p5_intf_sel: Holding the current port 5 interface select + * + * @irq: IRQ number of the switch + * @irq_domain: IRQ domain of the switch irq_chip + * @irq_enable: IRQ enable bits, synced to SYS_INT_EN */ struct mt7530_priv { struct device *dev; @@ -782,6 +795,9 @@ struct mt7530_priv { struct mt7530_port ports[MT7530_NUM_PORTS]; /* protect among processes for registers access*/ struct mutex reg_mutex; + int irq; + struct irq_domain *irq_domain; + u32 irq_enable; }; struct mt7530_hw_vlan_entry { From patchwork Thu Apr 8 12:39:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qingfang Deng X-Patchwork-Id: 418707 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A551C43460 for ; Thu, 8 Apr 2021 12:39:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C7FBF61165 for ; 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Thu, 08 Apr 2021 05:39:52 -0700 (PDT) From: DENG Qingfang To: "David S. Miller" , Andrew Lunn , Florian Fainelli , Heiner Kallweit , Jakub Kicinski , Landen Chao , Matthias Brugger , Russell King , Sean Wang , Vivien Didelot , Vladimir Oltean , Rob Herring , Linus Walleij , Greg Kroah-Hartman , Sergio Paracuellos , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-staging@lists.linux.dev, devicetree@vger.kernel.org, netdev@vger.kernel.org Cc: Weijie Gao , Chuanhong Guo , =?utf-8?q?Ren=C3=A9_van_Dorst?= , Frank Wunderlich , Thomas Gleixner , Marc Zyngier Subject: [RFC v3 net-next 3/4] dt-bindings: net: dsa: add MT7530 interrupt controller binding Date: Thu, 8 Apr 2021 20:39:18 +0800 Message-Id: <20210408123919.2528516-4-dqfext@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210408123919.2528516-1-dqfext@gmail.com> References: <20210408123919.2528516-1-dqfext@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add device tree binding to support MT7530 interrupt controller. Signed-off-by: DENG Qingfang Reviewed-by: Andrew Lunn --- RFC v2 -> RFC v3: - No changes. Documentation/devicetree/bindings/net/dsa/mt7530.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/mt7530.txt b/Documentation/devicetree/bindings/net/dsa/mt7530.txt index de04626a8e9d..26b34888eb62 100644 --- a/Documentation/devicetree/bindings/net/dsa/mt7530.txt +++ b/Documentation/devicetree/bindings/net/dsa/mt7530.txt @@ -81,6 +81,11 @@ Optional properties: - gpio-controller: Boolean; if defined, MT7530's LED controller will run on GPIO mode. - #gpio-cells: Must be 2 if gpio-controller is defined. +- interrupt-controller: Boolean; Enables the internal interrupt controller. + +If interrupt-controller is defined, the following property is required. + +- interrupts: Parent interrupt for the interrupt controller. See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional required, optional properties and how the integrated switch subnodes must From patchwork Thu Apr 8 12:39:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Qingfang Deng X-Patchwork-Id: 418020 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 809A1C433B4 for ; Thu, 8 Apr 2021 12:40:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 56DD661132 for ; Thu, 8 Apr 2021 12:40:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231574AbhDHMkN (ORCPT ); Thu, 8 Apr 2021 08:40:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55962 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231597AbhDHMkL (ORCPT ); Thu, 8 Apr 2021 08:40:11 -0400 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D1E6AC061760; Thu, 8 Apr 2021 05:40:00 -0700 (PDT) Received: by mail-pj1-x102b.google.com with SMTP id kk2-20020a17090b4a02b02900c777aa746fso1284283pjb.3; Thu, 08 Apr 2021 05:40:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SmFnhaRyZGKmhh6YeRu24XJccjOmUgsYe3aUSqwEOJM=; b=sdrEyJmGy8XW5Tzk4vxJNZ8GlNfQeQ8WXFXrGGIx/uGcosQHu/5191zepwOkcbLF+i AOruGbLsMv4y19ByxfOYte2JeWh0dGSamkX9OMk8nWIeaZLsN5y4xBY3ZsfEtEuvCF/q Z1eDnT73strNZt2ZmehAlPjFXSQ3acTrOAFqi7oz67pNod5+7/cqpJes4zjp6yULS9wc 0mDf9lWINdxUfp/4HMwcR9bZAh1KWSidqFYKdlxGGSsZ2sruUIgWn1j9WE3mjSsgrmiA Xj4fOscrKjbMUbKyNdHkRyCs25myAKjiQ2RmU2uJpemu1q3gXFyYUGGkOISY9k50vINO OT0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SmFnhaRyZGKmhh6YeRu24XJccjOmUgsYe3aUSqwEOJM=; b=OWycVq64eKH3zjCdt+n3JGzHsP1r0h2Fh/Ywuqt6xNQuY1vEonGlMDARpTuhyy/Wgv sfulKly3d1B+04TZpPXg7GhD2oz+0gFuF4lfsZeRM9Ai4NiCOTi+L5LKiuiDq6/TV3VC AP1pPNUo8ZBcDsEgjT02zbavNRPnUlpg7M2g5qpbV2BcnRETibxAFbDzHW+nlO7uqtqA tDRbN6RiHf9opPplKWB/gxYs0Rg6kpuA3ElWr36AX6H/yVzXnqLhhkx6jQbgvuBCOrG6 Yskhv7GRK9onLqzUJr3tYhYL4axEJy61aocsq+5ADC5zMbaPUCgW1yGciFm3/S38vRjc ARlw== X-Gm-Message-State: AOAM530JOdCSlqsIQPvHfFZd6oYzRATkhr4sDWMG432305NEZ6AiJeUN cyNjVKnc2zQ3HIRjVNkXXoc= X-Google-Smtp-Source: ABdhPJwek5HN1INa68+/CiKVytrivW+Z1sTojuAw8HeUS+/ee91/803ebFNmLRdXTFarQLbaJDtvbg== X-Received: by 2002:a17:903:185:b029:e9:9253:5328 with SMTP id z5-20020a1709030185b02900e992535328mr2507786plg.58.1617885600491; Thu, 08 Apr 2021 05:40:00 -0700 (PDT) Received: from localhost.localdomain ([138.197.212.246]) by smtp.gmail.com with ESMTPSA id e65sm25831311pfe.9.2021.04.08.05.39.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Apr 2021 05:39:59 -0700 (PDT) From: DENG Qingfang To: "David S. Miller" , Andrew Lunn , Florian Fainelli , Heiner Kallweit , Jakub Kicinski , Landen Chao , Matthias Brugger , Russell King , Sean Wang , Vivien Didelot , Vladimir Oltean , Rob Herring , Linus Walleij , Greg Kroah-Hartman , Sergio Paracuellos , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-staging@lists.linux.dev, devicetree@vger.kernel.org, netdev@vger.kernel.org Cc: Weijie Gao , Chuanhong Guo , =?utf-8?q?Ren=C3=A9_van_Dorst?= , Frank Wunderlich , Thomas Gleixner , Marc Zyngier Subject: [RFC v3 net-next 4/4] staging: mt7621-dts: enable MT7530 interrupt controller Date: Thu, 8 Apr 2021 20:39:19 +0800 Message-Id: <20210408123919.2528516-5-dqfext@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210408123919.2528516-1-dqfext@gmail.com> References: <20210408123919.2528516-1-dqfext@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Enable MT7530 interrupt controller in the MT7621 SoC. Signed-off-by: DENG Qingfang Reviewed-by: Andrew Lunn --- RFC v2 -> RFC v3: - No changes. drivers/staging/mt7621-dts/mt7621.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi index 16fc94f65486..ebf8b0633e88 100644 --- a/drivers/staging/mt7621-dts/mt7621.dtsi +++ b/drivers/staging/mt7621-dts/mt7621.dtsi @@ -447,6 +447,9 @@ switch0: switch0@0 { mediatek,mcm; resets = <&rstctrl 2>; reset-names = "mcm"; + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = ; ports { #address-cells = <1>;