From patchwork Mon Jun 11 15:48:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 138247 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp4216447lji; Mon, 11 Jun 2018 08:49:53 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLlW33KeWEKE48goyTbaZgAKcXt8zMVbXKs4DK/QFR4v0BUPewPea51HwEdhEMok957ksKA X-Received: by 2002:a50:83c2:: with SMTP id 60-v6mr6728645edi.263.1528732193346; Mon, 11 Jun 2018 08:49:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528732193; cv=none; d=google.com; s=arc-20160816; b=e2bzc7HT75zj9YsbRS72SZnMjQmfnCVBY9xIph9BfWiEsBbvGzEtlYxX/vEh1q0rFB dyfRqznCgwL9uchr0pT+WHk2ZsRmIk5mU/FXmhDVx8syJahA5fLTpXR8FfGfpyYc3kzl O87YjPCYZWPddZ7qDTnS/KZzpubafhpdVecoaY04sinicYF1SJhaeM7wItX+MJTWHO4Q o8F7CN4hMEmYT/uanUVDMffKyC7XdUSadWS1CqBkDB5w4BQsfz3TRZEHjWJkO0Y/Xpzx QVQ4LRcdgwVAXoPO+7AIeUEFsa+4jfezo6Oq6IT5Idqn+l03sUZyuCo0YstQhsEH8hY+ a9OQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:arc-authentication-results; bh=kTME/sULEAxvX0zvx4HS48thPGrbJUvSMRCIzOiDnvw=; b=pg4bt9OdN7P3RGDfzFWUqcuWzVH4n2n0AkiHsSTDgcdFvUs88ga+3gRHHM/l+aaMbV raee//l3J+R6CvZXobOko6nzQksJs3jJABXmYS8ADBZ1yYRuFBV7tFkkjFAeIhCSxCiY wWhuF+bS7j0iqVjhrYYeuumbS3pgADTmLmnK1Ncw7bjBgn85yaeyrs4RGE2XJUdIkmfl VGBjMppXs4h9XjbexVBT1lyDX50nbrxz5QfLfQmtuWjjBnX8/vGCd0MDgkbtjGQI6Apj PlSlpfvkLdQ74JEfU5SisTm90pfofQEwiyVnd/9OuvIjRF7npFUPI+bJfsjqpT4VBHHm mChg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Gjg+abKF; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id 19-v6si418679edu.414.2018.06.11.08.49.53; Mon, 11 Jun 2018 08:49:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Gjg+abKF; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id E8CD4C21DED; Mon, 11 Jun 2018 15:49:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=KHOP_BIG_TO_CC, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B41FEC21D4A; Mon, 11 Jun 2018 15:49:30 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 876E0C21DFD; Mon, 11 Jun 2018 15:49:23 +0000 (UTC) Received: from mail-pg0-f68.google.com (mail-pg0-f68.google.com [74.125.83.68]) by lists.denx.de (Postfix) with ESMTPS id 4C62CC21DF8 for ; Mon, 11 Jun 2018 15:49:19 +0000 (UTC) Received: by mail-pg0-f68.google.com with SMTP id e11-v6so9956771pgq.0 for ; Mon, 11 Jun 2018 08:49:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7bGRGmCRcrjmX7BvvOf4/7Shw8EKwF0SBEYrggTl5x4=; b=Gjg+abKFSNAyDO4mr1IMd9wkYC8WIfawLXUbtx8UJlY7O5RinjNXM9zW3h1zgqgc5L D27GbWrf00V7upvp5na+S9NXJ3SKuqrCcHjCQw0mJn6IzNfSRakp84aeNBzcQUCjBhAb G0/VroqF0PQcSOaiJp/S5RZDIvnY1/XHRF4Vg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7bGRGmCRcrjmX7BvvOf4/7Shw8EKwF0SBEYrggTl5x4=; b=Ii0cHXpl2QkZb5JHN58wGimMEpA+UUw8ZYNH0GJR7QhPgSn8L8RlyMNWMTB/ZglMcv oaGZKB4xqOuQr6ePyelcF0ek++rzah3btluLXYg20DaCwlamonBqa3kCKbuNSRPQA8ad 3Ft6m/V8FME9U/6TySoLDUIlZCuKXDybJDkb6pBIf5pjRwvI6HQhWNa7tlcrnLQCY6Tx dwpW/kBujPl4gOXcvqEBx9ll0h8lPShzvMPzTZ6EPBFP/gQ6EOk7fS87ieFu7Wb0/Blr 01L28NRuEkOZLB9tAVRgNM56nMcAGJJDicxEQdwxgvULkCW+cLIun+At7ZUM+/2GnAvw CPOA== X-Gm-Message-State: APt69E2NAS+uA2mqQV+gi3UUUJWqpp6RaPygiXaoVs3W3yz//O0M9LgP 1dobeEjGMI/8VPWphQN/upK5 X-Received: by 2002:a65:4a42:: with SMTP id a2-v6mr15507877pgu.367.1528732157802; Mon, 11 Jun 2018 08:49:17 -0700 (PDT) Received: from localhost.localdomain ([2405:204:7288:73c5:d4c6:ffd5:c258:b7e0]) by smtp.gmail.com with ESMTPSA id s1-v6sm31638261pgv.48.2018.06.11.08.49.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Jun 2018 08:49:17 -0700 (PDT) From: Manivannan Sadhasivam To: albert.u.boot@aribaud.net, sjg@chromium.org, marek.vasut+renesas@gmail.com, u-boot@lists.denx.de Date: Mon, 11 Jun 2018 21:18:24 +0530 Message-Id: <20180611154832.3251-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180611154832.3251-1-manivannan.sadhasivam@linaro.org> References: <20180611154832.3251-1-manivannan.sadhasivam@linaro.org> Cc: daniel.thompson@linaro.org, manivannanece23@gmail.com, bdong@ucrobotics.com, thomas.liau@actions-semi.com, hzhang@ucrobotics.com, amit.kucheria@linaro.org, liuwei@actions-semi.com, afaerber@suse.de, jeff.chen@actions-semi.com, mp-cs@actions-semi.com Subject: [U-Boot] [RESEND][PATCH 1/9] arm: Add support for Actions Semi OWL SoC family X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This commit adds Actions Semi OWL SoC family support with S900 as the first target SoC. Signed-off-by: Manivannan Sadhasivam --- arch/arm/Kconfig | 9 +++++++++ arch/arm/Makefile | 1 + arch/arm/dts/s900.dtsi | 23 +++++++++++++++++++++++ arch/arm/mach-owl/Kconfig | 6 ++++++ arch/arm/mach-owl/Makefile | 3 +++ arch/arm/mach-owl/sysmap-s900.c | 32 ++++++++++++++++++++++++++++++++ 6 files changed, 74 insertions(+) create mode 100644 arch/arm/dts/s900.dtsi create mode 100644 arch/arm/mach-owl/Kconfig create mode 100644 arch/arm/mach-owl/Makefile create mode 100644 arch/arm/mach-owl/sysmap-s900.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index dde422bc5d..ec0bb5a42b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -699,6 +699,13 @@ config ARCH_MX5 select BOARD_EARLY_INIT_F imply MXC_GPIO +config ARCH_OWL + bool "Actions Semi OWL SoCs" + select ARM64 + select DM + select DM_SERIAL + select OF_CONTROL + config ARCH_QEMU bool "QEMU Virtual Platform" select DM @@ -1335,6 +1342,8 @@ source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig" source "arch/arm/mach-orion5x/Kconfig" +source "arch/arm/mach-owl/Kconfig" + source "arch/arm/mach-rmobile/Kconfig" source "arch/arm/mach-meson/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 680c6e8516..f15b2287df 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -66,6 +66,7 @@ machine-$(CONFIG_ARCH_MVEBU) += mvebu # TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X machine-$(CONFIG_ORION5X) += orion5x machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2 +machine-$(CONFIG_ARCH_OWL) += owl machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx machine-$(CONFIG_ARCH_SUNXI) += sunxi machine-$(CONFIG_ARCH_SNAPDRAGON) += snapdragon diff --git a/arch/arm/dts/s900.dtsi b/arch/arm/dts/s900.dtsi new file mode 100644 index 0000000000..3bd14b82d4 --- /dev/null +++ b/arch/arm/dts/s900.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Device Tree Source for Actions Semi S900 SoC +// +// Copyright (C) 2015 Actions Semi Co., Ltd. +// Copyright (C) 2018 Manivannan Sadhasivam + +/dts-v1/; + +/ { + compatible = "actions,s900"; + #address-cells = <0x2>; + #size-cells = <0x2>; + + soc { + u-boot,dm-pre-reloc; + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + }; +}; + diff --git a/arch/arm/mach-owl/Kconfig b/arch/arm/mach-owl/Kconfig new file mode 100644 index 0000000000..f695c16d1e --- /dev/null +++ b/arch/arm/mach-owl/Kconfig @@ -0,0 +1,6 @@ +if ARCH_OWL + +config SYS_SOC + default "owl" + +endif diff --git a/arch/arm/mach-owl/Makefile b/arch/arm/mach-owl/Makefile new file mode 100644 index 0000000000..1b43dc2921 --- /dev/null +++ b/arch/arm/mach-owl/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += sysmap-s900.o diff --git a/arch/arm/mach-owl/sysmap-s900.c b/arch/arm/mach-owl/sysmap-s900.c new file mode 100644 index 0000000000..f78b639740 --- /dev/null +++ b/arch/arm/mach-owl/sysmap-s900.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Actions Semi S900 Memory map + * + * Copyright (C) 2015 Actions Semi Co., Ltd. + * Copyright (C) 2018 Manivannan Sadhasivam + */ + +#include +#include + +static struct mm_region s900_mem_map[] = { + { + .virt = 0x0UL, /* DDR */ + .phys = 0x0UL, /* DDR */ + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xE0000000UL, /* Peripheral block */ + .phys = 0xE0000000UL, /* Peripheral block */ + .size = 0x08000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = s900_mem_map; From patchwork Mon Jun 11 15:48:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 138248 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp4217069lji; Mon, 11 Jun 2018 08:50:30 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJWPycP/unHNJfqeo6elIDQwHO8RQJfBCHcHH9duHDS71O7nZDJfieutcnUH14CzTUBGnr7 X-Received: by 2002:a50:f743:: with SMTP id j3-v6mr19023356edn.37.1528732230445; Mon, 11 Jun 2018 08:50:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528732230; cv=none; d=google.com; s=arc-20160816; b=mz+BLZk/Q3St6yJrV4sfzRBtkbuQMEtaQtcDJRBamwbKlnTBEExjKE4YYK1pE6wsIC tHotwYNssEc9n7MJdQWHgPBTII0xjW5mVAI8B8ABaGCY/3WsziCjfpZHbemVk7ANChpi 9jmB8xPI4fCDP4sp2MXrfeJyVql47kgc33CJAHooamY/VXBWQRr4IkOmIupzqaPvIfki BU0CI4ivJCwVHY7+VnCW4IUxFzGODWHRXqVM4pyw14ArVvwSQjd8Fz4JKeQa8dvkoqLk E82VzHhSpqi4PYGyGmaexOJwGtO4VLL+cwxwKwKxK5g++JhW/WnE1MKRLMkrAmUxzL4m DH/g== ARC-Message-Signature: i=1; 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[81.169.180.215]) by mx.google.com with ESMTP id w9-v6si246133edb.260.2018.06.11.08.50.30; Mon, 11 Jun 2018 08:50:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=QeQYwSKt; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 0913CC21D8A; Mon, 11 Jun 2018 15:50:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 1CAA1C21D9A; Mon, 11 Jun 2018 15:49:58 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 7FB06C21DA6; Mon, 11 Jun 2018 15:49:40 +0000 (UTC) Received: from mail-pf0-f196.google.com (mail-pf0-f196.google.com [209.85.192.196]) by lists.denx.de (Postfix) with ESMTPS id 85468C21D83 for ; Mon, 11 Jun 2018 15:49:36 +0000 (UTC) Received: by mail-pf0-f196.google.com with SMTP id y5-v6so9542553pfn.4 for ; Mon, 11 Jun 2018 08:49:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=w0VlMCxnDuZEJwOAz4zvxi6yyBTqnZPl1S0IV/NJ96E=; b=QeQYwSKt5JzllBG5l4n9S1ufyWV/MKjrdfwcZCa8ZH5bzhqxJfiNJ8/9LQM+fgu5rL WwK4DUx6MsUsjxTVIxZXRT73NKk0VGDxmF/WsH1ZLOLKSBYpOvZAOsfb6YGTEu94gBoi z+wncyVbcq01OQ9s14F9WldEIK0SBMFVkWFCk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=w0VlMCxnDuZEJwOAz4zvxi6yyBTqnZPl1S0IV/NJ96E=; b=j0Km5qEwYp2iBeebOKHOSqBwHBBd82Ga0K1bCTPYXOlLIUwwiNDdp4Yu9ye1syzKRe YfugOwlxQfJk6hxGLXK590bUKOjIRHxkIa296x3dwHVwmrbhiebUpGdwi1YeZOFhwF5d N1BjUU2P4TW7SDHcX+7hUYwyQqrvG4TGB1Sf7tbn/KYDYYiFygEOks5+WkbAValoaf/+ Ti5Brh9KePRmNCBbiajHH9xN2raljzjdoZKVJdlLHj0VVeaUhD3AFq62Yjg+3Ww4ocO0 ckFoofppdGCpj60ZizTesmRWm/IiT5WSLdO6ZyHHSjB7rfUL7cDleDX9HVN+C06AKqqH bvqQ== X-Gm-Message-State: APt69E0ZCpoOV22Id/PiJWC4dSoChhFds0FiUncKSKLii3MQwDWSP+n+ RGjoAiGiXgY+a/zm53A8MhHf X-Received: by 2002:a62:df12:: with SMTP id u18-v6mr18222688pfg.230.1528732174846; Mon, 11 Jun 2018 08:49:34 -0700 (PDT) Received: from localhost.localdomain ([2405:204:7288:73c5:d4c6:ffd5:c258:b7e0]) by smtp.gmail.com with ESMTPSA id s1-v6sm31638261pgv.48.2018.06.11.08.49.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Jun 2018 08:49:34 -0700 (PDT) From: Manivannan Sadhasivam To: albert.u.boot@aribaud.net, sjg@chromium.org, marek.vasut+renesas@gmail.com, u-boot@lists.denx.de Date: Mon, 11 Jun 2018 21:18:25 +0530 Message-Id: <20180611154832.3251-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180611154832.3251-1-manivannan.sadhasivam@linaro.org> References: <20180611154832.3251-1-manivannan.sadhasivam@linaro.org> Cc: daniel.thompson@linaro.org, manivannanece23@gmail.com, bdong@ucrobotics.com, thomas.liau@actions-semi.com, hzhang@ucrobotics.com, amit.kucheria@linaro.org, liuwei@actions-semi.com, afaerber@suse.de, jeff.chen@actions-semi.com, mp-cs@actions-semi.com Subject: [U-Boot] [RESEND][PATCH 2/9] board: Add uCRobotics Bubblegum-96 board support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This commit adds uCRobotics Bubblegum-96 board support. This board is one of the 96Boards Consumer Edition platform based on Actions Semi S900 SoC. Features: - Actions Semi S900 SoC (4xCortex A53, Power VR G6230 GPU) - 2GiB RAM - 8GiB eMMC, uSD slot - WiFi, Bluetooth and GPS module - 2x Host, 1x Device USB port - HDMI - 20-pin low speed and 40-pin high speed expanders, 6 LED, 3 buttons U-Boot will be loaded by ATF at EL2 execution level. Relevant driver support will be added in further commits. Signed-off-by: Manivannan Sadhasivam --- arch/arm/Kconfig | 1 + arch/arm/dts/bubblegum_96.dts | 19 +++++++ arch/arm/mach-owl/Kconfig | 21 ++++++++ board/ucRobotics/bubblegum_96/Kconfig | 15 ++++++ board/ucRobotics/bubblegum_96/MAINTAINERS | 6 +++ board/ucRobotics/bubblegum_96/Makefile | 3 ++ board/ucRobotics/bubblegum_96/bubblegum_96.c | 56 ++++++++++++++++++++ configs/bubblegum_96_defconfig | 22 ++++++++ include/configs/bubblegum_96.h | 43 +++++++++++++++ 9 files changed, 186 insertions(+) create mode 100644 arch/arm/dts/bubblegum_96.dts create mode 100644 board/ucRobotics/bubblegum_96/Kconfig create mode 100644 board/ucRobotics/bubblegum_96/MAINTAINERS create mode 100644 board/ucRobotics/bubblegum_96/Makefile create mode 100644 board/ucRobotics/bubblegum_96/bubblegum_96.c create mode 100644 configs/bubblegum_96_defconfig create mode 100644 include/configs/bubblegum_96.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ec0bb5a42b..6e203f96aa 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1431,6 +1431,7 @@ source "board/spear/spear600/Kconfig" source "board/spear/x600/Kconfig" source "board/st/stv0991/Kconfig" source "board/tcl/sl50/Kconfig" +source "board/ucRobotics/bubblegum_96/Kconfig" source "board/birdland/bav335x/Kconfig" source "board/timll/devkit3250/Kconfig" source "board/toradex/colibri_pxa270/Kconfig" diff --git a/arch/arm/dts/bubblegum_96.dts b/arch/arm/dts/bubblegum_96.dts new file mode 100644 index 0000000000..4e34ebaa49 --- /dev/null +++ b/arch/arm/dts/bubblegum_96.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Device Tree Source for Bubblegum-96 +// +// Copyright (C) 2015 Actions Semi Co., Ltd. +// Copyright (C) 2018 Manivannan Sadhasivam + +/dts-v1/; +#include "s900.dtsi" + +/ { + model = "Bubblegum-96"; + compatible = "ucrobotics,bubblegum-96", "actions,s900"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; +}; diff --git a/arch/arm/mach-owl/Kconfig b/arch/arm/mach-owl/Kconfig index f695c16d1e..b0b506dbb4 100644 --- a/arch/arm/mach-owl/Kconfig +++ b/arch/arm/mach-owl/Kconfig @@ -3,4 +3,25 @@ if ARCH_OWL config SYS_SOC default "owl" +choice + prompt "Actions OWL SoCs board select" + optional + +config TARGET_BUBBLEGUM_96 + bool "96Boards Bubblegum-96" + help + Support for 96Boards Bubblegum-96. This board complies with + 96Board Consumer Edition Specification. Features: + - Actions Semi S900 SoC (4xCortex A53, Power VR G6230 GPU) + - 2GiB RAM + - 8GiB eMMC, uSD slot + - WiFi, Bluetooth and GPS module + - 2x Host, 1x Device USB port + - HDMI + - 20-pin low speed and 40-pin high speed expanders, 6 LED, 3 buttons + +endchoice + +source "board/ucRobotics/bubblegum_96/Kconfig" + endif diff --git a/board/ucRobotics/bubblegum_96/Kconfig b/board/ucRobotics/bubblegum_96/Kconfig new file mode 100644 index 0000000000..2dd40d9b6a --- /dev/null +++ b/board/ucRobotics/bubblegum_96/Kconfig @@ -0,0 +1,15 @@ +if TARGET_BUBBLEGUM_96 + +config SYS_BOARD + default "bubblegum_96" + +config SYS_VENDOR + default "ucRobotics" + +config SYS_SOC + default "s900" + +config SYS_CONFIG_NAME + default "bubblegum_96" + +endif diff --git a/board/ucRobotics/bubblegum_96/MAINTAINERS b/board/ucRobotics/bubblegum_96/MAINTAINERS new file mode 100644 index 0000000000..d0cb7278c6 --- /dev/null +++ b/board/ucRobotics/bubblegum_96/MAINTAINERS @@ -0,0 +1,6 @@ +BUBBLEGUM_96 BOARD +M: Manivannan Sadhasivam +S: Maintained +F: board/ucRobotics/bubblegum_96/ +F: include/configs/bubblegum_96.h +F: configs/bubblegum_96_defconfig diff --git a/board/ucRobotics/bubblegum_96/Makefile b/board/ucRobotics/bubblegum_96/Makefile new file mode 100644 index 0000000000..c4b524def2 --- /dev/null +++ b/board/ucRobotics/bubblegum_96/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y := bubblegum_96.o diff --git a/board/ucRobotics/bubblegum_96/bubblegum_96.c b/board/ucRobotics/bubblegum_96/bubblegum_96.c new file mode 100644 index 0000000000..a4c202da19 --- /dev/null +++ b/board/ucRobotics/bubblegum_96/bubblegum_96.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Bubblegum-96 Boards Support + * + * Copyright (C) 2018 Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * dram_init - sets uboots idea of sdram size + */ +int dram_init(void) +{ + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + return 0; +} + +/* This is called after dram_init() so use get_ram_size result */ +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; + + return 0; +} + +static void show_psci_version(void) +{ + struct arm_smccc_res res; + + arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res); + + printf("PSCI: v%ld.%ld\n", + PSCI_VERSION_MAJOR(res.a0), + PSCI_VERSION_MINOR(res.a0)); +} + +int board_init(void) +{ + show_psci_version(); + + return 0; +} + +void reset_cpu(ulong addr) +{ + psci_system_reset(); +} diff --git a/configs/bubblegum_96_defconfig b/configs/bubblegum_96_defconfig new file mode 100644 index 0000000000..a2bd7e80e2 --- /dev/null +++ b/configs/bubblegum_96_defconfig @@ -0,0 +1,22 @@ +CONFIG_ARM=y +CONFIG_ARCH_OWL=y +CONFIG_TARGET_BUBBLEGUM_96=y +CONFIG_SYS_TEXT_BASE=0x11000000 +CONFIG_IDENT_STRING="\nBubblegum-96" +CONFIG_DEFAULT_DEVICE_TREE="bubblegum_96" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_USE_BOOTARGS=y +CONFIG_ARM_SMCCC=y +CONFIG_BOOTARGS="console=ttyOWL5,115200n8" +CONFIG_BOOTDELAY=5 +CONFIG_SYS_PROMPT="U-Boot => " +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIMER=y +CONFIG_CLK=y +CONFIG_CLK_OWL=y +CONFIG_CLK_S900=y +CONFIG_OWL_SERIAL=y diff --git a/include/configs/bubblegum_96.h b/include/configs/bubblegum_96.h new file mode 100644 index 0000000000..a8f38a23f9 --- /dev/null +++ b/include/configs/bubblegum_96.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Board configuration file for Bubblegum-96 + * + * Copyright (C) 2015 Actions Semi Co., Ltd. + * Copyright (C) 2018 Manivannan Sadhasivam + * + */ + +#ifndef _BUBBLEGUM_96_H_ +#define _BUGGLEGUM_96_H_ + +/* SDRAM Definitions */ +#define CONFIG_SYS_SDRAM_BASE 0x0 +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_SIZE 0x80000000 + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY (24000000) /* 24MHz */ + +#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) + +/* Some commands use this as the default load address */ +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7ffc0) + +/* + * This is the initial SP which is used only briefly for relocating the u-boot + * image to the top of SDRAM. After relocation u-boot moves the stack to the + * proper place. + */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x7ff00) + +/* UART Definitions */ +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_ENV_SIZE 0x2000 + +/* Console configuration */ +#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#endif From patchwork Mon Jun 11 15:48:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 138249 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp4217982lji; Mon, 11 Jun 2018 08:51:29 -0700 (PDT) X-Google-Smtp-Source: ADUXVKIbEF23k/sFurBbodvJ3Ew/z1e9LeyXA+2FYln0Qs4XWunGfLSLqdLiqQit+X4SUIXCvteX X-Received: by 2002:a50:d08e:: with SMTP id v14-v6mr18734012edd.182.1528732289441; Mon, 11 Jun 2018 08:51:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528732289; cv=none; d=google.com; s=arc-20160816; b=Yz7PxjJEBiK8n6ros7BURAac6xzIeApjf5TdwEdBDxtBcJWgVGpf+TFlsmIXiXSeO9 i1c3FSi7p3c0m57qm4OqQlLAB3Rym/RjCIe3pIqYdqEJ8Y+AcVyajUu6rau5pcSbrCzt +oa4wczAzjCITJxOcfw6ZvWErnUvY1xWVRJAMIpd1AGWkl0tqPBu3tgIFi1QX5ALIVh/ 34Yl5oEKKJT3wd+fzdFFKe2t0KMInJtlMETob5v7cGwz/fEFj7F7adgwZqda23GCCIsa yb2+TOvuLYterYn1pbyTsf+a3v8LIYJMWxFs88yqhQF4FFZo8RWK5cNzrKBtrpRHu/cr YEfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:arc-authentication-results; bh=iHaYyc+7Oh6vBzZLvpkEHP52RpYPXncq4V5OrWOaZo4=; b=N+fAVj3BE10P9YdHa2dqp+dggyP5KV3eReeBortf8mIcPY/71eK674BIlbMFnuJinH hc9Jryuiqe58u7/v2QjRGvx1cEHkJ6QUYOOe151pmy2vO5OdCDx6TfZKgkWBKr1QT6j2 4FHwgAfIKf9GGSIAP7wjoyJEhAj0QHJI9wfgcraEUnqs5bSE13cQa/oIu8MqObideXzk QXhiB3Mcz6hMTR95yUB3zcBhkfvwN7XMVDqVgwzoXkJf5gG4CLnSn+yRZFax4Sj8BvqM Fw7dHMUkJuvv18KL4SvI8MQeDgv1b8nn9xZ8/qPyOq8xkIjjaPzjOKCR0MOL51+LygW/ 6COg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=d5m3VrU2; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id s12-v6si4029340edb.332.2018.06.11.08.51.29; Mon, 11 Jun 2018 08:51:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=d5m3VrU2; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id EBD91C21DF8; Mon, 11 Jun 2018 15:50:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=KHOP_BIG_TO_CC, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A09D5C21D9A; Mon, 11 Jun 2018 15:50:40 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 96DDCC21DA1; Mon, 11 Jun 2018 15:50:11 +0000 (UTC) Received: from mail-pl0-f68.google.com (mail-pl0-f68.google.com [209.85.160.68]) by lists.denx.de (Postfix) with ESMTPS id AC941C21E0B for ; Mon, 11 Jun 2018 15:50:05 +0000 (UTC) Received: by mail-pl0-f68.google.com with SMTP id n10-v6so12561579plp.0 for ; Mon, 11 Jun 2018 08:50:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VmfMqN6PBmC9ebQlHlANGND5cbFry1Tfn6ATnZ3xGEQ=; b=d5m3VrU2KIyh8kDLLDaZChRpQZ7y6+V71lKHg1eSqmmI33IAPS7rieAL80lxFEyhWH /VKlx22HriBSv17HU0V5IuJNxGQBHP+mLTErWc/RjtCCIn2GDnOCrjWk5G17YZFny2dS DcMEJH0cwbFM65+5Gst0ljgCd73tUoao+GSWw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VmfMqN6PBmC9ebQlHlANGND5cbFry1Tfn6ATnZ3xGEQ=; b=sGm1KBJTFgiSr5uqBu8OwmznTDqE90D7FsFuNfKhSFaABNGP9RRi5gYIFHf6zLcaIy UwW9lV1YtUXTzGBYlRBFnSatGIHsPDEvHnzynWRrQGud8O+jsBkdMacE139JDYj4E3y4 yjlfTiPE/hsgOEGpK4wrqds3wTMkpq4zC8oZBX2gZeHk3cURXeO/f0huNFHoDltuCYFX 3DqAxK2+aa2ON46GyFLd2b2KA3zARi/EXzRRSGfpRiZVBgSDgaIhYZpLAlEUcVpH3AAM I674ksag4IhDie4Cl/BqmOuvGJixDmGerSMCZQy1EdT44uqHX79HUf8KvewfgscTvdQ4 pHSQ== X-Gm-Message-State: APt69E0NNhX/MN0ukcgZmPHXnHDzV0A974B73TisH5mVS45T8kfv3Gd8 MBw1n9p/hZR6vlHB31s1mn8L X-Received: by 2002:a17:902:6802:: with SMTP id h2-v6mr6800987plk.113.1528732204285; Mon, 11 Jun 2018 08:50:04 -0700 (PDT) Received: from localhost.localdomain ([2405:204:7288:73c5:d4c6:ffd5:c258:b7e0]) by smtp.gmail.com with ESMTPSA id s1-v6sm31638261pgv.48.2018.06.11.08.49.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Jun 2018 08:50:03 -0700 (PDT) From: Manivannan Sadhasivam To: albert.u.boot@aribaud.net, sjg@chromium.org, marek.vasut+renesas@gmail.com, u-boot@lists.denx.de Date: Mon, 11 Jun 2018 21:18:27 +0530 Message-Id: <20180611154832.3251-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180611154832.3251-1-manivannan.sadhasivam@linaro.org> References: <20180611154832.3251-1-manivannan.sadhasivam@linaro.org> Cc: daniel.thompson@linaro.org, manivannanece23@gmail.com, bdong@ucrobotics.com, thomas.liau@actions-semi.com, hzhang@ucrobotics.com, amit.kucheria@linaro.org, liuwei@actions-semi.com, afaerber@suse.de, jeff.chen@actions-semi.com, mp-cs@actions-semi.com Subject: [U-Boot] [RESEND][PATCH 4/9] arm: dts: s900: Add Clock Management Unit (CMU) nodes X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This commit adds Clock Management Unit (CMU) nodes for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam --- arch/arm/dts/s900.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/dts/s900.dtsi b/arch/arm/dts/s900.dtsi index 3bd14b82d4..e9d47b1ff1 100644 --- a/arch/arm/dts/s900.dtsi +++ b/arch/arm/dts/s900.dtsi @@ -6,18 +6,40 @@ // Copyright (C) 2018 Manivannan Sadhasivam /dts-v1/; +#include / { compatible = "actions,s900"; #address-cells = <0x2>; #size-cells = <0x2>; + losc: losc { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + + diff24M: diff24M { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + #clock-cells = <0>; + }; + soc { u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <0x2>; #size-cells = <0x2>; ranges; + + cmu: clock-controller@e0160000 { + u-boot,dm-pre-reloc; + compatible = "actions,s900-cmu"; + reg = <0x0 0xe0160000 0x0 0x1000>; + clocks = <&losc>, <&diff24M>; + clock-names = "losc", "diff24M"; + #clock-cells = <1>; + }; }; }; From patchwork Mon Jun 11 15:48:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 138251 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp4219896lji; Mon, 11 Jun 2018 08:53:29 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJljqRHOj3MhP1se/eau3HyNlA/C3aEIlzDixUHEExmejS22CStWTGW4tc4Q/0L4FUuZ6hT X-Received: by 2002:a50:9385:: with SMTP id o5-v6mr2893447eda.291.1528732409009; Mon, 11 Jun 2018 08:53:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528732409; cv=none; d=google.com; s=arc-20160816; b=XLSCuZJf79TEBgrhy1zuPa5c0L6pMlsi4C9U6lbZqXSrq+RHdKnbQrZdhbNbiGCBhg /sqWVs9h5Vc9w9PJmQiYXxlALd3hjE1DvwPoOfZ52iEjIOsgf0IZ1rInfhW9SdjUrFik 3fTAmd9mgXOXa333Vh+vrWhHUVRMDuHZsoxxa03TqbDNrdZd64elOJXOSlJNohFZaXV7 91nouf2O/rcck1YhLU4jX3LtqS+LEakb4kXVx9fqMPh+orKfA41ILNX1GEat4GnNDDXc LKaIUvl7iXg/e9sBy1ZxkJeeURo7uCdvQYWv+xI9zP5IKN5/gE6j68Q+/9Msza9SAJGk Yu4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:arc-authentication-results; bh=Nyk/qqPBhMbZeKC5nkp6vetlPCuBEvshNAcsqEyBZgQ=; b=PPc873sIxazJ/wdvqz9hhXDuKMkK9ByfTZ413bBvVpabB/Qge0eKGI5bDKXkzOe0zY If0eu3Gmki7bQz0LTnskUcoBaSNZ6MfSHig+0b11VjZtQp86BlDKfO4r41gEISgjAJIu jGQlYB5h4Qxvp49XJdc1waAyLdFDg0SlxbFYcy3D+btDll/v2uwQIAc9f3O0ribloir4 FxLSNv9yVKSw0NlnYVDQ8R62SmUuJOZvPIW6MpfQyZUzgiiBH7jCbBsZw7oUD4F+pOWG NTFHBRzw6N6XD1+4hsvF3BN1cJRxaDAvr2eNqK+M23rChbcYMlebb21uH2OAV/eEuqxP Z9SA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=HEP4qLtu; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id e30-v6si1350272ede.310.2018.06.11.08.53.28; Mon, 11 Jun 2018 08:53:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=HEP4qLtu; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 92643C21DF8; Mon, 11 Jun 2018 15:51:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B167DC21DCA; Mon, 11 Jun 2018 15:51:28 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0B33DC21DF3; Mon, 11 Jun 2018 15:50:24 +0000 (UTC) Received: from mail-pf0-f196.google.com (mail-pf0-f196.google.com [209.85.192.196]) by lists.denx.de (Postfix) with ESMTPS id 5D767C21E13 for ; Mon, 11 Jun 2018 15:50:15 +0000 (UTC) Received: by mail-pf0-f196.google.com with SMTP id y8-v6so1384160pfm.10 for ; Mon, 11 Jun 2018 08:50:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6C8nPJNiwald6vRz8AWrdVNfxPj6F6MTCXgBvDrP8vI=; b=HEP4qLtueXIcbyqFKq57WSreyTT5LRAEp7N9B3KCKBmRAPQPfsogRDBMUKr1Vd1eBo QrI12qz3G/HklAdLVEbdGWlheAZvfMuGOq4klyOIaRW16hNoh8Hz0kPZqa+wAWhr4wer 9pg9ojMh4w2HESx7bSGlTupr2twpszIAh1vwc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6C8nPJNiwald6vRz8AWrdVNfxPj6F6MTCXgBvDrP8vI=; b=W3QN5IEi4weovnl8Or31k72p+clFZQzdwpYAOVFAl+U0trGmpm06Y4PMUdfJvZ/zxq AaKICCmhscwlg/L3+tz9VYf18dFZvavw26EDUsW5nhIHJY21ww9oTi+A6AT89yPEg7Bl Pw/mjQBe28D8KeMcNX+zVgSaszic4GJ2A8D6pTrwvvDjZabQCHPnfnS8udpYccB059Dz ob1JNoVOqIvGDrdhebSZuXdu/kn/5YmQfdfMI5ho1umhW3PJAiEFMspGUdxUjfzHDANU NtizgmQKN2sKAUFycYLH8Lg8N2A1zOMhKD0p0DB5T6m+1ZpnZjja5yzrOe/jdFeLmIw3 K5Pg== X-Gm-Message-State: APt69E1HnG4JPFXcpRngwPCl43dX9dEykePtjy701KImswcwLIMgsndR 6PP49E2lwk7pwfeCm+IhYR01 X-Received: by 2002:a63:6fce:: with SMTP id k197-v6mr15435018pgc.307.1528732213839; Mon, 11 Jun 2018 08:50:13 -0700 (PDT) Received: from localhost.localdomain ([2405:204:7288:73c5:d4c6:ffd5:c258:b7e0]) by smtp.gmail.com with ESMTPSA id s1-v6sm31638261pgv.48.2018.06.11.08.50.04 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Jun 2018 08:50:13 -0700 (PDT) From: Manivannan Sadhasivam To: albert.u.boot@aribaud.net, sjg@chromium.org, marek.vasut+renesas@gmail.com, u-boot@lists.denx.de Date: Mon, 11 Jun 2018 21:18:28 +0530 Message-Id: <20180611154832.3251-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180611154832.3251-1-manivannan.sadhasivam@linaro.org> References: <20180611154832.3251-1-manivannan.sadhasivam@linaro.org> Cc: daniel.thompson@linaro.org, manivannanece23@gmail.com, bdong@ucrobotics.com, thomas.liau@actions-semi.com, hzhang@ucrobotics.com, amit.kucheria@linaro.org, liuwei@actions-semi.com, afaerber@suse.de, jeff.chen@actions-semi.com, mp-cs@actions-semi.com Subject: [U-Boot] [RESEND][PATCH 5/9] clk: Add Actions Semi OWL clock support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This commit adds Actions Semi OWL family base clock and S900 SoC specific clock support. For S900 peripheral clock support, only UART clock has been added for now. Signed-off-by: Manivannan Sadhasivam --- arch/arm/include/asm/arch-owl/clk_owl.h | 61 +++++++++++++ arch/arm/include/asm/arch-owl/regs_s900.h | 64 +++++++++++++ arch/arm/mach-owl/Kconfig | 2 +- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/owl/Kconfig | 12 +++ drivers/clk/owl/Makefile | 4 + drivers/clk/owl/clk_owl.c | 60 +++++++++++++ drivers/clk/owl/clk_s900.c | 104 ++++++++++++++++++++++ 9 files changed, 308 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/arch-owl/clk_owl.h create mode 100644 arch/arm/include/asm/arch-owl/regs_s900.h create mode 100644 drivers/clk/owl/Kconfig create mode 100644 drivers/clk/owl/Makefile create mode 100644 drivers/clk/owl/clk_owl.c create mode 100644 drivers/clk/owl/clk_s900.c diff --git a/arch/arm/include/asm/arch-owl/clk_owl.h b/arch/arm/include/asm/arch-owl/clk_owl.h new file mode 100644 index 0000000000..1ad8e80e28 --- /dev/null +++ b/arch/arm/include/asm/arch-owl/clk_owl.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Actions Semi OWL Clock Definitions + * + * Copyright (C) 2015 Actions Semi Co., Ltd. + * Copyright (C) 2018 Manivannan Sadhasivam + * + */ + +#ifndef _OWL_CLK_OWL_H_ +#define _OWL_CLK_OWL_H_ + +#include + +struct owl_clk_priv { + phys_addr_t base; +}; + +/* BUSCLK register definitions */ +#define CMU_PDBGDIV_8 7 +#define CMU_PDBGDIV_SHIFT 26 +#define CMU_PDBGDIV_DIV (CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT) +#define CMU_PERDIV_8 7 +#define CMU_PERDIV_SHIFT 20 +#define CMU_PERDIV_DIV (CMU_PERDIV_8 << CMU_PERDIV_SHIFT) +#define CMU_NOCDIV_2 1 +#define CMU_NOCDIV_SHIFT 19 +#define CMU_NOCDIV_DIV (CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT) +#define CMU_DMMCLK_SRC_APLL 2 +#define CMU_DMMCLK_SRC_SHIFT 10 +#define CMU_DMMCLK_SRC (CMU_DMMCLK_SRC_APLL << CMU_DMMCLK_SRC_SHIFT) +#define CMU_APBCLK_DIV BIT(8) +#define CMU_NOCCLK_SRC BIT(7) +#define CMU_AHBCLK_DIV BIT(4) +#define CMU_CORECLK_MASK 3 +#define CMU_CORECLK_CPLL BIT(1) +#define CMU_CORECLK_HOSC BIT(0) + +/* COREPLL register definitions */ +#define CMU_COREPLL_EN BIT(9) +#define CMU_COREPLL_HOSC_EN BIT(8) +#define CMU_COREPLL_OUT (1104 / 24) + +/* DEVPLL register definitions */ +#define CMU_DEVPLL_CLK BIT(12) +#define CMU_DEVPLL_EN BIT(8) +#define CMU_DEVPLL_OUT (660 / 6) + +/* UARTCLK register definitions */ +#define CMU_UARTCLK_SRC_DEVPLL BIT(16) + +/* DEVCLKEN1 register definitions */ +#define CMU_DEVCLKEN1_UART5 BIT(21) + +#define PLL_STABILITY_WAIT_US 50 + +void owl_clk_init(struct owl_clk_priv *priv); +int owl_periph_clk_enable(struct clk *clk); +int owl_periph_clk_disable(struct clk *clk); + +#endif diff --git a/arch/arm/include/asm/arch-owl/regs_s900.h b/arch/arm/include/asm/arch-owl/regs_s900.h new file mode 100644 index 0000000000..9e9106ddaa --- /dev/null +++ b/arch/arm/include/asm/arch-owl/regs_s900.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Actions Semi S900 Register Definitions + * + * Copyright (C) 2015 Actions Semi Co., Ltd. + * Copyright (C) 2018 Manivannan Sadhasivam + * + */ + +#ifndef _OWL_REGS_S900_H_ +#define _OWL_REGS_S900_H_ + +/* CMU registers */ +#define CMU_COREPLL (0x0000) +#define CMU_DEVPLL (0x0004) +#define CMU_DDRPLL (0x0008) +#define CMU_NANDPLL (0x000C) +#define CMU_DISPLAYPLL (0x0010) +#define CMU_AUDIOPLL (0x0014) +#define CMU_TVOUTPLL (0x0018) +#define CMU_BUSCLK (0x001C) +#define CMU_SENSORCLK (0x0020) +#define CMU_LCDCLK (0x0024) +#define CMU_DSICLK (0x0028) +#define CMU_CSICLK (0x002C) +#define CMU_DECLK (0x0030) +#define CMU_BISPCLK (0x0034) +#define CMU_IMXCLK (0x0038) +#define CMU_HDECLK (0x003C) +#define CMU_VDECLK (0x0040) +#define CMU_VCECLK (0x0044) +#define CMU_NANDCCLK (0x004C) +#define CMU_SD0CLK (0x0050) +#define CMU_SD1CLK (0x0054) +#define CMU_SD2CLK (0x0058) +#define CMU_UART0CLK (0x005C) +#define CMU_UART1CLK (0x0060) +#define CMU_UART2CLK (0x0064) +#define CMU_PWM0CLK (0x0070) +#define CMU_PWM1CLK (0x0074) +#define CMU_PWM2CLK (0x0078) +#define CMU_PWM3CLK (0x007C) +#define CMU_USBPLL (0x0080) +#define CMU_ASSISTPLL (0x0084) +#define CMU_EDPCLK (0x0088) +#define CMU_GPU3DCLK (0x0090) +#define CMU_CORECTL (0x009C) +#define CMU_DEVCLKEN0 (0x00A0) +#define CMU_DEVCLKEN1 (0x00A4) +#define CMU_DEVRST0 (0x00A8) +#define CMU_DEVRST1 (0x00AC) +#define CMU_UART3CLK (0x00B0) +#define CMU_UART4CLK (0x00B4) +#define CMU_UART5CLK (0x00B8) +#define CMU_UART6CLK (0x00BC) +#define CMU_TLSCLK (0x00C0) +#define CMU_SD3CLK (0x00C4) +#define CMU_PWM4CLK (0x00C8) +#define CMU_PWM5CLK (0x00CC) +#define CMU_ANALOGDEBUG (0x00D4) +#define CMU_TVOUTPLLDEBUG0 (0x00EC) +#define CMU_TVOUTPLLDEBUG1 (0x00FC) + +#endif diff --git a/arch/arm/mach-owl/Kconfig b/arch/arm/mach-owl/Kconfig index b0b506dbb4..199e772988 100644 --- a/arch/arm/mach-owl/Kconfig +++ b/arch/arm/mach-owl/Kconfig @@ -4,7 +4,7 @@ config SYS_SOC default "owl" choice - prompt "Actions OWL SoCs board select" + prompt "Actions Semi OWL SoCs board select" optional config TARGET_BUBBLEGUM_96 diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index edb4ca58ea..18bf8a6d28 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -89,6 +89,7 @@ source "drivers/clk/exynos/Kconfig" source "drivers/clk/at91/Kconfig" source "drivers/clk/renesas/Kconfig" source "drivers/clk/mvebu/Kconfig" +source "drivers/clk/owl/Kconfig" config ICS8N3QV01 bool "Enable ICS8N3QV01 VCXO driver" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 58139b13a8..078f8d7ae1 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o obj-$(CONFIG_CLK_BOSTON) += clk_boston.o obj-$(CONFIG_CLK_EXYNOS) += exynos/ obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o +obj-$(CONFIG_CLK_OWL) += owl/ obj-$(CONFIG_CLK_RENESAS) += renesas/ obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o diff --git a/drivers/clk/owl/Kconfig b/drivers/clk/owl/Kconfig new file mode 100644 index 0000000000..661f1981b9 --- /dev/null +++ b/drivers/clk/owl/Kconfig @@ -0,0 +1,12 @@ +config CLK_OWL + bool "Actions Semi OWL clock drivers" + depends on CLK && ARCH_OWL + help + Enable support for clock managemet unit present in Actions Semi + OWL SoCs. + +config CLK_S900 + bool "Actions Semi S900 clock driver" + depends on CLK_OWL && ARM64 + help + Enable support for the clocks in Actions Semi S900 SoC. diff --git a/drivers/clk/owl/Makefile b/drivers/clk/owl/Makefile new file mode 100644 index 0000000000..b21f23002d --- /dev/null +++ b/drivers/clk/owl/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-$(CONFIG_CLK_OWL) += clk_owl.o +obj-$(CONFIG_CLK_S900) += clk_s900.o diff --git a/drivers/clk/owl/clk_owl.c b/drivers/clk/owl/clk_owl.c new file mode 100644 index 0000000000..c289825dab --- /dev/null +++ b/drivers/clk/owl/clk_owl.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Actions Semi OWL SoCs Clock driver + * + * Copyright (C) 2015 Actions Semi Co., Ltd. + * Copyright (C) 2018 Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static int owl_clk_probe(struct udevice *dev) +{ + struct owl_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr(dev); + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + /* setup necessary clocks */ + owl_clk_init(priv); + + return 0; +} + +static int owl_clk_enable(struct clk *clk) +{ + return owl_periph_clk_enable(clk); +} + +static int owl_clk_disable(struct clk *clk) +{ + return owl_periph_clk_disable(clk); +} + +static struct clk_ops owl_clk_ops = { + .enable = owl_clk_enable, + .disable = owl_clk_disable, +}; + +static const struct udevice_id owl_clk_ids[] = { + { .compatible = "actions,s900-cmu" }, + { } +}; + +U_BOOT_DRIVER(clk_owl) = { + .name = "clk_owl", + .id = UCLASS_CLK, + .of_match = owl_clk_ids, + .ops = &owl_clk_ops, + .priv_auto_alloc_size = sizeof(struct owl_clk_priv), + .probe = owl_clk_probe, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/owl/clk_s900.c b/drivers/clk/owl/clk_s900.c new file mode 100644 index 0000000000..8fe225b0de --- /dev/null +++ b/drivers/clk/owl/clk_s900.c @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Actions Semi S900 clock driver + * + * Copyright (C) 2015 Actions Semi Co., Ltd. + * Copyright (C) 2018 Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include + +#include + +void owl_clk_init(struct owl_clk_priv *priv) +{ + u32 bus_clk = 0, core_pll, dev_pll; + + /* Enable ASSIST_PLL */ + setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0)); + + udelay(PLL_STABILITY_WAIT_US); + + /* Source HOSC to DEV_CLK */ + clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK); + + /* Configure BUS_CLK */ + bus_clk |= (CMU_PDBGDIV_DIV | CMU_PERDIV_DIV | CMU_NOCDIV_DIV | + CMU_DMMCLK_SRC | CMU_APBCLK_DIV | CMU_AHBCLK_DIV | + CMU_NOCCLK_SRC | CMU_CORECLK_HOSC); + writel(bus_clk, priv->base + CMU_BUSCLK); + + udelay(PLL_STABILITY_WAIT_US); + + /* Configure CORE_PLL */ + core_pll = readl(priv->base + CMU_COREPLL); + core_pll |= (CMU_COREPLL_EN | CMU_COREPLL_HOSC_EN | CMU_COREPLL_OUT); + writel(core_pll, priv->base + CMU_COREPLL); + + udelay(PLL_STABILITY_WAIT_US); + + /* Configure DEV_PLL */ + dev_pll = readl(priv->base + CMU_DEVPLL); + dev_pll |= (CMU_DEVPLL_EN | CMU_DEVPLL_OUT); + writel(dev_pll, priv->base + CMU_DEVPLL); + + udelay(PLL_STABILITY_WAIT_US); + + /* Source CORE_PLL for CORE_CLK */ + clrsetbits_le32(priv->base + CMU_BUSCLK, CMU_CORECLK_MASK, + CMU_CORECLK_CPLL); + + /* Source DEV_PLL for DEV_CLK */ + setbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK); + + udelay(PLL_STABILITY_WAIT_US); +} + +void owl_uart_clk_enable(struct owl_clk_priv *priv) +{ + /* Source HOSC for UART5 interface */ + clrbits_le32(priv->base + CMU_UART5CLK, CMU_UARTCLK_SRC_DEVPLL); + + /* Enable UART5 interface clock */ + setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5); +} + +void owl_uart_clk_disable(struct owl_clk_priv *priv) +{ + /* Disable UART5 interface clock */ + clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5); +} + +int owl_periph_clk_enable(struct clk *clk) +{ + struct owl_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case CLOCK_UART5: + owl_uart_clk_enable(priv); + break; + default: + return 0; + } + + return 0; +} + +int owl_periph_clk_disable(struct clk *clk) +{ + struct owl_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case CLOCK_UART5: + owl_uart_clk_disable(priv); + break; + default: + return 0; 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[81.169.180.215]) by mx.google.com with ESMTP id a21-v6si940950eds.294.2018.06.11.08.53.48; Mon, 11 Jun 2018 08:53:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=NpAeGs5g; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 9B872C21DDC; Mon, 11 Jun 2018 15:51:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 94293C21DB6; Mon, 11 Jun 2018 15:51:22 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id CAE32C21D8E; Mon, 11 Jun 2018 15:50:30 +0000 (UTC) Received: from mail-pf0-f193.google.com (mail-pf0-f193.google.com [209.85.192.193]) by lists.denx.de (Postfix) with ESMTPS id 867DBC21DC1 for ; Mon, 11 Jun 2018 15:50:24 +0000 (UTC) Received: by mail-pf0-f193.google.com with SMTP id a22-v6so10444578pfo.12 for ; Mon, 11 Jun 2018 08:50:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=k7bmf4upKR0JnD3ND9OsWQbf1WYfy6xMWbeNlwS5OMk=; b=NpAeGs5gX5xnCHS2f8W9a3dQ5gRWkg80lrUfB0jbSCD9T8SPeqZBsP8N/e5wkH51mC yKXXsvlL1xa02Xaf8RGxnGny5pkKsjPvg/7sY592zJPVOLS059IHfV/zA/QbdThH3rs8 XbYXOQfse+k/OGVHEjiCl0muH+BBUWGyU2LG0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=k7bmf4upKR0JnD3ND9OsWQbf1WYfy6xMWbeNlwS5OMk=; b=Vq3lmUbOyyFJUyP7U3HRQaGj+rTK5FBFNYEcEh8427N5Tm3yhiui7UrYdMOTTOQ/i9 3L2oJHTYpVsjI7UpN2bdqBy6XStFYCKGPP3ni59TUmb8xB9j4T/319DtTVJ8UGV8WLnN 5VWPiNZVIRVsh3e4XDrjleb994C4eylX6xev5kohmKAH7ARTYoWxv0gVGlzlNGnVh8fw yxoinUcOrNkB7zxkFxHPhpCguKrZ+EBo7Bq+85EU1IU4PJgIVgBZwnd2OhhLv3YU++Pv UoWD8+AxVE8/ptoRBoeiPKLiK1IKPtSol6wMIokPazh6Hm0Ay4dsOO9zC+TZbcSUNAOD jNtg== X-Gm-Message-State: APt69E2mK+46PO39JI/wYALy60jlfMKlqbVceFl2JlVVkWBL6nqIK8SC v/I7zmB/nWZy0crzrkB0yv3m X-Received: by 2002:a62:32c6:: with SMTP id y189-v6mr18198472pfy.241.1528732223117; Mon, 11 Jun 2018 08:50:23 -0700 (PDT) Received: from localhost.localdomain ([2405:204:7288:73c5:d4c6:ffd5:c258:b7e0]) by smtp.gmail.com with ESMTPSA id s1-v6sm31638261pgv.48.2018.06.11.08.50.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Jun 2018 08:50:22 -0700 (PDT) From: Manivannan Sadhasivam To: albert.u.boot@aribaud.net, sjg@chromium.org, marek.vasut+renesas@gmail.com, u-boot@lists.denx.de Date: Mon, 11 Jun 2018 21:18:29 +0530 Message-Id: <20180611154832.3251-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180611154832.3251-1-manivannan.sadhasivam@linaro.org> References: <20180611154832.3251-1-manivannan.sadhasivam@linaro.org> Cc: daniel.thompson@linaro.org, manivannanece23@gmail.com, bdong@ucrobotics.com, thomas.liau@actions-semi.com, hzhang@ucrobotics.com, amit.kucheria@linaro.org, liuwei@actions-semi.com, afaerber@suse.de, jeff.chen@actions-semi.com, mp-cs@actions-semi.com Subject: [U-Boot] [RESEND][PATCH 6/9] arm: dts: s900: Add UART node X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This commit adds UART node for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam --- arch/arm/dts/s900.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/s900.dtsi b/arch/arm/dts/s900.dtsi index e9d47b1ff1..2bbb30a5a8 100644 --- a/arch/arm/dts/s900.dtsi +++ b/arch/arm/dts/s900.dtsi @@ -32,6 +32,14 @@ #size-cells = <0x2>; ranges; + uart5: serial@e012a000 { + u-boot,dm-pre-reloc; + compatible = "actions,s900-serial"; + reg = <0x0 0xe012a000 0x0 0x1000>; + clocks = <&cmu CLOCK_UART5>; + status = "disabled"; + }; + cmu: clock-controller@e0160000 { u-boot,dm-pre-reloc; compatible = "actions,s900-cmu"; From patchwork Mon Jun 11 15:48:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 138254 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp4220261lji; Mon, 11 Jun 2018 08:53:53 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKbsGTeqer8zIOTm3VtYdDODv82LrrEHfQID+HeHexxujY8S9L6g9xuiGIo7Hr9wQ17WKM5 X-Received: by 2002:a50:992a:: with SMTP id k39-v6mr19169074edb.45.1528732433073; Mon, 11 Jun 2018 08:53:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528732433; cv=none; d=google.com; s=arc-20160816; b=jRvWdlhC1wgo1Di++DmOYDJzsG7I7/paa6NaElc20UrvP/bIbERI9L9UoEckLlz0Kk gxjwOCyNG5cMPmChaoTC0fTtrxPZNTAjVE2oopCS610yd92x+m+LhJYIObCVzmEt9mz1 wD9uFZy46ffl6lY28I4FiHrIi9lD1oCRLHggEL/QfPdqDe90eiYOFQi34jwO6HRwM++Q 3VcE3a/IIw6R9RiGMGQYpGGGznLBvOMNWXX40KOmHV99EcR9ekDpj35FAGu/yOh8vXU2 iTtCRJftqnagAoOeFlnTyBPgMWQrn7vd2Nut+4lMJXM53j3KWa/EIAdi3zo3LqE5xPww zpCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:arc-authentication-results; bh=cqdUAC6rhHXLOtA0D7CVZYFJcPpmgovQGGmZlVmVl1M=; b=UnW2e9kIj9K/0Wq2/oEZo9+c9i8pmbH3S4bfqiD1o7CUNYr05kTdgnJMglANu1Y2rX fivuu+7QTU1q3TxwSoqSAaoezu4v7j/F9fp8QivHPvDYwB36EDMhS8sC5rDBV7oUT1rW 7c66BZ3NECYozBTX7WqzRgkdkSfKo+2kND6/47dqRqM50dzx2iOuCGdGUZeElZAYs6M/ pSdUCw/iMyy+mHFUzqZS4c0++ee48rkVlycKo/uJfbtpZlhvV72Dy/Sp7vjiBJtdi9Yu XVFlmSfNKC6sFSpAffK44DICAOJ5V5ZM/ELQdGOPN1oLMqReW9Q7xKuOADFiLY0o3Mel 11xQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=VDIE3yvl; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id g42-v6si6269916edg.360.2018.06.11.08.53.52; Mon, 11 Jun 2018 08:53:53 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=VDIE3yvl; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id A6371C21C6A; Mon, 11 Jun 2018 15:52:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=KHOP_BIG_TO_CC, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 76BACC21D83; Mon, 11 Jun 2018 15:52:05 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D3147C21D8E; Mon, 11 Jun 2018 15:50:35 +0000 (UTC) Received: from mail-pl0-f66.google.com (mail-pl0-f66.google.com [209.85.160.66]) by lists.denx.de (Postfix) with ESMTPS id 0F33CC21D8A for ; Mon, 11 Jun 2018 15:50:32 +0000 (UTC) Received: by mail-pl0-f66.google.com with SMTP id c41-v6so12558128plj.10 for ; Mon, 11 Jun 2018 08:50:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=1WzApZPHdn9rPPykhS8KTFiPpyPh9KeuGwLhdvlSLUE=; b=VDIE3yvlPuOniWIV6y42v+/pPifrb7+3BeSgb/ZKHOvzL2QJAdqZJXKyVi7dI2wBXW VG7Q66D0mRBbkVO8C/Zio3ED5/zjMY6+CmT8rJuokUPSL8IL2oOcjpVAqO4cdS25ksmQ jBXTz6uNC6qYcDoiMn8XWs7rjefmwulcSMlmo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1WzApZPHdn9rPPykhS8KTFiPpyPh9KeuGwLhdvlSLUE=; b=kw0ZxIR+mWgtnRr+GwKdkefAEr/oBnMlFqBE9B1PRqsmIUiflrfIwXshmm0OHE01ky DM9qd1fqvXBC9jM8ejMSaQBpc+3lsPH0lhKBivkp46CUGoHN4O9nRmoPKAkoHx1CXC/5 g8wglzc240RPo1A3Q8fTen1K/haUzWRR8ACT84mcgoGAX0hJ/Hp20Oi1OTaZ8FPYqY8f Pg6WDLNli6VD/HlVN67nFY0ANqfxJ6O+aYzsIvDRJICZF6JkNgjkcgsSS1rBO2gBeHUB nzeI4VrEHXv089E7WfoqmlJvH+roAB70ZT9GVLC8wC4GJeuvFdjRb74l9V0hOkMeP7Cw wGRw== X-Gm-Message-State: APt69E3uSwQ66FpHM1KARkeOe7BULe9zzCLDU0vSaj+61dO3zjFrwdaH MnKrMXxDjwQWos4Kp1alTfix X-Received: by 2002:a17:902:be0b:: with SMTP id r11-v6mr19658202pls.182.1528732230609; Mon, 11 Jun 2018 08:50:30 -0700 (PDT) Received: from localhost.localdomain ([2405:204:7288:73c5:d4c6:ffd5:c258:b7e0]) by smtp.gmail.com with ESMTPSA id s1-v6sm31638261pgv.48.2018.06.11.08.50.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Jun 2018 08:50:29 -0700 (PDT) From: Manivannan Sadhasivam To: albert.u.boot@aribaud.net, sjg@chromium.org, marek.vasut+renesas@gmail.com, u-boot@lists.denx.de Date: Mon, 11 Jun 2018 21:18:30 +0530 Message-Id: <20180611154832.3251-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180611154832.3251-1-manivannan.sadhasivam@linaro.org> References: <20180611154832.3251-1-manivannan.sadhasivam@linaro.org> Cc: daniel.thompson@linaro.org, manivannanece23@gmail.com, bdong@ucrobotics.com, thomas.liau@actions-semi.com, hzhang@ucrobotics.com, amit.kucheria@linaro.org, liuwei@actions-semi.com, afaerber@suse.de, jeff.chen@actions-semi.com, mp-cs@actions-semi.com Subject: [U-Boot] [RESEND][PATCH 7/9] arm: dts: bubblegum_96: Enable UART5 for serial console X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This commit enables UART5 found in S900 SoC for serial console support. Signed-off-by: Manivannan Sadhasivam --- arch/arm/dts/bubblegum_96.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/dts/bubblegum_96.dts b/arch/arm/dts/bubblegum_96.dts index 4e34ebaa49..5b58d15594 100644 --- a/arch/arm/dts/bubblegum_96.dts +++ b/arch/arm/dts/bubblegum_96.dts @@ -12,8 +12,20 @@ model = "Bubblegum-96"; compatible = "ucrobotics,bubblegum-96", "actions,s900"; + aliases { + serial5 = &uart5; + }; + + chosen { + stdout-path = "serial5:115200n8"; + }; + memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; }; + +&uart5 { + status = "okay"; +}; From patchwork Mon Jun 11 15:48:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 138252 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp4220108lji; Mon, 11 Jun 2018 08:53:43 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLCmjcXyX5K8LEep9m+lRiyl4MguxU2mIXyhMb/rUnHQrh89eJQ/TjHeP+/6khW5h8Ml5k5 X-Received: by 2002:a50:92d3:: with SMTP id l19-v6mr19074575eda.52.1528732423027; Mon, 11 Jun 2018 08:53:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1528732423; cv=none; d=google.com; s=arc-20160816; b=oKp5Unl9VEF4XLncGpzIuEQgkN4Jp0+JunezxswTmItYLeD1S6ZRuveyr5hjt1qbWN hoVVd1gF9Yp5s+uyXeW1CppihqpGmwtKNo0ZV7QNdtLxB8pUuKefpZR4bMLSzLEU2+Xt zUVmWIm3cO0QfnOj+mRGWlJG0DoZg7Z9lOm64358MgUIAyx3yEK3ldzcu9eiME6p2YC9 5uJotI/Ol4vU4K2NxAIlKsF0wOp63Qc8V6E2s3755SSdCwr3iTpJMgndeTj8/gtcSZ1C 8FXfoKeZkEND89yGhsjR/smCkUFFpVdLk1HsOO9tjzXDsDNMoGXeMCagiW6d/TeLHOFF UBLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:dkim-signature:arc-authentication-results; bh=otl8Uc8EiKsGI/ktuCa8ylpK8OB+hOn7AtHtBUvyxow=; b=qSu440x1PUrwo4uTI494cvwoozhccKFEt6I0/iKskjP6QFsxWAetGlqBZNukZV/wKU Sry2b/HZSZwoViOp9vOYjf2wbBnAy/y6AQu8PRw9EtwtXcz3/1g9UJelTZSKHbIAb9LO Lm87qXfkYThpIzieIRPfWLyxSyLObssuAJ/3IzaKc0EDPsjADqJwFuWNaJFTjfDE/ba4 Sx6JYvQ5KyZGJSHaDZE//2U79Om81vpOnSrnABzObddAL+z78EKQX4mZAfvl2oNq6mwO MexdFIYTQoYjYfbXEdY8lVE4ASmVjhDwzrQ1eQz2bSe+PGQ1oXyDNEXF5XhbTMaK0nra daeQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=L1SsYDWx; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id z38-v6si1753347edb.261.2018.06.11.08.53.42; Mon, 11 Jun 2018 08:53:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=L1SsYDWx; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id A25E0C21D74; Mon, 11 Jun 2018 15:51:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=KHOP_BIG_TO_CC, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5182EC21CB1; Mon, 11 Jun 2018 15:50:54 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B8203C21DAF; Mon, 11 Jun 2018 15:50:45 +0000 (UTC) Received: from mail-pl0-f68.google.com (mail-pl0-f68.google.com [209.85.160.68]) by lists.denx.de (Postfix) with ESMTPS id 5020FC21D8A for ; Mon, 11 Jun 2018 15:50:41 +0000 (UTC) Received: by mail-pl0-f68.google.com with SMTP id t12-v6so12550030plo.7 for ; Mon, 11 Jun 2018 08:50:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=f/1fdxVAA0aTSFOpliNxb0P9mrDViKV0R/4zJaQgJ9k=; b=L1SsYDWx6eojhki10Jmd3sOJhUJu1YLED7byH6jU6SI4JHl1QucVfzUOSMhaHhoA8Y ckbVRpvy34yO7/NQ611DfOpkrB9dFYeXrsCbKkaW8QOlGvfpvVU+pMvLz342DfqUNLc/ xxhLT75yf9zvB7NKcE/xth/zVvMuWXn+ivG3s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=f/1fdxVAA0aTSFOpliNxb0P9mrDViKV0R/4zJaQgJ9k=; b=AoSaYyhJsNSz+qxrr0ABGsreEnTqtmHGtTmWFyYvnOGmW8YeIZdF20b4ERTONvWgsT 0ZMX8IqS2mvRX3fJzkPiB1CVsSXk8BqE9r6j2zVhOHwO2nZ2Y2M98Xq5F7a+lBRWA+NS K5E32AnurX2bWuw2rDFuSyJKbIgIiVAiFcNmTytCiO40yNlrtn3BROmis1f+T2n5QWgC cg42q4prh0oTz2WCHeDdC2NLqww3hUfynzwwUkRz2GLLRDrEVsUlQVSTlqSvHIuukDvK EISSkR0NbJt66uk1+MrQiTZd8p68m606yX7ZZX+GECOmIhNGiievVYZWzz8sco6SYWtm Isfw== X-Gm-Message-State: APt69E2hKdpyxVzBzHgWVS+Pb7dIAmO57oh/NAXUePZTRiJcZpFmjUOC jQAk6vrNtFFDkC/cUbqOVMei X-Received: by 2002:a17:902:c85:: with SMTP id 5-v6mr12807347plt.126.1528732239838; Mon, 11 Jun 2018 08:50:39 -0700 (PDT) Received: from localhost.localdomain ([2405:204:7288:73c5:d4c6:ffd5:c258:b7e0]) by smtp.gmail.com with ESMTPSA id s1-v6sm31638261pgv.48.2018.06.11.08.50.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Jun 2018 08:50:39 -0700 (PDT) From: Manivannan Sadhasivam To: albert.u.boot@aribaud.net, sjg@chromium.org, marek.vasut+renesas@gmail.com, u-boot@lists.denx.de Date: Mon, 11 Jun 2018 21:18:31 +0530 Message-Id: <20180611154832.3251-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180611154832.3251-1-manivannan.sadhasivam@linaro.org> References: <20180611154832.3251-1-manivannan.sadhasivam@linaro.org> Cc: daniel.thompson@linaro.org, manivannanece23@gmail.com, bdong@ucrobotics.com, thomas.liau@actions-semi.com, hzhang@ucrobotics.com, amit.kucheria@linaro.org, liuwei@actions-semi.com, afaerber@suse.de, jeff.chen@actions-semi.com, mp-cs@actions-semi.com Subject: [U-Boot] [RESEND][PATCH 8/9] serial: Add Actions Semi OWL UART support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This commit adds Actions Semi OWL family UART support. This driver relies on baudrate configured by primary bootloaders. Signed-off-by: Manivannan Sadhasivam --- drivers/serial/Kconfig | 8 +++ drivers/serial/Makefile | 1 + drivers/serial/serial_owl.c | 136 ++++++++++++++++++++++++++++++++++++ 3 files changed, 145 insertions(+) create mode 100644 drivers/serial/serial_owl.c diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 2940bd05dc..766e5ced03 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -625,6 +625,14 @@ config MSM_SERIAL for example APQ8016 and MSM8916. Single baudrate is supported in current implementation (115200). +config OWL_SERIAL + bool "Actions Semi OWL UART" + depends on DM_SERIAL && ARCH_OWL + help + If you have a Actions Semi OWL based board and want to use the on-chip + serial port, say Y to this option. If unsure, say N. + Single baudrate is supported in current implementation (115200). + config PXA_SERIAL bool "PXA serial port support" help diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index e66899489e..9fa81d855d 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -64,6 +64,7 @@ obj-$(CONFIG_MSM_SERIAL) += serial_msm.o obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o +obj-$(CONFIG_OWL_SERIAL) += serial_owl.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_owl.c b/drivers/serial/serial_owl.c new file mode 100644 index 0000000000..6fd97e2502 --- /dev/null +++ b/drivers/serial/serial_owl.c @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Actions Semi OWL SoCs UART driver + * + * Copyright (C) 2015 Actions Semi Co., Ltd. + * Copyright (C) 2018 Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* UART Registers */ +#define OWL_UART_CTL (0x0000) +#define OWL_UART_RXDAT (0x0004) +#define OWL_UART_TXDAT (0x0008) +#define OWL_UART_STAT (0x000C) + +/* UART_CTL Register Definitions */ +#define OWL_UART_CTL_PRS_NONE GENMASK(6, 4) +#define OWL_UART_CTL_STPS BIT(2) +#define OWL_UART_CTL_DWLS 3 + +/* UART_STAT Register Definitions */ +#define OWL_UART_STAT_TFES BIT(10) /* TX FIFO Empty Status */ +#define OWL_UART_STAT_RFFS BIT(9) /* RX FIFO full Status */ +#define OWL_UART_STAT_TFFU BIT(6) /* TX FIFO full Status */ +#define OWL_UART_STAT_RFEM BIT(5) /* RX FIFO Empty Status */ + +struct owl_serial_priv { + phys_addr_t base; +}; + +int owl_serial_setbrg(struct udevice *dev, int baudrate) +{ + /* Driver supports only fixed baudrate */ + return 0; +} + +static int owl_serial_getc(struct udevice *dev) +{ + struct owl_serial_priv *priv = dev_get_priv(dev); + + if (readl(priv->base + OWL_UART_STAT) & OWL_UART_STAT_RFEM) + return -EAGAIN; + + return (int)(readl(priv->base + OWL_UART_RXDAT)); +} + +static int owl_serial_putc(struct udevice *dev, const char ch) +{ + struct owl_serial_priv *priv = dev_get_priv(dev); + + if (readl(priv->base + OWL_UART_STAT) & OWL_UART_STAT_TFFU) + return -EAGAIN; + + writel(ch, priv->base + OWL_UART_TXDAT); + + return 0; +} + +static int owl_serial_pending(struct udevice *dev, bool input) +{ + struct owl_serial_priv *priv = dev_get_priv(dev); + unsigned int stat = readl(priv->base + OWL_UART_STAT); + + if (input) + return !(stat & OWL_UART_STAT_RFEM); + else + return !(stat & OWL_UART_STAT_TFES); +} + +static int owl_serial_probe(struct udevice *dev) +{ + struct owl_serial_priv *priv = dev_get_priv(dev); + struct clk clk; + u32 uart_ctl; + int ret; + + /* Set data, parity and stop bits */ + uart_ctl = readl(priv->base + OWL_UART_CTL); + uart_ctl &= ~(OWL_UART_CTL_PRS_NONE); + uart_ctl &= ~(OWL_UART_CTL_STPS); + uart_ctl |= OWL_UART_CTL_DWLS; + writel(uart_ctl, priv->base + OWL_UART_CTL); + + /* Enable UART clock */ + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) + return ret; + + ret = clk_enable(&clk); + if (ret < 0) + return ret; + + return 0; +} + +static int owl_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct owl_serial_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr(dev); + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + return 0; +} + +static const struct dm_serial_ops owl_serial_ops = { + .putc = owl_serial_putc, + .pending = owl_serial_pending, + .getc = owl_serial_getc, + .setbrg = owl_serial_setbrg, +}; + +static const struct udevice_id owl_serial_ids[] = { + { .compatible = "actions,s900-serial" }, + { } +}; + +U_BOOT_DRIVER(serial_owl) = { + .name = "serial_owl", + .id = UCLASS_SERIAL, + .of_match = owl_serial_ids, + .ofdata_to_platdata = owl_serial_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct owl_serial_priv), + .probe = owl_serial_probe, + .ops = &owl_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; 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[81.169.180.215]) by mx.google.com with ESMTP id f23-v6si18718991eda.356.2018.06.11.08.55.42; Mon, 11 Jun 2018 08:55:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=C3SnUYHg; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 00DD3C21E08; Mon, 11 Jun 2018 15:54:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=KHOP_BIG_TO_CC, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3DF39C21E1B; Mon, 11 Jun 2018 15:54:07 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0947BC21DFD; Mon, 11 Jun 2018 15:50:53 +0000 (UTC) Received: from mail-pl0-f65.google.com (mail-pl0-f65.google.com [209.85.160.65]) by lists.denx.de (Postfix) with ESMTPS id 85FE4C21CB1 for ; Mon, 11 Jun 2018 15:50:49 +0000 (UTC) Received: by mail-pl0-f65.google.com with SMTP id c41-v6so12558580plj.10 for ; Mon, 11 Jun 2018 08:50:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VkL6qS4NwmMucrnyVeQgEQcqxyBMq198pb4L5/vGEpY=; b=C3SnUYHgid5VDksE025/gkbqFJX88ancsMPv9KFKl5ASw4kpklGptTn92Pab5bZSiz pn0NyQCObMGcNkNxzGvxF1FzlQMxybgVQRlPirijkvA0cu9ufJcH99+8oRbJqpsgmOx8 vInBx6KJXnPOJCkWueV9UCoWkuHTnlx7UL/Vk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VkL6qS4NwmMucrnyVeQgEQcqxyBMq198pb4L5/vGEpY=; b=fWGi63OL2ZHCi7XG56teZdoQ0zH91dayxf205uLQssaglOyx3OeMx1PnNEsPBGKBZZ R5O2ZGwbYTiPPN1alFYrrYHkLYhT5TRLTqShhLkxO/tpVwWjUytNUTb9nx2YfpHiMTCi uIKqocP+twGRkiIoH1JKR1kDgFBd+FrOw8X7tY7nXsCTl1IBcn+KbPbgbu1YNhFLjmiz v1O0LG97qP/QirZjWMxTcQ/cg3/Pbu3+Q1lubupPEPeJsnWx6F6BslZuFcb9/dLpLMpw bedndIIrMjPcGnr3tP7BGosh0j45RTVQazSE/d6/qcvBd030dgu3NDhcS3wDWNhNbzGC 1Fkw== X-Gm-Message-State: APt69E09FSUlGzCxKOn6KlS4EUlcHjjMU3rjlwfimZpuJNQCKpFYkrVY TsAcg+ZKwIYOpcLtTXihV7TF X-Received: by 2002:a17:902:728a:: with SMTP id d10-v6mr19245203pll.192.1528732248119; Mon, 11 Jun 2018 08:50:48 -0700 (PDT) Received: from localhost.localdomain ([2405:204:7288:73c5:d4c6:ffd5:c258:b7e0]) by smtp.gmail.com with ESMTPSA id s1-v6sm31638261pgv.48.2018.06.11.08.50.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Jun 2018 08:50:47 -0700 (PDT) From: Manivannan Sadhasivam To: albert.u.boot@aribaud.net, sjg@chromium.org, marek.vasut+renesas@gmail.com, u-boot@lists.denx.de Date: Mon, 11 Jun 2018 21:18:32 +0530 Message-Id: <20180611154832.3251-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180611154832.3251-1-manivannan.sadhasivam@linaro.org> References: <20180611154832.3251-1-manivannan.sadhasivam@linaro.org> Cc: daniel.thompson@linaro.org, manivannanece23@gmail.com, bdong@ucrobotics.com, thomas.liau@actions-semi.com, hzhang@ucrobotics.com, amit.kucheria@linaro.org, liuwei@actions-semi.com, afaerber@suse.de, jeff.chen@actions-semi.com, mp-cs@actions-semi.com Subject: [U-Boot] [RESEND][PATCH 9/9] MAINTAINERS: Add entries for Actions Semi OWL family X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add myself as the Maintainer for Actions Semi OWL family and its relevant board, drivers. Signed-off-by: Manivannan Sadhasivam --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 642c448093..0f70cb04fe 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -145,6 +145,15 @@ T: git git://git.denx.de/u-boot-pxa.git F: arch/arm/cpu/pxa/ F: arch/arm/include/asm/arch-pxa/ +ARM OWL +M: Manivannan Sadhasivam +S: Maintained +F: arch/arm/include/asm/arch-owl/ +F: arch/arm/mach-owl/ +F: board/ucRobotics/ +F: drivers/clk/owl/ +F: drivers/serial/serial_owl.c + ARM RENESAS RMOBILE/R-CAR M: Nobuhiro Iwamatsu M: Marek Vasut