From patchwork Fri Apr 16 08:40:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steen Hegelund X-Patchwork-Id: 422825 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8103EC43462 for ; Fri, 16 Apr 2021 08:41:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2E18661166 for ; Fri, 16 Apr 2021 08:41:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240555AbhDPIla (ORCPT ); Fri, 16 Apr 2021 04:41:30 -0400 Received: from esa.microchip.iphmx.com ([68.232.153.233]:53338 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239882AbhDPIl2 (ORCPT ); Fri, 16 Apr 2021 04:41:28 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1618562464; x=1650098464; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8lTZOjpt/PsZ0L6mL9vuEq3HADt4pfMakp+8pxOPEJk=; b=lGofTreeGtdrhRbb3kbrSgNqezIGn0Sxd7XspPXTKPtzGPX1qdYBTMMz Wba1ONTnzElddmyOS++BBhytngSAwIdmbzJr0l1r00KkbRwYChuSKHFh3 Cj1Hq0wwHlQweVg1QK0xZAqbpFtsP6ioc6wrBiXSxkWLbc0Zz4H0+CRQj UdmAIl4HNlMvUaVyxyPCZR7yv/uURwVrund4uRNFCIEOM/yQkOdrdioy8 iAuxfNrsLNZIEFIoOyo7GXs1kt+gc9qvAra84d+vT/0gC5NRvWsBvO7EM O5MGilK2Ocbjt419l0360wnidolvNablyzUvGtmG6Vj2z9kKUgvWF6t2I g==; IronPort-SDR: Ha6NQ0j0CyD2wsaq7XsdO2Euv7+sh+eBpsXlZ5y52Mx46fmY+ed1kesyLwx2NelqvkM/NxS1E5 RgAWy0HfIdM9ErtRcbk6MB3H++4cREZE7mkVSlisjsA6x49BYSHDjo2jQt8GAWHWDe2WYITkwp Oy/GOPAqlDHBFObS8LGAssse1rV8N9vexGmGf9RC2yM37FIicaoNfMtiyQSAc0GqCO7ocWG044 7/MTFtgT0y48H4pQCEkiIP1SYuwK40lIutn1H8MRJYeiCEFH5xkhv9ZfVF/y2LPeF1914XgLZ9 b5w= X-IronPort-AV: E=Sophos;i="5.82,226,1613458800"; d="scan'208";a="116692462" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Apr 2021 01:41:02 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Fri, 16 Apr 2021 01:41:01 -0700 Received: from mchp-dev-shegelun.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Fri, 16 Apr 2021 01:40:59 -0700 From: Steen Hegelund To: Philipp Zabel , Rob Herring CC: Steen Hegelund , Andrew Lunn , Microchip Linux Driver Support , Alexandre Belloni , Gregory Clement , , , , "Rob Herring" Subject: [PATCH v9 1/3] dt-bindings: reset: microchip sparx5 reset driver bindings Date: Fri, 16 Apr 2021 10:40:52 +0200 Message-ID: <20210416084054.2922327-2-steen.hegelund@microchip.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210416084054.2922327-1-steen.hegelund@microchip.com> References: <20210416084054.2922327-1-steen.hegelund@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the Sparx5 reset device driver bindings The driver uses a syscon and an IO range on sparx5 for access to the reset control and the reset status. Sparx5 will no longer use the existing Ocelot chip reset driver, but use this new switch reset driver as it has the reset controller interface that allows the first client to perform the reset on behalf of all the Sparx5 component drivers. Signed-off-by: Steen Hegelund Reviewed-by: Rob Herring --- .../bindings/reset/microchip,rst.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml diff --git a/Documentation/devicetree/bindings/reset/microchip,rst.yaml b/Documentation/devicetree/bindings/reset/microchip,rst.yaml new file mode 100644 index 000000000000..370579aeeca1 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Microchip Sparx5 Switch Reset Controller + +maintainers: + - Steen Hegelund + - Lars Povlsen + +description: | + The Microchip Sparx5 Switch provides reset control and implements the following + functions + - One Time Switch Core Reset (Soft Reset) + +properties: + $nodename: + pattern: "^reset-controller@[0-9a-f]+$" + + compatible: + const: microchip,sparx5-switch-reset + + reg: + items: + - description: global control block registers + + reg-names: + items: + - const: gcb + + "#reset-cells": + const: 1 + + cpu-syscon: + $ref: "/schemas/types.yaml#/definitions/phandle" + description: syscon used to access CPU reset + +required: + - compatible + - reg + - reg-names + - "#reset-cells" + - cpu-syscon + +additionalProperties: false + +examples: + - | + reset: reset-controller@11010008 { + compatible = "microchip,sparx5-switch-reset"; + reg = <0x11010008 0x4>; + reg-names = "gcb"; + #reset-cells = <1>; + cpu-syscon = <&cpu_ctrl>; + }; + From patchwork Fri Apr 16 08:40:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steen Hegelund X-Patchwork-Id: 423575 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90421C433B4 for ; Fri, 16 Apr 2021 08:41:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 74066611AE for ; Fri, 16 Apr 2021 08:41:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240542AbhDPIlk (ORCPT ); Fri, 16 Apr 2021 04:41:40 -0400 Received: from esa.microchip.iphmx.com ([68.232.154.123]:4861 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240572AbhDPIlb (ORCPT ); Fri, 16 Apr 2021 04:41:31 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1618562466; x=1650098466; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xboU3TO7GJRPpG7WTJfaV2IWSqO0VeAzKYAu121oemk=; b=YydCYjO5OLgNMX8h2lAx20sJjGWoVg+EorRIbLKTrbhpBAybXhp6shrX pDl6wOT8E/XAOm88/EPPhy4vJh1CQu6fYK+XLXWWbh/m7D0hu49/ITzGC GepcWEGxenG2UDxzAovEjUzKWOAvMr38Xna2XdZgMZHdoPhDRKj/HSysv vEqVAgqSi+5BcAj0DEnLfZijW3uEt+1Fft5X67J4tJwPBy+eKr4WKP2Kq gg6YT1cfUZejEOO9zFzA3RbS3WOxAoHi6mIIJT/HkEiLFdfvxRnKCE7NG QgKtSbgv3yS2HBDWtWB1jPaa0uYieQsjWCovGpRnGhSg0uZqx7rcVFiEy Q==; IronPort-SDR: JSWFwF3awOSEQ3akSCeSKD45X3NpLH0YyknPPOgcJR94ZsEiggTU/oFclO8tV5jmD4QJOL/dBF ALUbxnZ3FHK4CUzoEz7e1PSD6gaWFmcItkdb+SJ/nXHa37i7oFynx9gHwVn1YNFd/yk+i1Obfy H2BJIa7m3agPeQ29C+L6QWnA4Qo3jdDDgSlUrDxE/ueqKsr94szIX2lF0c6d9JsM+Tdvskahn4 XyMyAXJIDdruThOtWv53o1yncMH9M8tNFUV7AjMYX35QkO8UAzC5xMPVIOu2k/6wb+lsI1ffCr fwU= X-IronPort-AV: E=Sophos;i="5.82,226,1613458800"; d="scan'208";a="111062406" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 16 Apr 2021 01:41:05 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Fri, 16 Apr 2021 01:41:06 -0700 Received: from mchp-dev-shegelun.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Fri, 16 Apr 2021 01:41:03 -0700 From: Steen Hegelund To: Philipp Zabel , Rob Herring CC: Steen Hegelund , Andrew Lunn , Microchip Linux Driver Support , Alexandre Belloni , Gregory Clement , , , Subject: [PATCH v9 3/3] arm64: dts: reset: add microchip sparx5 switch reset driver Date: Fri, 16 Apr 2021 10:40:54 +0200 Message-ID: <20210416084054.2922327-4-steen.hegelund@microchip.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210416084054.2922327-1-steen.hegelund@microchip.com> References: <20210416084054.2922327-1-steen.hegelund@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This provides reset driver support for the Microchip Sparx5 PCB134 and PCB135 reference boards. The Sparx5 Switch will no longer use the Ocelot Chip Reset Driver (with the compatible string "microchip,sparx5-chip-reset"), but use a separate driver that exposes a reset controller interface and has the compatiple string "microchip,sparx5-switch-reset". Eventually the Sparx5 reset support will be removed from the Ocelot chip reset driver. Signed-off-by: Steen Hegelund Reviewed-by: Alexandre Belloni --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 380281f312d8..dc3ada5cf9fc 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -132,9 +132,12 @@ mux: mux-controller { }; }; - reset@611010008 { - compatible = "microchip,sparx5-chip-reset"; + reset: reset-controller@611010008 { + compatible = "microchip,sparx5-switch-reset"; reg = <0x6 0x11010008 0x4>; + reg-names = "gcb"; + #reset-cells = <1>; + cpu-syscon = <&cpu_ctrl>; }; uart0: serial@600100000 {