From patchwork Fri Jun 15 02:04:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 138642 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp249073lji; Thu, 14 Jun 2018 19:04:52 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLOVWOsrmncLaLLZe/CPuaRUJveU3d0Hq19a/3HWZ4ZtUyZ/1qMsUPgw8Y0G8uVfU05PbEB X-Received: by 2002:a17:902:4545:: with SMTP id m63-v6mr5790505pld.268.1529028292301; Thu, 14 Jun 2018 19:04:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529028292; cv=none; d=google.com; s=arc-20160816; b=hO5b51fDf1oUum5KDQzQKbhnRHNfDzeFznDTztZUXcozuT3oRpuGevnbyTjGJ3ruDY /BNoBgL20hH6PKzE45yyZ2AFrwCuvr1Lr5UxS0DFoDEb+it7FuAl+422b478XQ1f3b0K aMF0JSo7UqG2yDKbMvakywqMaP09gUYJc1k/PrbUH4R1YltAX3YE0tYSPWDMvAhLbWN7 trNjuuiuSVbw28wWRrLNd09VJjhMCCPjc6mjus2HSQtzoe58HvgFm/wTfeyL/Tt3sx63 jpdRoXPmbdIkTKK8TlFjpAc/OwPjtCGG0nAUa8fQ74Pyt+PNIK6bX3xJclbnR+WPFKU0 dtVw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=3FkQjw0tnznQzkqhNl9915wjCXW19DdBddES+/u0pdI=; b=JQ/+qHm5SoQuAjGmqHFzX5yBCep3v78pTmbpRniKgK8DlFQhR927o5vp/LfVz7mYFX nLAJ9M9IpuYzQSEAIKIGucUtYqfVY73diAnQ4q6x9FOvBUHPP1zTr1T1qBkcaUyqUYUN aTgQVsK6kKIU3uVUor1Kg43t6XzR7qUc9Z4nmBNh1+gVT7dPhDJObA1gBCn1daMYqusY rlzXcY1Q1E4xOPHdOkLtZ8qmlkRKsMo14J6RNNa8gT8ozzjEZBijVpCL0vz1+BJVW7Iv XvbXIYFGMpXfW18lDnK8fQ222zI47gsdQi12qSFb2ztCjpSH2TDM8eMXlTVJ7z0BUFUE OsyA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HW9zZO7h; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g17-v6si6578040plo.355.2018.06.14.19.04.52; Thu, 14 Jun 2018 19:04:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HW9zZO7h; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965418AbeFOCEt (ORCPT + 30 others); Thu, 14 Jun 2018 22:04:49 -0400 Received: from mail-pl0-f68.google.com ([209.85.160.68]:44124 "EHLO mail-pl0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965317AbeFOCEq (ORCPT ); Thu, 14 Jun 2018 22:04:46 -0400 Received: by mail-pl0-f68.google.com with SMTP id z9-v6so4524435plk.11 for ; Thu, 14 Jun 2018 19:04:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3FkQjw0tnznQzkqhNl9915wjCXW19DdBddES+/u0pdI=; b=HW9zZO7hejz4TlVe51+27U2fh7I5Dalfh8DeArj+79MNzXuIuQKK5UVBqsy5zGzGnN +ld7wC66ouHlRr0BQqIyEeThpwkxG+A0PMhLIkQ9ZXo6AkdXw8xJRi3X0bpZy0oR2Fyn Cm0gerReU3XWKqHLfnkAux0dDXy8USsYuZwl4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3FkQjw0tnznQzkqhNl9915wjCXW19DdBddES+/u0pdI=; b=LS1mUEJr5VhYYXIMhdv4dO7EPWSZwdtj+JHlc3ydHogicAsrD0N9o6W+pp3eNKnMgc kbM5e6D7ld1fTn0iqnWgNMRhp6K4E9Huras5AHVw/rJRJ/quzfW/77uBU1F8TKJVy5yQ 5bZ3ituKLvOUdOtdkH84RySlKsw/Sghg8aGDNBRXDXOUlJFx1ObwZBlK5NQbOo+M7WFw 1lj6BawLcf5FdEv8h/9aJCgVyDYH4lJbQCQv/qhnSx3pxfoLdPJGD28MtZ84GQHOLDC5 I03uJ52Ln+yeL7X5gg4YIQ18cMYfoENkx/vO3fJjNXiXUrZVDZypy0lPrrQ8LXe0cDPB e3KA== X-Gm-Message-State: APt69E00HM/JJZNxj2jeVhoEWOXpkB9tqpiAYRHU4aG5SVXMoGFVp//N MFCvPWJGgYk00EL0FYMJvs2OFA== X-Received: by 2002:a17:902:4203:: with SMTP id g3-v6mr5588112pld.315.1529028286198; Thu, 14 Jun 2018 19:04:46 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id k69-v6sm9504953pgc.39.2018.06.14.19.04.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 14 Jun 2018 19:04:45 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , zhang.lyra@gmail.com Subject: [PATCH V2 1/7] mmc: sdhci: add sd host v4 mode Date: Fri, 15 Jun 2018 10:04:09 +0800 Message-Id: <1529028255-6022-2-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529028255-6022-1-git-send-email-zhang.chunyan@linaro.org> References: <1529028255-6022-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For SD host controller version 4.00 or later ones, there're two modes of implementation - Version 3.00 compatible mode or Version 4 mode. This patch introduces a flag to record this. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 6 ++++++ drivers/mmc/host/sdhci.h | 6 ++++++ 2 files changed, 12 insertions(+) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 2ededa7f..cf5695f 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3302,6 +3302,12 @@ void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1) v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION); host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT; + if (host->version >= SDHCI_SPEC_400) { + if (sdhci_readw(host, SDHCI_HOST_CONTROL2) & + SDHCI_CTRL_V4_MODE) + host->v4_mode = true; + } + if (host->quirks & SDHCI_QUIRK_MISSING_CAPS) return; diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index c95b0a4..128b0ba 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -184,6 +184,7 @@ #define SDHCI_CTRL_DRV_TYPE_D 0x0030 #define SDHCI_CTRL_EXEC_TUNING 0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 +#define SDHCI_CTRL_V4_MODE 0x1000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 #define SDHCI_CAPABILITIES 0x40 @@ -270,6 +271,8 @@ #define SDHCI_SPEC_100 0 #define SDHCI_SPEC_200 1 #define SDHCI_SPEC_300 2 +#define SDHCI_SPEC_400 3 +#define SDHCI_SPEC_410 4 /* * End of controller registers. @@ -551,6 +554,9 @@ struct sdhci_host { u32 sdma_boundary; unsigned long private[0] ____cacheline_aligned; + + /* Host Version 4 Enable */ + bool v4_mode; }; struct sdhci_ops { From patchwork Fri Jun 15 02:04:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 138644 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp249283lji; Thu, 14 Jun 2018 19:05:06 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJta3OhrceeKEdOBdjRvFbv2Eyndv+tc+Yor5s9Hq3BEArQU3ETq6Q0GGdcyjEB/V2uWkm7 X-Received: by 2002:a17:902:4545:: with SMTP id m63-v6mr5791308pld.268.1529028306104; Thu, 14 Jun 2018 19:05:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529028306; cv=none; d=google.com; s=arc-20160816; b=LBEOtPKXJGO/9bvajGEbI5rqcGCy4Cg0qQL5O1LL9dnK5p5rT4Q33E3zy3x/bFA1AV K/N9+xlG2NurB/lGWC/HyVqlGYQdGcbTwQsD+gpkHbowTSqQyGsEqHQb2QThDyA/nWFA WEaQJ+qD9bjQx0MPCHid37mVpzJAcXXWCkCUgBl6P+FrEso8iVqROU7+qbg6UuQCoc/e 2sCkzm2t2MS8JQ1oPPv9ldpMloVIDjlwR7t+Uu6+OGWwpAVTSni4yWmHTdjbrmkKKGtk tpWW5057fR1B5/FYoNn39VpU800TIsHtOZdweiOtWZXSduysifkzMmDkP1Mbc3tBDQD+ s+KA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=+3GjdRwaIJtxrpzrWThzILTOwfyJwnhrNFXpyH81hF8=; b=ISfZ11RgsIgX2nZ7RwIrm1SNJEfBF7rc2F7lxF4enAQOGpzS3nz5t0xzA1KMrcEcNs rbvtPueiIK2+ZwztPR+F4XEU4y0AFwi/QpqRC9l/1l7IzjgIpNd+4/Wzlt7aVgQ7dRxt BAtABghDdtO9KpyfmAkylbI52Cip+z6/a1u7WkrsuxLAM8wmhAgZwkz+r5moYIdw7fy2 gZKTqwOi0H8uZNucw0ut2XVCVNJR2lbUKZqOvIYbil9Wh98Ip0oQBn88UvGjYRt3CoU8 l4QNl/Q3RP1cdFaN2PK/Vw+Bexk/1NyuVfgBDVunSGi52YnU2t7NtcpTOCBNhuC0hZJN Ng4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H4B8HXrQ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y62-v6si6881948pff.54.2018.06.14.19.05.05; Thu, 14 Jun 2018 19:05:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H4B8HXrQ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965465AbeFOCFE (ORCPT + 30 others); Thu, 14 Jun 2018 22:05:04 -0400 Received: from mail-pf0-f196.google.com ([209.85.192.196]:45799 "EHLO mail-pf0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965432AbeFOCFB (ORCPT ); Thu, 14 Jun 2018 22:05:01 -0400 Received: by mail-pf0-f196.google.com with SMTP id a22-v6so4119732pfo.12 for ; Thu, 14 Jun 2018 19:05:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+3GjdRwaIJtxrpzrWThzILTOwfyJwnhrNFXpyH81hF8=; b=H4B8HXrQPHzHmXvLO2uJhO7+tZm4DOKq+G6jz/S5lZHV/azrP0GuUV20nywHh9VCFw hcYLbncnueJ500OdOAJiudqqc+Q4aYAwNQ7y8oAfv9x4RgYam80rrFyK316Un4tpbf5e mdNUSOoMkzPFWam1MxzBRGSUbO/y6bb0So7dg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+3GjdRwaIJtxrpzrWThzILTOwfyJwnhrNFXpyH81hF8=; b=B6iTqgf47j2HnE1qfo489wTh30S/f+iUZJYstcqcJcLLzVVdKVu9l4lmGkY6Ca9q6I XgdNbRG7weiHQAvPw0DrjI+uUGZomBA9dibzdB+tp+aRbXi0scSWMnDkWyBXdqG/aBMX nq+48tBKXj3/2QWcr0h3QXPxPOFD3mZxXNUzqaHx3r5HPjdnMVyYm98dLjvMeTRI3z3T m9Bi6xGUzURWyx3XsoxbUFcSUPIH/T/f1N1L0gZ8s5fOE3ASEGGr1T0mnSuFEutJtXNM YUyvqgTkvJ9HaRaJwUKNvJi/GteaPx5ZrZGtkSTPaehYKWAfr6CA+MXrtkXL1lM84PjQ Z89w== X-Gm-Message-State: APt69E0dVCxFiiCTtOsyDq7MgeIsLtcLEVfq7wr37kKstRC/5xsICiTM nBHLHFNVBrcQG6CiMbSmgst6uA== X-Received: by 2002:a65:4784:: with SMTP id e4-v6mr4361419pgs.58.1529028301131; Thu, 14 Jun 2018 19:05:01 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id k69-v6sm9504953pgc.39.2018.06.14.19.04.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 14 Jun 2018 19:05:00 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , zhang.lyra@gmail.com Subject: [PATCH V2 3/7] mmc: sdhci: add ADMA2 64-bit addressing support for V4 mode Date: Fri, 15 Jun 2018 10:04:11 +0800 Message-Id: <1529028255-6022-4-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529028255-6022-1-git-send-email-zhang.chunyan@linaro.org> References: <1529028255-6022-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ADMA2 64-bit addressing support is divided into V3 mode and V4 mode. So there are two kinds of descriptors for ADMA2 64-bit addressing i.e. 96-bit Descriptor for V3 mode, and 128-bit Descriptor for V4 mode. 128-bit Descriptor is aligned to 8-byte. For V4 mode, ADMA2 64-bit addressing is enabled via Host Control 2 register. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 50 +++++++++++++++++++++++++++++++++++------------- drivers/mmc/host/sdhci.h | 23 +++++++++++++++++----- 2 files changed, 55 insertions(+), 18 deletions(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index f57201f..5d3b0d8 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -585,6 +585,8 @@ static void sdhci_adma_table_pre(struct sdhci_host *host, void *desc, *align; char *buffer; int len, offset, i; + unsigned int adma2_align = SDHCI_ADMA2_ALIGN(host); + unsigned int adma2_mask = SDHCI_ADMA2_MASK(host); /* * The spec does not specify endianness of descriptor table. @@ -608,8 +610,8 @@ static void sdhci_adma_table_pre(struct sdhci_host *host, * buffer for the (up to three) bytes that screw up the * alignment. */ - offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) & - SDHCI_ADMA2_MASK; + offset = (adma2_align - (addr & adma2_align)) & + adma2_mask; if (offset) { if (data->flags & MMC_DATA_WRITE) { buffer = sdhci_kmap_atomic(sg, &flags); @@ -623,8 +625,8 @@ static void sdhci_adma_table_pre(struct sdhci_host *host, BUG_ON(offset > 65536); - align += SDHCI_ADMA2_ALIGN; - align_addr += SDHCI_ADMA2_ALIGN; + align += adma2_align; + align_addr += adma2_align; desc += host->desc_sz; @@ -668,13 +670,15 @@ static void sdhci_adma_table_post(struct sdhci_host *host, void *align; char *buffer; unsigned long flags; + unsigned int adma2_align = SDHCI_ADMA2_ALIGN(host); + unsigned int adma2_mask = SDHCI_ADMA2_MASK(host); if (data->flags & MMC_DATA_READ) { bool has_unaligned = false; /* Do a quick scan of the SG list for any unaligned mappings */ for_each_sg(data->sg, sg, host->sg_count, i) - if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { + if (sg_dma_address(sg) & adma2_mask) { has_unaligned = true; break; } @@ -686,15 +690,15 @@ static void sdhci_adma_table_post(struct sdhci_host *host, align = host->align_buffer; for_each_sg(data->sg, sg, host->sg_count, i) { - if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { - size = SDHCI_ADMA2_ALIGN - - (sg_dma_address(sg) & SDHCI_ADMA2_MASK); + if (sg_dma_address(sg) & adma2_mask) { + size = adma2_align - + (sg_dma_address(sg) & adma2_mask); buffer = sdhci_kmap_atomic(sg, &flags); memcpy(buffer, align, size); sdhci_kunmap_atomic(buffer, &flags); - align += SDHCI_ADMA2_ALIGN; + align += adma2_align; } } } @@ -3400,6 +3404,26 @@ static int sdhci_allocate_bounce_buffer(struct sdhci_host *host) return 0; } +static inline bool sdhci_use_64bit_dma(struct sdhci_host *host) +{ + u32 addr64bit_en; + + /* + * According to SD Host Controller spec v4.10, bit[27] added from + * version 4.10 in Capabilities Register is used as 64-bit System + * Address support for V4 mode, 64-bit DMA Addressing for V4 mode + * is enabled only if 64-bit Addressing =1 in the Host Control 2 + * register. + */ + if (host->version == SDHCI_SPEC_410 && host->v4_mode) { + addr64bit_en = (sdhci_readw(host, SDHCI_HOST_CONTROL2) & + SDHCI_CTRL_64BIT_ADDR); + return addr64bit_en && (host->caps & SDHCI_CAN_64BIT_V4); + } + + return host->caps & SDHCI_CAN_64BIT; +} + int sdhci_setup_host(struct sdhci_host *host) { struct mmc_host *mmc; @@ -3471,7 +3495,7 @@ int sdhci_setup_host(struct sdhci_host *host) * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to * implement. */ - if (host->caps & SDHCI_CAN_64BIT) + if (sdhci_use_64bit_dma(host)) host->flags |= SDHCI_USE_64_BIT_DMA; if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { @@ -3505,15 +3529,15 @@ int sdhci_setup_host(struct sdhci_host *host) */ if (host->flags & SDHCI_USE_64_BIT_DMA) { host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * - SDHCI_ADMA2_64_DESC_SZ; - host->desc_sz = SDHCI_ADMA2_64_DESC_SZ; + SDHCI_ADMA2_64_DESC_SZ(host); + host->desc_sz = SDHCI_ADMA2_64_DESC_SZ(host); } else { host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * SDHCI_ADMA2_32_DESC_SZ; host->desc_sz = SDHCI_ADMA2_32_DESC_SZ; } - host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN; + host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN(host); buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz + host->adma_table_sz, &dma, GFP_KERNEL); if (!buf) { diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 128b0ba..820a863 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -185,6 +185,7 @@ #define SDHCI_CTRL_EXEC_TUNING 0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 #define SDHCI_CTRL_V4_MODE 0x1000 +#define SDHCI_CTRL_64BIT_ADDR 0x2000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 #define SDHCI_CAPABILITIES 0x40 @@ -206,6 +207,7 @@ #define SDHCI_CAN_VDD_300 0x02000000 #define SDHCI_CAN_VDD_180 0x04000000 #define SDHCI_CAN_64BIT 0x10000000 +#define SDHCI_CAN_64BIT_V4 0x8000000 #define SDHCI_SUPPORT_SDR50 0x00000001 #define SDHCI_SUPPORT_SDR104 0x00000002 @@ -297,9 +299,14 @@ struct sdhci_adma2_32_desc { __le32 addr; } __packed __aligned(4); -/* ADMA2 data alignment */ -#define SDHCI_ADMA2_ALIGN 4 -#define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1) +/* + * ADMA2 data alignment + * According to SD Host Controller spec v4.10, if Host Version 4 Enable is set + * in the Host Control 2 register, 128-bit Descriptor will be selected which + * shall be aligned 8-byte address boundary. + */ +#define SDHCI_ADMA2_ALIGN(host) ((host)->v4_mode ? 8 : 4) +#define SDHCI_ADMA2_MASK(host) (SDHCI_ADMA2_ALIGN(host) - 1) /* * ADMA2 descriptor alignment. Some controllers (e.g. Intel) require 8 byte @@ -308,8 +315,14 @@ struct sdhci_adma2_32_desc { */ #define SDHCI_ADMA2_DESC_ALIGN 8 -/* ADMA2 64-bit DMA descriptor size */ -#define SDHCI_ADMA2_64_DESC_SZ 12 +/* + * ADMA2 64-bit DMA descriptor size + * According to SD Host Controller spec v4.10, there are two kinds of + * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit + * Descriptor, if Host Version 4 Enable is set in the Host Control 2 + * register, 128-bit Descriptor will be selected. + */ +#define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12) /* * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte From patchwork Fri Jun 15 02:04:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 138645 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp249412lji; Thu, 14 Jun 2018 19:05:14 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJNUfHympWxlt6Z22s5fm43JA0yQaozQGw5xZRR0krRoPpaLk4NHRBNntatWaPGkJXR0sNa X-Received: by 2002:a63:6e82:: with SMTP id j124-v6mr4430877pgc.349.1529028314795; Thu, 14 Jun 2018 19:05:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529028314; cv=none; d=google.com; s=arc-20160816; b=ZA+1v9hE+hy9CWYFe0+KxI8ydhZ0y09O3zsEYvlJBcNrQTHR1e1wj5kc57bKqjOihP dTLxHie65bCKOdbkAGVIXhwZ4ycP6r6OrLA657P6kJshWzhxj1AFR6xgeo0jjjFxIQ7n 6eTjR399hThVPb6Q3QihArvnDKL76Az4O5hDyEFFocDvohAi5fcJ9i2KI+yMnzJ/FH2A KlPgGZZy6NI7FaQyaHKHV+KLXxpkuekqOSIr8XsCdGMbIRKJVJwKIU+SjClL6CV70iLs f9knfJzFSeoMSzXCM8u2GJql/QiNpRV+a3xaEYE6aQCdxNul1xCIbc47EfWOV7Sk7ere AtBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=2kKdK2qZqm7YxqxQreraVLLw0s8TN4UgsB3k/YpdPQI=; b=eIJKitXcZTnir3+G2seao95LvCNIxcXmvYqlEZH28KrdnuivWpMoKXtX+m8SW4jWda CA5RsnIJ7b0YDdzm7VkM/pU7l5ZYRX6SRd6sTKGRQMVq487RxHL4G0gMWIFyDcagJOJ1 ZT0QU+I3aOgQHjwmtzxjvE3QewQJiNNYxK1y0Xai0V7zXhy5oDZgSG7OWfkNPPU9FOrb G6VZYcZI2Mos4mw0+l+e3eLVud9rX+LyUPbKbBATXtzd2fzQERLWtD1bsbTLkjl0wvlG bKNUrpPp9PXYY0haESDwE5AO37fcSoHqQkfFbnYZAaxoRNnruOqaUgwEdOw//Lmvo+b7 /U/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=X42FyhXC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n68-v6si6642021pfb.152.2018.06.14.19.05.14; Thu, 14 Jun 2018 19:05:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=X42FyhXC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965486AbeFOCFM (ORCPT + 30 others); Thu, 14 Jun 2018 22:05:12 -0400 Received: from mail-pl0-f65.google.com ([209.85.160.65]:44143 "EHLO mail-pl0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965432AbeFOCFI (ORCPT ); Thu, 14 Jun 2018 22:05:08 -0400 Received: by mail-pl0-f65.google.com with SMTP id z9-v6so4524854plk.11 for ; Thu, 14 Jun 2018 19:05:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2kKdK2qZqm7YxqxQreraVLLw0s8TN4UgsB3k/YpdPQI=; b=X42FyhXCSenAv4Ga0WliOss8Cl4vi1DAOFgbG7LsvEkAlK+cozcgvYSxeKDBsForin n/y8/QlrCYewK5IuFj+O1Cq0LtADv76oEypKgWDIi6R1+WiSf2WPenAvItnsQ/Gpqweg m0nCrcwHPSKyp7nwaNgHYIfjmTmpw0qmJdoto= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2kKdK2qZqm7YxqxQreraVLLw0s8TN4UgsB3k/YpdPQI=; b=ZzAks3tduzQPoI44czszOdHGTJK+6OExGns3FbsuK+T4bM5w24OXIZIjiXeIyt8Jxc 4Fs4S9NA1/x9WXNlykGBOGqULysmUckn5oF/X7pa8rskMplg6u8M4JbWJ238u04Ju7P2 F75GRkyGeq94oy5Agl3Ttfv2dVvXVqnSZQw5WPBOd9obCETluGEkYX1CQrc+aqyWG/Fl dYxtM2nSih0JnbpVfVgSjms1KfDVfcV39cEUb6dqQhjTBN7Dk9v+B1Wm8KfQNg4J0zNZ jp6gY/0ccf3ebTT26y/aVKHjybHubUQl9Seqz9+H4w++WHPH30i2oCzIRtUk4z4vdgC5 kNAQ== X-Gm-Message-State: APt69E3RbrK3ibmK0hGmS7y+nsymHumi/SafGS+2ayQVi0BRJgO60+yT Xq6TEGmmFTYHKL2C7FE8xusX4w== X-Received: by 2002:a17:902:8206:: with SMTP id x6-v6mr5621199pln.220.1529028308184; Thu, 14 Jun 2018 19:05:08 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id k69-v6sm9504953pgc.39.2018.06.14.19.05.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 14 Jun 2018 19:05:07 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , zhang.lyra@gmail.com Subject: [PATCH V2 4/7] mmc: sdhci: add 32-bit block count support for v4 mode Date: Fri, 15 Jun 2018 10:04:12 +0800 Message-Id: <1529028255-6022-5-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529028255-6022-1-git-send-email-zhang.chunyan@linaro.org> References: <1529028255-6022-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When Host Version 4 is enabled, SDMA System Address register is re-defined as 32-bit Block Count, and SDMA uses ADMA System Address register (05Fh-058h) instead. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 3 ++- drivers/mmc/host/sdhci.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 5d3b0d8..b8ee124 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -943,7 +943,8 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) /* Set the DMA boundary value and block size */ sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz), SDHCI_BLOCK_SIZE); - sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); + reg = host->v4_mode ? SDHCI_32BIT_BLK_CNT : SDHCI_BLOCK_COUNT; + sdhci_writew(host, data->blocks, reg); } static inline bool sdhci_auto_cmd12(struct sdhci_host *host, diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 820a863..1e84539 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -28,6 +28,7 @@ #define SDHCI_DMA_ADDRESS 0x00 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS +#define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS #define SDHCI_BLOCK_SIZE 0x04 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) From patchwork Fri Jun 15 02:04:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 138647 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp249575lji; Thu, 14 Jun 2018 19:05:27 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKA/MBqNbgk9GYebbsJQQTG2dr7yhTB8hBGc9N6FYxGIXvdKknLSEh0rR00267qwmd7x23m X-Received: by 2002:a62:701:: with SMTP id b1-v6mr12043588pfd.252.1529028327615; Thu, 14 Jun 2018 19:05:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529028327; cv=none; d=google.com; s=arc-20160816; b=F8s/1cu3PNePFxw9LKNlNqBWcfOXxeFyJ11dwZVHU2OrzwrwRwl27r3C1m4dQNBGQW ILAJxSVqLvSDB4pRavVVMU+QVnCEKkmhN0lmh0xcO3Y04pfbQSkXUWT61ONeZ9nIKYag b8a+X5B/NRu1+Bgi5L1TlOaNX4FbytS1IAcHxmKiIQ2ylQYbbcjeF9X0STPkRg5F2xhi L6GZ39TmyV4vZDpwbj7cF9tMGsF4On2SXz4lnKrNDB28KsQ8mapzm04AISt3T8y9W5Im Qe/AzK4IBxoDbsIWAVXNsLWX5rIGLH+tZ4G37scnn3z7EKuHXn3uBotE71zJo7tg/p8m /Nxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=BjX5zM0LmbVITOBlvqQNXo2Pc3GMMZYVlIYP2wQGNF4=; b=zPvQkL9tW2YGryr+DsrfMRrcamICiAvQMOOCCKxe1XdmmXVaRlOyr4F3whNqeuFSrK /eZgYupcI75no4LTnkiCn6bomzXWwasBz0KFoz9+8/5e+h/HkZTFEIlSkK8msCylhkyY a2cP422rDv91MmLBGeO0fagMbBbhwg5RBiCN633S7z8KIikDe6GVroEIHnFS+rtEfmJN 36cXN9Td1vQ6zmfhhjZN5i6HtOtRGy+RwltBZXu/SwWPNCgfvFYFgi3dHC+zdDzjV5Vh bREnskehQjvt3GklXV29DExhSMBduKt2LiMozfT5lvXXFiZ3F+nOZ8C2vEyu4mSrRZiH F8Wg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XL2RydPO; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a3-v6si8080570pll.412.2018.06.14.19.05.27; Thu, 14 Jun 2018 19:05:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XL2RydPO; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965524AbeFOCF0 (ORCPT + 30 others); Thu, 14 Jun 2018 22:05:26 -0400 Received: from mail-pg0-f65.google.com ([74.125.83.65]:37488 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965475AbeFOCFV (ORCPT ); Thu, 14 Jun 2018 22:05:21 -0400 Received: by mail-pg0-f65.google.com with SMTP id r21-v6so3742989pgv.4 for ; Thu, 14 Jun 2018 19:05:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BjX5zM0LmbVITOBlvqQNXo2Pc3GMMZYVlIYP2wQGNF4=; b=XL2RydPOtgtcMHtYb2/Rt2GL3bD/xbiz5SatYvtwJ9EcRPTjA9Xl9h/J0JaaD6gqHi V7uNiAs1zwIn4W9IROIPGflxg3ZBin0VmkhdebwHrE18h4Mw1QpQBZqtybm4hRRkqQ2Y ESbmVX0/2PFU98ZEopQavSQbyfWAsr13kOTco= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BjX5zM0LmbVITOBlvqQNXo2Pc3GMMZYVlIYP2wQGNF4=; b=LAlrAt1SE2+MWgZ8tiCaILnSfOZje7U4lppV1O/ZBfnDumqe+Z2xCRA97fBG6JKPGE YmMtLNBAe4B4iJaOVim9rgjMc1Nik8hHdPGqwYFfpRG24JdWz8OurKN4+fIg5UfE98Xa n5IcMMrFNyQkisz8tC7k0Hfy+GTen3sPh8qPXkqRFmXaaKIKOYer/owkK7QI8XnkBCrM huano8GKPLfX4XOIiIwg3TWJ7cFfRF6iTSrcI56+96gtD97s9Pt1OAHE/ARToetzzjNS 5m2lSgugkIenPfHUvc5QP8GCcH0GYrmQMTgijCnFALIW4+GaYNaaqLpUPA1hPb6Tax6h gWbA== X-Gm-Message-State: APt69E1R0BSvBNWBTOLR7M/FedLs3XZ4NOyHSxD7DthHBggneuORTavt vevetn4T5Je1ir4FjcrCG+mUXg== X-Received: by 2002:a63:5f12:: with SMTP id t18-v6mr4297044pgb.81.1529028320613; Thu, 14 Jun 2018 19:05:20 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id k69-v6sm9504953pgc.39.2018.06.14.19.05.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 14 Jun 2018 19:05:19 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , zhang.lyra@gmail.com Subject: [PATCH V2 6/7] mmc: sdhci-sprd: added Spreadtrum's initial host controller Date: Fri, 15 Jun 2018 10:04:14 +0800 Message-Id: <1529028255-6022-7-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529028255-6022-1-git-send-email-zhang.chunyan@linaro.org> References: <1529028255-6022-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chunyan Zhang This patch adds the initial support of Secure Digital Host Controller Interface compliant controller found in some latest Spreadtrum chipsets. This patch has been tested on the version of SPRD-R11 controller. R11 is a variant based on SD v4.0 specification. With this driver, R11 mmc can be initialized, can be mounted, read and written. Original-by: Billows Wu Signed-off-by: Chunyan Zhang --- drivers/mmc/host/Kconfig | 13 ++ drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-sprd.c | 426 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 440 insertions(+) create mode 100644 drivers/mmc/host/sdhci-sprd.c -- 2.7.4 diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 9589f9c..1b0ee11 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -584,6 +584,19 @@ config MMC_SDRICOH_CS To compile this driver as a module, choose M here: the module will be called sdricoh_cs. +config MMC_SDHCI_SPRD + tristate "Spreadtrum SDIO host Controller" + depends on ARCH_SPRD + depends on MMC_SDHCI_PLTFM + select MMC_SDHCI_IO_ACCESSORS + help + This selects the SDIO Host Controller in Spreadtrum + SoCs, this driver supports R11(IP version: R11P0). + + If you have a controller with this interface, say Y or M here. + + If unsure, say N. + config MMC_TMIO_CORE tristate diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 6aead24..5835bc4 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -88,6 +88,7 @@ obj-$(CONFIG_MMC_SDHCI_ST) += sdhci-st.o obj-$(CONFIG_MMC_SDHCI_MICROCHIP_PIC32) += sdhci-pic32.o obj-$(CONFIG_MMC_SDHCI_BRCMSTB) += sdhci-brcmstb.o obj-$(CONFIG_MMC_SDHCI_OMAP) += sdhci-omap.o +obj-$(CONFIG_MMC_SDHCI_SPRD) += sdhci-sprd.o obj-$(CONFIG_MMC_CQHCI) += cqhci.o ifeq ($(CONFIG_CB710_DEBUG),y) diff --git a/drivers/mmc/host/sdhci-sprd.c b/drivers/mmc/host/sdhci-sprd.c new file mode 100644 index 0000000..f1b0f2b --- /dev/null +++ b/drivers/mmc/host/sdhci-sprd.c @@ -0,0 +1,426 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Secure Digital Host Controller +// +// Copyright (C) 2018 Spreadtrum, Inc. +// Author: Chunyan Zhang + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sdhci-pltfm.h" + +#define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208 +#define SDHCIBSPRD_IT_WR_DLY_INV (1 << 5) +#define SDHCI_SPRD_BIT_CMD_DLY_INV (1 << 13) +#define SDHCI_SPRD_BIT_POSRD_DLY_INV (1 << 21) +#define SDHCI_SPRD_BIT_NEGRD_DLY_INV (1 << 29) + +#define SDHCI_SPRD_REG_32_BUSY_POSI 0x250 +#define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN (1 << 25) +#define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN (1 << 24) + +#define SDHCI_SPRD_REG_DEBOUNCE 0x28C +#define SDHCI_SPRD_BIT_DLL_BAK (1 << 0) +#define SDHCI_SPRD_BIT_DLL_VAL (1 << 1) + +#define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B + +/* SDHCI_HOST_CONTROL2 */ +#define SDHCI_SPRD_CTRL_HS200 0x0005 +#define SDHCI_SPRD_CTRL_HS400 0x0006 + +/* SDHCI_SOFTWARE_RESET */ +#define SDHCI_HW_RESET_CARD 0x8 /* For Spreadtrum's design */ + +#define SDHCI_SPRD_MAX_CUR 0xFFFFFF +#define SDHCI_SPRD_CLK_MAX_DIV 0x3FF + +#define SDHCI_SPRD_CLK_DEF_RATE 26000000 + +struct sdhci_sprd_host { + u32 version; + struct clk *clk_sdio; + struct clk *clk_enable; + u32 base_rate; +}; + +#define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host)) + +static void sdhci_sprd_init_config(struct sdhci_host *host) +{ + u16 val; + + /* set 64-bit addressing modes */ + val = sdhci_readw(host, SDHCI_HOST_CONTROL2); + val |= SDHCI_CTRL_64BIT_ADDR; + sdhci_writew(host, val, SDHCI_HOST_CONTROL2); + + /* set dll backup mode */ + val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); + val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL; + sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); +} + +static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg) +{ + if (unlikely(reg == SDHCI_MAX_CURRENT)) + return SDHCI_SPRD_MAX_CUR; + + return readl_relaxed(host->ioaddr + reg); +} + +static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg) +{ + /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */ + if (unlikely(reg == SDHCI_MAX_CURRENT)) + return; + + if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE)) + val = val & SDHCI_SPRD_INT_SIGNAL_MASK; + + return writel_relaxed(val, host->ioaddr + reg); +} + +static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg) +{ + if (unlikely(reg == SDHCI_SOFTWARE_RESET)) { + if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD) + val |= SDHCI_HW_RESET_CARD; + } + + return writeb_relaxed(val, host->ioaddr + reg); +} + +static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host) +{ + u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + + ctrl &= (~SDHCI_CLOCK_CARD_EN); + sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); +} + +static inline void +sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en) +{ + u32 dll_dly_offset; + + dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); + if (en) + dll_dly_offset |= mask; + else + dll_dly_offset &= ~mask; + sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); +} + +static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk) +{ + u32 div; + + /* select 2x clock source */ + if (base_clk <= clk * 2) + return 0; + + div = (u32) (base_clk / (clk * 2)); + + if ((base_clk / div) > (clk * 2)) + div++; + + if (div > SDHCI_SPRD_CLK_MAX_DIV) + div = SDHCI_SPRD_CLK_MAX_DIV; + + if (div % 2) + div = (div + 1) / 2; + else + div = div / 2; + + return div; +} + +static inline void _sdhci_sprd_set_clock(struct sdhci_host *host, + unsigned int clk) +{ + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + u32 div, val, mask; + + div = sdhci_sprd_calc_div(sprd_host->base_rate, clk); + + clk |= ((div & 0x300) >> 2) | ((div & 0xFF) << 8); + sdhci_enable_clk(host, clk); + + /* enable auto gate sdhc_enable_auto_gate */ + val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); + mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | + SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; + if (mask != (val & mask)) { + val |= mask; + sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); + } +} + +static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock) +{ + bool en = false; + + if (clock == 0) { + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); + } else if (clock != host->clock) { + sdhci_sprd_sd_clk_off(host); + _sdhci_sprd_set_clock(host, clock); + + if (clock <= 400000) + en = true; + sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV | + SDHCI_SPRD_BIT_POSRD_DLY_INV, en); + } else { + _sdhci_sprd_set_clock(host, clock); + } + +} + +static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host) +{ + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + + return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX); +} + +static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host) +{ + return 400000; +} + +static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host, + unsigned int timing) +{ + u16 ctrl_2; + + if (timing == host->timing) + return; + + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + /* Select Bus Speed Mode for host */ + ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; + switch (timing) { + case MMC_TIMING_UHS_SDR12: + ctrl_2 = SDHCI_CTRL_UHS_SDR12; + break; + case MMC_TIMING_MMC_HS: + case MMC_TIMING_SD_HS: + case MMC_TIMING_UHS_SDR25: + ctrl_2 = SDHCI_CTRL_UHS_SDR25; + break; + case MMC_TIMING_UHS_SDR50: + ctrl_2 = SDHCI_CTRL_UHS_SDR50; + break; + case MMC_TIMING_UHS_SDR104: + ctrl_2 = SDHCI_CTRL_UHS_SDR104; + break; + case MMC_TIMING_UHS_DDR50: + case MMC_TIMING_MMC_DDR52: + ctrl_2 = SDHCI_CTRL_UHS_DDR50; + break; + case MMC_TIMING_MMC_HS200: + ctrl_2 = SDHCI_SPRD_CTRL_HS200; + break; + case MMC_TIMING_MMC_HS400: + ctrl_2 = SDHCI_SPRD_CTRL_HS400; + break; + default: + break; + } + + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); +} + +static void sdhci_sprd_hw_reset(struct sdhci_host *host) +{ + int val; + + /* Note: don't use sdhci_readb/writeb() API here */ + val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET); + val &= ~SDHCI_HW_RESET_CARD; + writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); + udelay(10); + + val |= SDHCI_HW_RESET_CARD; + writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); + udelay(300); +} + +static struct sdhci_ops sdhci_sprd_ops = { + .read_l = sdhci_sprd_readl, + .write_l = sdhci_sprd_writel, + .write_b = sdhci_sprd_writeb, + .set_clock = sdhci_sprd_set_clock, + .get_max_clock = sdhci_sprd_get_max_clock, + .get_min_clock = sdhci_sprd_get_min_clock, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_sprd_set_uhs_signaling, + .hw_reset = sdhci_sprd_hw_reset, +}; + +static const struct sdhci_pltfm_data sdhci_sprd_pdata = { + .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, + .quirks2 = SDHCI_QUIRK2_BROKEN_HS200, + .ops = &sdhci_sprd_ops, +}; + +static int sdhci_sprd_probe(struct platform_device *pdev) +{ + struct sdhci_host *host; + struct sdhci_sprd_host *sprd_host; + struct clk *clk; + int ret = 0; + + host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host)); + if (IS_ERR(host)) + return PTR_ERR(host); + + host->dma_mask = DMA_BIT_MASK(64); + pdev->dev.dma_mask = &host->dma_mask; + + host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | + MMC_CAP_ERASE | MMC_CAP_CMD23; + mmc_of_parse(host->mmc); + if (ret) + goto pltfm_free; + + sprd_host = TO_SPRD_HOST(host); + + clk = devm_clk_get(&pdev->dev, "sdio"); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + goto pltfm_free; + } + sprd_host->clk_sdio = clk; + sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio); + if (!sprd_host->base_rate) + sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE; + + clk = devm_clk_get(&pdev->dev, "enable"); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + goto pltfm_free; + } + sprd_host->clk_enable = clk; + + clk_prepare_enable(sprd_host->clk_sdio); + clk_prepare_enable(sprd_host->clk_enable); + + sdhci_sprd_init_config(host); + + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >> + SDHCI_VENDOR_VER_SHIFT); + + pm_runtime_get_noresume(&pdev->dev); + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + pm_runtime_set_autosuspend_delay(&pdev->dev, 50); + pm_runtime_use_autosuspend(&pdev->dev); + pm_suspend_ignore_children(&pdev->dev, 1); + + ret = sdhci_add_host(host); + if (ret) { + dev_err(&pdev->dev, "failed to add mmc host: %d\n", ret); + goto pm_runtime_disable; + } + + pm_runtime_mark_last_busy(&pdev->dev); + pm_runtime_put_autosuspend(&pdev->dev); + + return 0; + +pm_runtime_disable: + pm_runtime_disable(&pdev->dev); + pm_runtime_set_suspended(&pdev->dev); + + clk_disable_unprepare(sprd_host->clk_sdio); + clk_disable_unprepare(sprd_host->clk_enable); + +pltfm_free: + sdhci_pltfm_free(pdev); + return ret; +} + +static int sdhci_sprd_remove(struct platform_device *pdev) +{ + struct sdhci_host *host = platform_get_drvdata(pdev); + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + struct mmc_host *mmc = host->mmc; + + mmc_remove_host(mmc); + clk_disable_unprepare(sprd_host->clk_sdio); + clk_disable_unprepare(sprd_host->clk_enable); + + mmc_free_host(mmc); + + return 0; +} + +static const struct of_device_id sdhci_sprd_of_match[] = { + { .compatible = "sprd,sdhci-r11", }, + { } +}; +MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match); + +#ifdef CONFIG_PM +static int sdhci_sprd_runtime_suspend(struct device *dev) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + + sdhci_runtime_suspend_host(host); + + clk_disable_unprepare(sprd_host->clk_sdio); + clk_disable_unprepare(sprd_host->clk_enable); + + return 0; +} + +static int sdhci_sprd_runtime_resume(struct device *dev) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + + clk_prepare_enable(sprd_host->clk_enable); + clk_prepare_enable(sprd_host->clk_sdio); + + sdhci_runtime_resume_host(host); + + return 0; +} +#endif + +static const struct dev_pm_ops sdhci_sprd_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) + SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend, + sdhci_sprd_runtime_resume, NULL) +}; + +static struct platform_driver sdhci_sprd_driver = { + .probe = sdhci_sprd_probe, + .remove = sdhci_sprd_remove, + .driver = { + .name = "sdhci_sprd_r11", + .of_match_table = of_match_ptr(sdhci_sprd_of_match), + .pm = &sdhci_sprd_pm_ops, + }, +}; +module_platform_driver(sdhci_sprd_driver); + +MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:sdhci-sprd-r11"); From patchwork Fri Jun 15 02:04:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 138648 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp249649lji; Thu, 14 Jun 2018 19:05:35 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJYjndqhTly6qG89mEJ1s/PwQLnxBOZyOW5c10vHmNdpB178lJG2LznnkmWPayaZJPUQCTN X-Received: by 2002:a62:859c:: with SMTP id m28-v6mr11986053pfk.42.1529028335254; Thu, 14 Jun 2018 19:05:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529028335; cv=none; d=google.com; s=arc-20160816; b=P1H9s45jKqYZ+RootjF9XcCybH4K/d4mAx46Ym+lbATgzjBUopir7uJ9OpkO2ZfyNt yqr5H6Igez+4wt7RmaspJstvcnqtk0+CUMN5VIjdsSGkGx5B1cWuFg8gtPUZGF/lQty+ V7c9no13wYlIH6n+JG6eFdSODObxROHZTcX6oSyD1WM2FAm73KnnCstTS4zCMkWwMsoV KU2s6FwJwFAzVtKgwJe8ZGpSzPapSJK12BBxk2wOQHUAxm+doI/gU83fy9fJ2srQE6BQ +FppdI32mqSnZ53FLdv6F0GANUYEdFundoqMNXCpd3GZqm5v++V2BEgTi6Km8ucOL60n Q4fQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=iMrql5pChvk0l0OVuaoPU9zdtIybInbwoq7vsafDp1A=; b=GPVR9hltrShZ2IH00AGzicJabdQB4vd/PBiwFZBsFf+vDK+wopa16hjOeNzMhHir6Q yrvabY38KFx5R4Qk0iDHEwPpKh3K4vbRfk/4bcbF31rIhCqjvxbbmJ1OYoVRGUhTEGip aKNPqPwiITQ2cfwWX77Esd1sLPihsX9m221/EyyEo8LFxV1ceTYF7iS9+3q4VyviZebt lfOG9Uppt41MR4e/T854LofrPGUK75M98rTJtNrvBuztxv1r3DZO/gundZQOauKa2ZeC J4cv+VQR2Vbc9fDE5n38URC3tB4rvm11a+ombwyvEH/kgLEQMW/7NIow+S6MKObt1Ydh G6/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZFwLRIYf; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k7-v6si5476071pgt.235.2018.06.14.19.05.34; Thu, 14 Jun 2018 19:05:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZFwLRIYf; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965537AbeFOCFc (ORCPT + 30 others); Thu, 14 Jun 2018 22:05:32 -0400 Received: from mail-pf0-f193.google.com ([209.85.192.193]:33543 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965475AbeFOCF0 (ORCPT ); Thu, 14 Jun 2018 22:05:26 -0400 Received: by mail-pf0-f193.google.com with SMTP id b17-v6so4134071pfi.0 for ; Thu, 14 Jun 2018 19:05:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iMrql5pChvk0l0OVuaoPU9zdtIybInbwoq7vsafDp1A=; b=ZFwLRIYf1YMykqsQUjRHRqpN6ibWMmukmz+3u1v2oql47QrPLYYZMaXn8EblWJ6SAy 6E0gBwWqnlRh9auRrDR2Y4FhwuTaI+7V1XmoFOpoCqg3Bq4G7IzdMrj8BJZetfMpbSlj n3glKy+FwSivSAjshgGEAnlJhXx/xHq7vsAq0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iMrql5pChvk0l0OVuaoPU9zdtIybInbwoq7vsafDp1A=; b=AqYCKxIpd7c6rH2QDj3csfNjuR8I6OqKMDuIZ8mAw969e+p7LH1zABPd/wQf/4GVnp juJELckiiXPy+dPnzM4Y8cv1PIGrmchghfmte91UlU7jPSt1z5t+m6nA/sJZiemBYcKk hogojFaluamUbsrDAya5CULL/dpenMax9W7XLvCCyTlZMQ0jkmDQehFVjmwcPuVih1J1 t8A7hZREgvFbUR9Qe2AoPCOK6EvH/oKa1OggqpJR38pIWWJlpBqjj40G3UhIhpheMwSN bPB6NLaAPxZnB7OCV2QIGGcbTCpOh45GZPtJSWNOt0rqxNBC6CUoaCbksp99QE4MBGnN pkDg== X-Gm-Message-State: APt69E2ZDqBaQrOKubH+FACppoJiMukilFz+u71HzyaBf629I/pQOuA0 D6dukTBxh9pIPkEKGuVcvx395wYyV40= X-Received: by 2002:a62:4556:: with SMTP id s83-v6mr12043599pfa.73.1529028326182; Thu, 14 Jun 2018 19:05:26 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id k69-v6sm9504953pgc.39.2018.06.14.19.05.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 14 Jun 2018 19:05:25 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , zhang.lyra@gmail.com Subject: [PATCH V2 7/7] dt-bindings: sdhci-sprd: Add bindings for the sdhci-sprd controller Date: Fri, 15 Jun 2018 10:04:15 +0800 Message-Id: <1529028255-6022-8-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1529028255-6022-1-git-send-email-zhang.chunyan@linaro.org> References: <1529028255-6022-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chunyan Zhang This patch adds the device-tree binding documentation for Spreadtrum SDHCI driver. Signed-off-by: Chunyan Zhang --- .../devicetree/bindings/mmc/sdhci-sprd.txt | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-sprd.txt -- 2.7.4 diff --git a/Documentation/devicetree/bindings/mmc/sdhci-sprd.txt b/Documentation/devicetree/bindings/mmc/sdhci-sprd.txt new file mode 100644 index 0000000..45c9978 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/sdhci-sprd.txt @@ -0,0 +1,41 @@ +* Spreadtrum SDHCI controller (sdhci-sprd) + +The Secure Digital (SD) Host controller on Spreadtrum SoCs provides an interface +for MMC, SD and SDIO types of cards. + +This file documents differences between the core properties in mmc.txt +and the properties used by the sdhci-sprd driver. + +Required properties: +- compatible: Should contain "sprd,sdhci-r11". +- reg: physical base address of the controller and length. +- interrupts: Interrupts used by the SDHCI controller. +- clocks: Should contain phandle for the clock feeding the SDHCI controller +- clock-names: Should contain the following: + "sdio" - SDIO source clock (required) + "enable" - gate clock which used for enabling/disabling the device (required) + +Optional properties: +- assigned-clocks: the same with "sdio" clock +- assigned-clock-parents: the default parent of "sdio" clock + +Examples: + +sdio0: sdio@20600000 { + compatible = "sprd,sdhci-r11"; + reg = <0 0x20600000 0 0x1000>; + interrupts = ; + + clock-names = "sdio", "enable"; + clocks = <&ap_clk CLK_EMMC_2X>, + <&apahb_gate CLK_EMMC_EB>; + assigned-clocks = <&ap_clk CLK_EMMC_2X>; + assigned-clock-parents = <&rpll CLK_RPLL_390M>; + + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + cap-mmc-hw-reset; + status = "okay"; +};