From patchwork Wed Jun 20 12:11:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 139321 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp713120lji; Wed, 20 Jun 2018 05:13:35 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJ0rg+bU270UZqjZpgnHbznvMWV8eToDPDQ/tVKnxKrJ4uCFZ2bfxuF6WjVpZQFgI5eCSrL X-Received: by 2002:a62:1282:: with SMTP id 2-v6mr3111124pfs.243.1529496815245; Wed, 20 Jun 2018 05:13:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529496815; cv=none; d=google.com; s=arc-20160816; b=HEWuCzZDXJVSYDj/ybpGuJghEmNK+kg6T3viiaxhGIzoauOpy8168fYzNPkYh9YyqN BOtMNoC8pGL0RTxPcPpo9rUDAps4M7CV38LUSXzJK43iTeuMAMgOauCMI5WVwEfulfYj jCRWD/vClCjqiidAQDGe7WdjNKq/026x9WQHkC3SJg/YvKg14yxSFIvDR7XGh9LwQiFQ KjLWE+fw4u07pnoh71N9DRYyCHu7bMvNwNzWWCTMCD5JCK7LvMH2ELg/siyP6DsTh2qf 4IpNE6ttfLZJq9AJchDnVmgq3CiEXPmHXzDsPIdMFgVtNGIKSBOucyKVXpD6Xyj24/GT yrbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=mMiG6cM8VBvBAXZfGrxSfXokkjogyEYvlGb3JfwBdAo=; b=Txmc5B4nUY4H0NZnij4eB2Dov/5YR52keinF5I1iO7BjXwM0ZHsydRm6X4aJyKnrh/ nFAmYxzn6lwAGFpou0FwAeoRsb8g4iQ9Q52LVB+aYSqCPO3GPTocec8MkxX3+oUb24tA B/WR0j/ONxbrIUWQfrKbLTe+pjBp31VTlpPiE6LOIiuUQEdlWKQgSJnSSlQVzlZj1ByH qE0QtMiBrSqdGSvk0gxLxwQ6uoiTrcl8tWa1O6pENtiToxGzL/I6UQN7LEga8HuZxIBu Oy7fngVKh5sqUKY1WKnolV8GIoQePaizBI3avmOKbIGZaS7XRB0K4nHEglKgc8wOM9iw 9zUw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=amUAOkXl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r6-v6si1829821pgp.426.2018.06.20.05.13.34; Wed, 20 Jun 2018 05:13:35 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=amUAOkXl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754186AbeFTMNc (ORCPT + 30 others); Wed, 20 Jun 2018 08:13:32 -0400 Received: from mail-wm0-f67.google.com ([74.125.82.67]:53856 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751337AbeFTMLu (ORCPT ); Wed, 20 Jun 2018 08:11:50 -0400 Received: by mail-wm0-f67.google.com with SMTP id x6-v6so5604190wmc.3 for ; Wed, 20 Jun 2018 05:11:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mMiG6cM8VBvBAXZfGrxSfXokkjogyEYvlGb3JfwBdAo=; b=amUAOkXlniCfXibXy+jGsZmSGD6ZETsVvMsqABtHU6TJaWv+cPaqVbZxo9klgmFDLO Cp/GmWzH3c9zDEhTrfpdQRwDYt1u3XG3ZEB7CDuFqjUnCvRrP+MJeajW24Rdrcln/DAP hNaTlvkEBBonTN9r0pWH0Wd5rhEEVIWlr1p98= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mMiG6cM8VBvBAXZfGrxSfXokkjogyEYvlGb3JfwBdAo=; b=r7InCvdRQrONNQgVHJ6X96CKTynW5H51a0uDAhBgiOCMmrIYv/87/XQEcxdtUsICRr WZDq09umcDx+5/MvtvamR3t7n1pbcVBg1lNLNZj5aOEDJehMAayT7tcvc50tYCPY8DdF B+X7JNaX9bYJPhnNMAakV4Dm4V05KxcUhZhhJaqB8/iXu1MC3ik53M2RHkVtOl2qoI5J E8yxUr3NPsI46qe0f9h7dU9oa3+kCdjiCK9j/TtpjrFQU9ZtVIT5qXDX0ncM/N37NJeI zrQroghvzVYXcF9ZqA/8lkG5F4hJM2Ut6lmh3b6qcjBIMYPk+w0U7oPqT0WbX4eRPkWU y/zA== X-Gm-Message-State: APt69E2f+NnJDMVqRP7PDxM01GIVKbqLgCPYzH25njhFJS0JLwdo0j5I 9PMQgCqgm7/U61qfWLlODEveKw== X-Received: by 2002:a1c:ea9b:: with SMTP id g27-v6mr1446987wmi.21.1529496709603; Wed, 20 Jun 2018 05:11:49 -0700 (PDT) Received: from localhost.localdomain ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id e14-v6sm1656483wmh.17.2018.06.20.05.11.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 20 Jun 2018 05:11:48 -0700 (PDT) From: Georgi Djakov To: linux-pm@vger.kernel.org, gregkh@linuxfoundation.org Cc: rjw@rjwysocki.net, robh+dt@kernel.org, mturquette@baylibre.com, khilman@baylibre.com, vincent.guittot@linaro.org, skannan@codeaurora.org, bjorn.andersson@linaro.org, amit.kucheria@linaro.org, seansw@qti.qualcomm.com, daidavid1@codeaurora.org, evgreen@chromium.org, mark.rutland@arm.com, lorenzo.pieralisi@arm.com, abailon@baylibre.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v5 3/8] interconnect: Add debugfs support Date: Wed, 20 Jun 2018 15:11:36 +0300 Message-Id: <20180620121141.15403-4-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180620121141.15403-1-georgi.djakov@linaro.org> References: <20180620121141.15403-1-georgi.djakov@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a functionality to provide information about the current constraints per each node and provider. Signed-off-by: Georgi Djakov --- drivers/interconnect/core.c | 78 +++++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/interconnect/core.c b/drivers/interconnect/core.c index e7f96fc6722e..dafc001ce758 100644 --- a/drivers/interconnect/core.c +++ b/drivers/interconnect/core.c @@ -6,6 +6,7 @@ * Author: Georgi Djakov */ +#include #include #include #include @@ -15,10 +16,12 @@ #include #include #include +#include static DEFINE_IDR(icc_idr); static LIST_HEAD(icc_provider_list); static DEFINE_MUTEX(icc_lock); +static struct dentry *icc_debugfs_dir; /** * struct icc_req - constraints that are attached to each node @@ -47,6 +50,81 @@ struct icc_path { struct icc_req reqs[0]; }; +#ifdef CONFIG_DEBUG_FS + +static void icc_summary_show_one(struct seq_file *s, struct icc_node *n) +{ + if (!n) + return; + + seq_printf(s, "%-30s %12d %12d\n", + n->name, n->avg_bw, n->peak_bw); +} + +static int icc_summary_show(struct seq_file *s, void *data) +{ + struct icc_provider *provider; + + seq_puts(s, " node avg peak\n"); + seq_puts(s, "--------------------------------------------------------\n"); + + mutex_lock(&icc_lock); + + list_for_each_entry(provider, &icc_provider_list, provider_list) { + struct icc_node *n; + + list_for_each_entry(n, &provider->nodes, node_list) { + struct icc_req *r; + + icc_summary_show_one(s, n); + hlist_for_each_entry(r, &n->req_list, req_node) { + if (!r->dev) + continue; + + seq_printf(s, " %-26s %12d %12d\n", + dev_name(r->dev), r->avg_bw, + r->peak_bw); + } + } + } + + mutex_unlock(&icc_lock); + + return 0; +} + +static int icc_summary_open(struct inode *inode, struct file *file) +{ + return single_open(file, icc_summary_show, inode->i_private); +} + +static const struct file_operations icc_summary_fops = { + .open = icc_summary_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int __init icc_debugfs_init(void) +{ + struct dentry *file; + + icc_debugfs_dir = debugfs_create_dir("interconnect", NULL); + if (!icc_debugfs_dir) { + pr_err("interconnect: error creating debugfs directory\n"); + return -ENODEV; + } + + file = debugfs_create_file("interconnect_summary", 0444, + icc_debugfs_dir, NULL, &icc_summary_fops); + if (!file) + return -ENODEV; + + return 0; +} +late_initcall(icc_debugfs_init); +#endif + static struct icc_node *node_find(const int id) { struct icc_node *node; From patchwork Wed Jun 20 12:11:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 139319 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp712681lji; Wed, 20 Jun 2018 05:13:09 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJbYwosW9uldv82cPZg2MiPZePIXVxAkoYmztRfXIRICiggjZ9pfcp5/NgycCs1YedqUFvV X-Received: by 2002:a17:902:7c8b:: with SMTP id y11-v6mr22846974pll.222.1529496789654; Wed, 20 Jun 2018 05:13:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529496789; cv=none; d=google.com; s=arc-20160816; b=GOq55pErhUhxfH0jeJyuiJFsypIPJnV73SGIuwPEY2kd+wR9eVM82PaK8Fj1s3jhoV OQ45OrvNf4KT6SOO49JxgjRSVYjr8NExFjWAz1UYuwVUqt9VcYcOIqyI6qrOg5924WH6 YtPaQdnNVY90AfYQwTvrmxAYfz4fQeDvXqFvKVxCYOZC3unCPND/tkXlZ3Xg0gdEd0u+ odgjCRqXsAz7DgVisQsX6jcZry/7CqW2RhtzekSC5SQRHz13hHi6v0NaK/j51uhFqkSF 7wPSP0682tctxEyRso/JLf+NUTG26gpPCtcFXmYmOi7FLpWWeDHUrBt3R5EeWVQgaHwF TiwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=YQedRsQJNuAfIwCAUJuQkZ5zDukYeoDlE3WusBgILBs=; b=cd4ze9TMwHupD8F6jCKbA7ERIxUMfdRi7akyY34HCfDLAxh85sIWpXoZEnOVrpouUx T26HNOi0C0+RvMWAM7ZVfn+wkeVkKnWUwKoRhlOwr5W4M+zx3oxezy7bqCwdBxvKshQt LmDSl6Aaf9FdL/ADjRVukfSZmGFLhrO2lmmMdZKWa9y5M25NYMNf8KcgVhNxg3qsuWXV PWBzXPpv4qENUZISAGKHF5A/JJdER+Uisv2/mF1Hb+7B/ozJ6X+taWLnPEr00PvrnGP+ 3kMSG9xkfT1+RnvSwSYUM6iK5vXZw+2p737+c5a28Vi97GSE8vbZVTBWUPtFN2YYtjFz SGxw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SXSahKX8; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l19-v6si1935860pgn.625.2018.06.20.05.13.09; Wed, 20 Jun 2018 05:13:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SXSahKX8; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932224AbeFTMNI (ORCPT + 30 others); Wed, 20 Jun 2018 08:13:08 -0400 Received: from mail-wm0-f67.google.com ([74.125.82.67]:52452 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753760AbeFTMLw (ORCPT ); Wed, 20 Jun 2018 08:11:52 -0400 Received: by mail-wm0-f67.google.com with SMTP id p126-v6so5641700wmb.2 for ; Wed, 20 Jun 2018 05:11:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YQedRsQJNuAfIwCAUJuQkZ5zDukYeoDlE3WusBgILBs=; b=SXSahKX8uWMyt1WblmdQznBnUg+i40t+18Ryu5eMBARRnuV+m2LufALCVc1UMvScsE BC9LdUuvTv9Y22jCdpdUrsZoKUNICANCohGWsokaYI108xs/nBux8CQvKQScpolCbOCa 0MXDjn8CPatrrqFDyjpwcVpZcnPxA+RJikokg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YQedRsQJNuAfIwCAUJuQkZ5zDukYeoDlE3WusBgILBs=; b=CyTnS84Tk46a2aJ/AoplqAzfsgTusw0vxGEO0CfnyF9YT/o9YrPWn4tJotWvfyS8Cn 9JVkQcbapZE4XFPxJvrKuHdU8kRMmb6+g5graXxldHu2aeyiTPQHS9tjQhVwAoGIkD4S zdw55Rd1+yABjKAx6yoK9lBvcSdXb7r11+oQkGim9ubXW/M1fNXXqP2ITht1R1LhmOS3 IJ6P/vDx0iBN9K5uvR+DOcUgYuFEp1FaRyyDRVjVSdM29lttLto1dyT0fEH0/M9qVFqu 1EELSc9PGaeQHmX+TiVTjXmo+xdqAkSePOJBq03XT6PaIoSjBekegfgRBoz2naXGAbtn n13Q== X-Gm-Message-State: APt69E3w08hEO1vRVmguqdQJcL/fU4w+NEnwCAX+ys1kmZONUhJ8+40K zQ3e2tlz3cht2s2a1YAXkj9oSw== X-Received: by 2002:a1c:c90:: with SMTP id 138-v6mr1463663wmm.110.1529496711240; Wed, 20 Jun 2018 05:11:51 -0700 (PDT) Received: from localhost.localdomain ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id e14-v6sm1656483wmh.17.2018.06.20.05.11.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 20 Jun 2018 05:11:50 -0700 (PDT) From: Georgi Djakov To: linux-pm@vger.kernel.org, gregkh@linuxfoundation.org Cc: rjw@rjwysocki.net, robh+dt@kernel.org, mturquette@baylibre.com, khilman@baylibre.com, vincent.guittot@linaro.org, skannan@codeaurora.org, bjorn.andersson@linaro.org, amit.kucheria@linaro.org, seansw@qti.qualcomm.com, daidavid1@codeaurora.org, evgreen@chromium.org, mark.rutland@arm.com, lorenzo.pieralisi@arm.com, abailon@baylibre.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v5 4/8] interconnect: qcom: Add RPM communication Date: Wed, 20 Jun 2018 15:11:37 +0300 Message-Id: <20180620121141.15403-5-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180620121141.15403-1-georgi.djakov@linaro.org> References: <20180620121141.15403-1-georgi.djakov@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On some Qualcomm SoCs, there is a remote processor, which controls some of the Network-On-Chip interconnect resources. Other CPUs express their needs by communicating with this processor. Add a driver to handle comminication with this remote processor. Signed-off-by: Georgi Djakov --- .../bindings/interconnect/qcom-smd.txt | 32 +++++++ drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/smd-rpm.c | 90 +++++++++++++++++++ drivers/interconnect/qcom/smd-rpm.h | 15 ++++ 4 files changed, 139 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom-smd.txt create mode 100644 drivers/interconnect/qcom/Makefile create mode 100644 drivers/interconnect/qcom/smd-rpm.c create mode 100644 drivers/interconnect/qcom/smd-rpm.h diff --git a/Documentation/devicetree/bindings/interconnect/qcom-smd.txt b/Documentation/devicetree/bindings/interconnect/qcom-smd.txt new file mode 100644 index 000000000000..88a5aeb50935 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom-smd.txt @@ -0,0 +1,32 @@ +Qualcomm SMD-RPM interconnect driver binding +------------------------------------------------ +The RPM (Resource Power Manager) is a dedicated hardware engine +for managing the shared SoC resources in order to keep the lowest +power profile. It communicates with other hardware subsystems via +the shared memory driver (SMD) back-end and accepts requests for +various resources. + +Required properties : +- compatible : shall contain only one of the following: + "qcom,interconnect-smd-rpm" + +Example: + smd { + compatible = "qcom,smd"; + + rpm { + interrupts = <0 168 1>; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + + rpm_requests { + compatible = "qcom,rpm-msm8916"; + qcom,smd-channels = "rpm_requests"; + + interconnect-smd-rpm { + compatible = "qcom,interconnect-smd-rpm"; + }; + + }; + }; + }; diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile new file mode 100644 index 000000000000..2a0c41db91c4 --- /dev/null +++ b/drivers/interconnect/qcom/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-y += smd-rpm.o diff --git a/drivers/interconnect/qcom/smd-rpm.c b/drivers/interconnect/qcom/smd-rpm.c new file mode 100644 index 000000000000..0cf772f51642 --- /dev/null +++ b/drivers/interconnect/qcom/smd-rpm.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RPM over SMD communication wrapper for interconects + * + * Copyright (C) 2018 Linaro Ltd + * Author: Georgi Djakov + */ + +#include +#include +#include +#include +#include +#include +#include "smd-rpm.h" + +#define RPM_KEY_BW 0x00007762 + +static struct qcom_icc_rpm { + struct qcom_smd_rpm *rpm; +} icc_rpm_smd; + +struct icc_rpm_smd_req { + __le32 key; + __le32 nbytes; + __le32 value; +}; + +bool qcom_icc_rpm_smd_available(void) +{ + if (!icc_rpm_smd.rpm) + return false; + + return true; +} + +int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val) +{ + struct icc_rpm_smd_req req = { + .key = cpu_to_le32(RPM_KEY_BW), + .nbytes = cpu_to_le32(sizeof(u32)), + .value = cpu_to_le32(val), + }; + + return qcom_rpm_smd_write(icc_rpm_smd.rpm, ctx, rsc_type, id, &req, + sizeof(req)); +} +EXPORT_SYMBOL(qcom_icc_rpm_smd_send); + +static int qcom_icc_rpm_smd_probe(struct platform_device *pdev) +{ + icc_rpm_smd.rpm = dev_get_drvdata(pdev->dev.parent); + if (!icc_rpm_smd.rpm) { + dev_err(&pdev->dev, "unable to retrieve handle to RPM\n"); + return -ENODEV; + } + + return 0; +} + +static const struct of_device_id qcom_icc_rpm_smd_dt_match[] = { + { .compatible = "qcom,interconnect-smd-rpm", }, + { }, +}; + +MODULE_DEVICE_TABLE(of, qcom_interconnect_rpm_smd_dt_match); + +static struct platform_driver qcom_interconnect_rpm_smd_driver = { + .driver = { + .name = "qcom-interconnect-smd-rpm", + .of_match_table = qcom_icc_rpm_smd_dt_match, + }, + .probe = qcom_icc_rpm_smd_probe, +}; + +static int __init rpm_smd_interconnect_init(void) +{ + return platform_driver_register(&qcom_interconnect_rpm_smd_driver); +} +subsys_initcall(rpm_smd_interconnect_init); + +static void __exit rpm_smd_interconnect_exit(void) +{ + platform_driver_unregister(&qcom_interconnect_rpm_smd_driver); +} +module_exit(rpm_smd_interconnect_exit) + +MODULE_AUTHOR("Georgi Djakov "); +MODULE_DESCRIPTION("Qualcomm SMD RPM interconnect driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/interconnect/qcom/smd-rpm.h b/drivers/interconnect/qcom/smd-rpm.h new file mode 100644 index 000000000000..0f4a3da31cf6 --- /dev/null +++ b/drivers/interconnect/qcom/smd-rpm.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, Linaro Ltd. + * Author: Georgi Djakov + */ + +#ifndef __LINUX_INTERCONNECT_QCOM_RPM_H +#define __LINUX_INTERCONNECT_QCOM_RPM_H + +#include + +bool qcom_icc_rpm_smd_available(void); +int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val); + +#endif From patchwork Wed Jun 20 12:11:38 2018 Content-Type: text/plain; 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Signed-off-by: Georgi Djakov --- .../bindings/interconnect/qcom-msm8916.txt | 39 ++ include/dt-bindings/interconnect/qcom.h | 350 ++++++++++++++++++ 2 files changed, 389 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom-msm8916.txt create mode 100644 include/dt-bindings/interconnect/qcom.h diff --git a/Documentation/devicetree/bindings/interconnect/qcom-msm8916.txt b/Documentation/devicetree/bindings/interconnect/qcom-msm8916.txt new file mode 100644 index 000000000000..f309eaed3d19 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom-msm8916.txt @@ -0,0 +1,39 @@ +Qualcomm MSM8916 Network-On-Chip interconnect driver binding +---------------------------------------------------- + +Required properties : +- compatible : shall contain only one of the following: + "qcom,msm8916-bimc" + "qcom,msm8916-pnoc" + "qcom,msm8916-snoc" +- #interconnect-cells : should contain 1 +- reg : shall contain base register location and length + +Optional properties : +clocks : list of phandles and specifiers to all interconnect bus clocks +clock-names : clock names should include both "bus_clk" and "bus_a_clk" + +Examples: + + snoc: snoc@580000 { + compatible = "qcom,msm8916-snoc"; + #interconnect-cells = <1>; + reg = <0x580000 0x14000>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_SNOC_CLK>, <&rpmcc RPM_SMD_SNOC_A_CLK>; + }; + bimc: bimc@400000 { + compatible = "qcom,msm8916-bimc"; + #interconnect-cells = <1>; + reg = <0x400000 0x62000>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_BIMC_CLK>, <&rpmcc RPM_SMD_BIMC_A_CLK>; + }; + pnoc: pnoc@500000 { + compatible = "qcom,msm8916-pnoc"; + #interconnect-cells = <1>; + reg = <0x500000 0x11000>; + clock-names = "bus_clk", "bus_a_clk"; + clocks = <&rpmcc RPM_SMD_PCNOC_CLK>, <&rpmcc RPM_SMD_PCNOC_A_CLK>; + }; + diff --git a/include/dt-bindings/interconnect/qcom.h b/include/dt-bindings/interconnect/qcom.h new file mode 100644 index 000000000000..2cd378d2f575 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom.h @@ -0,0 +1,350 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Qualcomm interconnect IDs + * + * Copyright (c) 2018, Linaro Ltd. + * Author: Georgi Djakov + */ + +#ifndef __QCOM_INTERCONNECT_IDS_H +#define __QCOM_INTERCONNECT_IDS_H + +#define FAB_BIMC 0 +#define FAB_SYS_NOC 1024 +#define FAB_MMSS_NOC 2048 +#define FAB_OCMEM_NOC 3072 +#define FAB_PERIPH_NOC 4096 +#define FAB_CONFIG_NOC 5120 +#define FAB_OCMEM_VNOC 6144 + +#define MASTER_AMPSS_M0 1 +#define MASTER_AMPSS_M1 2 +#define APPSS_MASTER_FAB_MMSS 3 +#define APPSS_MASTER_FAB_SYSTEM 4 +#define SYSTEM_MASTER_FAB_APPSS 5 +#define MASTER_SPS 6 +#define MASTER_ADM_PORT0 7 +#define MASTER_ADM_PORT1 8 +#define SYSTEM_MASTER_ADM1_PORT0 9 +#define MASTER_ADM1_PORT1 10 +#define MASTER_LPASS_PROC 11 +#define MASTER_MSS_PROCI 12 +#define MASTER_MSS_PROCD 13 +#define MASTER_MSS_MDM_PORT0 14 +#define MASTER_LPASS 15 +#define SYSTEM_MASTER_CPSS_FPB 16 +#define SYSTEM_MASTER_SYSTEM_FPB 17 +#define SYSTEM_MASTER_MMSS_FPB 18 +#define MASTER_ADM1_CI 19 +#define MASTER_ADM0_CI 20 +#define MASTER_MSS_MDM_PORT1 21 +#define MASTER_MDP_PORT0 22 +#define MASTER_MDP_PORT1 23 +#define MMSS_MASTER_ADM1_PORT0 24 +#define MASTER_ROTATOR 25 +#define MASTER_GRAPHICS_3D 26 +#define MASTER_JPEG_DEC 27 +#define MASTER_GRAPHICS_2D_CORE0 28 +#define MASTER_VFE 29 +#define MASTER_VPE 30 +#define MASTER_JPEG_ENC 31 +#define MASTER_GRAPHICS_2D_CORE1 32 +#define MMSS_MASTER_APPS_FAB 33 +#define MASTER_HD_CODEC_PORT0 34 +#define MASTER_HD_CODEC_PORT1 35 +#define MASTER_SPDM 36 +#define MASTER_RPM 37 +#define MASTER_MSS 38 +#define MASTER_RIVA 39 +#define SYSTEM_MASTER_UNUSED_6 40 +#define MASTER_MSS_SW_PROC 41 +#define MASTER_MSS_FW_PROC 42 +#define MMSS_MASTER_UNUSED_2 43 +#define MASTER_GSS_NAV 44 +#define MASTER_PCIE 45 +#define MASTER_SATA 46 +#define MASTER_CRYPTO 47 +#define MASTER_VIDEO_CAP 48 +#define MASTER_GRAPHICS_3D_PORT1 49 +#define MASTER_VIDEO_ENC 50 +#define MASTER_VIDEO_DEC 51 +#define MASTER_LPASS_AHB 52 +#define MASTER_QDSS_BAM 53 +#define MASTER_SNOC_CFG 54 +#define MASTER_CRYPTO_CORE0 55 +#define MASTER_CRYPTO_CORE1 56 +#define MASTER_MSS_NAV 57 +#define MASTER_OCMEM_DMA 58 +#define MASTER_WCSS 59 +#define MASTER_QDSS_ETR 60 +#define MASTER_USB3 61 +#define MASTER_JPEG 62 +#define MASTER_VIDEO_P0 63 +#define MASTER_VIDEO_P1 64 +#define MASTER_MSS_PROC 65 +#define MASTER_JPEG_OCMEM 66 +#define MASTER_MDP_OCMEM 67 +#define MASTER_VIDEO_P0_OCMEM 68 +#define MASTER_VIDEO_P1_OCMEM 69 +#define MASTER_VFE_OCMEM 70 +#define MASTER_CNOC_ONOC_CFG 71 +#define MASTER_RPM_INST 72 +#define MASTER_RPM_DATA 73 +#define MASTER_RPM_SYS 74 +#define MASTER_DEHR 75 +#define MASTER_QDSS_DAP 76 +#define MASTER_TIC 77 +#define MASTER_SDCC_1 78 +#define MASTER_SDCC_3 79 +#define MASTER_SDCC_4 80 +#define MASTER_SDCC_2 81 +#define MASTER_TSIF 82 +#define MASTER_BAM_DMA 83 +#define MASTER_BLSP_2 84 +#define MASTER_USB_HSIC 85 +#define MASTER_BLSP_1 86 +#define MASTER_USB_HS 87 +#define MASTER_PNOC_CFG 88 +#define MASTER_V_OCMEM_GFX3D 89 +#define MASTER_IPA 90 +#define MASTER_QPIC 91 +#define MASTER_MDPE 92 +#define MASTER_USB_HS2 93 +#define MASTER_VPU 94 +#define MASTER_UFS 95 +#define MASTER_BCAST 96 +#define MASTER_CRYPTO_CORE2 97 +#define MASTER_EMAC 98 +#define MASTER_VPU_1 99 +#define MASTER_PCIE_1 100 +#define MASTER_USB3_1 101 +#define MASTER_CNOC_MNOC_MMSS_CFG 102 +#define MASTER_CNOC_MNOC_CFG 103 +#define MASTER_TCU_0 104 +#define MASTER_TCU_1 105 +#define MASTER_CPP 106 +#define MASTER_AUDIO 107 + +#define SNOC_MM_INT_0 10000 +#define SNOC_MM_INT_1 10001 +#define SNOC_MM_INT_2 10002 +#define SNOC_MM_INT_BIMC 10003 +#define SNOC_INT_0 10004 +#define SNOC_INT_1 10005 +#define SNOC_INT_BIMC 10006 +#define SNOC_BIMC_0_MAS 10007 +#define SNOC_BIMC_1_MAS 10008 +#define SNOC_QDSS_INT 10009 +#define PNOC_SNOC_MAS 10010 +#define PNOC_SNOC_SLV 10011 +#define PNOC_INT_0 10012 +#define PNOC_INT_1 10013 +#define PNOC_M_0 10014 +#define PNOC_M_1 10015 +#define BIMC_SNOC_MAS 10016 +#define BIMC_SNOC_SLV 10017 +#define PNOC_SLV_0 10018 +#define PNOC_SLV_1 10019 +#define PNOC_SLV_2 10020 +#define PNOC_SLV_3 10021 +#define PNOC_SLV_4 10022 +#define PNOC_SLV_8 10023 +#define PNOC_SLV_9 10024 +#define SNOC_BIMC_0_SLV 10025 +#define SNOC_BIMC_1_SLV 10026 +#define MNOC_BIMC_MAS 10027 +#define MNOC_BIMC_SLV 10028 +#define BIMC_MNOC_MAS 10029 +#define BIMC_MNOC_SLV 10030 +#define SNOC_BIMC_MAS 10031 +#define SNOC_BIMC_SLV 10032 +#define CNOC_SNOC_MAS 10033 +#define CNOC_SNOC_SLV 10034 +#define SNOC_CNOC_MAS 10035 +#define SNOC_CNOC_SLV 10036 +#define OVNOC_SNOC_MAS 10037 +#define OVNOC_SNOC_SLV 10038 +#define SNOC_OVNOC_MAS 10039 +#define SNOC_OVNOC_SLV 10040 +#define SNOC_PNOC_MAS 10041 +#define SNOC_PNOC_SLV 10042 +#define BIMC_INT_APPS_EBI 10043 +#define BIMC_INT_APPS_SNOC 10044 +#define SNOC_BIMC_2_MAS 10045 +#define SNOC_BIMC_2_SLV 10046 +#define PNOC_SLV_5 10047 +#define PNOC_SLV_7 10048 +#define PNOC_INT_2 10049 +#define PNOC_INT_3 10050 +#define PNOC_INT_4 10051 +#define PNOC_INT_5 10052 +#define PNOC_INT_6 10053 +#define PNOC_INT_7 10054 + +#define SLAVE_EBI_CH0 512 +#define SLAVE_EBI_CH1 513 +#define SLAVE_AMPSS_L2 514 +#define APPSS_SLAVE_FAB_MMSS 515 +#define APPSS_SLAVE_FAB_SYSTEM 516 +#define SYSTEM_SLAVE_FAB_APPS 517 +#define SLAVE_SPS 518 +#define SLAVE_SYSTEM_IMEM 519 +#define SLAVE_AMPSS 520 +#define SLAVE_MSS 521 +#define SLAVE_LPASS 522 +#define SYSTEM_SLAVE_CPSS_FPB 523 +#define SYSTEM_SLAVE_SYSTEM_FPB 524 +#define SYSTEM_SLAVE_MMSS_FPB 525 +#define SLAVE_CORESIGHT 526 +#define SLAVE_RIVA 527 +#define SLAVE_SMI 528 +#define MMSS_SLAVE_FAB_APPS 529 +#define MMSS_SLAVE_FAB_APPS_1 530 +#define SLAVE_MM_IMEM 531 +#define SLAVE_CRYPTO 532 +#define SLAVE_SPDM 533 +#define SLAVE_RPM 534 +#define SLAVE_RPM_MSG_RAM 535 +#define SLAVE_MPM 536 +#define SLAVE_PMIC1_SSBI1_A 537 +#define SLAVE_PMIC1_SSBI1_B 538 +#define SLAVE_PMIC1_SSBI1_C 539 +#define SLAVE_PMIC2_SSBI2_A 540 +#define SLAVE_PMIC2_SSBI2_B 541 +#define SLAVE_GSBI1_UART 542 +#define SLAVE_GSBI2_UART 543 +#define SLAVE_GSBI3_UART 544 +#define SLAVE_GSBI4_UART 545 +#define SLAVE_GSBI5_UART 546 +#define SLAVE_GSBI6_UART 547 +#define SLAVE_GSBI7_UART 548 +#define SLAVE_GSBI8_UART 549 +#define SLAVE_GSBI9_UART 550 +#define SLAVE_GSBI10_UART 551 +#define SLAVE_GSBI11_UART 552 +#define SLAVE_GSBI12_UART 553 +#define SLAVE_GSBI1_QUP 554 +#define SLAVE_GSBI2_QUP 555 +#define SLAVE_GSBI3_QUP 556 +#define SLAVE_GSBI4_QUP 557 +#define SLAVE_GSBI5_QUP 558 +#define SLAVE_GSBI6_QUP 559 +#define SLAVE_GSBI7_QUP 560 +#define SLAVE_GSBI8_QUP 561 +#define SLAVE_GSBI9_QUP 562 +#define SLAVE_GSBI10_QUP 563 +#define SLAVE_GSBI11_QUP 564 +#define SLAVE_GSBI12_QUP 565 +#define SLAVE_EBI2_NAND 566 +#define SLAVE_EBI2_CS0 567 +#define SLAVE_EBI2_CS1 568 +#define SLAVE_EBI2_CS2 569 +#define SLAVE_EBI2_CS3 570 +#define SLAVE_EBI2_CS4 571 +#define SLAVE_EBI2_CS5 572 +#define SLAVE_USB_FS1 573 +#define SLAVE_USB_FS2 574 +#define SLAVE_TSIF 575 +#define SLAVE_MSM_TSSC 576 +#define SLAVE_MSM_PDM 577 +#define SLAVE_MSM_DIMEM 578 +#define SLAVE_MSM_TCSR 579 +#define SLAVE_MSM_PRNG 580 +#define SLAVE_GSS 581 +#define SLAVE_SATA 582 +#define SLAVE_USB3 583 +#define SLAVE_WCSS 584 +#define SLAVE_OCIMEM 585 +#define SLAVE_SNOC_OCMEM 586 +#define SLAVE_SERVICE_SNOC 587 +#define SLAVE_QDSS_STM 588 +#define SLAVE_CAMERA_CFG 589 +#define SLAVE_DISPLAY_CFG 590 +#define SLAVE_OCMEM_CFG 591 +#define SLAVE_CPR_CFG 592 +#define SLAVE_CPR_XPU_CFG 593 +#define SLAVE_MISC_CFG 594 +#define SLAVE_MISC_XPU_CFG 595 +#define SLAVE_VENUS_CFG 596 +#define SLAVE_MISC_VENUS_CFG 597 +#define SLAVE_GRAPHICS_3D_CFG 598 +#define SLAVE_MMSS_CLK_CFG 599 +#define SLAVE_MMSS_CLK_XPU_CFG 600 +#define SLAVE_MNOC_MPU_CFG 601 +#define SLAVE_ONOC_MPU_CFG 602 +#define SLAVE_SERVICE_MNOC 603 +#define SLAVE_OCMEM 604 +#define SLAVE_SERVICE_ONOC 605 +#define SLAVE_SDCC_1 606 +#define SLAVE_SDCC_3 607 +#define SLAVE_SDCC_2 608 +#define SLAVE_SDCC_4 609 +#define SLAVE_BAM_DMA 610 +#define SLAVE_BLSP_2 611 +#define SLAVE_USB_HSIC 612 +#define SLAVE_BLSP_1 613 +#define SLAVE_USB_HS 614 +#define SLAVE_PDM 615 +#define SLAVE_PERIPH_APU_CFG 616 +#define SLAVE_PNOC_MPU_CFG 617 +#define SLAVE_PRNG 618 +#define SLAVE_SERVICE_PNOC 619 +#define SLAVE_CLK_CTL 620 +#define SLAVE_CNOC_MSS 621 +#define SLAVE_SECURITY 622 +#define SLAVE_TCSR 623 +#define SLAVE_TLMM 624 +#define SLAVE_CRYPTO_0_CFG 625 +#define SLAVE_CRYPTO_1_CFG 626 +#define SLAVE_IMEM_CFG 627 +#define SLAVE_MESSAGE_RAM 628 +#define SLAVE_BIMC_CFG 629 +#define SLAVE_BOOT_ROM 630 +#define SLAVE_CNOC_MNOC_MMSS_CFG 631 +#define SLAVE_PMIC_ARB 632 +#define SLAVE_SPDM_WRAPPER 633 +#define SLAVE_DEHR_CFG 634 +#define SLAVE_QDSS_CFG 635 +#define SLAVE_RBCPR_CFG 636 +#define SLAVE_RBCPR_QDSS_APU_CFG 637 +#define SLAVE_SNOC_MPU_CFG 638 +#define SLAVE_CNOC_ONOC_CFG 639 +#define SLAVE_CNOC_MNOC_CFG 640 +#define SLAVE_PNOC_CFG 641 +#define SLAVE_SNOC_CFG 642 +#define SLAVE_EBI1_DLL_CFG 643 +#define SLAVE_PHY_APU_CFG 644 +#define SLAVE_EBI1_PHY_CFG 645 +#define SLAVE_SERVICE_CNOC 646 +#define SLAVE_IPS_CFG 647 +#define SLAVE_QPIC 648 +#define SLAVE_DSI_CFG 649 +#define SLAVE_UFS_CFG 650 +#define SLAVE_RBCPR_CX_CFG 651 +#define SLAVE_RBCPR_MX_CFG 652 +#define SLAVE_PCIE_CFG 653 +#define SLAVE_USB_PHYS_CFG 654 +#define SLAVE_VIDEO_CAP_CFG 655 +#define SLAVE_AVSYNC_CFG 656 +#define SLAVE_CRYPTO_2_CFG 657 +#define SLAVE_VPU_CFG 658 +#define SLAVE_BCAST_CFG 659 +#define SLAVE_KLM_CFG 660 +#define SLAVE_GENI_IR_CFG 661 +#define SLAVE_OCMEM_GFX 662 +#define SLAVE_CATS_128 663 +#define SLAVE_OCMEM_64 664 +#define SLAVE_PCIE_0 665 +#define SLAVE_PCIE_1 666 +#define SLAVE_PCIE_0_CFG 667 +#define SLAVE_PCIE_1_CFG 668 +#define SLAVE_SRVC_MNOC 669 +#define SLAVE_USB_HS2 670 +#define SLAVE_AUDIO 671 +#define SLAVE_TCU 672 +#define SLAVE_APPSS 673 +#define SLAVE_PCIE_PARF 674 +#define SLAVE_USB3_PHY_CFG 675 +#define SLAVE_IPA_CFG 676 + +#endif From patchwork Wed Jun 20 12:11:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 139316 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp711581lji; Wed, 20 Jun 2018 05:12:06 -0700 (PDT) X-Google-Smtp-Source: ADUXVKL8XapPgvVPTgaEmAXdpFkIm6I27F+kq3MHFKZtlA2WVzn7eoFW5kavZ16J656GsQ7Cd6wD X-Received: by 2002:a63:7a07:: with SMTP id v7-v6mr18404479pgc.444.1529496726451; Wed, 20 Jun 2018 05:12:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529496726; cv=none; d=google.com; s=arc-20160816; b=EjbLXU1R22ucjljFCwrCjBvzq/uBTDAW3JArHz0ZOvD8NghHbazzRbmKOhsQVUBoAU E5En7KDhIUfqGUq+CfEbtbBC1OasiIZBpRd/84iR+XlihGUWCm0n+qG5l5sGEO3cQO1Z kaeZja1VcrF+4MBCaiD/u/MQEeDfbF3KFFoPUL1ebnPUTQ0k3cLu4G2rqP40AGRYC/8l A5bQUKfXMFaNnB7NdLSDRqoDvChgfzGdc1LBZlUIf1mFDcW0gz/lNbC+M70vX0hxqVEv JnbRTa7bGn9ihD2ghIUT84Nx0OaubAO2PBSY60vs0iqe8kawXc6cVJKGgfZpwfRkzfBY uw6A== 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[209.132.180.67]) by mx.google.com with ESMTP id s25-v6si1697670pgd.188.2018.06.20.05.12.06; Wed, 20 Jun 2018 05:12:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Q2XhiVbN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754104AbeFTMMB (ORCPT + 30 others); Wed, 20 Jun 2018 08:12:01 -0400 Received: from mail-wm0-f67.google.com ([74.125.82.67]:35851 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753972AbeFTML4 (ORCPT ); Wed, 20 Jun 2018 08:11:56 -0400 Received: by mail-wm0-f67.google.com with SMTP id v131-v6so6469060wma.1 for ; Wed, 20 Jun 2018 05:11:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mfYBsOuU9GlAuZKYSFUKaYFA5KRmc33aHmG2/icRqFs=; b=Q2XhiVbNCxXjD+ePNyIplZKsq2beCZ03LL2C3yFmrMWXleD1OAsr8nk+noHehzERtD pONPr+0vZ8xxzHK2uqeclQHrOeIA/3mK+KtvzjJ5mHqvSfpFrH4SAEqTdYc8CSrbiVxJ NhlEOTNiafPGob3l8j6/+fmzcaANxTOfB4csY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mfYBsOuU9GlAuZKYSFUKaYFA5KRmc33aHmG2/icRqFs=; b=eRyAkK06D2V7nJUQpC9AmJjjBtwj+36FKWPOrwQuXVZoLENformu4jBUzUbYYeO1zc qdMf8DouHhzSHeQSoE7MgsdEfjwBxeNgVJh+E8KuKbHatuThJCwUpf7i19622eCI5oLR UnSL4OcfL7hhenT5OmXTrUn8WzuzKIU+R6CeN45zrqvPoD7q99Ucmd1lKyM86G+TigJK xxpBpvfKN9ONHd3XqoKnrIB5Bm7DJMeypde+eKv7jGomkdUgBtmelMxg3dXg8QgfKX84 +KQGkGXFlx18EBuX6y+bZlg2DfIW+2lG9FtmLvXF24YT4Agp3ugx3Fi12pRmY6LZ7nVT YOFA== X-Gm-Message-State: APt69E0hgw8TSqprzHB5vXtO49ltqlu4+mdbiC0pITxcP9LawyH2cNqx SGbUf/QvfjWkouWAdZ0wV4khhg== X-Received: by 2002:a1c:5d0e:: with SMTP id r14-v6mr1487809wmb.152.1529496714635; Wed, 20 Jun 2018 05:11:54 -0700 (PDT) Received: from localhost.localdomain ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id e14-v6sm1656483wmh.17.2018.06.20.05.11.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 20 Jun 2018 05:11:53 -0700 (PDT) From: Georgi Djakov To: linux-pm@vger.kernel.org, gregkh@linuxfoundation.org Cc: rjw@rjwysocki.net, robh+dt@kernel.org, mturquette@baylibre.com, khilman@baylibre.com, vincent.guittot@linaro.org, skannan@codeaurora.org, bjorn.andersson@linaro.org, amit.kucheria@linaro.org, seansw@qti.qualcomm.com, daidavid1@codeaurora.org, evgreen@chromium.org, mark.rutland@arm.com, lorenzo.pieralisi@arm.com, abailon@baylibre.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v5 6/8] interconnect: qcom: Add msm8916 interconnect provider driver Date: Wed, 20 Jun 2018 15:11:39 +0300 Message-Id: <20180620121141.15403-7-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180620121141.15403-1-georgi.djakov@linaro.org> References: <20180620121141.15403-1-georgi.djakov@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add driver for the Qualcomm interconnect buses found in msm8916 based platforms. Signed-off-by: Georgi Djakov --- drivers/interconnect/Kconfig | 5 + drivers/interconnect/Makefile | 1 + drivers/interconnect/qcom/Kconfig | 11 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/msm8916.c | 495 ++++++++++++++++++++++++++++ 5 files changed, 514 insertions(+) create mode 100644 drivers/interconnect/qcom/Kconfig create mode 100644 drivers/interconnect/qcom/msm8916.c diff --git a/drivers/interconnect/Kconfig b/drivers/interconnect/Kconfig index a261c7d41deb..07a8276fa35a 100644 --- a/drivers/interconnect/Kconfig +++ b/drivers/interconnect/Kconfig @@ -8,3 +8,8 @@ menuconfig INTERCONNECT If unsure, say no. +if INTERCONNECT + +source "drivers/interconnect/qcom/Kconfig" + +endif diff --git a/drivers/interconnect/Makefile b/drivers/interconnect/Makefile index 97fca2e09d24..7944cbca0527 100644 --- a/drivers/interconnect/Makefile +++ b/drivers/interconnect/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_INTERCONNECT) += core.o +obj-$(CONFIG_INTERCONNECT_QCOM) += qcom/ diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig new file mode 100644 index 000000000000..86465dc37bd4 --- /dev/null +++ b/drivers/interconnect/qcom/Kconfig @@ -0,0 +1,11 @@ +config INTERCONNECT_QCOM + bool "Qualcomm Network-on-Chip interconnect drivers" + depends on INTERCONNECT + depends on ARCH_QCOM || COMPILE_TEST + default y + +config INTERCONNECT_QCOM_MSM8916 + tristate "Qualcomm MSM8916 interconnect driver" + depends on INTERCONNECT_QCOM + help + This is a driver for the Qualcomm Network-on-Chip on msm8916-based platforms. diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile index 2a0c41db91c4..e8b24c334c5d 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -1,2 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 obj-y += smd-rpm.o + +obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) += msm8916.o diff --git a/drivers/interconnect/qcom/msm8916.c b/drivers/interconnect/qcom/msm8916.c new file mode 100644 index 000000000000..c34f18cdea33 --- /dev/null +++ b/drivers/interconnect/qcom/msm8916.c @@ -0,0 +1,495 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Linaro Ltd + * Author: Georgi Djakov + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "smd-rpm.h" + +#define RPM_MASTER_FIELD_BW 0x00007762 +#define RPM_BUS_MASTER_REQ 0x73616d62 +#define RPM_BUS_SLAVE_REQ 0x766c7362 + +#define to_qcom_provider(_provider) \ + container_of(_provider, struct qcom_icc_provider, provider) + +enum qcom_qos_mode { + QCOM_QOS_MODE_BYPASS = 0, + QCOM_QOS_MODE_FIXED, + QCOM_QOS_MODE_MAX, +}; + +struct qcom_icc_provider { + struct icc_provider provider; + void __iomem *base; + struct clk *bus_clk; + struct clk *bus_a_clk; +}; + +#define MSM8916_MAX_LINKS 8 + +/** + * struct qcom_icc_node - Qualcomm specific interconnect nodes + * @name: the node name used in debugfs + * @links: an array of nodes where we can go next while traversing + * @id: a unique node identifier + * @num_links: the total number of @links + * @port: the offset index into the masters QoS register space + * @buswidth: width of the interconnect between a node and the bus (bytes) + * @ap_owned: the AP CPU does the writing to QoS registers + * @rpm: reference to the RPM SMD driver + * @qos_mode: QoS mode for ap_owned resources + * @mas_rpm_id: RPM id for devices that are bus masters + * @slv_rpm_id: RPM id for devices that are bus slaves + * @rate: current bus clock rate in Hz + */ +struct qcom_icc_node { + unsigned char *name; + u16 links[MSM8916_MAX_LINKS]; + u16 id; + u16 num_links; + u16 port; + u16 buswidth; + bool ap_owned; + struct qcom_smd_rpm *rpm; + enum qcom_qos_mode qos_mode; + int mas_rpm_id; + int slv_rpm_id; + u64 rate; +}; + +struct qcom_icc_desc { + struct qcom_icc_node **nodes; + size_t num_nodes; +}; + +#define DEFINE_QNODE(_name, _id, _port, _buswidth, _ap_owned, \ + _mas_rpm_id, _slv_rpm_id, _qos_mode, \ + _numlinks, ...) \ + static struct qcom_icc_node _name = { \ + .id = _id, \ + .name = #_name, \ + .port = _port, \ + .buswidth = _buswidth, \ + .qos_mode = _qos_mode, \ + .ap_owned = _ap_owned, \ + .mas_rpm_id = _mas_rpm_id, \ + .slv_rpm_id = _slv_rpm_id, \ + .num_links = _numlinks, \ + .links = { __VA_ARGS__ }, \ + } + +DEFINE_QNODE(mas_video, MASTER_VIDEO_P0, 8, 16, 1, -1, -1, QCOM_QOS_MODE_BYPASS, 2, SNOC_MM_INT_0, SNOC_MM_INT_2); +DEFINE_QNODE(mas_jpeg, MASTER_JPEG, 6, 16, 1, -1, -1, QCOM_QOS_MODE_BYPASS, 2, SNOC_MM_INT_0, SNOC_MM_INT_2); +DEFINE_QNODE(mas_vfe, MASTER_VFE, 9, 16, 1, -1, -1, QCOM_QOS_MODE_BYPASS, 2, SNOC_MM_INT_1, SNOC_MM_INT_2); +DEFINE_QNODE(mas_mdp, MASTER_MDP_PORT0, 7, 16, 1, -1, -1, QCOM_QOS_MODE_BYPASS, 2, SNOC_MM_INT_0, SNOC_MM_INT_2); +DEFINE_QNODE(mas_qdss_bam, MASTER_QDSS_BAM, 11, 16, 1, -1, -1, QCOM_QOS_MODE_FIXED, 1, SNOC_QDSS_INT); +DEFINE_QNODE(mas_snoc_cfg, MASTER_SNOC_CFG, 0, 16, 0, 20, -1, QCOM_QOS_MODE_BYPASS, 1, SNOC_QDSS_INT); +DEFINE_QNODE(mas_qdss_etr, MASTER_QDSS_ETR, 10, 16, 1, -1, -1, QCOM_QOS_MODE_FIXED, 1, SNOC_QDSS_INT); +DEFINE_QNODE(mm_int_0, SNOC_MM_INT_0, 0, 16, 1, -1, -1, QCOM_QOS_MODE_FIXED, 1, SNOC_MM_INT_BIMC); +DEFINE_QNODE(mm_int_1, SNOC_MM_INT_1, 0, 16, 1, -1, -1, QCOM_QOS_MODE_FIXED, 1, SNOC_MM_INT_BIMC); +DEFINE_QNODE(mm_int_2, SNOC_MM_INT_2, 0, 16, 1, -1, -1, QCOM_QOS_MODE_FIXED, 1, SNOC_INT_0); +DEFINE_QNODE(mm_int_bimc, SNOC_MM_INT_BIMC, 0, 16, 1, -1, -1, QCOM_QOS_MODE_FIXED, 1, SNOC_BIMC_1_MAS); +DEFINE_QNODE(snoc_int_0, SNOC_INT_0, 0, 8, 0, 99, 130, QCOM_QOS_MODE_FIXED, 3, SLAVE_QDSS_STM, SLAVE_SYSTEM_IMEM, MNOC_BIMC_MAS); +DEFINE_QNODE(snoc_int_1, SNOC_INT_1, 0, 8, 0, 100, 131, QCOM_QOS_MODE_FIXED, 3, SYSTEM_SLAVE_FAB_APPS, SLAVE_CATS_128, SLAVE_OCMEM_64); +DEFINE_QNODE(snoc_int_bimc, SNOC_INT_BIMC, 0, 8, 0, 101, 132, QCOM_QOS_MODE_FIXED, 1, SNOC_BIMC_0_MAS); +DEFINE_QNODE(snoc_bimc_0_mas, SNOC_BIMC_0_MAS, 0, 8, 0, 3, -1, QCOM_QOS_MODE_FIXED, 1, SNOC_BIMC_0_SLV); +DEFINE_QNODE(snoc_bimc_1_mas, SNOC_BIMC_1_MAS, 0, 16, 1, -1, -1, QCOM_QOS_MODE_FIXED, 1, SNOC_BIMC_1_SLV); +DEFINE_QNODE(qdss_int, SNOC_QDSS_INT, 0, 8, 1, -1, -1, QCOM_QOS_MODE_FIXED, 2, SNOC_INT_0, SNOC_INT_BIMC); +DEFINE_QNODE(bimc_snoc_slv, BIMC_SNOC_SLV, 0, 8, 1, -1, -1, QCOM_QOS_MODE_FIXED, 2, SNOC_INT_0, SNOC_INT_1); +DEFINE_QNODE(snoc_pnoc_mas, MNOC_BIMC_MAS, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 1, MNOC_BIMC_SLV); +DEFINE_QNODE(pnoc_snoc_slv, PNOC_SNOC_SLV, 0, 8, 0, -1, 45, QCOM_QOS_MODE_FIXED, 3, SNOC_INT_0, SNOC_INT_BIMC, SNOC_INT_1); +DEFINE_QNODE(slv_srvc_snoc, SLAVE_SERVICE_SNOC, 0, 8, 0, -1, 29, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_qdss_stm, SLAVE_QDSS_STM, 0, 4, 0, -1, 30, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_imem, SLAVE_SYSTEM_IMEM, 0, 8, 0, -1, 26, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_apss, SYSTEM_SLAVE_FAB_APPS, 0, 4, 0, -1, 20, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_cats_0, SLAVE_CATS_128, 0, 16, 0, -1, 106, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_cats_1, SLAVE_OCMEM_64, 0, 8, 0, -1, 107, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(mas_apss, MASTER_AMPSS_M0, 0, 8, 1, -1, -1, QCOM_QOS_MODE_FIXED, 3, SLAVE_EBI_CH0, BIMC_SNOC_MAS, SLAVE_AMPSS_L2); +DEFINE_QNODE(mas_tcu0, MASTER_TCU_0, 5, 8, 1, -1, -1, QCOM_QOS_MODE_FIXED, 3, SLAVE_EBI_CH0, BIMC_SNOC_MAS, SLAVE_AMPSS_L2); +DEFINE_QNODE(mas_tcu1, MASTER_TCU_1, 6, 8, 1, -1, -1, QCOM_QOS_MODE_FIXED, 3, SLAVE_EBI_CH0, BIMC_SNOC_MAS, SLAVE_AMPSS_L2); +DEFINE_QNODE(mas_gfx, MASTER_GRAPHICS_3D, 2, 8, 1, -1, -1, QCOM_QOS_MODE_FIXED, 3, SLAVE_EBI_CH0, BIMC_SNOC_MAS, SLAVE_AMPSS_L2); +DEFINE_QNODE(bimc_snoc_mas, BIMC_SNOC_MAS, 0, 8, 1, -1, -1, QCOM_QOS_MODE_FIXED, 1, BIMC_SNOC_SLV); +DEFINE_QNODE(snoc_bimc_0_slv, SNOC_BIMC_0_SLV, 0, 8, 0, -1, 24, QCOM_QOS_MODE_FIXED, 1, SLAVE_EBI_CH0); +DEFINE_QNODE(snoc_bimc_1_slv, SNOC_BIMC_1_SLV, 0, 8, 1, -1, -1, QCOM_QOS_MODE_FIXED, 1, SLAVE_EBI_CH0); +DEFINE_QNODE(slv_ebi_ch0, SLAVE_EBI_CH0, 0, 8, 0, -1, 0, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_apps_l2, SLAVE_AMPSS_L2, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(snoc_pnoc_slv, MNOC_BIMC_SLV, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 1, PNOC_INT_0); +DEFINE_QNODE(pnoc_int_0, PNOC_INT_0, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 8, PNOC_SNOC_MAS, PNOC_SLV_0, PNOC_SLV_1, PNOC_SLV_2, PNOC_SLV_3, PNOC_SLV_4, PNOC_SLV_8, PNOC_SLV_9); +DEFINE_QNODE(pnoc_int_1, PNOC_INT_1, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 1, PNOC_SNOC_MAS); +DEFINE_QNODE(pnoc_m_0, PNOC_M_0, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 1, PNOC_INT_0); +DEFINE_QNODE(pnoc_m_1, PNOC_M_1, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 1, PNOC_SNOC_MAS); +DEFINE_QNODE(pnoc_s_0, PNOC_SLV_0, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 5, SLAVE_CLK_CTL, SLAVE_TLMM, SLAVE_MSM_TCSR, SLAVE_SECURITY, SLAVE_MSS); +DEFINE_QNODE(pnoc_s_1, PNOC_SLV_1, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 5, SLAVE_IMEM_CFG, SLAVE_CRYPTO_0_CFG, SLAVE_RPM_MSG_RAM, SLAVE_MSM_PDM, SLAVE_PRNG); +DEFINE_QNODE(pnoc_s_2, PNOC_SLV_2, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 5, SLAVE_SPDM, SLAVE_BOOT_ROM, SLAVE_BIMC_CFG, SLAVE_PNOC_CFG, SLAVE_PMIC_ARB); +DEFINE_QNODE(pnoc_s_3, PNOC_SLV_3, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 5, SLAVE_MPM, SLAVE_IPS_CFG, SLAVE_RBCPR_CFG, SLAVE_QDSS_CFG, SLAVE_DEHR_CFG); +DEFINE_QNODE(pnoc_s_4, PNOC_SLV_4, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 3, SLAVE_VENUS_CFG, SLAVE_CAMERA_CFG, SLAVE_DISPLAY_CFG); +DEFINE_QNODE(pnoc_s_8, PNOC_SLV_8, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 3, SLAVE_USB_HS, SLAVE_SDCC_1, SLAVE_BLSP_1); +DEFINE_QNODE(pnoc_s_9, PNOC_SLV_9, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 3, SLAVE_SDCC_4, SLAVE_LPASS, SLAVE_GRAPHICS_3D_CFG); +DEFINE_QNODE(slv_imem_cfg, SLAVE_IMEM_CFG, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_crypto_0_cfg, SLAVE_CRYPTO_0_CFG, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_msg_ram, SLAVE_RPM_MSG_RAM, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_pdm, SLAVE_MSM_PDM, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_prng, SLAVE_PRNG, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_clk_ctl, SLAVE_CLK_CTL, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_mss, SLAVE_MSS, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_tlmm, SLAVE_TLMM, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_tcsr, SLAVE_MSM_TCSR, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_security, SLAVE_SECURITY, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_spdm, SLAVE_SPDM, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_pnoc_cfg, SLAVE_PNOC_CFG, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_pmic_arb, SLAVE_PMIC_ARB, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_bimc_cfg, SLAVE_BIMC_CFG, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_boot_rom, SLAVE_BOOT_ROM, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_mpm, SLAVE_MPM, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_qdss_cfg, SLAVE_QDSS_CFG, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_rbcpr_cfg, SLAVE_RBCPR_CFG, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_snoc_cfg, SLAVE_IPS_CFG, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_dehr_cfg, SLAVE_DEHR_CFG, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_venus_cfg, SLAVE_VENUS_CFG, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_display_cfg, SLAVE_DISPLAY_CFG, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_camera_cfg, SLAVE_CAMERA_CFG, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_usb_hs, SLAVE_USB_HS, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_sdcc_1, SLAVE_SDCC_1, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_blsp_1, SLAVE_BLSP_1, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_sdcc_2, SLAVE_SDCC_4, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_gfx_cfg, SLAVE_GRAPHICS_3D_CFG, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(slv_audio, SLAVE_LPASS, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 0, 0); +DEFINE_QNODE(mas_blsp_1, MASTER_BLSP_1, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 1, PNOC_M_1); +DEFINE_QNODE(mas_spdm, MASTER_SPDM, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 1, PNOC_M_0); +DEFINE_QNODE(mas_dehr, MASTER_DEHR, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 1, PNOC_M_0); +DEFINE_QNODE(mas_audio, MASTER_LPASS, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 1, PNOC_M_0); +DEFINE_QNODE(mas_usb_hs, MASTER_USB_HS, 0, 4, 0, -1, -1, QCOM_QOS_MODE_FIXED, 1, PNOC_M_1); +DEFINE_QNODE(mas_pnoc_crypto_0, MASTER_CRYPTO_CORE0, 0, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 1, PNOC_INT_1); +DEFINE_QNODE(mas_pnoc_sdcc_1, MASTER_SDCC_1, 7, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 1, PNOC_INT_1); +DEFINE_QNODE(mas_pnoc_sdcc_2, MASTER_SDCC_2, 8, 8, 0, -1, -1, QCOM_QOS_MODE_FIXED, 1, PNOC_INT_1); +DEFINE_QNODE(pnoc_snoc_mas, PNOC_SNOC_MAS, 0, 8, 0, 29, -1, QCOM_QOS_MODE_FIXED, 1, PNOC_SNOC_SLV); + +static struct qcom_icc_node *msm8916_snoc_nodes[] = { + &mas_video, + &mas_jpeg, + &mas_vfe, + &mas_mdp, + &mas_qdss_bam, + &mas_snoc_cfg, + &mas_qdss_etr, + &mm_int_0, + &mm_int_1, + &mm_int_2, + &mm_int_bimc, + &snoc_int_0, + &snoc_int_1, + &snoc_int_bimc, + &snoc_bimc_0_mas, + &snoc_bimc_1_mas, + &qdss_int, + &bimc_snoc_slv, + &snoc_pnoc_mas, + &pnoc_snoc_slv, + &slv_srvc_snoc, + &slv_qdss_stm, + &slv_imem, + &slv_apss, + &slv_cats_0, + &slv_cats_1, +}; + +static struct qcom_icc_desc msm8916_snoc = { + .nodes = msm8916_snoc_nodes, + .num_nodes = ARRAY_SIZE(msm8916_snoc_nodes), +}; + +static struct qcom_icc_node *msm8916_bimc_nodes[] = { + &mas_apss, + &mas_tcu0, + &mas_tcu1, + &mas_gfx, + &bimc_snoc_mas, + &snoc_bimc_0_slv, + &snoc_bimc_1_slv, + &slv_ebi_ch0, + &slv_apps_l2, +}; + +static struct qcom_icc_desc msm8916_bimc = { + .nodes = msm8916_bimc_nodes, + .num_nodes = ARRAY_SIZE(msm8916_bimc_nodes), +}; + +static struct qcom_icc_node *msm8916_pnoc_nodes[] = { + &snoc_pnoc_slv, + &pnoc_int_0, + &pnoc_int_1, + &pnoc_m_0, + &pnoc_m_1, + &pnoc_s_0, + &pnoc_s_1, + &pnoc_s_2, + &pnoc_s_3, + &pnoc_s_4, + &pnoc_s_8, + &pnoc_s_9, + &slv_imem_cfg, + &slv_crypto_0_cfg, + &slv_msg_ram, + &slv_pdm, + &slv_prng, + &slv_clk_ctl, + &slv_mss, + &slv_tlmm, + &slv_tcsr, + &slv_security, + &slv_spdm, + &slv_pnoc_cfg, + &slv_pmic_arb, + &slv_bimc_cfg, + &slv_boot_rom, + &slv_mpm, + &slv_qdss_cfg, + &slv_rbcpr_cfg, + &slv_snoc_cfg, + &slv_dehr_cfg, + &slv_venus_cfg, + &slv_display_cfg, + &slv_camera_cfg, + &slv_usb_hs, + &slv_sdcc_1, + &slv_blsp_1, + &slv_sdcc_2, + &slv_gfx_cfg, + &slv_audio, + &mas_blsp_1, + &mas_spdm, + &mas_dehr, + &mas_audio, + &mas_usb_hs, + &mas_pnoc_crypto_0, + &mas_pnoc_sdcc_1, + &mas_pnoc_sdcc_2, + &pnoc_snoc_mas, +}; + +static struct qcom_icc_desc msm8916_pnoc = { + .nodes = msm8916_pnoc_nodes, + .num_nodes = ARRAY_SIZE(msm8916_pnoc_nodes), +}; + +static int qcom_icc_init(struct icc_node *node) +{ + struct qcom_icc_provider *qp = to_qcom_provider(node->provider); + int ret; + + /* TODO: init qos and priority */ + + clk_set_rate(qp->bus_clk, INT_MAX); + ret = clk_prepare_enable(qp->bus_clk); + if (ret) + pr_info("%s: error enabling bus clk (%d)\n", __func__, ret); + clk_set_rate(qp->bus_a_clk, INT_MAX); + ret = clk_prepare_enable(qp->bus_a_clk); + if (ret) + pr_info("%s: error enabling bus_a clk (%d)\n", __func__, ret); + + return 0; +} + +static int qcom_icc_aggregate(struct icc_node *node, u32 avg_bw, u32 peak_bw, + u32 *agg_avg, u32 *agg_peak) +{ + *agg_avg += avg_bw; + *agg_peak = max(*agg_peak, peak_bw); + + return 0; +} + +static int qcom_icc_set(struct icc_node *src, struct icc_node *dst, + u32 avg, u32 peak) +{ + struct qcom_icc_provider *qp; + struct qcom_icc_node *qn; + struct icc_node *node; + struct icc_provider *provider; + u64 avg_bw = icc_units_to_bps(avg); + u64 peak_bw = icc_units_to_bps(peak); + u64 rate = 0; + int ret = 0; + + if (!src) + node = dst; + else + node = src; + + qn = node->data; + provider = node->provider; + qp = to_qcom_provider(node->provider); + + /* set bandwidth */ + if (qn->ap_owned) { + /* TODO: set QoS */ + } else { + /* send message to the RPM processor */ + if (qn->mas_rpm_id != -1) { + ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE, + RPM_BUS_MASTER_REQ, + qn->mas_rpm_id, + avg_bw); + } + + if (qn->slv_rpm_id != -1) { + ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE, + RPM_BUS_SLAVE_REQ, + qn->slv_rpm_id, + avg_bw); + } + } + + rate = max(avg_bw, peak_bw); + + do_div(rate, qn->buswidth); + + if (qn->rate != rate) { + ret = clk_set_rate(qp->bus_clk, rate); + if (ret) { + pr_err("set clk rate %lld error %d\n", rate, ret); + return ret; + } + + ret = clk_set_rate(qp->bus_a_clk, rate); + if (ret) { + pr_err("set clk rate %lld error %d\n", rate, ret); + return ret; + } + + qn->rate = rate; + } + + return ret; +} + +static int qnoc_probe(struct platform_device *pdev) +{ + const struct qcom_icc_desc *desc; + struct qcom_icc_node **qnodes; + struct qcom_icc_provider *qp; + struct resource *res; + struct icc_provider *provider; + size_t num_nodes, i; + int ret; + + /* wait for RPM */ + if (!qcom_icc_rpm_smd_available()) + return -EPROBE_DEFER; + + desc = of_device_get_match_data(&pdev->dev); + if (!desc) + return -EINVAL; + + qnodes = desc->nodes; + num_nodes = desc->num_nodes; + + qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL); + if (!qp) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + qp->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(qp->base)) + return PTR_ERR(qp->base); + + qp->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); + if (IS_ERR(qp->bus_clk)) + return PTR_ERR(qp->bus_clk); + + qp->bus_a_clk = devm_clk_get(&pdev->dev, "bus_a_clk"); + if (IS_ERR(qp->bus_a_clk)) + return PTR_ERR(qp->bus_a_clk); + + provider = &qp->provider; + provider->dev = &pdev->dev; + provider->set = &qcom_icc_set; + provider->aggregate = &qcom_icc_aggregate; + INIT_LIST_HEAD(&provider->nodes); + provider->data = qp; + + ret = icc_provider_add(provider); + if (ret) { + dev_err(&pdev->dev, "error adding interconnect provider\n"); + return ret; + } + + for (i = 0; i < num_nodes; i++) { + struct icc_node *node; + int ret; + size_t j; + + node = icc_node_create(qnodes[i]->id); + if (IS_ERR(node)) { + ret = PTR_ERR(node); + goto err; + } + + node->name = qnodes[i]->name; + node->data = qnodes[i]; + icc_node_add(node, provider); + + dev_dbg(&pdev->dev, "registered node %s\n", node->name); + + ret = qcom_icc_init(node); + if (ret) + dev_err(&pdev->dev, "%s init error (%d)\n", node->name, + ret); + + /* populate links */ + for (j = 0; j < qnodes[i]->num_links; j++) + if (qnodes[i]->links[j]) + icc_link_create(node, qnodes[i]->links[j]); + } + + platform_set_drvdata(pdev, provider); + + return ret; +err: + icc_provider_del(provider); + return ret; +} + +static int qnoc_remove(struct platform_device *pdev) +{ + struct icc_provider *provider = platform_get_drvdata(pdev); + + icc_provider_del(provider); + + return 0; +} + +static const struct of_device_id qnoc_of_match[] = { + { .compatible = "qcom,msm8916-pnoc", .data = &msm8916_pnoc }, + { .compatible = "qcom,msm8916-snoc", .data = &msm8916_snoc }, + { .compatible = "qcom,msm8916-bimc", .data = &msm8916_bimc }, + { }, +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver = { + .probe = qnoc_probe, + .remove = qnoc_remove, + .driver = { + .name = "qnoc-msm8916", + .of_match_table = qnoc_of_match, + }, +}; +module_platform_driver(qnoc_driver); +MODULE_AUTHOR("Georgi Djakov "); +MODULE_DESCRIPTION("Qualcomm msm8916 NoC driver"); +MODULE_LICENSE("GPL v2"); From patchwork Wed Jun 20 12:11:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 139318 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp712365lji; 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[209.132.180.67]) by mx.google.com with ESMTP id j10-v6si2117250pff.269.2018.06.20.05.12.51; Wed, 20 Jun 2018 05:12:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IOTI8fNr; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754159AbeFTMMu (ORCPT + 30 others); Wed, 20 Jun 2018 08:12:50 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:51157 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753995AbeFTML5 (ORCPT ); Wed, 20 Jun 2018 08:11:57 -0400 Received: by mail-wm0-f66.google.com with SMTP id e16-v6so5631696wmd.0 for ; Wed, 20 Jun 2018 05:11:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IqhM5Ox8GZtLGas2YyRL1o8i1y7I7Q6nRSIg2WoLuIA=; b=IOTI8fNrS86MKNRUjjEtu6tRplQMqLzzb0Wwd8ektRS96w/GT4ZcpL1yim7fFKSzSx AUC2BKwJxW3zim77Yp9JlitDEVgsqob1S4dbH+lmOYmBXzVLrt4Kb0AL9eSh5AP4gKI4 zhBY23t+yF3u0A0igMHhGqFSb3d3dT7Ms+iuk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IqhM5Ox8GZtLGas2YyRL1o8i1y7I7Q6nRSIg2WoLuIA=; b=Asl8BjeUpEt9Bdu+YVU7a5XlJVa7od0DSKUwhsV0Rqx4V2X6sEaT4wyMRnP+Gs3lmG cvl6nVCsz5SoKT/kW4KJ2iWgxD84ErmR0SybC98VEpKjbgrMm3Rhs3SbqyptLt+zHe7+ Fnk+/hwO3iWdc69IQK44dJaCIKzNpnWenI8+2M2tsDFYqEzHQYwmNIdvLWmTymrfWwyY ReW7iZGNM/9p2QCA/nVwLWAUIMHPbKelDGWEFdhR7ZpH3/JZjtkVxXTTcHtBPQdbb5gc sHOglTlJIfn5VoTmXyL/F3gDRsengygQddAbiEw2Zr8bUmUgNehY5OoIWcMVnfzilp4r aUfQ== X-Gm-Message-State: APt69E3cTGLAiTJQ8IUT3QyZJmkVdjBzy2lcY6Q4kNQvJ9yTTkH7alKN USpThdHCeH9LTFEo+ToVJV0COQ== X-Received: by 2002:a1c:28c6:: with SMTP id o189-v6mr1636268wmo.102.1529496716284; Wed, 20 Jun 2018 05:11:56 -0700 (PDT) Received: from localhost.localdomain ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id e14-v6sm1656483wmh.17.2018.06.20.05.11.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 20 Jun 2018 05:11:55 -0700 (PDT) From: Georgi Djakov To: linux-pm@vger.kernel.org, gregkh@linuxfoundation.org Cc: rjw@rjwysocki.net, robh+dt@kernel.org, mturquette@baylibre.com, khilman@baylibre.com, vincent.guittot@linaro.org, skannan@codeaurora.org, bjorn.andersson@linaro.org, amit.kucheria@linaro.org, seansw@qti.qualcomm.com, daidavid1@codeaurora.org, evgreen@chromium.org, mark.rutland@arm.com, lorenzo.pieralisi@arm.com, abailon@baylibre.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v5 7/8] dt-bindings: Introduce interconnect consumers bindings Date: Wed, 20 Jun 2018 15:11:40 +0300 Message-Id: <20180620121141.15403-8-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180620121141.15403-1-georgi.djakov@linaro.org> References: <20180620121141.15403-1-georgi.djakov@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add documentation for the interconnect consumer bindings, that will allow to link a device node (consumer) to its interconnect controller hardware. Tha aim is to enable drivers to request a framework API to configure an interconnect path by providing their struct device pointer and a name. Signed-off-by: Georgi Djakov --- .../bindings/interconnect/interconnect.txt | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/Documentation/devicetree/bindings/interconnect/interconnect.txt b/Documentation/devicetree/bindings/interconnect/interconnect.txt index 6e2b2971b094..0ad65dccbe8b 100644 --- a/Documentation/devicetree/bindings/interconnect/interconnect.txt +++ b/Documentation/devicetree/bindings/interconnect/interconnect.txt @@ -31,3 +31,30 @@ Example: clocks = <&rpmcc RPM_SMD_SNOC_CLK>, <&rpmcc RPM_SMD_SNOC_A_CLK>; }; + + += interconnect consumers = + +The interconnect consumers are device nodes which consume the interconnect +path(s) provided by the interconnect provider. There can be multiple +interconnect providers on a SoC and the consumer may consume multiple paths +from different providers depending on use case and the components it has to +interact with. + +Required properties: +interconnects : Pairs of phandles and interconnect provider specifier to denote + the edge source and destination ports of the interconnect path. + +Optional properties: +interconnect-names : List of interconnect path name strings sorted in the same + order as the interconnects property. Consumers drivers will use + interconnect-names to match interconnect paths with interconnect + specifiers. + +Example: + + sdhci@7864000 { + ... + interconnects = <&pnoc MASTER_SDCC_1 &bimc SLAVE_EBI_CH0>; + interconnect-names = "ddr"; + };