From patchwork Tue May 4 05:28:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 430965 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0750BC43470 for ; Tue, 4 May 2021 05:28:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DE025611EE for ; Tue, 4 May 2021 05:28:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229737AbhEDF3w (ORCPT ); Tue, 4 May 2021 01:29:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50250 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229786AbhEDF3v (ORCPT ); Tue, 4 May 2021 01:29:51 -0400 Received: from mail-pg1-x52d.google.com (mail-pg1-x52d.google.com [IPv6:2607:f8b0:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F9C4C061761 for ; Mon, 3 May 2021 22:28:57 -0700 (PDT) Received: by mail-pg1-x52d.google.com with SMTP id m124so402346pgm.13 for ; Mon, 03 May 2021 22:28:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ts19LcXzJnm2OK0dKlHI64T4AANtdk+C1elhddnhZ4k=; b=TSRMvon4FdD8NHLI1+656d3UAALnt4POSawOiyDfsw8RDog22qyaig24zVhKgU6Wbu I29fbfqm6Q9sJ1PWouIm+m+Dy2hgxOaXdzysEXWj3o8tTXn9My7oyVirKEtAbsAH3rpR XOehcTuE6yAgqffZgx0XoRDN/nSjCFOpWDo+d2TPdlgRPZrPa7Q7ZlFCbs6bhrX2UFHn A2n1KEYY3Vl43/dTFaAVSl1EOKW00l7uxcJawHnOHEktNmS6uG+wF/Hgr1ZB84TGsMjs hh/i3GzH84QTgcEldcynV0F8RTvFjdeoI5y83pjOJedJ8ek5bhamoq+mdN3wZGu9Of0q +adQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ts19LcXzJnm2OK0dKlHI64T4AANtdk+C1elhddnhZ4k=; b=eaS7oeDqVSNIIkVjlWUv8qwzpUMYso3Y9gbiaMOH7s+9FSNn3K6+XVBDDheuW3eqEB +5e//MDMldRvL/DR2wqTBN55ClkVDLLbpfo4Ns+rdQ9EwZteZHUmpdFEm1KUwVMSvoa5 YSyPcyDnf+6TGryrNjoJkp9OoRI/FpYHYTWMJvAcvrmXseOCgLnf8XHxCQuo+69X9IDc CFusL+uACkvyxReNxD7qd78s0plBwHvMjBo8ATNLSpLkfU40jkIypNmDOxrxcHKGAI8R 8sp3TMQVCvYiLOan08P7FUnbkp4Tlop2mp07l5nezXW9GJ67FPUOy5zHvfFuBTFAi2u6 2bqw== X-Gm-Message-State: AOAM532NiPtZ0NK4JHdi/Blh4wSs2A9TWIV7Zewh4hHdiwLqaF6IFTma z69z0+stSI+EgFwr9s9YysNLPA== X-Google-Smtp-Source: ABdhPJz2XiWwCEp746etZEjp1bdfE8F+eo84izKixIQN16nnxgI0pOpet0UmOEQ5ZaSq+9EMM8UpCA== X-Received: by 2002:a17:90a:1782:: with SMTP id q2mr3457058pja.73.1620106136731; Mon, 03 May 2021 22:28:56 -0700 (PDT) Received: from localhost.localdomain (80.251.214.228.16clouds.com. [80.251.214.228]) by smtp.gmail.com with ESMTPSA id 145sm5933229pfv.196.2021.05.03.22.28.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 May 2021 22:28:56 -0700 (PDT) From: Shawn Guo To: Stephen Boyd Cc: Bjorn Andersson , Rob Herring , Sivaprakash Murugesan , Benjamin Li , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Shawn Guo Subject: [PATCH 1/5] clk: qcom: apcs-msm8916: Flag a53mux instead of a53pll as critical Date: Tue, 4 May 2021 13:28:40 +0800 Message-Id: <20210504052844.21096-2-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504052844.21096-1-shawn.guo@linaro.org> References: <20210504052844.21096-1-shawn.guo@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The clock source for MSM8916 cpu cores is like below. |\ a53pll --------| \ a53mux +------+ | |------------| cpus | gpll0_vote --------| / +------+ |/ So clock a53mux rather than a53pll is actually the clock source of cpu cores. It makes more sense to flag a53mux rather than a53pll as critical, since a53pll could be irrelevant if a53mux switches its parent clock to be gpll0_vote. Signed-off-by: Shawn Guo --- drivers/clk/qcom/a53-pll.c | 1 - drivers/clk/qcom/apcs-msm8916.c | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/clk/qcom/a53-pll.c b/drivers/clk/qcom/a53-pll.c index 45cfc57bff92..8614b0b0e82c 100644 --- a/drivers/clk/qcom/a53-pll.c +++ b/drivers/clk/qcom/a53-pll.c @@ -70,7 +70,6 @@ static int qcom_a53pll_probe(struct platform_device *pdev) init.parent_names = (const char *[]){ "xo" }; init.num_parents = 1; init.ops = &clk_pll_sr2_ops; - init.flags = CLK_IS_CRITICAL; pll->clkr.hw.init = &init; ret = devm_clk_register_regmap(dev, &pll->clkr); diff --git a/drivers/clk/qcom/apcs-msm8916.c b/drivers/clk/qcom/apcs-msm8916.c index cf69a97d0439..d7ac6d6b15b6 100644 --- a/drivers/clk/qcom/apcs-msm8916.c +++ b/drivers/clk/qcom/apcs-msm8916.c @@ -65,7 +65,7 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev) init.parent_data = pdata; init.num_parents = ARRAY_SIZE(pdata); init.ops = &clk_regmap_mux_div_ops; - init.flags = CLK_SET_RATE_PARENT; + init.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT; a53cc->clkr.hw.init = &init; a53cc->clkr.regmap = regmap; From patchwork Tue May 4 05:28:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 430797 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3474859jao; Mon, 3 May 2021 22:29:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx20D/wCPT+Lhu8LolmGV3PbP5VrsS6UQ2Jn2yOm8OlMElS2VgwXNciQ6mHd53BE5+ae4vr X-Received: by 2002:a17:90a:e003:: with SMTP id u3mr2832358pjy.77.1620106146331; Mon, 03 May 2021 22:29:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620106146; cv=none; d=google.com; s=arc-20160816; b=L1GbOhIsr+QngksmRpXci5yLXP67ymhH4m1l0mbS11OawIAJ2lb8anwUAFI3RaYSs1 9EnHax8YuNXmFlC8QbMgdvfzd1BZKwm1D5ceb26qe8AuQl0y0KB8zEKww9iT3iyn+p+T WdOCstv7lHFFEcXejfGZn1zzkn5uYnAEaXbNSmMSqxmsQ1gkCj0+io/JpDA1xWzmLb6+ IfAas9ArcmFwxBpb48OSE+jrfMUnCaPeNUxyofWJuR6zhn1SgCX711TQqAoxvV25B5Sq MSwcv4bh6ACN4SzEsZoXBhYyALgn08HhSwT2qWGNlo5xqbEqG4WJmGdtRk+DXHhMfPQR i/eg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=X/MGql9b3iDHbEGk1fEF6JKWQobHRfGqiTtP2HlirKU=; b=Eemt12CECa6x61/6iCHwn/85zI9FsFLl/+LxGeHqIIknaEBpvOahQyxU37dgU/GARo dBAAeQB0BcUaxtejfmoEnyXEttoXoaieErr4dVUwAMXcnbwpe4gJim6St5GuuU+Vd8Ky LHzQDNGbvUGTLu5RF+ZIzTVMXMIByvlzo+odP7uao5RisipPYnKPUIH1kRoNEFNXjl7D 48UPguR8ZHXct/bEIvy+fllGGuEwYviRO0c4vbVftSK8t1bK+7Tp1giourgPSoSH2qhA m/o5+HxYmxoXttSz1ktYXNFEMYeVtMCJoTfd3ljenYgXPOPrMY5mB9nE/0V955n3m9g+ jMOw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iS9nCRP7; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[80.251.214.228]) by smtp.gmail.com with ESMTPSA id 145sm5933229pfv.196.2021.05.03.22.28.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 May 2021 22:28:59 -0700 (PDT) From: Shawn Guo To: Stephen Boyd Cc: Bjorn Andersson , Rob Herring , Sivaprakash Murugesan , Benjamin Li , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Shawn Guo Subject: [PATCH 2/5] dt-bindings: clock: update qcom, a53pll bindings for MSM8939 support Date: Tue, 4 May 2021 13:28:41 +0800 Message-Id: <20210504052844.21096-3-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504052844.21096-1-shawn.guo@linaro.org> References: <20210504052844.21096-1-shawn.guo@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Update qcom,a53pll bindings for MSM8939 support: - Add optional clock-output-names property. - Add MSM8939 specific compatibles. - Add MSM8939 examples. Signed-off-by: Shawn Guo --- .../bindings/clock/qcom,a53pll.yaml | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml index db3d0ea6bc7a..7a410a76be2f 100644 --- a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml @@ -18,6 +18,9 @@ properties: enum: - qcom,ipq6018-a53pll - qcom,msm8916-a53pll + - qcom,msm8939-a53pll-c0 + - qcom,msm8939-a53pll-c1 + - qcom,msm8939-a53pll-cci reg: maxItems: 1 @@ -33,6 +36,9 @@ properties: items: - const: xo + clock-output-names: + maxItems: 1 + required: - compatible - reg @@ -57,3 +63,31 @@ examples: clocks = <&xo>; clock-names = "xo"; }; + #Example 3 - A53 PLLs found on MSM8939 devices + - | + a53pll_c1: clock-controller@b016000 { + compatible = "qcom,msm8939-a53pll-c1"; + reg = <0xb016000 0x40>; + #clock-cells = <0>; + clocks = <&xo_board>; + clock-names = "xo"; + clock-output-names = "a53pll_c1"; + }; + + a53pll_c0: clock-controller@b116000 { + compatible = "qcom,msm8939-a53pll-c0"; + reg = <0xb116000 0x40>; + #clock-cells = <0>; + clocks = <&xo_board>; + clock-names = "xo"; + clock-output-names = "a53pll_c0"; + }; + + a53pll_cci: clock-controller@b1d0000 { + compatible = "qcom,msm8939-a53pll-cci"; + reg = <0xb1d0000 0x40>; + #clock-cells = <0>; + clocks = <&xo_board>; + clock-names = "xo"; + clock-output-names = "a53pll_cci"; + }; From patchwork Tue May 4 05:28:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 430798 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3474879jao; Mon, 3 May 2021 22:29:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxlY0Py4uTpwr4cC+ZfQwu9v5BvR2eLeItokks+6s1PW2i3Az3zGqU40tQLLK9KMEaYgRoI X-Received: by 2002:a17:90b:38f:: with SMTP id ga15mr25612826pjb.196.1620106147403; Mon, 03 May 2021 22:29:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620106147; cv=none; d=google.com; s=arc-20160816; b=Q58XONYHT51kJXPEzAUsGfktqo3BUMBTU0p8gCUpTVRW4ng2IUk/XX9N7iKxl71c34 ZdyV1dGEefDxR/ySR+OzDwSNjHt+pDXVFm9RGFUg/sYJJWwltsd74k5Ia/HkWhkxvofP 2v+t1XoLEyG22s+6VQ8C29gUSsr/kUgFYRx5mbEuy4G7MmaTvyKyHY5i+QrC3LrgOI8X V5hgWiiGoljQ8AcagVXFljxsy+eL+QIU70N7MOIr8kJ+VXNxtjp6t/XmK47ytb8Gg5Wf LMD4/RMIjnaUNF3/qbZAdnEOYCVO0QE+M+HPwZoHGozF5jnKD+b/cWI6+BMuMsr+rbg2 GzWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=gIUTD/xcjRZwD9lqPa/K9njfq+3aHSwHrSeb5ACE0xU=; b=jTnk44vsIKCNa+BeAdRocQa6/Tv9Ol2Lpzgg0agQ7Hchyex/u/SVKgbEolcvGraWRw aTZ43bdw9i5S9oo/FpEO/mSPusZof4S/HERmoKd0x7Dngw93MipOg3z1CVxn8wOHZbGK GvGomjpDzn5DqIjLReC0J2WxW95g50uh4FryDqKmKfC9Vur9NUGLENI/qY32F+fRCUK6 EdPHUDS0D5vwrzReQBjJRhTBgYMTy0EWpapwJWqYd8BI6qOtnu6a7+2IccRxFh2IcxV0 vnbY/VvAIzhLD6AbiDXI5F4K/TKzPyrV+/YaMFLcW2J782uFxhv+7o5+lpmzkl1YAW87 dO1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QIVCAcQd; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[80.251.214.228]) by smtp.gmail.com with ESMTPSA id 145sm5933229pfv.196.2021.05.03.22.29.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 May 2021 22:29:02 -0700 (PDT) From: Shawn Guo To: Stephen Boyd Cc: Bjorn Andersson , Rob Herring , Sivaprakash Murugesan , Benjamin Li , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Shawn Guo Subject: [PATCH 3/5] clk: qcom: apcs-msm8916: Retrieve clock name from DT Date: Tue, 4 May 2021 13:28:42 +0800 Message-Id: <20210504052844.21096-4-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504052844.21096-1-shawn.guo@linaro.org> References: <20210504052844.21096-1-shawn.guo@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Unlike MSM8916 which has only one APCS clock, MSM8939 gets three for Cluster0 (little cores), Cluster1 (big cores) and CCI (Cache Coherent Interconnect). Instead of hard coding APCS (and A53PLL) clock name, retrieve the name from DT, so that multiple APCS clocks can be registered. Signed-off-by: Shawn Guo --- drivers/clk/qcom/a53-pll.c | 5 ++++- drivers/clk/qcom/apcs-msm8916.c | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/clk/qcom/a53-pll.c b/drivers/clk/qcom/a53-pll.c index 8614b0b0e82c..964f5ab7d02f 100644 --- a/drivers/clk/qcom/a53-pll.c +++ b/drivers/clk/qcom/a53-pll.c @@ -42,6 +42,7 @@ static int qcom_a53pll_probe(struct platform_device *pdev) struct clk_pll *pll; void __iomem *base; struct clk_init_data init = { }; + const char *clk_name = NULL; int ret; pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); @@ -66,7 +67,9 @@ static int qcom_a53pll_probe(struct platform_device *pdev) pll->status_bit = 16; pll->freq_tbl = a53pll_freq; - init.name = "a53pll"; + of_property_read_string(pdev->dev.of_node, "clock-output-names", + &clk_name); + init.name = clk_name ? clk_name : "a53pll"; init.parent_names = (const char *[]){ "xo" }; init.num_parents = 1; init.ops = &clk_pll_sr2_ops; diff --git a/drivers/clk/qcom/apcs-msm8916.c b/drivers/clk/qcom/apcs-msm8916.c index d7ac6d6b15b6..b8bbfe9622e1 100644 --- a/drivers/clk/qcom/apcs-msm8916.c +++ b/drivers/clk/qcom/apcs-msm8916.c @@ -49,6 +49,7 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev) struct clk_regmap_mux_div *a53cc; struct regmap *regmap; struct clk_init_data init = { }; + const char *clk_name = NULL; int ret = -ENODEV; regmap = dev_get_regmap(parent, NULL); @@ -61,7 +62,9 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev) if (!a53cc) return -ENOMEM; - init.name = "a53mux"; + of_property_read_string(parent->of_node, "clock-output-names", + &clk_name); + init.name = clk_name ? clk_name : "a53mux"; init.parent_data = pdata; init.num_parents = ARRAY_SIZE(pdata); init.ops = &clk_regmap_mux_div_ops; From patchwork Tue May 4 05:28:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 430799 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3474896jao; Mon, 3 May 2021 22:29:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw9kQUhVYSiV8hrPsRtmcVWUIrbXB0AzSO/4U1WJNig42WLb1ZwDJzvVLHwfPMn4Pu8eaFP X-Received: by 2002:aa7:9299:0:b029:21d:7ad1:2320 with SMTP id j25-20020aa792990000b029021d7ad12320mr22366034pfa.22.1620106148833; Mon, 03 May 2021 22:29:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620106148; cv=none; d=google.com; s=arc-20160816; b=nih0hEZgxj6r7pNkbZ5VED1BSsjcMSzaCkGJ0W/yZboWByyTXW6ZJ3e28Qthm3D+27 TIr+b42POKxYTZk+bA4D/DHfy9ZNUFt+l9WhpaAxoH340j9dM/t35oGQ9W8CQ7Jmwhyc NrlK6wHXpUPfDALBLeQSknoMjuNWIRS0nf/A6eAHF79uDI5GgtqM2UZgwkMY6pkqwzld gvWxwN69CimAotMsexQPIp3qsCp7J/34Vf3GhTU73GaYiZ0oUWMXPUxz6WixrxPuiAG7 mD7IR9JZ+6JuYtOFnFv1DT8cj0WvUiq9lwHjKyuiQCpX7iLYPQhYsK5RaBVw+oWsmD/4 CKdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=RjDDEQHznq8kml6OFuSumxrNRPKtAVnBXfVZoTIOBJk=; b=FbbHEwd23thYesd5swLRK8E0CcKkCJvwGRLi1KR6hmIMCn7g5Tt8QvLjoroGftqJVr l7SQpfdkelNPsLjNeFjXds9hrkYwxlR9jHPst5+AQmpQRPyJuYiKUMpOMwWh/oJoGLNv z7eFZRRsEbEAHvZJzx6rreQjIrcPZfcdZII8UBKVBv8cTSNRaZmKiry4gyeG3mhBGX3P Xa6n5PLh7YFEui02mbAgY+QS60LOXF213r7AuqtEu/tTUGGCHRkSXYLjDdjR2TZHtNkb mw/rsTcamGkfMzPwtYmYOJFjOeRkI3UpsS91mGcjUUpecj62Taxh/YTYHIQ5WzugdmOU jrrA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=edgEPWYj; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[80.251.214.228]) by smtp.gmail.com with ESMTPSA id 145sm5933229pfv.196.2021.05.03.22.29.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 May 2021 22:29:05 -0700 (PDT) From: Shawn Guo To: Stephen Boyd Cc: Bjorn Andersson , Rob Herring , Sivaprakash Murugesan , Benjamin Li , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Shawn Guo Subject: [PATCH 4/5] clk: qcom: a53-pll: Pass freq_tbl via match data Date: Tue, 4 May 2021 13:28:43 +0800 Message-Id: <20210504052844.21096-5-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504052844.21096-1-shawn.guo@linaro.org> References: <20210504052844.21096-1-shawn.guo@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The frequency table is SoC specific. Instead of hard coding, pass it via match data, so that the driver can work for more than just MSM8916. This is a preparation change for adding MSM8939 A53PLL support. Signed-off-by: Shawn Guo --- drivers/clk/qcom/a53-pll.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/drivers/clk/qcom/a53-pll.c b/drivers/clk/qcom/a53-pll.c index 964f5ab7d02f..bfa048dc01ec 100644 --- a/drivers/clk/qcom/a53-pll.c +++ b/drivers/clk/qcom/a53-pll.c @@ -15,7 +15,7 @@ #include "clk-pll.h" #include "clk-regmap.h" -static const struct pll_freq_tbl a53pll_freq[] = { +static const struct pll_freq_tbl msm8916_freq[] = { { 998400000, 52, 0x0, 0x1, 0 }, { 1094400000, 57, 0x0, 0x1, 0 }, { 1152000000, 62, 0x0, 0x1, 0 }, @@ -43,8 +43,13 @@ static int qcom_a53pll_probe(struct platform_device *pdev) void __iomem *base; struct clk_init_data init = { }; const char *clk_name = NULL; + const struct pll_freq_tbl *freq_tbl; int ret; + freq_tbl = device_get_match_data(&pdev->dev); + if (!freq_tbl) + return -ENODEV; + pll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL); if (!pll) return -ENOMEM; @@ -65,7 +70,7 @@ static int qcom_a53pll_probe(struct platform_device *pdev) pll->mode_reg = 0x00; pll->status_reg = 0x1c; pll->status_bit = 16; - pll->freq_tbl = a53pll_freq; + pll->freq_tbl = freq_tbl; of_property_read_string(pdev->dev.of_node, "clock-output-names", &clk_name); @@ -92,7 +97,7 @@ static int qcom_a53pll_probe(struct platform_device *pdev) } static const struct of_device_id qcom_a53pll_match_table[] = { - { .compatible = "qcom,msm8916-a53pll" }, + { .compatible = "qcom,msm8916-a53pll", .data = msm8916_freq }, { } }; From patchwork Tue May 4 05:28:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 430800 Delivered-To: patch@linaro.org Received: by 2002:a02:c901:0:0:0:0:0 with SMTP id t1csp3474955jao; Mon, 3 May 2021 22:29:15 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyJBTX/xbTj0x6jY1ZniZIXmKmz9iWuXk27ipFBSst+6+i2yx1nvikUhEOmnMixSKvcqzJy X-Received: by 2002:a17:90a:be10:: with SMTP id a16mr2694567pjs.112.1620106155112; Mon, 03 May 2021 22:29:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1620106155; cv=none; d=google.com; s=arc-20160816; b=ruNLJEOD3bcUSdFJht+ZlLJmIrsyczETCyAaMkPDExATiBXumO7kL/sYu8gnyG3Qho pm4zS5x7dkWbQ8/IEYL73bwdbJhYU94DJkGrSMOs4XQJmaFfn2OXBTRlzksbe7cv9gy/ d8jH3oB0xuM+JFsGZIDW9PcJV19oegoFwTbH9/DHNL3rKPv+AcOhLYiWfLtSS7IZy8y2 EHT5tfytToTLuN6eFU2Cr9nd0KdD18C4f9Vx/DWYIxjwnLypLnC0abUVD8byCXPf5VCn CZ4Hmd6CjRumCAsdOA3wfsrdoGUwwOHyA/efznLip0s0TkU/tecphrU7eri0ifrdObtu KxvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=aNWYHyF10Ocv0rGRJlTBLbyA6sxWZ+weiafnUhBtEKk=; b=eM8zw6IZtVeA7lV3umwafJZWd1G3J71IIh6xZ/INYWujVcqhRd4b0ZsIv35UuhTPbV EFiSZz1Yc8tzAq6KgtMcfgZmPim8eGDL8Kg9wssaw2gEzoWWS1SHyWdOT6C21/tTStlu smj0++7cmJ8tbRMyGqYPf1nZaMNHlbPY0nil1pYFYBP1fozXP7Dk4TRStHRcZ0lCgLP0 6NOYfsiYyt4tT4VaBhcCcaGmEBH0YsX3S6TGOLLKTuRoIuBb0ETRWFBDutOAgtLFZ3+i DZsyqS6f5WKShXRozABhtCg+wJisC4kQWzlqV/JL1y91JYYi6K6byG+sISFlJ5F24EnU 6a4A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H16lLhHB; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[80.251.214.228]) by smtp.gmail.com with ESMTPSA id 145sm5933229pfv.196.2021.05.03.22.29.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 May 2021 22:29:08 -0700 (PDT) From: Shawn Guo To: Stephen Boyd Cc: Bjorn Andersson , Rob Herring , Sivaprakash Murugesan , Benjamin Li , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Shawn Guo Subject: [PATCH 5/5] clk: qcom: a53-pll: Add MSM8939 a53pll clocks Date: Tue, 4 May 2021 13:28:44 +0800 Message-Id: <20210504052844.21096-6-shawn.guo@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210504052844.21096-1-shawn.guo@linaro.org> References: <20210504052844.21096-1-shawn.guo@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org It adds support for MSM8939 a53pll clock of Cluster0, Cluster1 and CCI (Cache Coherent Interconnect). The frequency data comes from vendor kernel. Signed-off-by: Shawn Guo --- drivers/clk/qcom/a53-pll.c | 42 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) -- 2.17.1 diff --git a/drivers/clk/qcom/a53-pll.c b/drivers/clk/qcom/a53-pll.c index bfa048dc01ec..8c6f8bcc6128 100644 --- a/drivers/clk/qcom/a53-pll.c +++ b/drivers/clk/qcom/a53-pll.c @@ -26,6 +26,45 @@ static const struct pll_freq_tbl msm8916_freq[] = { { } }; +static const struct pll_freq_tbl msm8939_c0_freq[] = { + { 998400000, 52, 0x0, 0x1, 0 }, + { 1113600000, 58, 0x0, 0x1, 0 }, + { 1209600000, 63, 0x0, 0x1, 0 }, +}; + +static const struct pll_freq_tbl msm8939_c1_freq[] = { + { 652800000, 34, 0x0, 0x1, 0 }, + { 691200000, 36, 0x0, 0x1, 0 }, + { 729600000, 38, 0x0, 0x1, 0 }, + { 806400000, 42, 0x0, 0x1, 0 }, + { 844800000, 44, 0x0, 0x1, 0 }, + { 883200000, 46, 0x0, 0x1, 0 }, + { 960000000, 50, 0x0, 0x1, 0 }, + { 998400000, 52, 0x0, 0x1, 0 }, + { 1036800000, 54, 0x0, 0x1, 0 }, + { 1113600000, 58, 0x0, 0x1, 0 }, + { 1209600000, 63, 0x0, 0x1, 0 }, + { 1190400000, 62, 0x0, 0x1, 0 }, + { 1267200000, 66, 0x0, 0x1, 0 }, + { 1344000000, 70, 0x0, 0x1, 0 }, + { 1363200000, 71, 0x0, 0x1, 0 }, + { 1420800000, 74, 0x0, 0x1, 0 }, + { 1459200000, 76, 0x0, 0x1, 0 }, + { 1497600000, 78, 0x0, 0x1, 0 }, + { 1536000000, 80, 0x0, 0x1, 0 }, + { 1574400000, 82, 0x0, 0x1, 0 }, + { 1612800000, 84, 0x0, 0x1, 0 }, + { 1632000000, 85, 0x0, 0x1, 0 }, + { 1651200000, 86, 0x0, 0x1, 0 }, + { 1689600000, 88, 0x0, 0x1, 0 }, + { 1708800000, 89, 0x0, 0x1, 0 }, +}; + +static const struct pll_freq_tbl msm8939_cci_freq[] = { + { 403200000, 21, 0x0, 0x1, 0 }, + { 595200000, 31, 0x0, 0x1, 0 }, +}; + static const struct regmap_config a53pll_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -98,6 +137,9 @@ static int qcom_a53pll_probe(struct platform_device *pdev) static const struct of_device_id qcom_a53pll_match_table[] = { { .compatible = "qcom,msm8916-a53pll", .data = msm8916_freq }, + { .compatible = "qcom,msm8939-a53pll-c0", .data = &msm8939_c0_freq }, + { .compatible = "qcom,msm8939-a53pll-c1", .data = &msm8939_c1_freq }, + { .compatible = "qcom,msm8939-a53pll-cci", .data = &msm8939_cci_freq }, { } };