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X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [RISU PATCH v4 01/22] risu_reginfo_aarch64: include signal.h for FPSIMD_MAGIC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Building with the Bionic Beaver cross compilers fails which probably means we were getting this as a side effect before. Include the correct header to get at these bits. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- risu_reginfo_aarch64.c | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c index e3fadde..3bb4339 100644 --- a/risu_reginfo_aarch64.c +++ b/risu_reginfo_aarch64.c @@ -13,6 +13,7 @@ #include #include #include +#include /* for FPSIMD_MAGIC */ #include "risu.h" #include "risu_reginfo_aarch64.h" From patchwork Fri Jun 22 14:11:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 139654 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp927652lji; Fri, 22 Jun 2018 07:16:44 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdPZRkhUt0cFEtLFmZFtjn4FbjZWZ+BAYK8tmJtscZjZXlbALeH4s+wbsh+Zt2Z+E/HGWAI X-Received: by 2002:a0c:9781:: with SMTP id l1-v6mr1558520qvd.64.1529677003984; Fri, 22 Jun 2018 07:16:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529677003; cv=none; d=google.com; s=arc-20160816; b=sAJL3dP5CFyHIIVZt/VEP/jYy8mHE2G3fz9Bo4MQG9whlZLnBZLkgwqG0DV14S49fv l9uWK+Q9UVsDTCmeoFuaSjKmdakdEX7182kW5jtraJIbRLh8wUVal6a0iNuZpqn0L/fe /B5oa+1U6gJFtUu2mfXE/lzFaDCLn9Z9dqlNT1ec+mHf3S99chg+xJ3PtPzfPw3mdDrY eyedKT/cTwG0XVtW9CSPwI0O1HxmaPz2Tagp+0cLz0w7xa/bVx+RRBnCG97OK7+uQM1n KtsFxxeYVb2jpabBODaYyXnRFeMUl33FIAq7NB4LRJjrNmdTFkwq0/bT7mfL8+Lf0O4z DlEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=bgMNNtAr5aCYiieHt/4kjMLdGIRPF8kWyQwrJxVNpCo=; b=uQxiQr9WApAylQrw6DLBGMgSE3OFdVeHZ5QQT6+kz1litkmhnelsDNtiHRG/AywSlT gm8TrhLXRz7UYwWD9MSL7xSsAxoKUlK2Gn04SOiIXboDbQWtfUwPTZS1e1iXofckOFuJ L6kRCTNoQlGEMxAvKtZaZyy1LCZ+07A4Iy9nwUoQv5EenCl4H88Yef/XpDsATruVhPj8 nVc9eT+q+7ifKX4dXV+dtlk/pbDQ2/nJLZ0jju2EkEMryHsHEk4SqkVlhCZe46EPmUrq Z2fnbz7N3vlp608zNby+2r9QSYD4FCYzfGYH1zN3AQLGE2nqSukviWEnR+zM77+oLTJs Y70Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SedgR4TN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [RISU PATCH v4 02/22] comms: include header for writev X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The compiler complains about implicit declarations otherwise. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- comms.c | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/comms.c b/comms.c index 2900c33..6946fd9 100644 --- a/comms.c +++ b/comms.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include From patchwork Fri Jun 22 14:11:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 139662 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp942009lji; Fri, 22 Jun 2018 07:30:04 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJY4d4beiq8bT3xn/w+6IO6TF1GH/mvBVI+4WCRYg+WQv2FE53oQ+NxmIXGdFSXKoOhTQ5g X-Received: by 2002:ac8:720f:: with SMTP id a15-v6mr1487023qtp.243.1529677804355; Fri, 22 Jun 2018 07:30:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529677804; cv=none; d=google.com; s=arc-20160816; b=EKh7eR7Ps8FXusIhWTVGFI0mJ3JY5xKtxCGpwRd46HrjdoLxsZ96tkzOsGRcPPueeF Z+CvKRtAzy10Nzivty1+BgIWDfZKWdr0S66Edm8N/8Py3YHSHyiv9tkEBj2j0Z+fagQn wVgD1liiMZWtPbTSEG3fFVUM269zyH54rINfS2WPZqTKVOkGrFwwiPmxpugSXS9uWzNE 5OQsnrs3VQdZdfksyL44o9QqPkgGqGrpwe77jFaOzRVYl11iJDSgCHhne4+lmpjPu6CM HA4TLOYBAe0M9rtLbKip/t7uZiQiM1pOe1W42bEA4JPVFhLCbBxfowRbFXiSPj7j6U66 YhMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=l+WH06Feov5hiPGPGR0GWwYb3SlHAVq5TbDc9rdgEGw=; b=AP1ZYYEkocG99r0lk1GjtWWCGc3PnTujDv62WBY9LwL/QQGc9j0Z/SrNtOxadLCkNh BSi0/hYzux/cNnZ1tyYHM6DJ6F2iK0FWXRtQGOLnWVzpW6VGE7hZYUIGYZ0KIDMvZ/Yo cr6otxne5xO9Epx5ou32ykVGB0inzjbIQfgqRd6DQOY1EzLd3gFsijAP2nL6U7Y85DGf z0j4r/DK7qsjzHTjdBNQpWROdHOiPHGNoWuGs/XWB/q3zyP+6uLqJBrDd5S7THBk+B68 iTsZzGVL5MWPfR231LnzuHZu1oCHop94Y8WdP1d+m9rY5Cv9BFB0PUUv06VrxG7hN8Fd 9zSw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Z3eY5v32; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::235 Subject: [Qemu-devel] [RISU PATCH v4 03/22] build-all-arches: expand the range of docker images X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We won't actually want power, we want ppc64el for the 64 bit version. Also we will soon have m68k so include that as well. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- build-all-archs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 diff --git a/build-all-archs b/build-all-archs index fa2ac90..a2f5cff 100755 --- a/build-all-archs +++ b/build-all-archs @@ -39,7 +39,7 @@ while [[ "$1" = -* ]]; do ;; --use-docker) if [ -z "$arg" ]; then - default_tags=$(docker images qemu --format "{{.Repository}}:{{.Tag}}" | grep "\(arm\|power\).*cross$") + default_tags=$(docker images qemu --format "{{.Repository}}:{{.Tag}}" | grep "\(arm\|ppc64el\|m68k\).*cross$") docker_tags=$(echo $default_tags | sed 's/\n/\s/g' ) else docker_tags="$arg" From patchwork Fri Jun 22 14:11:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 139660 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp940750lji; Fri, 22 Jun 2018 07:28:52 -0700 (PDT) X-Google-Smtp-Source: AAOMgpehf99jyCwl7cWmvcXURVvVsO0gfDwoOdWlb6wnPSzDxLEn9iwH3e8uUXSULxuICv8OK0PW X-Received: by 2002:ac8:3065:: with SMTP id g34-v6mr1514212qte.317.1529677732686; Fri, 22 Jun 2018 07:28:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529677732; cv=none; d=google.com; s=arc-20160816; b=LBOkqTAxpMBzVh6zSCKy85woUWmkL0jz8IUV6ImtILOftDMNa9d2ZwXzmEbwWpJEUF 2pbmTvLEo6jLBAsLc98a+jdjLblPyb4bwPbeOVLOOR38+fPF0NQxlUXQAsZJoKmksxdu AOuPbv5p62EvsgXnK7RfoBzwJZPwNbAyuMVe8Y7eRzRvwTJ3JNXQtH3F22RWHen7qlKE AOFpOOVcA4mdWmZ0wX9HjUemcwIyVzwco9ErBKJjEhzqZArny0R1ZcCdUG8qqLvGvi6w axXlbaBkjDZe9r4Ft3STnynzMUeVdwkQnREbVO/lHj5VuDN+tGzMGf0oCTrtajPmYEpg clHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=I2gocXId63VjHU4zxg+0vNSJIkmrjZ9YOwljyIOrCkQ=; b=zx/o6yi0ywBK7vsEJ86wSlp7ND2rFDpVOYJ/rWOsaFFSc/dUORr1pVHenMml9ZEsml CbwR4XOlSUlFw4Zxhlzh2UdgPZMElFnaiNYxCQ0syX480xQzI7yYd+D2zHPWOGki5o3k 6BqOyduAaxlW1EqqGfEsJZHa/36dvI+U7jy3YLf8DTc80eD52gFWIEZ+hIw+OkNmh5XT JHnh5QTz8xICt3eNyqmz0wVM7AL9deu0iCDLK3qcQDUHNU4cJeH8VzIIoGHOuoFrM10q RL/Sh6SXIJdnrb7pTKEEBlmbGxEl9Z7GHN2LYmO/kIs2pSvUET3W0MByOog7bxgqIi+a trig== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZIU2j6Uo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::231 Subject: [Qemu-devel] [RISU PATCH v4 04/22] build-all-arches: do a distclean $(SRC) configured X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This can cause much confusion when you have been building in your source tree. I've added a distclean so we don't unexpectedly drop the config for normal make clean invocations. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- Makefile | 3 +++ build-all-archs | 10 ++++++++++ 2 files changed, 13 insertions(+) -- 2.17.1 diff --git a/Makefile b/Makefile index ca80eef..16e48a0 100644 --- a/Makefile +++ b/Makefile @@ -51,3 +51,6 @@ $(PROG): $(OBJS) clean: rm -f $(PROG) $(OBJS) $(BINS) + +distclean: clean + rm -f config.h Makefile.in diff --git a/build-all-archs b/build-all-archs index a2f5cff..a7cd7c2 100755 --- a/build-all-archs +++ b/build-all-archs @@ -54,6 +54,16 @@ while [[ "$1" = -* ]]; do esac done +# +# If you are developing your primary architecture directly out of the +# source tree you can confuse any out-of-tree builds thanks to random +# crap in your VPATH. Let's detect that and save some hair pulling. +# +if [ -e Makefile.in ]; then + echo "Cleaning in-src-tree build" + make distclean +fi + # Debian stretch and Ubuntu Xenial have cross compiler packages for # all of these: # gcc-arm-linux-gnueabihf gcc-aarch64-linux-gnu gcc-m68k-linux-gnu From patchwork Fri Jun 22 14:11:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 139653 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp927504lji; Fri, 22 Jun 2018 07:16:35 -0700 (PDT) X-Google-Smtp-Source: AAOMgpebKcilMa+zAEZJLlLvQfFGXjln8jrfihV65MmN8/DFYDq7nvaDd3Sh2I9sO93rlu0QZE4Z X-Received: by 2002:a37:2ac7:: with SMTP id q68-v6mr1403982qkq.374.1529676995030; Fri, 22 Jun 2018 07:16:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529676995; cv=none; d=google.com; s=arc-20160816; b=q4KAl09PHDrfich2X4rKvfD3MyN4ystO8rYDGb/k9xOuAoBvaPp81IPjuSrfFEnnTs JylnykJJzYvDH67qc4t9KwjJlrA1ByCV0ydU0vj6zgA2WQuL9Afd8kzCS7IL5Aau7X7X BgSQlv2cA5YD/cdJ05N9w8tzTm98Ec0C9CShZ3htJ3+h0TjvzmVbBAdH8f1b49BVZerJ Jovdgflgfz7hYQ83TK/eDoicLactk6gtpPRdDedpWat/MdasZU/C3zc8L2qoSOUFdg16 ECz9KdxnyXjIOAkdiTVleouSfsNRfViUGp3XGTFw6dCWwSIa6GYKUe8OHFA+7q21aiVG akzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=fnpGrO7LfHgDM9qOgnz9eQOPP3P2qdZCTNj/MmDlLto=; b=mfTKKEBfzoslUY8VFk8DtWkSSRoV8kumcNUa4FKD1NIIWdI62nXM/WIWCyak5m5am9 g1moPbHU6SKq8orcJnIv9u4+Fobn619VAF7CKJygZUiYqUhw9QVxmLosFs/jFL815/q5 3nDrI51SjJVE5mIAhzunx2YLJbjOZgyGHkfqnn3lT8i9VqRE4hoxFqRAoHPtqFckxxFq lu9+cUtZLqM1ZUK39Ceitt5DzmmI0aKeIXaRLEKi0V4CDyUpuxgbBsMS8Z2VSBACGDy0 Qhx1CBqDfRWpfp3eG4G+iGlOPlp9csEc0XMJtPoHENWGRHdwWll6Wl6/GsSjD7mcvbcu vRfA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NRnkXG37; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::234 Subject: [Qemu-devel] [RISU PATCH v4 05/22] risu: add zlib indication to help text X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is a simple aide-memoir as it can be tricky to determine this with a simple statically compiled binary. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- risu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/risu.c b/risu.c index 616fc33..c684c90 100644 --- a/risu.c +++ b/risu.c @@ -39,6 +39,9 @@ size_t signal_count; #ifdef HAVE_ZLIB #include gzFile gz_trace_file; +#define TRACE_TYPE "compressed" +#else +#define TRACE_TYPE "uncompressed" #endif sigjmp_buf jmpbuf; @@ -273,7 +276,7 @@ void usage(void) fprintf(stderr, "between master and apprentice risu processes.\n\n"); fprintf(stderr, "Options:\n"); fprintf(stderr, " --master Be the master (server)\n"); - fprintf(stderr, " -t, --trace=FILE Record/playback trace file\n"); + fprintf(stderr, " -t, --trace=FILE Record/playback " TRACE_TYPE " trace file\n"); fprintf(stderr, " -h, --host=HOST Specify master host machine (apprentice only)" "\n"); From patchwork Fri Jun 22 14:11:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 139657 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp934539lji; Fri, 22 Jun 2018 07:22:56 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfbCX42g2vePL1V3cjvDszZwPbIvsxm4h/Cmekk4EPvUWZn2j6EHGt3NkRT7SZJTxHz2tjg X-Received: by 2002:a0c:a063:: with SMTP id b90-v6mr1570168qva.115.1529677376125; Fri, 22 Jun 2018 07:22:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529677376; cv=none; d=google.com; s=arc-20160816; b=HgHAM90chrU7ApVEjCDkqSLby36Z1q0bRgkvnPQxF4O2NLYJYpMqZ8D2QsoQnSaZKT IXUOIkOFMbpfDKwRgRLFqzEARm2uGuI2KO1OGjV4lXUEDTE1VZcCdlPkoC5sVAsMt1oc P03ofJp4DB0CI6nfUG3B6oIOh4a8mLKhbKf3tTm54hjDPKSfwEYSg8cCEKlZ/wRHabg/ b4ngOBi7MDbABP/L0LwdX0tfInFv5lTXY5al0tUBS0gSECv/fZ8N3nMFIUBlIKfKdbum 62nOgIeqhgVyca6Rd1GCN441Jkt2PsGgJS+uDf08tbyw8ipL/axSjMvbnjLchIuQ9y98 Yhvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=S5aeXl2jMTNr7C2+coNwoFnZk8CSHuSU2dRVO3ZEBAo=; b=rSwlpwc0kDJRiPjLN2juGYfTYLn9O0b5PvhKcTFOZVgEVJRB6QkgOg+qne6TEEztp7 +bwouQsstcTBFzJBfmf5eCLMWZVrkYUXFgH5Iz3D4qJw/HNpQ2hs1OlEssqlRbyVDPHj tBR66YeNbvF1YwZfoZ0R6YS/jQqi9Up+OkQ4W0WtbD6W6q5yMdgPoJVzAKSg1KSKyCZm 42n/c4KqXY3nj2Z1C7isHmfZBVy9PXXO7PgAuHwR/3AyQ5l3WAKvPC9YKCpdB1an847j ZDPk/Wyc2X91VNc1EFJ4JBCKE3h2SzmyPFrpZMiB7LDCU3Oo6XEQ9nHyOWLUkHE52Ns8 5T+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RnD+7w+i; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id a9-v6si6085624qvh.29.2018.06.22.07.22.55 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 22 Jun 2018 07:22:56 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=RnD+7w+i; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34346 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWMxj-0006b5-BW for patch@linaro.org; Fri, 22 Jun 2018 10:22:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38514) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWMnO-000661-D9 for qemu-devel@nongnu.org; Fri, 22 Jun 2018 10:12:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fWMnN-00068a-6a for qemu-devel@nongnu.org; Fri, 22 Jun 2018 10:12:14 -0400 Received: from mail-wr0-x242.google.com ([2a00:1450:400c:c0c::242]:33027) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fWMnM-00067R-QM for qemu-devel@nongnu.org; Fri, 22 Jun 2018 10:12:13 -0400 Received: by mail-wr0-x242.google.com with SMTP id k16-v6so6883507wro.0 for ; Fri, 22 Jun 2018 07:12:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S5aeXl2jMTNr7C2+coNwoFnZk8CSHuSU2dRVO3ZEBAo=; b=RnD+7w+iKFNsJVKX6Vzm58YxaOMzNDiau6qWuCf4aMOmTOT9a0T6wF7PWJTdtzq1yw G5B9VxoFGKzE+1kOLd36DxQQY8WSz1BUWe0B1KqJN5If3eVoMJwUt11Xv0Y221FkoG1/ 1pWBWajSYnJeo8C93xacSFfL98HkGwtZWY79I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S5aeXl2jMTNr7C2+coNwoFnZk8CSHuSU2dRVO3ZEBAo=; b=bUtmriaEqAGkl1NGYy421R/ke9MdArm87NAsa0XudVoKO4E+KP/P1h1rCSVzJibhQL cw8xHrvKw68/nLHhSK0DoaU3ZCy0iJF4nAQcarZtIFp9ir3FLv/8LFjc/jcnv1hiUMrL 7t7ZJ2G0iAdOjvXhETu6FdrMhIfHt0yQgx+m7qWOsn6h+ux9nzqtTO0uuTakEVtWJTwE pDpxKACkhj8xusYhvNFhoVeATSdTPMwWIj07LPNxX/RSNIlBNnsya3+hFAdttspwZh2B qs2mYZfd0JHN+BtjQ8Ihy+aU3F4lp4qU3O2CKuFSyRU8hF+6GIBJfdwkxZBoIrb6lWma FyBA== X-Gm-Message-State: APt69E2CtV8swNHrGhJsPVoIG3BTe6Ij/D/Vh8Zh/4phP6elkUK+8n9f 7g+TS7bVorZ4XHdr/VhOu4TCmw== X-Received: by 2002:adf:f40a:: with SMTP id g10-v6mr1762229wro.256.1529676731879; Fri, 22 Jun 2018 07:12:11 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id b186-v6sm2028443wmh.4.2018.06.22.07.12.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Jun 2018 07:12:08 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 9CDB03E0930; Fri, 22 Jun 2018 15:12:05 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: peter.maydell@linaro.org Date: Fri, 22 Jun 2018 15:11:49 +0100 Message-Id: <20180622141205.16306-7-alex.bennee@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180622141205.16306-1-alex.bennee@linaro.org> References: <20180622141205.16306-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [RISU PATCH v4 06/22] Makefile: include risu_reginfo_$(ARCH) in HDRS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Otherwise changes to reginfo don't cause the whole thing to be re-built causing much confusion when bisecting. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 diff --git a/Makefile b/Makefile index 16e48a0..4aad448 100644 --- a/Makefile +++ b/Makefile @@ -21,7 +21,7 @@ ALL_CFLAGS = -Wall -D_GNU_SOURCE -DARCH=$(ARCH) $(BUILD_INC) $(CFLAGS) $(EXTRA_C PROG=risu SRCS=risu.c comms.c reginfo.c risu_$(ARCH).c risu_reginfo_$(ARCH).c -HDRS=risu.h +HDRS=risu.h risu_reginfo_$(ARCH).h BINS=test_$(ARCH).bin # For dumping test patterns From patchwork Fri Jun 22 14:11:50 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 139667 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp948435lji; Fri, 22 Jun 2018 07:35:16 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKTd4pNcPvtF9jx0uH8+zI1o04QBGaf1yj5pXNNV4b0RORKPGe1SiRgIwq5ILooa7NtqFJY X-Received: by 2002:aed:3108:: with SMTP id 8-v6mr1593922qtg.107.1529678116213; Fri, 22 Jun 2018 07:35:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529678116; cv=none; d=google.com; s=arc-20160816; b=vdj3Lz+VeXdvoee2wCUfamtmydXYVunXqRKHNQKuY4sLNfSapSFYnsi1g+2I9Ogvf7 2aYH9eQjU05n9TYqpMS6+fR0KkkU256acURm/4xMXlYt8SPoiSqzgeDQRUrShNdWVTnr Whzk3wCPd5L/pW1uJIW1l9tl1pWL/CYnMOXJws11YIb5Euoclizqi72NG41iuYfml2A9 qEyiFd1F5RkyQ4hUA0+9zIRsEerO0iSKih6tPc13QgHpe3pjfjT31AUWpUPema7ioh7n u2XbH9waIJ6I0Z1HrCkqDdQ1GZaZGckGh2n4zTckOVd7uuZfiirDHZsqeXiohvoKENa7 oK6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=IEGZXFnFNMOWMxKC/DUaSek0uOvs3FGzAO/YFETY3Ak=; b=J3IfDhIOd3x8y2E2gXT9rrNpFt5sFot119TzxqUrKClH3cSbjwKgyQMLNcD9euzP6B UO/98v+RoWsKL2S0ucAJsdKx4QALououXbUyTMzxyuiInR/TRzMIgyWkuD/IjA+1n0lC P8ulquxoHwdK5asSrXq6LG13AwMWIBoH/0Sb9ZfmSZwfD7XX5s9lVFxEZvkp82KAvLS3 ufHas+2pHK45W7VD8F0gmWzKJZScx5kQw+JHDeKZ4ZysGGYXf/uCZrqMumyItq75Dipn rSb58APWJGapGIAjDitsXsGk2sCj6SNmyd4izwHcjaVaAFuI80YG6s8EXitQxxw3zHFN MOvA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HlGabiBE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::241 Subject: [Qemu-devel] [RISU PATCH v4 07/22] risugen: add --sve support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is similar to the approach used by the FP/simd data in so far as we generate a block of random data and then load into it. The loading is actually done by the current vector length but that is implicit in the run anyway. Signed-off-by: Alex Bennée --- v2 - only one SIMD/FP/SVE block as they alias - move efficient loading as suggested by Dave --- risugen | 3 +++ risugen_arm.pm | 56 ++++++++++++++++++++++++++++++++++++++++++-------- 2 files changed, 50 insertions(+), 9 deletions(-) -- 2.17.1 Reviewed-by: Richard Henderson diff --git a/risugen b/risugen index 488d804..de3f5ea 100755 --- a/risugen +++ b/risugen @@ -319,6 +319,7 @@ sub main() my $condprob = 0; my $fpscr = 0; my $fp_enabled = 1; + my $sve_enabled = 1; my $big_endian = 0; my ($infile, $outfile); @@ -336,6 +337,7 @@ sub main() }, "be" => sub { $big_endian = 1; }, "no-fp" => sub { $fp_enabled = 0; }, + "sve" => sub { $sve_enabled = 1; }, ) or return 1; # allow "--pattern re,re" and "--pattern re --pattern re" @pattern_re = split(/,/,join(',',@pattern_re)); @@ -363,6 +365,7 @@ sub main() 'fpscr' => $fpscr, 'numinsns' => $numinsns, 'fp_enabled' => $fp_enabled, + 'sve_enabled' => $sve_enabled, 'outfile' => $outfile, 'details' => \%insn_details, 'keys' => \@insn_keys, diff --git a/risugen_arm.pm b/risugen_arm.pm index 2f10d58..bb3ee90 100644 --- a/risugen_arm.pm +++ b/risugen_arm.pm @@ -472,14 +472,51 @@ sub write_random_aarch64_fpdata() } } -sub write_random_aarch64_regdata($) +sub write_random_aarch64_svedata() { - my ($fp_enabled) = @_; + # Load SVE registers + my $align = 16; + my $vq = 16; # quadwords per vector + my $datalen = (32 * $vq * 16) + $align; + + write_pc_adr(0, (3 * 4) + ($align - 1)); # insn 1 + write_align_reg(0, $align); # insn 2 + write_jump_fwd($datalen); # insn 3 + + # align safety + for (my $i = 0; $i < ($align / 4); $i++) { + # align with nops + insn32(0xd503201f); + }; + + for (my $rt = 0; $rt <= 31; $rt++) { + for (my $q = 0; $q < $vq; $q++) { + write_random_fpreg_var(4); # quad + } + } + + # Reset all the predicate registers to all true + for (my $p = 0; $p < 16; $p++) { + insn32(0x2518e3e0 | $p); + } + + for (my $rt = 0; $rt <= 31; $rt++) { + # ldr z$rt, [x0, #$rt, mul vl] + insn32(0x85804000 + $rt + (($rt & 7) << 10) + (($rt & 0x18) << 13)); + } +} + +sub write_random_aarch64_regdata($$) +{ + my ($fp_enabled, $sve_enabled) = @_; # clear flags insn32(0xd51b421f); # msr nzcv, xzr - if ($fp_enabled) { - # load floating point / SIMD registers + # Load floating point / SIMD registers + # (one or the other as they overlap) + if ($sve_enabled) { + write_random_aarch64_svedata(); + } elsif ($fp_enabled) { write_random_aarch64_fpdata(); } @@ -490,12 +527,12 @@ sub write_random_aarch64_regdata($) } } -sub write_random_register_data($) +sub write_random_register_data($$) { - my ($fp_enabled) = @_; + my ($fp_enabled, $sve_enabled) = @_; if ($is_aarch64) { - write_random_aarch64_regdata($fp_enabled); + write_random_aarch64_regdata($fp_enabled, $sve_enabled); } else { write_random_arm_regdata($fp_enabled); } @@ -893,6 +930,7 @@ sub write_test_code($$$$$$$$) my $fpscr = $params->{ 'fpscr' }; my $numinsns = $params->{ 'numinsns' }; my $fp_enabled = $params->{ 'fp_enabled' }; + my $sve_enabled = $params->{ 'sve_enabled' }; my $outfile = $params->{ 'outfile' }; my %insn_details = %{ $params->{ 'details' } }; @@ -918,7 +956,7 @@ sub write_test_code($$$$$$$$) write_memblock_setup(); } # memblock setup doesn't clean its registers, so this must come afterwards. - write_random_register_data($fp_enabled); + write_random_register_data($fp_enabled, $sve_enabled); write_switch_to_test_mode(); for my $i (1..$numinsns) { @@ -930,7 +968,7 @@ sub write_test_code($$$$$$$$) # Rewrite the registers periodically. This avoids the tendency # for the VFP registers to decay to NaNs and zeroes. if ($periodic_reg_random && ($i % 100) == 0) { - write_random_register_data($fp_enabled); + write_random_register_data($fp_enabled, $sve_enabled); write_switch_to_test_mode(); } progress_update($i); From patchwork Fri Jun 22 14:11:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 139658 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp935220lji; Fri, 22 Jun 2018 07:23:31 -0700 (PDT) X-Google-Smtp-Source: ADUXVKIpGXF0wt+iq/e4dE5OMeEyV4RDSbjesj5x64tLaHTXYJmMlsm/Nvkac/hcSTmF/wMBNi// X-Received: by 2002:ac8:3318:: with SMTP id t24-v6mr1583224qta.119.1529677411281; Fri, 22 Jun 2018 07:23:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529677411; cv=none; d=google.com; s=arc-20160816; b=K72JGlYrClM981CPEZvOUulhXGipXaA6mYYjZBLvc/EpKSiAhPxpFQLdstHCaYJSoB 1etFcBhw43rKyQUiP5mx7AaUafS4azDNMHXR4BsDRA8LSUOaqQoFniXBZWy9bhbdP1Ft ZVG0nSth88zKqx+W2/P+/NzPAICTilwNC204BI/5hQ221W/thkZLjVMutDhNMaUfvULr EakUnLrISLfM+ESllfwq4jkjCg/7B7VjQT+hq/NJ0fWlPTkH7nJcELf5EEC8bgkUBpeb BYNnnktRiccDy8QR9AjizAZ8uCAFxOeEqrCLejZp04SI8Bl9YRnGTB864f3uB5O/7Phc oFUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=0Xm+ER24biXy+jhU0foOUmeppdyuMIuvTildhLQkYKo=; b=hymXHCN+g+i7nBg5vGsZj7aHtISgMnEyCDr22WJo3T9GF4wwBUEF8ZPC5GANtDcI6p iOYJpttQJJLYw89LV1+9OlMXOIpJ4WklukN8jhql0gwWecPqVjnp68s7Nc9tLb0TIjVc HGonphX1zxX1deLZnTjABguIu+fpxL2TbQzEfPCH9p3Wxw3RqxrrSPOJyJYRBNPjT0SY JiMz+eQZ7ecRpQA2HZeO4R3C0vE5wfe3QkiuMwYmCUUEeVcPfK13EmMp4WPUgwNHIIMZ E6ZffMcJ3zl//4eNrDTL6L9jY3v4KLVrh6yIL+XW0Vhsc7dwH0B0P7IQnENC1ECzcd4Y brKQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="FoE/K8YW"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::243 Subject: [Qemu-devel] [RISU PATCH v4 08/22] risugen: Initialize sve predicates with random data X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Using ptrue makes most of the uses of predicates trivial. Therefore, initialize them to something interesting. Signed-off-by: Richard Henderson Signed-off-by: Alex Bennée --- risugen_arm.pm | 48 ++++++++++++++++++++++++++++++++++-------------- 1 file changed, 34 insertions(+), 14 deletions(-) -- 2.17.1 diff --git a/risugen_arm.pm b/risugen_arm.pm index bb3ee90..83e521d 100644 --- a/risugen_arm.pm +++ b/risugen_arm.pm @@ -174,6 +174,24 @@ sub write_sxt32($$) insn32(0x93407c00 | $rn << 5 | $rd); } +sub write_add_rri($$$) +{ + my ($rd, $rn, $i) = @_; + my $sh; + + die "write_add_rri: invalid operation for this arch.\n" if (!$is_aarch64); + + if ($i >= 0 && $i < 0x1000) { + $sh = 0; + } elsif (($i & 0xfff) || $i >= 0x1000000) { + die "invalid immediate for this arch,\n"; + } else { + $sh = 1; + $i >>= 12; + } + insn32(0x91000000 | ($rd << 0) | ($rn << 5) | ($i << 10) | ($sh << 22)); +} + sub write_sub_rrr($$$) { my ($rd, $rn, $rm) = @_; @@ -477,33 +495,35 @@ sub write_random_aarch64_svedata() # Load SVE registers my $align = 16; my $vq = 16; # quadwords per vector - my $datalen = (32 * $vq * 16) + $align; - - write_pc_adr(0, (3 * 4) + ($align - 1)); # insn 1 - write_align_reg(0, $align); # insn 2 - write_jump_fwd($datalen); # insn 3 + my $veclen = 32 * $vq * 16; + my $predlen = 16 * $vq * 2; + my $datalen = $veclen + $predlen; - # align safety - for (my $i = 0; $i < ($align / 4); $i++) { - # align with nops - insn32(0xd503201f); - }; + write_pc_adr(0, 2 * 4); # insn 1 + write_jump_fwd($datalen); # insn 2 for (my $rt = 0; $rt <= 31; $rt++) { for (my $q = 0; $q < $vq; $q++) { write_random_fpreg_var(4); # quad } } - - # Reset all the predicate registers to all true - for (my $p = 0; $p < 16; $p++) { - insn32(0x2518e3e0 | $p); + for (my $rt = 0; $rt <= 15; $rt++) { + for (my $q = 0; $q < $vq; $q++) { + insn16(rand(0xffff)); + } } for (my $rt = 0; $rt <= 31; $rt++) { # ldr z$rt, [x0, #$rt, mul vl] insn32(0x85804000 + $rt + (($rt & 7) << 10) + (($rt & 0x18) << 13)); } + + write_add_rri(0, 0, $veclen); + + for (my $rt = 0; $rt <= 15; $rt++) { + # ldr p$rt, [x0, #$pt, mul vl] + insn32(0x85800000 + $rt + (($rt & 7) << 10) + (($rt & 0x18) << 13)); + } } sub write_random_aarch64_regdata($$) From patchwork Fri Jun 22 14:11:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 139668 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp952324lji; Fri, 22 Jun 2018 07:38:49 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdBjhYC7OxWpWLL9+SybxAt4ec5p2tugzkm1W0Ji379DREzQCXIarXbkslQzBHo+xoY7LEz X-Received: by 2002:a0c:aac7:: with SMTP id g7-v6mr1620822qvb.76.1529678329169; Fri, 22 Jun 2018 07:38:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529678329; cv=none; d=google.com; s=arc-20160816; b=ppU5UE5Y6RcEyaw6pzD5UlrwMpuksWLHzQTPHUVY+bXWeOdacWhnSFWCY616U8QgD8 DNC+h4g05gh7f6ddMt/+ApTLHwzrVFPIPVcU8nkIXf6yuzEWNcY7wfucgsEJKyFmi6OR op9wMQrN07PQdp+FL6WZLf1zK34z6MQ3svXAfmQcf/cyWwcScq4xF66J0/mydZmzNdfC 6xM+mdwrWe8bkenqyg5OR36I62DlbONQpI749s+l9nh5VPXDUSR/9Jo8jaiJ1ku71gph 1rF/7cJCcq8aJddvgLp2nydwwaBib3SojmiwyKKupgteFi3RLAqpsYYa6otjg10S0Y+p 3OFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=yGIXH0KQMm00dKEL2Etwd2IPZwUNEDVV+bNKLpa67ZE=; b=zCr2DjxO+c2wuNauaefa5WfOcgZz7cFSP5Hk/njmjgqtIlxIGoZYwZvLSaqQ9f/z4+ uO0u2xaAlcyzTD1FZ/SrmDwCscaA8O9+HWiO1Y7RuclW7a8FGEX3M1psishCM3wc/sJF V6cgZSxeECfutGApqK4RYawKuJ1smGC1xPY/jiVrlfiIIUhX7rumEbwBNajE5cC2k/dH fMHgaj9MdC3UkN/U7srh+ZlVUyQGuFBnF2gKpuIRk7etsSSNiuXLINMk6ZLwmEcp1eSM Ks/QNLKDxG2kfAKh5qjGPSCzR5sZMqPWZ9gg5r6NdVAFHG7V18DSbsKIFJgJJeCodAwo bQWA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Hw5dNkVJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::234 Subject: [Qemu-devel] [RISU PATCH v4 09/22] risugen: use fewer insns for aarch64 immediate load X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Alex Bennée --- risugen_arm.pm | 32 +++++++++++++++++++------------- 1 file changed, 19 insertions(+), 13 deletions(-) -- 2.17.1 Signed-off-by: Richard Henderson diff --git a/risugen_arm.pm b/risugen_arm.pm index 83e521d..485e94e 100644 --- a/risugen_arm.pm +++ b/risugen_arm.pm @@ -261,15 +261,13 @@ sub write_mov_rr($$) sub write_mov_ri16($$$) { - # Write 16 bits of immediate to register, using either MOVW or MOVT + # Write 16 bits of immediate to register. my ($rd, $imm, $is_movt) = @_; - die "write_mov_ri16: immediate $imm out of range\n" if (($imm & 0xffff0000) != 0); - if ($is_aarch64) { - # Use MOVZ 0x52800000. is_movt means MOVK of high bits */ - insn32(0xd2800000 | ($is_movt << 29) | ($is_movt ? 16 << 17 : 0) | ($imm << 5) | $rd); + die "write_mov_ri16: invalid operation for this arch.\n" if ($is_aarch64); + die "write_mov_ri16: immediate $imm out of range\n" if (($imm & 0xffff0000) != 0); - } elsif ($is_thumb) { + if ($is_thumb) { # enc T3 my ($imm4, $i, $imm3, $imm8) = (($imm & 0xf000) >> 12, ($imm & 0x0800) >> 11, @@ -287,16 +285,24 @@ sub write_mov_ri16($$$) sub write_mov_ri($$) { - # We always use a MOVW/MOVT pair, for simplicity. - # on aarch64, we use a MOVZ/MOVK pair. my ($rd, $imm) = @_; - write_mov_ri16($rd, ($imm & 0xffff), 0); my $highhalf = ($imm >> 16) & 0xffff; - write_mov_ri16($rd, $highhalf, 1) if $highhalf; - if ($is_aarch64 && $imm < 0) { - # sign extend to allow small negative imm constants - write_sxt32($rd, $rd); + if ($is_aarch64) { + if ($imm < 0) { + # MOVN + insn32(0x92800000 | ((~$imm & 0xffff) << 5) | $rd); + # MOVK, LSL 16 + insn32(0xf2a00000 | ($highhalf << 5) | $rd) if $highhalf != 0xffff; + } else { + # MOVZ + insn32(0x52800000 | (($imm & 0xffff) << 5) | $rd); + # MOVK, LSL 16 + insn32(0xf2a00000 | ($highhalf << 5) | $rd) if $highhalf != 0; + } + } else { + write_mov_ri16($rd, ($imm & 0xffff), 0); + write_mov_ri16($rd, $highhalf, 1) if $highhalf; } } From patchwork Fri Jun 22 14:11:53 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 139669 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp952913lji; Fri, 22 Jun 2018 07:39:21 -0700 (PDT) X-Google-Smtp-Source: AAOMgpcl8mTs9jV3ilUReYZAauv1mVWw+2zQdFbAHzJ3pdquvxOCjnHDVuXjO55Mz4LLkrq4IROA X-Received: by 2002:a0c:874c:: with SMTP id 12-v6mr1633954qvi.223.1529678361411; Fri, 22 Jun 2018 07:39:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529678361; cv=none; d=google.com; s=arc-20160816; b=kMqiVCjb64QxbP8VCJ1XJeClHSbWALnWlQpFN0QenfJHE5bzkdI7v+IxuzcOPc32MW D/WnQVo7mmAJg2HtwgBL+QMl0kqWMIM9Rkkmh/IiqC0PKdJmOkydrTBTRdp9KCil8atW bIxgouehl4OCXKklmG0O+gRPma5jSn+dSQh0CpToNHq4qnsRDXoMz4G9QIMW6lZ3X0Pn uqWeNIqKfhEqEZaHWrWJY/Ha5WIh/Lm6oFnQx0OJQyLrmJ5FPYRSI+M7Md002JmGKAJl +GHrT5n+Hd8E09DA3OLX0BpghQP4WA3ayLidn7TwjMtOadW227odRL9WuojCu0vdHFpr ylNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=eUY/neGXdk4S8JqLBaT3aKaFiB1DXFXQWHVnmZJwCZM=; b=Xs+6qZUhOkYR3EvvMPRLgx2svjrE85GUHGwJAZDPTidNW2Ovpw7wr0SkdI461tZ/GR QRtzI4/vwh4B1QG+fJty/1VwgycpoyytTuo9FM96iiV/IHC+A2x6xm4wzDmsg6YkE059 eiqiot2DKj5JtG881PFInOzrozkzW1hUhfrizPnG22lIQ2/nCVkcLduDfQKhqru8L7lf 2w4P7AH1lI8x8RR/Gd97WKNtcqgMb70UA60kmc/GzvhmU2qmq0jTI0hu+rfpn7nLdHU3 /ampJcxeCxwEg2KpiQmFRbkr7dCo9QvTrTTPtuANVRlaQEcledkWohfSbD5KNYBucKxa LGcg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=a5EEgyVc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::243 Subject: [Qemu-devel] [RISU PATCH v4 10/22] risugen: add reg_plus_imm_pl and reg_plus_imm_vl address helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Alex Bennée --- risugen_arm.pm | 126 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 126 insertions(+) -- 2.17.1 Signed-off-by: Richard Henderson diff --git a/risugen_arm.pm b/risugen_arm.pm index 485e94e..696bf5f 100644 --- a/risugen_arm.pm +++ b/risugen_arm.pm @@ -306,6 +306,52 @@ sub write_mov_ri($$) } } +sub write_addpl_rri($$$) +{ + my ($rd, $rn, $imm) = @_; + die "write_addpl: invalid operation for this arch.\n" if (!$is_aarch64); + + insn32(0x04605000 | ($rn << 16) | (($imm & 0x3f) << 5) | $rd); +} + +sub write_addvl_rri($$$) +{ + my ($rd, $rn, $imm) = @_; + die "write_addvl: invalid operation for this arch.\n" if (!$is_aarch64); + + insn32(0x04205000 | ($rn << 16) | (($imm & 0x3f) << 5) | $rd); +} + +sub write_rdvl_ri($$) +{ + my ($rd, $imm) = @_; + die "write_rdvl: invalid operation for this arch.\n" if (!$is_aarch64); + + insn32(0x04bf5000 | (($imm & 0x3f) << 5) | $rd); +} + +sub write_madd_rrrr($$$$) +{ + my ($rd, $rn, $rm, $ra) = @_; + die "write_madd: invalid operation for this arch.\n" if (!$is_aarch64); + + insn32(0x9b000000 | ($rm << 16) | ($ra << 10) | ($rn << 5) | $rd); +} + +sub write_msub_rrrr($$$$) +{ + my ($rd, $rn, $rm, $ra) = @_; + die "write_msub: invalid operation for this arch.\n" if (!$is_aarch64); + + insn32(0x9b008000 | ($rm << 16) | ($ra << 10) | ($rn << 5) | $rd); +} + +sub write_mul_rrr($$$) +{ + my ($rd, $rn, $rm) = @_; + write_madd_rrrr($rd, $rn, $rm, 31); +} + # write random fp value of passed precision (1=single, 2=double, 4=quad) sub write_random_fpreg_var($) { @@ -767,6 +813,86 @@ sub reg_plus_imm($$@) return $base; } +sub reg_plus_imm_pl($$@) +{ + # Handle reg + immediate addressing mode + my ($base, $imm, @trashed) = @_; + if ($imm == 0) { + return reg($base, @trashed); + } + write_get_offset(); + + # Now r0 is the address we want to do the access to, + # so set the basereg by doing the inverse of the + # addressing mode calculation, ie base = r0 - imm + # + # Note that addpl has a 6-bit immediate, but ldr has a 9-bit + # immediate, so we need to be able to support larger immediates. + + if (-$imm >= -32 && -$imm <= 31) { + write_addpl_rri($base, 0, -$imm); + } else { + # We borrow r1 and r2 as a temporaries (not a problem + # as long as we don't leave anything in a register + # which depends on the location of the memory block) + write_mov_ri(1, 0); + write_mov_ri(2, $imm); + write_addpl_rri(1, 1, 1); + write_msub_rrrr($base, 1, 2, 0); + } + if (grep $_ == $base, @trashed) { + return -1; + } + return $base; +} + +sub reg_plus_imm_vl($$@) +{ + # The usual address formulation is + # elements = VL DIV esize + # mbytes = msize DIV 8 + # addr = base + imm * elements * mbytes + # Here we compute + # scale = log2(esize / msize) + # base + (imm * VL) >> scale + my ($base, $imm, $scale, @trashed) = @_; + if ($imm == 0) { + return reg($base, @trashed); + } + write_get_offset(); + + # Now r0 is the address we want to do the access to, + # so set the basereg by doing the inverse of the + # addressing mode calculation, ie base = r0 - imm + # + # Note that rdvl/addvl have a 6-bit immediate, but ldr has a 9-bit + # immediate, so we need to be able to support larger immediates. + + use integer; + my $mul = 1 << $scale; + my $imm_div = $imm / $mul; + + if ($imm == $imm_div * $mul && -$imm_div >= -32 && -$imm_div <= 31) { + write_addvl_rri($base, 0, -$imm_div); + } elsif ($imm >= -32 && $imm <= 31) { + write_rdvl_ri(1, $imm); + write_sub_rrrs($base, 0, 1, $SHIFT_ASR, $scale); + } else { + write_rdvl_ri(1, 1); + write_mov_ri(2, $imm); + if ($scale == 0) { + write_msub_rrrr($base, 1, 2, 0); + } else { + write_mul_rrr(1, 1, 2); + write_sub_rrrs($base, 0, 1, $SHIFT_ASR, $scale); + } + } + if (grep $_ == $base, @trashed) { + return -1; + } + return $base; +} + sub reg_minus_imm($$@) { my ($base, $imm, @trashed) = @_; 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X-Received-From: 2a00:1450:400c:c0c::241 Subject: [Qemu-devel] [RISU PATCH v4 11/22] risugen: add dtype_msz address helper X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson Signed-off-by: Alex Bennée --- risugen_arm.pm | 9 +++++++++ 1 file changed, 9 insertions(+) -- 2.17.1 diff --git a/risugen_arm.pm b/risugen_arm.pm index 696bf5f..8d423b1 100644 --- a/risugen_arm.pm +++ b/risugen_arm.pm @@ -765,6 +765,15 @@ sub write_get_offset() write_risuop($OP_GETMEMBLOCK); } +# Return the log2 of the memory size of an operation described by dtype. +sub dtype_msz($) +{ + my ($dtype) = @_; + my $dth = $dtype >> 2; + my $dtl = $dtype & 3; + return $dtl >= $dth ? $dth : 3 - $dth; +} + sub reg($@) { my ($base, @trashed) = @_; From patchwork Fri Jun 22 14:11:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 139661 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp941826lji; Fri, 22 Jun 2018 07:29:53 -0700 (PDT) X-Google-Smtp-Source: ADUXVKIvr0k8v6N0WevsINSNkuo34j4S2cEaB8GahED2XvB5m6mF4Lp1RGUy8TnfgDrFvHz2Xc54 X-Received: by 2002:a37:a8d6:: with SMTP id r205-v6mr1454669qke.93.1529677793243; Fri, 22 Jun 2018 07:29:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529677793; cv=none; d=google.com; s=arc-20160816; b=abJ0gACj9NGM5w+S+RTnMkvmHCjY7uXB1Df+kKqrouhjRokl1MLO2TPhSkXnMRyPC+ v29FjmJBvINqu98ZF8vj3OGPB8rMVr4ru1YlEsdxDtBx2NdWxa0dz+GPJQR80gvCSPYB X/gp+dY1aC9TXEC6nanpDrNhTPhkeePhWzcuDWNd0yq8VVKLeYUGAH4lYWzUstXoyujf 9nmFZmrLrmCmUGW5s937TeMy5zWzJMOUQU95p7AWl8JLCdYut2QeKmaX8z0dIYPa6UW1 UDrY1iNKAnobcLQ6I6m9ZpvyioykhiQfUi09qbJCTEpuw0mH0FCmS65uOvHfOlQ2v6kO 7UBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=/IZQ4p0hwe86+xUxCaKvDsHzWjVNlBH8FOK7w9lXmkc=; b=sr/uoEdfEva9mTyMqkFJ6Z8Vhkyw0W2eyrNcYfVtyd8mleHiCxEsURUxcpJLkDfYmz j/nhrV6UGreRGRd9zxVo5wLHk6CmoV1Tjpt90XCfWeAewMO+6JKhSs04nZ73OkNR/Q9D t2Jk2AVjB++mdo0bmXjfPneliQIn0qsnXhdJdbytFPvYN55JzLtT0R+l1douwLOJO4Rh 6WNlJn8sLf2ytVwK1bfR+TJQR4FKP273gA1/e5g70rL/eglk/CtQ+DBOoSux5ceuYwSe 9ketrf7Tat7QAuqd39NW0FsArXgv5v56up9b/fufk8s+/+06Nwf774EuX1t5R3NudsMk BT3g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ETWW926s; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id 37-v6si975735qtp.243.2018.06.22.07.29.53 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 22 Jun 2018 07:29:53 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ETWW926s; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34400 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWN4S-00047L-Bw for patch@linaro.org; Fri, 22 Jun 2018 10:29:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41833) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWMwz-0005wq-1q for qemu-devel@nongnu.org; Fri, 22 Jun 2018 10:22:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fWMwx-0003Yw-KY for qemu-devel@nongnu.org; Fri, 22 Jun 2018 10:22:08 -0400 Received: from mail-wr0-x231.google.com ([2a00:1450:400c:c0c::231]:41380) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fWMwx-0003YA-Bm for qemu-devel@nongnu.org; Fri, 22 Jun 2018 10:22:07 -0400 Received: by mail-wr0-x231.google.com with SMTP id h10-v6so6879736wrq.8 for ; Fri, 22 Jun 2018 07:22:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/IZQ4p0hwe86+xUxCaKvDsHzWjVNlBH8FOK7w9lXmkc=; b=ETWW926sgH+LggAQPT6aZOEhatpg84ZlkpAkIPq1l02LA88nKf+BlOT/Tq0kqA/p7M 94MKjiYaSikHCjcm1IFqYLO94xoh52Lh8y8V/BMM4PxOH0/4WatekuCZ6n7Mf9JEP1MH pavNR8plhT/AauZNhiYwQeQvh9YJZwIWqYFbE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/IZQ4p0hwe86+xUxCaKvDsHzWjVNlBH8FOK7w9lXmkc=; b=maU4EaE8lPWk/UnpK6AZJvM3EIqJKoZsWI4O9zqQxT2pf2hL+ljYjwr0ltf5Fp3A7E OoH3aQ7OImdMU9hyqnnbEihvWsfcVpM+XXKPcHQz0pRZCzUgQgRxLtSSCeFJHc1792xC VmY8aRtVnvrJoXiUJGi8JxbGCdog+JBb184XQVz7EgsxJtPfnjRU2CxOl0ma+S5hKI1R YntjqELYIFrW9YF6qv5RPQqhlZBHb7t3UqE5v7p7UeFJkmFD2RTPo29PTkcEmrAF44nv 0lOXJEFoaYDPsPyZfsLj81WjReyiq7NavOQ1bjcSHg9Rs85SGK88ngw6N4NSFtOPoqbj 5Z2w== X-Gm-Message-State: APt69E22Z8dddetGXHbBW1dkX4CeWIeptNs9+HCgOvtmuFkaf0VPwVAh 4KClxgMQpiPY3z6n/062oeK4iQ== X-Received: by 2002:adf:8142:: with SMTP id 60-v6mr1760989wrm.192.1529677326190; Fri, 22 Jun 2018 07:22:06 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id j131-v6sm3906967wmg.24.2018.06.22.07.22.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Jun 2018 07:22:04 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id E32A23E0B71; Fri, 22 Jun 2018 15:12:05 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: peter.maydell@linaro.org Date: Fri, 22 Jun 2018 15:11:55 +0100 Message-Id: <20180622141205.16306-13-alex.bennee@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180622141205.16306-1-alex.bennee@linaro.org> References: <20180622141205.16306-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::231 Subject: [Qemu-devel] [RISU PATCH v4 12/22] contrib/generate_all.sh: allow passing of arguments to risugen X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This allows us to use any new risugen options when generating all our test patterns. Signed-off-by: Alex Bennée --- contrib/generate_all.sh | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) -- 2.17.1 Reviewed-by: Richard Henderson diff --git a/contrib/generate_all.sh b/contrib/generate_all.sh index 1e6b847..651cb23 100755 --- a/contrib/generate_all.sh +++ b/contrib/generate_all.sh @@ -12,11 +12,11 @@ # Alex Bennée - initial implementation # # Usage: -# ./contrib/generate_all.sh +# ./contrib/generate_all.sh -- risugen args set -e -USAGE="Usage: `basename $0` [-h] [-n x] " +USAGE="Usage: `basename $0` [-h] [-n x] -- [risugen args]" SPLIT=4 RISUGEN=$(CDPATH= cd -- "$(dirname -- "$0")/.." && pwd -P)/risugen @@ -41,18 +41,24 @@ done # Remove the switches we parsed above. shift `expr $OPTIND - 1` -while [ $# -ne 0 ]; do +# Parse up to and including any -- +RISUGEN_ARGS="" +while [ $# -ne 0 ] && [ -z "$RISUGEN_ARGS" ]; do if [ -f $1 ]; then RISU_FILE=$1; elif [ -d $1 ]; then TARGET_DIR=$1; + elif [ "$1" = "--" ]; then + RISUGEN_ARGS=$1 elif [ ! -e $1 ]; then TARGET_DIR=$1 fi shift done +# anything left is for RISUGEN +RISUGEN_ARGS=$@ if test -z "${RISUGEN}" || test ! -x "${RISUGEN}"; then echo "Couldn't find risugen (${RISUGEN})" @@ -90,7 +96,7 @@ while test $# -gt 0 ; do fi done I_FILE="${I_FILE}_INC.risu.bin" - CMD="${RISUGEN} ${INSN_PATTERNS} ${RISU_FILE} ${I_FILE}" + CMD="${RISUGEN} ${RISUGEN_ARGS} ${INSN_PATTERNS} ${RISU_FILE} ${I_FILE}" echo "Running: $CMD" $CMD done From patchwork Fri Jun 22 14:11:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 139680 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp971959lji; Fri, 22 Jun 2018 07:57:51 -0700 (PDT) X-Google-Smtp-Source: AAOMgpf93oz7LPkPkbGCGc8qjZnFtDyCTeaoZr1oF3OZBFXNws1L3CLR5OlnHkEiReTBKLUH3qJE X-Received: by 2002:ae9:c10d:: with SMTP id z13-v6mr1569240qki.359.1529679471832; Fri, 22 Jun 2018 07:57:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529679471; cv=none; d=google.com; s=arc-20160816; b=vptGRpgsVOZdEcN5tEaNaJH7KhvBNHSQfLqpUKJZtCExw5SZazDJ9dkvNl7o3UBz/B WytxLlF2Of+Xw+buem1/nTUEch5pNpzUOal1ZLE89lOvExUlO2n3JKANuGLJ/2sc6y3b 3hXNr/PUsJIM8lru/6a6ubOfHivvDdMvSsFvobtFtziKRmflIZkpE2cyXDnCLPbUrLqm WUj5+iOqdZUe4t/ZZBF/9pD2pA0QY5Cv6DeJ4P2P3rk+QR2Kwkv2kXwOj6N/Se6x+xbV OQZ8DB3lWCuIbDEsGAv0mOUZgakCqnw3C5lH5Sc70B0UDD0a1lctEHICuteFxIWOqot4 SwQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=BN9TlWSjJtBY5uzotv2E0/KhskH7jcna9d7GkYd5aiA=; b=CQ6EY2wOHmZsZxUsSCrt988Bstv1cjHAl608ogKOlEmYeuJvy/5mFqeCe8Uc26RsTv ohId78D4ckkUt9wok6crQTI7Gcqe1oOFhCUn/zOZNQg1RdkJafywqjvjnbJQP2XiOc5y P+aERQWXQDfnTCGsC4vEdwlR6PGORJpTC9gYFnueJfsZsHmcvcqxF7Y3vCywydYbFi2x 27c1hcRGFFTHVA5HJ4lvkk1puHpSyqHfCMtLj2dZ7TejqX36PHBaoPvw1ZViRo9cGCSZ sF5GBR+PSnK3eCW+JLW1RWfml/BChrmqRMLpFa7LSsvXLbjAsbqQfna8HQ/KI/bSNrwj B89g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cONDAWzf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id m82-v6si3232080qki.213.2018.06.22.07.57.51 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 22 Jun 2018 07:57:51 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cONDAWzf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:34591 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWNVX-00019v-98 for patch@linaro.org; Fri, 22 Jun 2018 10:57:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41873) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fWMx0-0005yO-0t for qemu-devel@nongnu.org; Fri, 22 Jun 2018 10:22:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fWMwy-0003Zx-O6 for qemu-devel@nongnu.org; Fri, 22 Jun 2018 10:22:09 -0400 Received: from mail-wm0-x235.google.com ([2a00:1450:400c:c09::235]:35869) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fWMwy-0003ZG-DJ for qemu-devel@nongnu.org; Fri, 22 Jun 2018 10:22:08 -0400 Received: by mail-wm0-x235.google.com with SMTP id v131-v6so2837145wma.1 for ; Fri, 22 Jun 2018 07:22:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BN9TlWSjJtBY5uzotv2E0/KhskH7jcna9d7GkYd5aiA=; b=cONDAWzfmgxXivtwzSEUVMsYGwP/afnN9Z92kmAHCX9mw7UsJ1Z29UEz38BHIUQF5G 76LwD821rGHANB7FT/FVoXh34nJ3hfWEolN0Jo04tY0UJpzlvmLE2nW/8cJ9KJ70a5lQ /q8wtX1M8wmU6l2OHjmKCAnt9QkAeRmIaspCI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BN9TlWSjJtBY5uzotv2E0/KhskH7jcna9d7GkYd5aiA=; b=k9a/vpsyTZ5abV1Mzi6W1QnMQHjsZzHf5EBPY+jh9fGA4HGavTAHWUqyMSqHabBAAE hq2wKt2yAORgZkOzwvWhrXur37RnjMkuHNcwYN7J8j4AK93c4VTrDweUs0v8ukOl/pS4 JJ3lWSwJuzINFe9kzvZlrbcy8zUHszUt022oKMARkjwPln5QRKN0V6UAVs9XJ0AI8GCy jcmZ/HFbSshp3xrgTd8sYRLFg5ZndrBtYkXVvJOr8LAv5mO3KhcnoaA29UhC2t1Ll1E6 yirvBHyIhHA1bbTVRqB6gMLlnZ8gIknVVXEiDzR56DK3rLOJYxRSq/iw2Zom52s+4bS5 z8Pw== X-Gm-Message-State: APt69E26n5+MRUDedCuJa/Y29j5AiPvN/BAbBy73J904tf+cq3Dh/DKf 9JXyItMyC4KXwuF6aAJqJ3gaEw== X-Received: by 2002:a1c:b6c3:: with SMTP id g186-v6mr1857305wmf.40.1529677327304; Fri, 22 Jun 2018 07:22:07 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id h11-v6sm7378200wrs.85.2018.06.22.07.22.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 22 Jun 2018 07:22:04 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id EFD243E0BB0; Fri, 22 Jun 2018 15:12:05 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: peter.maydell@linaro.org Date: Fri, 22 Jun 2018 15:11:56 +0100 Message-Id: <20180622141205.16306-14-alex.bennee@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180622141205.16306-1-alex.bennee@linaro.org> References: <20180622141205.16306-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::235 Subject: [Qemu-devel] [RISU PATCH v4 13/22] risu: move optional args to each architecture X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The key variables here are: *arch_long_opts and *arch_extra_help. If they are not NULL then we concatenate the extra options to appropriate structure to enable the support. Adding architecture short options is not supported. This also includes moving the ARM specific test_fp_exc/test-fp-exc into ARM specific code. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- v2 - better concatenation of default and extra opts --- risu.c | 29 +++++++++++++++++++++++++---- risu.h | 6 ++++-- risu_reginfo_aarch64.c | 3 +++ risu_reginfo_arm.c | 11 +++++++++++ risu_reginfo_m68k.c | 3 +++ risu_reginfo_ppc64.c | 3 +++ 6 files changed, 49 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/risu.c b/risu.c index c684c90..18de351 100644 --- a/risu.c +++ b/risu.c @@ -46,8 +46,7 @@ gzFile gz_trace_file; sigjmp_buf jmpbuf; -/* Should we test for FP exception status bits? */ -int test_fp_exc; +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) /* Master functions */ @@ -283,6 +282,9 @@ void usage(void) fprintf(stderr, " -p, --port=PORT Specify the port to connect to/listen on " "(default 9191)\n"); + if (arch_extra_help) { + fprintf(stderr, "%s", arch_extra_help); + } } struct option * setup_options(char **short_opts) @@ -293,12 +295,31 @@ struct option * setup_options(char **short_opts) {"host", required_argument, 0, 'h'}, {"port", required_argument, 0, 'p'}, {"trace", required_argument, 0, 't'}, - {"test-fp-exc", no_argument, &test_fp_exc, 1}, {0, 0, 0, 0} }; + struct option *lopts = &default_longopts[0]; *short_opts = "h:p:t:"; - return default_longopts; + + if (arch_long_opts) { + const size_t osize = sizeof(struct option); + const int default_count = ARRAY_SIZE(default_longopts); + struct option *dptr; + int extra_count = 0; + + /* count additional opts */ + dptr = arch_long_opts; + do {} while (dptr[extra_count++].name); + + lopts = calloc(default_count + extra_count, osize); + + /* Copy default opts + extra opts */ + memcpy(lopts, default_longopts, default_count * osize); + dptr = &lopts[default_count - 1]; + memcpy(dptr, arch_long_opts, extra_count * osize); + } + + return lopts; } int main(int argc, char **argv) diff --git a/risu.h b/risu.h index 1c8ecee..89811f4 100644 --- a/risu.h +++ b/risu.h @@ -17,6 +17,10 @@ #include #include +/* Extra option processing for architectures */ +extern void *arch_long_opts; +extern char *arch_extra_help; + /* GCC computed include to pull in the correct risu_reginfo_*.h for * the architecture. */ @@ -36,8 +40,6 @@ void send_response_byte(int sock, int resp); extern uintptr_t image_start_address; extern void *memblock; -extern int test_fp_exc; - /* Ops code under test can request from risu: */ #define OP_COMPARE 0 #define OP_TESTEND 1 diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c index 3bb4339..ab12270 100644 --- a/risu_reginfo_aarch64.c +++ b/risu_reginfo_aarch64.c @@ -18,6 +18,9 @@ #include "risu.h" #include "risu_reginfo_aarch64.h" +void *arch_long_opts; +char *arch_extra_help; + /* reginfo_init: initialize with a ucontext */ void reginfo_init(struct reginfo *ri, ucontext_t *uc) { diff --git a/risu_reginfo_arm.c b/risu_reginfo_arm.c index 6b9ee7b..5acad02 100644 --- a/risu_reginfo_arm.c +++ b/risu_reginfo_arm.c @@ -13,12 +13,23 @@ #include #include #include +#include #include "risu.h" #include "risu_reginfo_arm.h" extern int insnsize(ucontext_t *uc); +/* Should we test for FP exception status bits? */ +static int test_fp_exc; +static struct option extra_opts[] = { + {"test-fp-exc", no_argument, &test_fp_exc, 1}, + {0, 0, 0, 0} +}; + +void *arch_long_opts = &extra_opts[0]; +char *arch_extra_help = " --test-fp-exc Check FP exception bits when comparing\n"; + static void reginfo_init_vfp(struct reginfo *ri, ucontext_t *uc) { /* Read VFP registers. These live in uc->uc_regspace, which is diff --git a/risu_reginfo_m68k.c b/risu_reginfo_m68k.c index 4ff0aa8..d429502 100644 --- a/risu_reginfo_m68k.c +++ b/risu_reginfo_m68k.c @@ -14,6 +14,9 @@ #include "risu.h" #include "risu_reginfo_m68k.h" +void *arch_long_opts; +char *arch_extra_help; + /* reginfo_init: initialize with a ucontext */ void reginfo_init(struct reginfo *ri, ucontext_t *uc) { diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c index 5f33648..395111c 100644 --- a/risu_reginfo_ppc64.c +++ b/risu_reginfo_ppc64.c @@ -22,6 +22,9 @@ #define XER 37 #define CCR 38 +void *arch_long_opts; +char *arch_extra_help; + /* reginfo_init: initialize with a ucontext */ void reginfo_init(struct reginfo *ri, ucontext_t *uc) { From patchwork Fri Jun 22 14:11:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 139666 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp947644lji; Fri, 22 Jun 2018 07:34:37 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLXslXWTq4jBHDyxCGmNIcW1V+P9mIZMGRJsLBDDXfneOPdIxkVRyQ5s0Ek7j3nKQtKZjVS X-Received: by 2002:ac8:411b:: with SMTP id q27-v6mr1628270qtl.50.1529678077239; Fri, 22 Jun 2018 07:34:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529678077; cv=none; d=google.com; s=arc-20160816; b=vuzo50WEXxm0zwN+vcmSubsia/gfAvovxHk/OZJhTa764WFthouLs5TAy1idoyUVtf dIL2PsFUXDbvbxrJko+i26/jtivqgeP8FFOP2TOSlyO+exYzsN02F40i5muuJeX1VYxu ZiMyFPHZedQ194eYY2aA7JY36/ZvikJdEOV47dYTepz/jajj1gBiVt482kn/SAPgvc7i oPS4L8OgvuVxWzYNYI8Aefs7lwDOP9r6o2N3wi7Sd4YE2dKk+udjdjYODTW3zGzBDS81 lLQOp2uwWTHioks0IQbJ80hR2myshv2E0We36dqXAQU39lVO5+sY3jsY7/6i7SpmooLy tawQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Bp/1YbPML67ffji3kuZga7TLev+DhxX9wc1+8T4FSYo=; b=Zyws1HGSqNJoiLt2HLK1gHVuDkQBb/rknE8kO/47SmoXVo2vEj0Lz8FPliKh5zpzHu g39Kbe9pVWXS4Vh1gvYGWq43ZyeIc7kpEcQ83G+6Sd5O0kUUmpnH2fV5eJ8eapmGqR46 zoTNH9H9lmsC0YKKXJak2PgVGXynmg5lOC3QDlRGxlBUByCQVi2FCsgPqx6NdF/lqZUo oetEdJG4kdj2Awg438inNXSeLKqznT0JsbBOaqSYhcj2xFZVlkZRQcCFFxIm6UJsx4/X ZDil4KB7eXydlKX0zm7JGNeKpRjMk/tKJdWlpbSe1OYAcNQkvvJpComJGK1+Tl801e1E 5gQw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="EMRdXx3/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::229 Subject: [Qemu-devel] [RISU PATCH v4 14/22] risu: add process_arch_opt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Allows the backend to do more that just set a flag when it comes to processing options. Signed-off-by: Richard Henderson [AJB: tweaked order, added stdlib includes] Signed-off-by: Alex Bennée --- risu.c | 33 +++++++++++---------------------- risu.h | 7 +++++-- risu_reginfo_aarch64.c | 10 ++++++++-- risu_reginfo_arm.c | 14 ++++++++++---- risu_reginfo_m68k.c | 10 ++++++++-- risu_reginfo_ppc64.c | 10 ++++++++-- 6 files changed, 50 insertions(+), 34 deletions(-) -- 2.17.1 diff --git a/risu.c b/risu.c index 18de351..01525d2 100644 --- a/risu.c +++ b/risu.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include @@ -27,7 +26,6 @@ #include #include "config.h" - #include "risu.h" void *memblock; @@ -287,7 +285,7 @@ void usage(void) } } -struct option * setup_options(char **short_opts) +static struct option * setup_options(char **short_opts) { static struct option default_longopts[] = { {"help", no_argument, 0, '?'}, @@ -303,20 +301,19 @@ struct option * setup_options(char **short_opts) if (arch_long_opts) { const size_t osize = sizeof(struct option); - const int default_count = ARRAY_SIZE(default_longopts); - struct option *dptr; - int extra_count = 0; + const int default_count = ARRAY_SIZE(default_longopts) - 1; + int arch_count; /* count additional opts */ - dptr = arch_long_opts; - do {} while (dptr[extra_count++].name); + for (arch_count = 0; arch_long_opts[arch_count].name; arch_count++) { + continue; + } - lopts = calloc(default_count + extra_count, osize); + lopts = calloc(default_count + arch_count + 1, osize); /* Copy default opts + extra opts */ memcpy(lopts, default_longopts, default_count * osize); - dptr = &lopts[default_count - 1]; - memcpy(dptr, arch_long_opts, extra_count * osize); + memcpy(lopts + default_count, arch_long_opts, arch_count * osize); } return lopts; @@ -343,34 +340,26 @@ int main(int argc, char **argv) switch (c) { case 0: - { /* flag set by getopt_long, do nothing */ break; - } case 't': - { trace_fn = optarg; trace = 1; break; - } case 'h': - { hostname = optarg; break; - } case 'p': - { /* FIXME err handling */ port = strtol(optarg, 0, 10); break; - } case '?': - { usage(); exit(1); - } default: - abort(); + assert(c >= FIRST_ARCH_OPT); + process_arch_opt(c, optarg); + break; } } diff --git a/risu.h b/risu.h index 89811f4..48c50d9 100644 --- a/risu.h +++ b/risu.h @@ -16,10 +16,13 @@ #include #include #include +#include /* Extra option processing for architectures */ -extern void *arch_long_opts; -extern char *arch_extra_help; +extern const struct option * const arch_long_opts; +extern const char * const arch_extra_help; +void process_arch_opt(int opt, const char *arg); +#define FIRST_ARCH_OPT 0x100 /* GCC computed include to pull in the correct risu_reginfo_*.h for * the architecture. diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c index ab12270..c270e0b 100644 --- a/risu_reginfo_aarch64.c +++ b/risu_reginfo_aarch64.c @@ -14,12 +14,18 @@ #include #include #include /* for FPSIMD_MAGIC */ +#include #include "risu.h" #include "risu_reginfo_aarch64.h" -void *arch_long_opts; -char *arch_extra_help; +const struct option * const arch_long_opts; +const char * const arch_extra_help; + +void process_arch_opt(int opt, const char *arg) +{ + abort(); +} /* reginfo_init: initialize with a ucontext */ void reginfo_init(struct reginfo *ri, ucontext_t *uc) diff --git a/risu_reginfo_arm.c b/risu_reginfo_arm.c index 5acad02..12ad0ef 100644 --- a/risu_reginfo_arm.c +++ b/risu_reginfo_arm.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include "risu.h" #include "risu_reginfo_arm.h" @@ -22,13 +22,19 @@ extern int insnsize(ucontext_t *uc); /* Should we test for FP exception status bits? */ static int test_fp_exc; -static struct option extra_opts[] = { +static const struct option extra_opts[] = { {"test-fp-exc", no_argument, &test_fp_exc, 1}, {0, 0, 0, 0} }; -void *arch_long_opts = &extra_opts[0]; -char *arch_extra_help = " --test-fp-exc Check FP exception bits when comparing\n"; +const struct option * const arch_long_opts = &extra_opts[0]; +const char * const arch_extra_help = + " --test-fp-exc Check FP exception bits when comparing\n"; + +void process_arch_opt(int opt, const char *arg) +{ + abort(); +} static void reginfo_init_vfp(struct reginfo *ri, ucontext_t *uc) { diff --git a/risu_reginfo_m68k.c b/risu_reginfo_m68k.c index d429502..7a1c5a9 100644 --- a/risu_reginfo_m68k.c +++ b/risu_reginfo_m68k.c @@ -10,12 +10,18 @@ #include #include #include +#include #include "risu.h" #include "risu_reginfo_m68k.h" -void *arch_long_opts; -char *arch_extra_help; +const struct option * const arch_long_opts; +const char * const arch_extra_help; + +void process_arch_opt(int opt, const char *arg) +{ + abort(); +} /* reginfo_init: initialize with a ucontext */ void reginfo_init(struct reginfo *ri, ucontext_t *uc) diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c index 395111c..4b70460 100644 --- a/risu_reginfo_ppc64.c +++ b/risu_reginfo_ppc64.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "risu.h" #include "risu_reginfo_ppc64.h" @@ -22,8 +23,13 @@ #define XER 37 #define CCR 38 -void *arch_long_opts; -char *arch_extra_help; +const struct option * const arch_long_opts; +const char * const arch_extra_help; + +void process_arch_opt(int opt, const char *arg) +{ + abort(); +} /* reginfo_init: initialize with a ucontext */ void reginfo_init(struct reginfo *ri, ucontext_t *uc) From patchwork Fri Jun 22 14:11:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 139673 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp963176lji; Fri, 22 Jun 2018 07:49:05 -0700 (PDT) X-Google-Smtp-Source: AAOMgpcz/NRa0O3xIaCw2f0pEGr+80BZo5eVk8OWmJJ2dNIbG9lCtuSPlsRUgQvJGzeng4hrWgDP X-Received: by 2002:a37:d683:: with SMTP id p3-v6mr1609064qkl.424.1529678945537; Fri, 22 Jun 2018 07:49:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529678945; cv=none; d=google.com; s=arc-20160816; b=V6XuHkj/tbpLJ0L80gkNfgfi6hwgt34ZpmwhpBOHnLwGbiQHAYdXmjQ9G4FA7EZ8TB j6S9tgRoB4q2Ykzxhi1R2EDFchidZDlMa+5BMp/BdhRGTSLDkNxV0I/Mh0Q8vs5XTJZY NKuk/VyS1FVIGGwmVxeBOj61JbVisNqqcveuNRCfjrKdyCkAfs5DjwjYXM0HcGIMaZj2 Xwd4lsY+fWlMXc3RZgqOvJYIZX6wQcGyJHjR8hhiGUsF3pm2sFLUGxPNbyn/6zPSSiWJ BzP1ZhiliTbtdesleLPIylJgW5UuXzWb8AUAFMnsYRDSO7Q6Iyc6HVmkHyO5tqlI2oDs wguw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=dBu+OmTs5lE40td1sq/PqPuyJsgcm3Rk9W/zTmauolc=; b=yXcZKxurA35D2VRY2VT5f9AaQQx7+bpwkXLF1K9Kr7ldP2rzum9Hg4QXvElvFTrJpT 0jaJ6ZUx/UXkNCxkgaSQnc7LKUFMfJsPsmNslIOrP5d7eqdOvOkLgBWTbi3R/P41/L1T 8RDYNpocwOYr2BVFo5Eef1UVDqUgKnR6DUcTjO9aFGhjz/qE229x6awIxBvxgeQhPuNX 3cg99zjS+76l2q2cc2KM5L0jeVOs648JqLbpock/Vaiu6Hd9XQ95Ki4tUujfC6X/brlg hzPtu2uOFa8QEuZszjS3dRPC/roJ7mCw8Howo87CF5RiejVRyzLypQ5Iko5/NN26nOYQ PyrQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ZYd0IYVf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::230 Subject: [Qemu-devel] [RISU PATCH v4 15/22] risu_reginfo_aarch64: drop stray ; X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- risu_reginfo_aarch64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c index c270e0b..34dd9af 100644 --- a/risu_reginfo_aarch64.c +++ b/risu_reginfo_aarch64.c @@ -66,7 +66,7 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc) for (i = 0; i < 32; i++) { ri->vregs[i] = fp->vregs[i]; } -}; +} /* reginfo_is_eq: compare the reginfo structs, returns nonzero if equal */ int reginfo_is_eq(struct reginfo *r1, struct reginfo *r2) From patchwork Fri Jun 22 14:11:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 139664 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp943695lji; Fri, 22 Jun 2018 07:31:21 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKcNN0ryPbcEkWrcOH6Ec3vWqesjmE3QMSdi/fvfswLn3iFuH59N28qDP/m/7pvAWxKCHBd X-Received: by 2002:aed:39ea:: with SMTP id m97-v6mr1522474qte.231.1529677881136; Fri, 22 Jun 2018 07:31:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529677881; cv=none; d=google.com; s=arc-20160816; b=QknXlEck6XOMnQBHUlcamSGxhrYhuA+tK3OwcAcoWGThwdvXwqFzXgX/hqLKR4An9g e12cX8OTvCodAtnekkqDtTSQlrzAcFmeQQahW+Le8xGGNT498+YMEY8c8+SFGXocNSak 8nSqqEUHs5p1RuA5rarOGmqkY44bxG5raIJxSJbx/WFbMmrsvKEV7EiQsAzWY2t2NCfJ +FJQedeJUC39ZJXiEFg136C6pBmDCFi5ZOZM1LvZGYHR+0xJDSPentPKhQV2OV3ZL+CK 9RZ440WUtE0uyqeU7j/pq927xBuWZ2NmP0ZZqfzbCw3T1jEYFpzhVgELlE/Pw7Pug3NE n+ZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=nY1mbDPdhT4h3XIsfZuzlnsw3ol/c3Sp62EFruoWlqg=; b=WxnQlgaHead0YPOF7kAWYjIJLG3lXda8cPaJwuTk9TeGPh7LjlC5KvUvKMXBDe87zV nNDV47VZ8sT/TYoSIh5E/Tu6dNrqfzGBJzmQsrPldrtl52A41nUajKPkc/iuXd4BtxP/ r2BIhv93OZkqjelXmAARr/yDPyzW2ICc+A3PgYDAAoDJKMX/UrrAGtw837+F1CbFEvUl +KvRvSuuc8UpD25W+Bx4mepKAgKHOl7EKoaF6rRyR6wl4HTDSb7iIJBuHZIevLfoJ4nX cA9I9qKCk9pk/LJbRik6Z3gD6x7pwWe83bRLyf0FyrglVskHsVnqfynI1mfM1zvnvoG+ f4PQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MsX9fvHz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::22c Subject: [Qemu-devel] [RISU PATCH v4 16/22] risu_reginfo_aarch64: unionify VFP regs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is preparation for the SVE work as we won't want to be carrying around both VFP and SVE registers at the same time as they overlap. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- risu_reginfo_aarch64.c | 16 ++++++++-------- risu_reginfo_aarch64.h | 9 ++++++++- 2 files changed, 16 insertions(+), 9 deletions(-) -- 2.17.1 diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c index 34dd9af..62a5599 100644 --- a/risu_reginfo_aarch64.c +++ b/risu_reginfo_aarch64.c @@ -64,7 +64,7 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc) ri->fpcr = fp->fpcr; for (i = 0; i < 32; i++) { - ri->vregs[i] = fp->vregs[i]; + ri->simd.vregs[i] = fp->vregs[i]; } } @@ -92,8 +92,8 @@ int reginfo_dump(struct reginfo *ri, FILE * f) for (i = 0; i < 32; i++) { fprintf(f, " V%2d : %016" PRIx64 "%016" PRIx64 "\n", i, - (uint64_t) (ri->vregs[i] >> 64), - (uint64_t) (ri->vregs[i] & 0xffffffffffffffff)); + (uint64_t) (ri->simd.vregs[i] >> 64), + (uint64_t) (ri->simd.vregs[i] & 0xffffffffffffffff)); } return !ferror(f); @@ -138,14 +138,14 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f) } for (i = 0; i < 32; i++) { - if (m->vregs[i] != a->vregs[i]) { + if (m->simd.vregs[i] != a->simd.vregs[i]) { fprintf(f, " V%2d : " "%016" PRIx64 "%016" PRIx64 " vs " "%016" PRIx64 "%016" PRIx64 "\n", i, - (uint64_t) (m->vregs[i] >> 64), - (uint64_t) (m->vregs[i] & 0xffffffffffffffff), - (uint64_t) (a->vregs[i] >> 64), - (uint64_t) (a->vregs[i] & 0xffffffffffffffff)); + (uint64_t) (m->simd.vregs[i] >> 64), + (uint64_t) (m->simd.vregs[i] & 0xffffffffffffffff), + (uint64_t) (a->simd.vregs[i] >> 64), + (uint64_t) (a->simd.vregs[i] & 0xffffffffffffffff)); } } diff --git a/risu_reginfo_aarch64.h b/risu_reginfo_aarch64.h index a05fb4e..a1c708b 100644 --- a/risu_reginfo_aarch64.h +++ b/risu_reginfo_aarch64.h @@ -13,6 +13,10 @@ #ifndef RISU_REGINFO_AARCH64_H #define RISU_REGINFO_AARCH64_H +struct simd_reginfo { + __uint128_t vregs[32]; +}; + struct reginfo { uint64_t fault_address; uint64_t regs[31]; @@ -24,7 +28,10 @@ struct reginfo { /* FP/SIMD */ uint32_t fpsr; uint32_t fpcr; - __uint128_t vregs[32]; + + union { + struct simd_reginfo simd; + }; }; #endif /* RISU_REGINFO_AARCH64_H */ From patchwork Fri Jun 22 14:12:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 139679 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp968294lji; Fri, 22 Jun 2018 07:54:10 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdnwRwLJ/RKEzju3MSWYOd+PTFKOCX0rk7NrCCSXn/g3NeYYNGY9s6jusYAweRrt3m5zut1 X-Received: by 2002:a0c:f54d:: with SMTP id p13-v6mr1685778qvm.149.1529679250078; Fri, 22 Jun 2018 07:54:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529679250; cv=none; d=google.com; s=arc-20160816; b=mEOtG5OIbABYOaihSvvWHxsK6hSqQSqEQUj1GAYcHxEZyuCivP/jQ101bLswmMa88U sb9tQsXnI0v+tD/uy12QZKcHPHdgyAV0/eyF/ID/UVB8enZh48EKKPCsbn4vVzTCF+8y o0zJk3eQ+TEKx+Dh8/uH9yvin2OkN3qdmaDJkPpsmfp/wvWaMBBIOHSTbtzJfwVhV8k7 NUhYGB5JLaqG996zGWstmHXK8B8Qhj5zqCyIk9TLSdCklD4ZNQx/rQwvMbBTPBe6AFtv 8yHeAn1BvrPMr7EqV/nyJNJ4xoz6aYvGgYcQlMMTNb0iAtdesRUXBMOVQW4bUosfB/5x qFEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=rzwy1wygd0hzu64f2W+6KlSmTAZV7pjBu+NhIXCdKKw=; b=q9uIH+Gtq15/MNpj6Mu1mj8xHZoJ7i54ajAL6a5m2R0oa0h4pnkYRmbpFCmcYC7NTd Aj9/5huVJOSTEJv+2eqESPO6fnqlt3FOFuPucKJdhQmjRHk422HuVOZM7Go2MqiSy4hk NMJkNZP+ztn/GWAm2v8iolCIOQNjwBrfCfPRtpmIYgG2xBBC/yXhblEm3GbMuyID07kn quVh7hxfUSJ3ebZYUOLr6luEHkTi+lU/34j/MQGeSd8hkGr0bkv1JfEcqtD6AERJKaO6 UQOpoAripjrZ31Uq4zoIX3Z52+mKb3NDLEF4aUPKxGOdlyEdtQhl+Ci82w26kKkei87p /jNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=d8NJfP37; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::232 Subject: [Qemu-devel] [RISU PATCH v4 17/22] risu_reginfo: introduce reginfo_size() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In preparation for conditionally supporting SVE we need to be able to have different sized reginfos. This introduces reginfo_size() to abstract the size away to the code the actually knows. For aarch64 we also use this while initialising the block. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- reginfo.c | 6 +++--- risu.h | 3 +++ risu_reginfo_aarch64.c | 11 ++++++++++- risu_reginfo_aarch64.h | 1 + risu_reginfo_arm.c | 5 +++++ risu_reginfo_m68k.c | 5 +++++ risu_reginfo_ppc64.c | 5 +++++ 7 files changed, 32 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/reginfo.c b/reginfo.c index 1f55d06..dd42ae2 100644 --- a/reginfo.c +++ b/reginfo.c @@ -39,7 +39,7 @@ int send_register_info(write_fn write_fn, void *uc) switch (op) { case OP_TESTEND: - write_fn(&ri, sizeof(ri)); + write_fn(&ri, reginfo_size()); /* if we are tracing write_fn will return 0 unlike a remote end, hence we force return of 1 here */ return 1; @@ -58,7 +58,7 @@ int send_register_info(write_fn write_fn, void *uc) /* Do a simple register compare on (a) explicit request * (b) end of test (c) a non-risuop UNDEF */ - return write_fn(&ri, sizeof(ri)); + return write_fn(&ri, reginfo_size()); } return 0; } @@ -101,7 +101,7 @@ int recv_and_compare_register_info(read_fn read_fn, /* Do a simple register compare on (a) explicit request * (b) end of test (c) a non-risuop UNDEF */ - if (read_fn(&apprentice_ri, sizeof(apprentice_ri))) { + if (read_fn(&apprentice_ri, reginfo_size())) { packet_mismatch = 1; resp = 2; } else if (!reginfo_is_eq(&master_ri, &apprentice_ri)) { diff --git a/risu.h b/risu.h index 48c50d9..8d2d646 100644 --- a/risu.h +++ b/risu.h @@ -133,4 +133,7 @@ int reginfo_dump(struct reginfo *ri, FILE * f); /* reginfo_dump_mismatch: print mismatch details to a stream, ret nonzero=ok */ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f); +/* return size of reginfo */ +const int reginfo_size(void); + #endif /* RISU_H */ diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c index 62a5599..5da9e39 100644 --- a/risu_reginfo_aarch64.c +++ b/risu_reginfo_aarch64.c @@ -15,6 +15,8 @@ #include #include /* for FPSIMD_MAGIC */ #include +#include +#include #include "risu.h" #include "risu_reginfo_aarch64.h" @@ -27,6 +29,13 @@ void process_arch_opt(int opt, const char *arg) abort(); } +const int reginfo_size(void) +{ + const int size = offsetof(struct reginfo, simd.end); + assert(sizeof(struct reginfo)==size); + return size; +} + /* reginfo_init: initialize with a ucontext */ void reginfo_init(struct reginfo *ri, ucontext_t *uc) { @@ -71,7 +80,7 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc) /* reginfo_is_eq: compare the reginfo structs, returns nonzero if equal */ int reginfo_is_eq(struct reginfo *r1, struct reginfo *r2) { - return memcmp(r1, r2, sizeof(*r1)) == 0; + return memcmp(r1, r2, reginfo_size()) == 0; } /* reginfo_dump: print state to a stream, returns nonzero on success */ diff --git a/risu_reginfo_aarch64.h b/risu_reginfo_aarch64.h index a1c708b..ef97622 100644 --- a/risu_reginfo_aarch64.h +++ b/risu_reginfo_aarch64.h @@ -15,6 +15,7 @@ struct simd_reginfo { __uint128_t vregs[32]; + char end[0]; }; struct reginfo { diff --git a/risu_reginfo_arm.c b/risu_reginfo_arm.c index 12ad0ef..3662f12 100644 --- a/risu_reginfo_arm.c +++ b/risu_reginfo_arm.c @@ -36,6 +36,11 @@ void process_arch_opt(int opt, const char *arg) abort(); } +const int reginfo_size(void) +{ + return sizeof(struct reginfo); +} + static void reginfo_init_vfp(struct reginfo *ri, ucontext_t *uc) { /* Read VFP registers. These live in uc->uc_regspace, which is diff --git a/risu_reginfo_m68k.c b/risu_reginfo_m68k.c index 7a1c5a9..32b28c8 100644 --- a/risu_reginfo_m68k.c +++ b/risu_reginfo_m68k.c @@ -23,6 +23,11 @@ void process_arch_opt(int opt, const char *arg) abort(); } +const int reginfo_size(void) +{ + return sizeof(struct reginfo); +} + /* reginfo_init: initialize with a ucontext */ void reginfo_init(struct reginfo *ri, ucontext_t *uc) { diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c index 4b70460..f9d2f0d 100644 --- a/risu_reginfo_ppc64.c +++ b/risu_reginfo_ppc64.c @@ -31,6 +31,11 @@ void process_arch_opt(int opt, const char *arg) abort(); } +const int reginfo_size(void) +{ + return sizeof(struct reginfo); +} + /* reginfo_init: initialize with a ucontext */ void reginfo_init(struct reginfo *ri, ucontext_t *uc) { From patchwork Fri Jun 22 14:12:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 139670 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp954001lji; Fri, 22 Jun 2018 07:40:23 -0700 (PDT) X-Google-Smtp-Source: AAOMgpf60puubBqAQlFlOfv4qY3dq5unrkycEimgOo4lT86LdmzQ1YqaKAQuBzRRSk0JKLxa3y3E X-Received: by 2002:a37:3755:: with SMTP id e82-v6mr1604803qka.131.1529678423195; Fri, 22 Jun 2018 07:40:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529678423; cv=none; d=google.com; s=arc-20160816; b=ioNjguAU5OY6BdNofANts//jwvrbx0IRFCLLQA68Brrb06NPq2mKoghMnCKmzYEQuF vPYgtjkE7AZ5QVh+Xi7mRD344Hj4UwqiNn8eaJvwV3gPzo1rc7Ax80JvGDPxL6bTzqgb hLd2MT1v/z2/anNZoujXJb+PeQWZasUktVSvLYsqrH1OVNFoSG5ofy3VqXaO7eWKOL4R ZTHl8CIezQI7AVIlAfgydsdI8/qlgbkKksByhxdIwyIae7MQi41a1v9uiXK2/Ybbv2p1 4K/xnn3T8k5lEAhJRqWHmbGFJh6PU9n6VQDzzSRFYshC/0+umfwPNt8aNnPGibfFBxp3 +N6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=dclRwBk0m7BKfnhe6PaRdYoaCNDPARqLQaSD7Izq0Vk=; b=MIpnw2jj9ocXACCWRovD96EWbZafYgntpp3gcGrP9Da1JrGNJFVOFwNLgyUatQARZ9 xxWIlXGR+PMr2G0dShTpUw1PI69DtF6WDSXGIoSewgStIfFjWbZQ5uN5htETvlhlXwNo XNtMLkjaiWqZAG/xlHYZTYz8F184d7GNA+M0aKJ3ynSQOL1FYJsMYP1D8s6DJJvtHOet HBRUJ/GxG+wmfLzdiD056d2GreVLAa5g8zRrvMikiyfiOEumLeYrE9sON7c6MBUk4vme D2UeDKwf9jQBfaekTtf2v8oVt3lgdHyHnCpg2DuAPFKtI7oqcgracQ5ni17/bol2XX1F 8pUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=cVanLzaq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [RISU PATCH v4 18/22] risu_reginfo_aarch64: left justify regnums and drop masks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Left justification is more pleasing to the eye than the default. We also drop the masking which isn't needed as we are casting to a smaller size anyway. This was split out of Richard's re-factoring work for SVE. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- risu_reginfo_aarch64.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) -- 2.17.1 diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c index 5da9e39..3ccaf0e 100644 --- a/risu_reginfo_aarch64.c +++ b/risu_reginfo_aarch64.c @@ -90,7 +90,7 @@ int reginfo_dump(struct reginfo *ri, FILE * f) fprintf(f, " faulting insn %08x\n", ri->faulting_insn); for (i = 0; i < 31; i++) { - fprintf(f, " X%2d : %016" PRIx64 "\n", i, ri->regs[i]); + fprintf(f, " X%-2d : %016" PRIx64 "\n", i, ri->regs[i]); } fprintf(f, " sp : %016" PRIx64 "\n", ri->sp); @@ -100,9 +100,9 @@ int reginfo_dump(struct reginfo *ri, FILE * f) fprintf(f, " fpcr : %08x\n", ri->fpcr); for (i = 0; i < 32; i++) { - fprintf(f, " V%2d : %016" PRIx64 "%016" PRIx64 "\n", i, + fprintf(f, " V%-2d : %016" PRIx64 "%016" PRIx64 "\n", i, (uint64_t) (ri->simd.vregs[i] >> 64), - (uint64_t) (ri->simd.vregs[i] & 0xffffffffffffffff)); + (uint64_t) (ri->simd.vregs[i])); } return !ferror(f); @@ -119,7 +119,7 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f) } for (i = 0; i < 31; i++) { if (m->regs[i] != a->regs[i]) { - fprintf(f, " X%2d : %016" PRIx64 " vs %016" PRIx64 "\n", + fprintf(f, " X%-2d : %016" PRIx64 " vs %016" PRIx64 "\n", i, m->regs[i], a->regs[i]); } } @@ -148,13 +148,13 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f) for (i = 0; i < 32; i++) { if (m->simd.vregs[i] != a->simd.vregs[i]) { - fprintf(f, " V%2d : " + fprintf(f, " V%-2d : " "%016" PRIx64 "%016" PRIx64 " vs " "%016" PRIx64 "%016" PRIx64 "\n", i, (uint64_t) (m->simd.vregs[i] >> 64), - (uint64_t) (m->simd.vregs[i] & 0xffffffffffffffff), + (uint64_t) m->simd.vregs[i], (uint64_t) (a->simd.vregs[i] >> 64), - (uint64_t) (a->simd.vregs[i] & 0xffffffffffffffff)); + (uint64_t) a->simd.vregs[i]); } } From patchwork Fri Jun 22 14:12:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 139671 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp957313lji; Fri, 22 Jun 2018 07:43:35 -0700 (PDT) X-Google-Smtp-Source: AAOMgpewvDXQhilgvUJ4UGg6rukdjhxSUpjT/NZnHivLGOfLCHkF6jwuWBqOWWcRawNaAoH1FyxC X-Received: by 2002:a0c:b5e9:: with SMTP id o41-v6mr1591472qvf.189.1529678615341; Fri, 22 Jun 2018 07:43:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529678615; cv=none; d=google.com; s=arc-20160816; b=fk8W2P25LrT42HTRMGYFSks9YxTzGRkXMX9rxkGt3omt83ZPFcmCsw/ZPuTPHuj7K1 96oBuQ/dZjpxjdXghy9+rsVNkSdDWTR2G0fEnZZg9t+LjtZ1hpFmkuM4xEflvHvI7Vq6 05VfQ1/nNs4yflRBntls7cme8iMpkYMhOw22MVHclR+vyBUGdCFcX0K4GKniAiVxo7jw cWTk9kkEofHx14BX7Ao/VKA9sT7nDd/WRCv59kmEADt2RiTSSseeLpZu62cSpiGfOwlH xyv5S18wepXk7D9tarqSp1fP40o4B0IrGlZUqGtlaU5U7CHli2158Pzv3ZYeHnzHQ7Wi zD3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=mWP40Stc1rcVLV+euOPJVniIvKfcUEsxA1LKizFB7t4=; b=VmMyEAWqlj3lEuxlBlDrmVJ2VaJMWubOQnUA5mvXa7tAbdi+19oDdXMTKcnzRLZPHU HZ5oTQ351+gEwQuB3Hl9NzWcHETmab5wc5AiTOiWQgn+73KDIkb8F5yghD9vVKWVLMVj nVcsDCBC6waK2OiiFZZTT7CoULmUbDfjMdBlb6FP2ZIX3eJUcjKdt4qY+4J4fEThYf25 sKs3jbK8fbwS+APNYY/1SHtXyuPN5iK1cBDp4cAg2DtVOuXmQHFsNzOljEwR8VEBU5KB uSRM6RvvszUSY+FogJaSRbineTpSsEkci7TDe4X+gkmdoL2mvT56s0fKiWS2wbKAyDFW 0Alw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=M+0AoNUz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [RISU PATCH v4 19/22] risu_reginfo_aarch64: add support for copying SVE register state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add the ability to save SVE registers from the signal context. This is controlled with an optional flag --test-sve. The whole thing is conditionally compiled when SVE support is in the sigcontext headers. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- v2 - support EXTRA_MAGIC contexts v3 - handle conditional bits - include in reginfo.h - move from helper function to main init function - (void *) cast for memcpy - additional ifdef SVE_MAGIC stuff --- risu_reginfo_aarch64.c | 107 ++++++++++++++++++++++++++++++++++++----- risu_reginfo_aarch64.h | 16 ++++++ 2 files changed, 110 insertions(+), 13 deletions(-) -- 2.17.1 diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c index 3ccaf0e..79db5dd 100644 --- a/risu_reginfo_aarch64.c +++ b/risu_reginfo_aarch64.c @@ -16,13 +16,26 @@ #include /* for FPSIMD_MAGIC */ #include #include -#include +#include #include "risu.h" #include "risu_reginfo_aarch64.h" +#ifndef SVE_MAGIC const struct option * const arch_long_opts; const char * const arch_extra_help; +#else + +/* Should we test SVE register state */ +static int test_sve; +static const struct option extra_opts[] = { + {"test-sve", no_argument, &test_sve, 1}, + {0, 0, 0, 0} +}; + +const struct option * const arch_long_opts = &extra_opts[0]; +const char * const arch_extra_help = " --test-sve Compare SVE registers\n"; +#endif void process_arch_opt(int opt, const char *arg) { @@ -31,8 +44,12 @@ void process_arch_opt(int opt, const char *arg) const int reginfo_size(void) { - const int size = offsetof(struct reginfo, simd.end); - assert(sizeof(struct reginfo)==size); + int size = offsetof(struct reginfo, simd.end); +#ifdef SVE_MAGIC + if (test_sve) { + size = offsetof(struct reginfo, sve.end); + } +#endif return size; } @@ -40,8 +57,12 @@ const int reginfo_size(void) void reginfo_init(struct reginfo *ri, ucontext_t *uc) { int i; - struct _aarch64_ctx *ctx; - struct fpsimd_context *fp; + struct _aarch64_ctx *ctx, *extra = NULL; + struct fpsimd_context *fp = NULL; +#ifdef SVE_MAGIC + struct sve_context *sve = NULL; +#endif + /* necessary to be able to compare with memcmp later */ memset(ri, 0, sizeof(*ri)); @@ -57,21 +78,81 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc) ri->faulting_insn = *((uint32_t *) uc->uc_mcontext.pc); ctx = (struct _aarch64_ctx *) &uc->uc_mcontext.__reserved[0]; - - while (ctx->magic != FPSIMD_MAGIC && ctx->size != 0) { - ctx += (ctx->size + sizeof(*ctx) - 1) / sizeof(*ctx); + while (ctx) { + switch (ctx->magic) { + case FPSIMD_MAGIC: + fp = (void *)ctx; + break; +#ifdef SVE_MAGIC + case SVE_MAGIC: + sve = (void *)ctx; + break; + case EXTRA_MAGIC: + extra = (void *)((struct extra_context *)(ctx))->datap; + break; +#endif + case 0: + /* End of list. */ + ctx = extra; + extra = NULL; + continue; + default: + /* Unknown record -- skip it. */ + break; + } + ctx = (void *)ctx + ctx->size; } - if (ctx->magic != FPSIMD_MAGIC || ctx->size != sizeof(*fp)) { - fprintf(stderr, - "risu_reginfo_aarch64: failed to get FP/SIMD state\n"); + if (!fp || fp->head.size != sizeof(*fp)) { + fprintf(stderr, "risu_reginfo_aarch64: failed to get FP/SIMD state\n"); return; } - - fp = (struct fpsimd_context *) ctx; ri->fpsr = fp->fpsr; ri->fpcr = fp->fpcr; +#ifdef SVE_MAGIC + if (test_sve) { + int vq = sve_vq_from_vl(sve->vl); /* number of quads for whole vl */ + + if (sve == NULL) { + fprintf(stderr, "risu_reginfo_aarch64: failed to get SVE state\n"); + return; + } + + ri->sve.vl = sve->vl; + + if (sve->head.size < SVE_SIG_CONTEXT_SIZE(vq)) { + if (sve->head.size == sizeof(*sve)) { + /* SVE state is empty -- not an error. */ + } else { + fprintf(stderr, "risu_reginfo_aarch64: " + "failed to get complete SVE state\n"); + } + return; + } + + /* Copy ZREG's one at a time */ + for (i = 0; i < SVE_NUM_ZREGS; i++) { + memcpy(&ri->sve.zregs[i], + (void *)sve + SVE_SIG_ZREG_OFFSET(vq, i), + SVE_SIG_ZREG_SIZE(vq)); + } + + /* Copy PREG's one at a time */ + for (i = 0; i < SVE_NUM_PREGS; i++) { + memcpy(&ri->sve.pregs[i], + (void *)sve + SVE_SIG_PREG_OFFSET(vq, i), + SVE_SIG_PREG_SIZE(vq)); + } + + /* Finally the FFR */ + memcpy(&ri->sve.ffr,(void *)sve + SVE_SIG_FFR_OFFSET(vq), + SVE_SIG_FFR_SIZE(vq)); + + return; + } +#endif + for (i = 0; i < 32; i++) { ri->simd.vregs[i] = fp->vregs[i]; } diff --git a/risu_reginfo_aarch64.h b/risu_reginfo_aarch64.h index ef97622..b3701b3 100644 --- a/risu_reginfo_aarch64.h +++ b/risu_reginfo_aarch64.h @@ -13,11 +13,24 @@ #ifndef RISU_REGINFO_AARCH64_H #define RISU_REGINFO_AARCH64_H +#include /* for SVE_MAGIC */ + struct simd_reginfo { __uint128_t vregs[32]; char end[0]; }; +#ifdef SVE_MAGIC +struct sve_reginfo { + /* SVE */ + uint16_t vl; /* current VL */ + __uint128_t zregs[SVE_NUM_ZREGS][SVE_VQ_MAX]; + uint16_t pregs[SVE_NUM_PREGS][SVE_VQ_MAX]; + uint16_t ffr[SVE_VQ_MAX]; + char end[0]; +}; +#endif + struct reginfo { uint64_t fault_address; uint64_t regs[31]; @@ -32,6 +45,9 @@ struct reginfo { union { struct simd_reginfo simd; +#ifdef SVE_MAGIC + struct sve_reginfo sve; +#endif }; }; From patchwork Fri Jun 22 14:12:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 139663 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp942636lji; Fri, 22 Jun 2018 07:30:35 -0700 (PDT) X-Google-Smtp-Source: AAOMgpeKvwIADGFodw6c6e/EqdYqesjc6Ootj3sC5z3KGuF3jN1OUge+6iCTNkpkdpJ9V1OkiHhH X-Received: by 2002:a0c:b34f:: with SMTP id a15-v6mr1626484qvf.116.1529677835428; Fri, 22 Jun 2018 07:30:35 -0700 (PDT) ARC-Seal: i=1; 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X-Received-From: 2a00:1450:400c:c09::236 Subject: [Qemu-devel] [RISU PATCH v4 20/22] risu_reginfo_aarch64: add SVE support to reginfo_dump_mismatch X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We also tweak the justification of the rest of the registers so the : lines up nicely across the register dump and diff dump. Signed-off-by: Alex Bennée --- v2 - include ffr in comparison - mild re-factor of preg cmp/diff v3 - re-factoring v4 - alignment/justification tweaks - merge chunks from the variable VQ patch --- risu_reginfo_aarch64.c | 140 ++++++++++++++++++++++++++++++++++++----- 1 file changed, 124 insertions(+), 16 deletions(-) -- 2.17.1 Reviewed-by: Richard Henderson diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c index 79db5dd..bf98ba1 100644 --- a/risu_reginfo_aarch64.c +++ b/risu_reginfo_aarch64.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "risu.h" #include "risu_reginfo_aarch64.h" @@ -146,12 +147,12 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc) } /* Finally the FFR */ - memcpy(&ri->sve.ffr,(void *)sve + SVE_SIG_FFR_OFFSET(vq), + memcpy(&ri->sve.ffr, (void *)sve + SVE_SIG_FFR_OFFSET(vq), SVE_SIG_FFR_SIZE(vq)); return; } -#endif +#endif /* SVE_MAGIC */ for (i = 0; i < 32; i++) { ri->simd.vregs[i] = fp->vregs[i]; @@ -164,6 +165,52 @@ int reginfo_is_eq(struct reginfo *r1, struct reginfo *r2) return memcmp(r1, r2, reginfo_size()) == 0; } +#ifdef SVE_MAGIC +static int sve_zreg_is_eq(int vq, const void *z1, const void *z2) +{ + return memcmp(z1, z2, vq * 16) == 0; +} + +static int sve_preg_is_eq(int vq, const void *p1, const void *p2) +{ + return memcmp(p1, p2, vq * 2) == 0; +} + +static void sve_dump_preg(FILE *f, int vq, const uint16_t *p) +{ + int q; + for (q = vq - 1; q >= 0; q--) { + fprintf(f, "%04x", p[q]); + } +} + +static void sve_dump_preg_diff(FILE *f, int vq, const uint16_t *p1, + const uint16_t *p2) +{ + sve_dump_preg(f, vq, p1); + fprintf(f, " vs "); + sve_dump_preg(f, vq, p2); + fprintf(f, "\n"); +} + +static void sve_dump_zreg_diff(FILE *f, int vq, const __uint128_t *z1, + const __uint128_t *z2) +{ + const char *pad = ""; + int q; + + for (q = 0; q < vq; ++q) { + if (z1[q] != z2[q]) { + fprintf(f, "%sq%-2d: %016" PRIx64 "%016" PRIx64 + " vs %016" PRIx64 "%016" PRIx64"\n", pad, q, + (uint64_t)(z1[q] >> 64), (uint64_t)z1[q], + (uint64_t)(z2[q] >> 64), (uint64_t)z2[q]); + pad = " "; + } + } +} +#endif + /* reginfo_dump: print state to a stream, returns nonzero on success */ int reginfo_dump(struct reginfo *ri, FILE * f) { @@ -171,17 +218,47 @@ int reginfo_dump(struct reginfo *ri, FILE * f) fprintf(f, " faulting insn %08x\n", ri->faulting_insn); for (i = 0; i < 31; i++) { - fprintf(f, " X%-2d : %016" PRIx64 "\n", i, ri->regs[i]); + fprintf(f, " X%-2d : %016" PRIx64 "\n", i, ri->regs[i]); } - fprintf(f, " sp : %016" PRIx64 "\n", ri->sp); - fprintf(f, " pc : %016" PRIx64 "\n", ri->pc); - fprintf(f, " flags : %08x\n", ri->flags); - fprintf(f, " fpsr : %08x\n", ri->fpsr); - fprintf(f, " fpcr : %08x\n", ri->fpcr); + fprintf(f, " sp : %016" PRIx64 "\n", ri->sp); + fprintf(f, " pc : %016" PRIx64 "\n", ri->pc); + fprintf(f, " flags : %08x\n", ri->flags); + fprintf(f, " fpsr : %08x\n", ri->fpsr); + fprintf(f, " fpcr : %08x\n", ri->fpcr); + +#ifdef SVE_MAGIC + if (test_sve) { + int q, vq = test_sve; + + fprintf(f, " vl : %d\n", ri->sve.vl); + + for (i = 0; i < 32; i++) { + fprintf(f, " Z%-2d q%-2d: %016" PRIx64 "%016" PRIx64 "\n", i, 0, + (uint64_t)(ri->sve.zregs[i][0] >> 64), + (uint64_t)ri->sve.zregs[i][0]); + for (q = 1; q < vq; ++q) { + fprintf(f, " q%-2d: %016" PRIx64 "%016" PRIx64 "\n", q, + (uint64_t)(ri->sve.zregs[i][q] >> 64), + (uint64_t)ri->sve.zregs[i][q]); + } + } + + for (i = 0; i < 16; i++) { + fprintf(f, " P%-2d : ", i); + sve_dump_preg(f, vq, &ri->sve.pregs[i][0]); + fprintf(f, "\n"); + } + fprintf(f, " FFR : "); + sve_dump_preg(f, vq, &ri->sve.ffr[0]); + fprintf(f, "\n"); + + return !ferror(f); + } +#endif for (i = 0; i < 32; i++) { - fprintf(f, " V%-2d : %016" PRIx64 "%016" PRIx64 "\n", i, + fprintf(f, " V%-2d : %016" PRIx64 "%016" PRIx64 "\n", i, (uint64_t) (ri->simd.vregs[i] >> 64), (uint64_t) (ri->simd.vregs[i])); } @@ -200,36 +277,67 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f) } for (i = 0; i < 31; i++) { if (m->regs[i] != a->regs[i]) { - fprintf(f, " X%-2d : %016" PRIx64 " vs %016" PRIx64 "\n", + fprintf(f, " X%-2d : %016" PRIx64 " vs %016" PRIx64 "\n", i, m->regs[i], a->regs[i]); } } if (m->sp != a->sp) { - fprintf(f, " sp : %016" PRIx64 " vs %016" PRIx64 "\n", + fprintf(f, " sp : %016" PRIx64 " vs %016" PRIx64 "\n", m->sp, a->sp); } if (m->pc != a->pc) { - fprintf(f, " pc : %016" PRIx64 " vs %016" PRIx64 "\n", + fprintf(f, " pc : %016" PRIx64 " vs %016" PRIx64 "\n", m->pc, a->pc); } if (m->flags != a->flags) { - fprintf(f, " flags : %08x vs %08x\n", m->flags, a->flags); + fprintf(f, " flags : %08x vs %08x\n", m->flags, a->flags); } if (m->fpsr != a->fpsr) { - fprintf(f, " fpsr : %08x vs %08x\n", m->fpsr, a->fpsr); + fprintf(f, " fpsr : %08x vs %08x\n", m->fpsr, a->fpsr); } if (m->fpcr != a->fpcr) { - fprintf(f, " fpcr : %08x vs %08x\n", m->fpcr, a->fpcr); + fprintf(f, " fpcr : %08x vs %08x\n", m->fpcr, a->fpcr); } +#ifdef SVE_MAGIC + if (test_sve) { + int vq = sve_vq_from_vl(m->sve.vl); + + if (m->sve.vl != a->sve.vl) { + fprintf(f, " vl : %d vs %d\n", m->sve.vl, a->sve.vl); + } + + for (i = 0; i < SVE_NUM_ZREGS; i++) { + if (!sve_zreg_is_eq(vq, &m->sve.zregs[i], &a->sve.zregs[i])) { + fprintf(f, " Z%-2d ", i); + sve_dump_zreg_diff(f, vq, &m->sve.zregs[i][0], + &a->sve.zregs[i][0]); + } + } + for (i = 0; i < SVE_NUM_PREGS; i++) { + if (!sve_preg_is_eq(vq, &m->sve.pregs[i], &a->sve.pregs[i])) { + fprintf(f, " P%-2d : ", i); + sve_dump_preg_diff(f, vq, &m->sve.pregs[i][0], + &a->sve.pregs[i][0]); + } + } + if (!sve_preg_is_eq(vq, &m->sve.ffr, &a->sve.ffr)) { + fprintf(f, " FFR : "); + sve_dump_preg_diff(f, vq, &m->sve.pregs[i][0], &a->sve.pregs[i][0]); + } + + return !ferror(f); + } +#endif + for (i = 0; i < 32; i++) { if (m->simd.vregs[i] != a->simd.vregs[i]) { - fprintf(f, " V%-2d : " + fprintf(f, " V%-2d : " "%016" PRIx64 "%016" PRIx64 " vs " "%016" PRIx64 "%016" PRIx64 "\n", i, (uint64_t) (m->simd.vregs[i] >> 64), From patchwork Fri Jun 22 14:12:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 139678 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp965907lji; Fri, 22 Jun 2018 07:51:44 -0700 (PDT) X-Google-Smtp-Source: ADUXVKLgy/b2E5m2BiyhO6U6PqRkFmyLbi3Ybj/wR+NPYgoM9QNZUJCJaUqg7aSLiTuUhXU+X7F2 X-Received: by 2002:a37:15aa:: with SMTP id 42-v6mr1609960qkv.428.1529679104571; Fri, 22 Jun 2018 07:51:44 -0700 (PDT) ARC-Seal: i=1; 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X-Received-From: 2a00:1450:400c:c0c::242 Subject: [Qemu-devel] [RISU PATCH v4 21/22] risu_reginfo_aarch64: limit SVE_VQ_MAX to current architecture X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson The kernel headers optimistically assume it's going to grow but as we are never going to use that many on current hardware we limit SVE_VQ_MAX to what we will. Signed-off-by: Richard Henderson Signed-off-by: Alex Bennée --- risu_reginfo_aarch64.h | 5 +++++ 1 file changed, 5 insertions(+) -- 2.17.1 diff --git a/risu_reginfo_aarch64.h b/risu_reginfo_aarch64.h index b3701b3..c33b86f 100644 --- a/risu_reginfo_aarch64.h +++ b/risu_reginfo_aarch64.h @@ -31,6 +31,11 @@ struct sve_reginfo { }; #endif +/* The kernel headers set this based on future arch extensions. + The current arch maximum is 16. Save space below. */ +#undef SVE_VQ_MAX +#define SVE_VQ_MAX 16 + struct reginfo { uint64_t fault_address; uint64_t regs[31]; From patchwork Fri Jun 22 14:12:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 139659 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp935572lji; Fri, 22 Jun 2018 07:23:51 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJss4iVP2PjcJkImDLdrabD5uYM5gXG9ZmOTF4TsuUUhn74CKfofXAmYefcy8mnaul/iwPc X-Received: by 2002:ac8:2d42:: with SMTP id o2-v6mr1564098qta.256.1529677431543; Fri, 22 Jun 2018 07:23:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529677431; cv=none; d=google.com; s=arc-20160816; b=oUVhvSar6tBhRnCAvI8syNxXvy5gxFE4XJ57KhBlyhpBmICW/Cq7jBmqslNmRjx611 oFAugos4m93XvWGaQKWCf/3rmUC758wOZZDdAg8TcFTgN1QZ7rXi4IBuSwk505rzOSNQ 9zr3Gjwj3vr06Zthgl23PUReVYK/Ql+ZJdZfR4cYKkMtcUwIBkksPdRud92W+a5roGFV sVWbFUaO9JAhYFfDscNxSdjzHNTBSK8nUWaHKWzihgdf2DL07puqY0E+iJmaWBm3vimV U3AERUVgUBiAfI2Bc7KOKOwbVCjv9QNnPm34Jb6atzCWohlBQwQ33vEhos0r7ivDz2Jl Gr0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=Sz7o6YO/4o6EHCNz75Wz5Zg04LtsPIQBylQwFuuURLo=; b=bHExD9HRds+zLpadaf9KCkbfmpYuwU0TdSZ/QpNcRA05hrHVwwZ7aiJBiY7d8dSEg7 Gl9egvIzpSBSEt7pwze6GZ9Arv1wGulLXuUZoFTQwkN1wf+xLP2FoAVOVa/pLNFJBcrq yEvDNuDpje3wBnyVBYnuZDMR5EhdEztXr3V1O6ge+U8+iEyf6DLesdtntVSrWpXHt8xQ J/1KBoWmLqc/ZujCsLtnRpLF0OamA3017IfNCjen4qf9ixSpwaE/CibfFlnG147eoW9U r1WpbvgX82F8PQO0GafNZ79q/zvijzUO4AFX4cO/732zQgyGpdVHDP6w6kJLYddedlXb Dfaw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NWzxIj86; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:400c:c0c::22a Subject: [Qemu-devel] [RISU PATCH v4 22/22] risu_reginfo_aarch64: handle variable VQ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This involves parsing the command line parameter and calling the kernel to set the VQ limit. We also add dumping of the register state in the main register dump. Signed-off-by: Alex Bennée --- risu_reginfo_aarch64.c | 38 +++++++++++++++++++++++++++++++++++--- 1 file changed, 35 insertions(+), 3 deletions(-) -- 2.17.1 Reviewed-by: Richard Henderson diff --git a/risu_reginfo_aarch64.c b/risu_reginfo_aarch64.c index bf98ba1..00d1c8b 100644 --- a/risu_reginfo_aarch64.c +++ b/risu_reginfo_aarch64.c @@ -18,6 +18,8 @@ #include #include #include +#include +#include #include "risu.h" #include "risu_reginfo_aarch64.h" @@ -30,17 +32,41 @@ const char * const arch_extra_help; /* Should we test SVE register state */ static int test_sve; static const struct option extra_opts[] = { - {"test-sve", no_argument, &test_sve, 1}, + {"test-sve", required_argument, NULL, FIRST_ARCH_OPT }, {0, 0, 0, 0} }; const struct option * const arch_long_opts = &extra_opts[0]; -const char * const arch_extra_help = " --test-sve Compare SVE registers\n"; +const char * const arch_extra_help + = " --test-sve= Compare SVE registers with VQ\n"; #endif void process_arch_opt(int opt, const char *arg) { +#ifdef SVE_MAGIC + long want, got; + + assert(opt == FIRST_ARCH_OPT); + test_sve = strtol(arg, 0, 10); + + if (test_sve <= 0 || test_sve > SVE_VQ_MAX) { + fprintf(stderr, "Invalid value for VQ (1-%d)\n", SVE_VQ_MAX); + exit(1); + } + want = sve_vl_from_vq(test_sve); + got = prctl(PR_SVE_SET_VL, want); + if (want != got) { + if (got < 0) { + perror("prctl PR_SVE_SET_VL"); + } else { + fprintf(stderr, "Unsupported value for VQ (%d != %d)\n", + test_sve, (int)sve_vq_from_vl(got)); + } + exit(1); + } +#else abort(); +#endif } const int reginfo_size(void) @@ -113,12 +139,18 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc) #ifdef SVE_MAGIC if (test_sve) { - int vq = sve_vq_from_vl(sve->vl); /* number of quads for whole vl */ + int vq = test_sve; if (sve == NULL) { fprintf(stderr, "risu_reginfo_aarch64: failed to get SVE state\n"); return; } + if (sve->vl != sve_vl_from_vq(vq)) { + fprintf(stderr, "risu_reginfo_aarch64: " + "unexpected SVE state: %d != %d\n", + sve->vl, sve_vl_from_vq(vq)); + return; + } ri->sve.vl = sve->vl;