From patchwork Fri Jun 29 08:38:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 140532 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp567861ljj; Fri, 29 Jun 2018 01:39:11 -0700 (PDT) X-Google-Smtp-Source: AAOMgpc/T+R4OEYabExKs25xnz1NuhqQyjTZtyApOm4x6Kt22HxfeuRROiWt2IPXFaXCJrVZgRNF X-Received: by 2002:a17:902:b785:: with SMTP id e5-v6mr6178541pls.339.1530261551053; Fri, 29 Jun 2018 01:39:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530261551; cv=none; d=google.com; s=arc-20160816; b=gqGQEp7elz6BVIBmCLcHlmeaol+s+zPhDVU0G+RJTBRVZ+PrnpUbd3Q7EPnhcvLgnP iidpAchYGIPkEbwdiyq8YyXQ9eR47efDeVspJTICnzb931i6kFhYSZ9Jc54fEKJ0lgnf gBcpofryJLJj1hFzLJra0Kio5ZGjv1Oa8mD9fvXzYR9Xxh+UdqLwk8qL27FBkvp493sC hLgszc+Yk0R/vBlgMcX/lI7Eb6UF8JMNsgkrvUaaAKD+ui0hjxIsUslkzSJ3f4xl06k5 qCtFd+IvofixjnZPFzEzzwwvMKWQ5WvVMC9Wk/ckj26dA3h69qQNyES5UEN5lmV8b1Yk hS6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=xMcWwS3rwzsWVJt8gFkbCmqAB25xzSqs9j5jpC06Yuw=; b=HoQBClIPZ+4mY01Mz/sXPiGvYQ3sZwcfeAJMi+fE22rGvtBBswj4xz1QbPqBbcLLAx uzjSckDxuA/y49hN7T6m8H7twEnYlrKPa2gX2dKbGhh6Q9E8ABun86flosaHVfyfO/2F ejrD6Lh1KbBsApAj/FRGVmjNEJNTRkkwQEGhFFU79IbVa1DuHr+Q3f/2xXF/ch2pxRuY 3MSsXCqP45TDKiV6NugYE1oagEMkSULNqXEqozwjjngMwjBkWQdvgqzoiL/enCE7t/Vp f9FZdc2I6379HZtdDhu20hgeodQ/wCSbnlWqzyS1b8kLFqj3Zt15rU5U/etLXmLrjF3g 8Peg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s9-v6si8736806plr.332.2018.06.29.01.39.10; Fri, 29 Jun 2018 01:39:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965502AbeF2IjI (ORCPT + 31 others); Fri, 29 Jun 2018 04:39:08 -0400 Received: from mx.socionext.com ([202.248.49.38]:43010 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965315AbeF2IjD (ORCPT ); Fri, 29 Jun 2018 04:39:03 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 29 Jun 2018 17:39:02 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 4281F1800FC; Fri, 29 Jun 2018 17:39:02 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 29 Jun 2018 17:39:02 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 863401A120D; Fri, 29 Jun 2018 17:39:01 +0900 (JST) From: Kunihiko Hayashi To: Kishon Vijay Abraham I , Rob Herring , Mark Rutland , Masahiro Yamada Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH 1/4] dt-bindings: phy: add DT bindings for UniPhier USB3 PHY driver Date: Fri, 29 Jun 2018 17:38:58 +0900 Message-Id: <1530261541-23104-2-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530261541-23104-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1530261541-23104-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add DT bindings for PHY interface built into USB3 controller implemented in UniPhier SoCs. Signed-off-by: Kunihiko Hayashi --- .../devicetree/bindings/phy/uniphier-usb3-phy.txt | 118 +++++++++++++++++++++ 1 file changed, 118 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/uniphier-usb3-phy.txt -- 2.7.4 diff --git a/Documentation/devicetree/bindings/phy/uniphier-usb3-phy.txt b/Documentation/devicetree/bindings/phy/uniphier-usb3-phy.txt new file mode 100644 index 0000000..3df4a486 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/uniphier-usb3-phy.txt @@ -0,0 +1,118 @@ +Socionext UniPhier USB3 PHY + +This describes the devicetree bindings for PHY interfaces built into +USB3 controller implemented on Socionext UniPhier SoCs. +The controller includes High-Speed PHY and Super-Speed PHY. + +USB3 High-Speed (HS) PHY +------------------------ + +Required properties: +- compatible: Should contain one of the following: + "socionext,uniphier-pro4-usb3-hsphy" - for Pro4 SoC + "socionext,uniphier-pxs2-usb3-hsphy" - for PXs2 SoC + "socionext,uniphier-ld20-usb3-hsphy" - for LD20 SoC + "socionext,uniphier-pxs3-usb3-hsphy" - for PXs3 SoC +- reg: Specifies offset and length of the register set for the device. +- #phy-cells: Should be 0. +- clocks: A list of phandles to the clock gate for USB3 glue layer. + According to the clock-names, appropriate clocks are required. +- clock-names: Should contain the following: + "gio", "link" - for Pro4 SoC + "link", "phy", "phy-ext" - for PXs3 SoC, "phy-ext" is optional. + "link", "phy" - for others +- resets: A list of phandles to the reset control for USB3 glue layer. + According to the reset-names, appropriate resets are required. +- reset-names: Should contain the following: + "gio", "link" - for Pro4 SoC + "link", "phy" - for others + +Optional properties: +- phy-supply: A phandle to the regulator for USB VBUS. +- nvmem-cells: Phandles to nvmem cell that contains the trimming data. + Available only for HS-PHY implemented on LD20 and PXs3, and + if unspecified, default value is used. +- nvmem-cell-names: Should be the following names, which correspond to + each nvmem-cells. + All of the 3 parameters associated with the following names are + required for each port, if any one is omitted, the trimming data + of the port will not be set at all. + "rterm", "sel_t", "hs_i" - Each cell name for phy parameters + +Refer to phy/phy-bindings.txt for the generic PHY binding properties. + +Example: + + usb-glue@65b00000 { + compatible = "socionext,uniphier-ld20-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65b00000 0x400>; + + usb_hsphy0: hs-phy@200 { + compatible = "socionext,uniphier-ld20-usb3-hsphy"; + reg = <0x200 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 16>; + phy-supply = <&usb_vbus0>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, + <&usb_hs_i0>; + }; + }; + + +USB3 Super-Speed (SS) PHY +------------------------- + +Required properties: +- compatible: Should contain one of the following: + "socionext,uniphier-pro4-usb3-ssphy" - for Pro4 SoC + "socionext,uniphier-pxs2-usb3-ssphy" - for PXs2 SoC + "socionext,uniphier-ld20-usb3-ssphy" - for LD20 SoC + "socionext,uniphier-pxs3-usb3-ssphy" - for PXs3 SoC +- reg: Specifies offset and length of the register set for the device. +- #phy-cells: Should be 0. +- clocks: A list of phandles to the clock gate for USB3 glue layer. + According to the clock-names, appropriate clocks are required. +- clock-names: + "gio", "link" - for Pro4 SoC + "link", "phy", "phy-ext" - for PXs3 SoC, "phy-ext" is optional. + "link", "phy" - for others +- resets: A list of phandles to the reset control for USB3 glue layer. + According to the reset-names, appropriate resets are required. +- reset-names: + "gio", "link" - for Pro4 SoC + "link", "phy" - for others + +Optional properties: +- phy-supply: A phandle to the regulator for USB VBUS. + +Refer to phy/phy-bindings.txt for the generic PHY binding properties. + +Example: + + usb-glue@65b00000 { + compatible = "socionext,uniphier-ld20-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65b00000 0x400>; + + usb_ssphy0: ss-phy@300 { + compatible = "socionext,uniphier-ld20-usb3-ssphy"; + reg = <0x300 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 16>; + phy-supply = <&usb_vbus0>; + }; + + other nodes ... + }; From patchwork Fri Jun 29 08:39:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 140534 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp568746ljj; Fri, 29 Jun 2018 01:40:23 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfgqiOufTtLYLRqQU1f+Vy9Ga8J2vEnUTMkrYzajNhuFjYbrsTg24t4FPDNXegCQxGAxYYe X-Received: by 2002:a65:6301:: with SMTP id g1-v6mr3529998pgv.324.1530261623025; Fri, 29 Jun 2018 01:40:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530261623; 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[209.132.180.67]) by mx.google.com with ESMTP id d2-v6si7312422pgv.562.2018.06.29.01.40.22; Fri, 29 Jun 2018 01:40:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965437AbeF2IjG (ORCPT + 31 others); Fri, 29 Jun 2018 04:39:06 -0400 Received: from mx.socionext.com ([202.248.49.38]:43004 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965334AbeF2IjE (ORCPT ); Fri, 29 Jun 2018 04:39:04 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 29 Jun 2018 17:39:02 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id C074560034; Fri, 29 Jun 2018 17:39:02 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 29 Jun 2018 17:39:02 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 11C951A120D; Fri, 29 Jun 2018 17:39:02 +0900 (JST) From: Kunihiko Hayashi To: Kishon Vijay Abraham I , Rob Herring , Mark Rutland , Masahiro Yamada Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH 3/4] dt-bindings: phy: add DT bindings for UniPhier USB2 PHY driver Date: Fri, 29 Jun 2018 17:39:00 +0900 Message-Id: <1530261541-23104-4-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530261541-23104-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1530261541-23104-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add DT bindings for PHY interface built into USB2 controller implemented on Socionext UniPhier SoCs. Signed-off-by: Kunihiko Hayashi --- .../devicetree/bindings/phy/uniphier-usb2-phy.txt | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/uniphier-usb2-phy.txt -- 2.7.4 diff --git a/Documentation/devicetree/bindings/phy/uniphier-usb2-phy.txt b/Documentation/devicetree/bindings/phy/uniphier-usb2-phy.txt new file mode 100644 index 0000000..95ee393 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/uniphier-usb2-phy.txt @@ -0,0 +1,45 @@ +Socionext UniPhier USB2 PHY + +This describes the devicetree bindings for PHY interface built into +USB2 controller implemented on Socionext UniPhier SoCs. + +Pro4 SoC has both USB2 and USB3 host controllers, however, this USB3 +controller doesn't include its own High-Speed PHY. This needs to specify +USB2 PHY instead of USB3 HS-PHY. + +Required properties: +- compatible: Should contain one of the following: + "socionext,uniphier-pro4-usb2-phy" - for Pro4 SoC + "socionext,uniphier-ld11-usb2-phy" - for LD11 SoC + +Sub-nodes: +Each PHY should be represented as a sub-node. + +Sub-nodes required properties: +- #phy-cells: Should be 0. +- reg: The number of the PHY. + +Sub-nodes optional properties: +- phy-supply: A phandle to the regulator for USB VBUS. + +Refer to phy/phy-bindings.txt for the generic PHY binding properties. + +Example: + soc-glue@5f800000 { + ... + usb-phy { + compatible = "socionext,uniphier-ld11-usb2-phy"; + usb_phy0: phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + ... + }; + }; + + usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + ... + phy-names = "usb"; + phys = <&usb_phy0>; + }; From patchwork Fri Jun 29 08:39:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 140535 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp568997ljj; Fri, 29 Jun 2018 01:40:40 -0700 (PDT) X-Google-Smtp-Source: ADUXVKK0KmqHYYSEc/Dqnl6JytGwn8ie9qcF6lSOcEuzTv+AOz5E67hSd52cLJdVEHi6pW0zPvhw X-Received: by 2002:a17:902:bf01:: with SMTP id bi1-v6mr13832922plb.43.1530261640224; Fri, 29 Jun 2018 01:40:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530261640; cv=none; d=google.com; s=arc-20160816; b=LBC3MfHbOzXxrzFbgH/c53FS4uB3f1ABFPpb5lKOdOcon4Lj0Yeyy/dUkA+/hC7BJ3 iTXxV4ctKFlgH2L7h4D9cWG0Aefhq+737KqnlH6ORCiYPVkvWwS7v3V2vvwir5UT0XKW gY/FDkHQ5KeikcVcDISD5ncdl83Sl1eWhhgaACac6mGNfFWHWSyx7AOwE47vLjrbDpx3 L/vzWlFal+VR2zQuhPfWHJfadFpsBVCT1gdrI6U7MG5R1z0bjkBz0lX7fwieVKRCkeDI 4t7erd8xP0/2wamGcMuT9PTXNPqCQVnIZb7gySOXXe8NHAmiUZ/c4T8FN7o8tL8v01rz d/HQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=v+X4lgk4EyXHO6gxaaQtOMpomATdeDeDPHFh666c/ds=; b=YBLWZVa1RDswp+I7RCfBOTJBZjh1UpkSG8C5D7TUSp2QAp9ERyvCaCEgTMSjG6Gg+z CbHPVkVzE4JtFjFtiY4WY32dnec38BXDM+xuup4cM+SaQZa2jjmDDYnSc5kZhdk838Wc ItDhO9JTgrqHJf1DxvjEcoyoBmnxj463K7JhMGZAACxJQHg9loUQGY0xF2dFuPnJOePP JYdwqKsF8ipM2Lf5TV5Pydca+FIBs8quAZaW2hqPbEYCvRICv8k49FmiQWASwJCLnGva RTGJvPWVVVWRHZMn3D6HXPnSmOkqfp5KRYDE+nF88N0fDtzPebGw58UKEsGPKpRkv1QT rpUQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p5-v6si4606301pfp.218.2018.06.29.01.40.39; Fri, 29 Jun 2018 01:40:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965765AbeF2Ikh (ORCPT + 31 others); Fri, 29 Jun 2018 04:40:37 -0400 Received: from mx.socionext.com ([202.248.49.38]:43010 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965371AbeF2IjF (ORCPT ); Fri, 29 Jun 2018 04:39:05 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 29 Jun 2018 17:39:02 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id C0F841800FC; Fri, 29 Jun 2018 17:39:02 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 29 Jun 2018 17:39:02 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 4C2F01A120E; Fri, 29 Jun 2018 17:39:02 +0900 (JST) From: Kunihiko Hayashi To: Kishon Vijay Abraham I , Rob Herring , Mark Rutland , Masahiro Yamada Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH 4/4] phy: socionext: add USB2 PHY driver for UniPhier SoC Date: Fri, 29 Jun 2018 17:39:01 +0900 Message-Id: <1530261541-23104-5-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1530261541-23104-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1530261541-23104-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a driver for PHY interface built into USB2 controller implemented on UniPhier SoCs. This driver supports HS-PHY for Pro4 and LD11. Signed-off-by: Kunihiko Hayashi --- drivers/phy/socionext/Kconfig | 13 ++ drivers/phy/socionext/Makefile | 1 + drivers/phy/socionext/phy-uniphier-usb2.c | 218 ++++++++++++++++++++++++++++++ 3 files changed, 232 insertions(+) create mode 100644 drivers/phy/socionext/phy-uniphier-usb2.c -- 2.7.4 diff --git a/drivers/phy/socionext/Kconfig b/drivers/phy/socionext/Kconfig index 4a172fc..497ca38 100644 --- a/drivers/phy/socionext/Kconfig +++ b/drivers/phy/socionext/Kconfig @@ -2,6 +2,19 @@ # PHY drivers for Socionext platforms. # +config PHY_UNIPHIER_USB2 + tristate "UniPhier USB2 PHY driver" + depends on ARCH_UNIPHIER || COMPILE_TEST + depends on OF && HAS_IOMEM + select GENERIC_PHY + select MFD_SYSCON + help + Enable this to support USB PHY implemented on USB2 controller + on UniPhier SoCs. This driver provides interface to interact + with USB 2.0 PHY that is part of the UniPhier SoC. + In case of Pro4, it is necessary to specify this USB2 PHY instead + of USB3 HS-PHY. + config PHY_UNIPHIER_USB3 tristate "UniPhier USB3 PHY driver" depends on ARCH_UNIPHIER || COMPILE_TEST diff --git a/drivers/phy/socionext/Makefile b/drivers/phy/socionext/Makefile index dfa5cec..6b4763e 100644 --- a/drivers/phy/socionext/Makefile +++ b/drivers/phy/socionext/Makefile @@ -3,4 +3,5 @@ # Makefile for the phy drivers. # +obj-$(CONFIG_PHY_UNIPHIER_USB2) += phy-uniphier-usb2.o obj-$(CONFIG_PHY_UNIPHIER_USB3) += phy-uniphier-usb3hs.o phy-uniphier-usb3ss.o diff --git a/drivers/phy/socionext/phy-uniphier-usb2.c b/drivers/phy/socionext/phy-uniphier-usb2.c new file mode 100644 index 0000000..bab9e38 --- /dev/null +++ b/drivers/phy/socionext/phy-uniphier-usb2.c @@ -0,0 +1,218 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * phy-uniphier-usb2.c - PHY driver for UniPhier USB2 controller + * Copyright 2015-2018 Socionext Inc. + * Author: + * Kunihiko Hayashi + */ + +#include +#include +#include +#include +#include +#include +#include + +#define PHY_PARAMS 2 + +struct uniphier_u2phy_soc_data { + struct { + u32 addr; + u32 val; + } param[PHY_PARAMS]; +}; + +struct uniphier_u2phy_priv { + struct regmap *regmap; + struct phy *phy; + const struct uniphier_u2phy_soc_data *data; + struct uniphier_u2phy_priv *next; +}; + +static int uniphier_u2phy_init(struct phy *phy) +{ + struct uniphier_u2phy_priv *priv = phy_get_drvdata(phy); + int i; + + if (!priv->data) + return 0; + + for (i = 0; i < PHY_PARAMS; i++) + regmap_write(priv->regmap, + priv->data->param[i].addr, + priv->data->param[i].val); + + return 0; +} + +static struct phy *uniphier_u2phy_xlate(struct device *dev, + struct of_phandle_args *args) +{ + struct uniphier_u2phy_priv *priv = dev_get_drvdata(dev); + + while (priv && args->np != priv->phy->dev.of_node) + priv = priv->next; + + if (!priv) { + dev_err(dev, "Failed to find appropriate phy\n"); + return ERR_PTR(-EINVAL); + } + + return priv->phy; +} + +static const struct phy_ops uniphier_u2phy_ops = { + .init = uniphier_u2phy_init, + .owner = THIS_MODULE, +}; + +static int uniphier_u2phy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *parent, *child; + struct uniphier_u2phy_priv *priv = NULL, *next = NULL; + struct phy_provider *phy_provider; + struct regmap *regmap; + struct phy *phy; + const struct uniphier_u2phy_soc_data *data; + int ret, data_idx, ndatas; + + data = of_device_get_match_data(dev); + if (WARN_ON(!data)) + return -EINVAL; + + /* get number of data */ + for (ndatas = 0; data[ndatas].param[0].addr; ndatas++) + ; + + parent = of_get_parent(dev->of_node); + regmap = syscon_node_to_regmap(parent); + of_node_put(parent); + if (IS_ERR(regmap)) { + dev_err(dev, "Failed to get regmap\n"); + return PTR_ERR(regmap); + } + + for_each_child_of_node(dev->of_node, child) { + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) { + ret = -ENOMEM; + goto out_put_child; + } + priv->regmap = regmap; + + phy = devm_phy_create(dev, child, &uniphier_u2phy_ops); + if (IS_ERR(phy)) { + dev_err(dev, "Failed to create phy\n"); + ret = PTR_ERR(phy); + goto out_put_child; + } + priv->phy = phy; + + ret = of_property_read_u32(child, "reg", &data_idx); + if (ret) { + dev_err(dev, "Failed to get reg property\n"); + goto out_put_child; + } + + if (data_idx < ndatas) + priv->data = &data[data_idx]; + else + dev_warn(dev, "No phy configuration: %s\n", + child->full_name); + + phy_set_drvdata(phy, priv); + priv->next = next; + next = priv; + } + + dev_set_drvdata(dev, priv); + phy_provider = devm_of_phy_provider_register(dev, + uniphier_u2phy_xlate); + if (IS_ERR(phy_provider)) + return PTR_ERR(phy_provider); + + return 0; + +out_put_child: + of_node_put(child); + + return ret; +} + +static const struct uniphier_u2phy_soc_data uniphier_pro4_data[] = { + { + .param = { + { 0x500, 0x05142400 }, + { 0x50c, 0x00010010 }, + }, + }, + { + .param = { + { 0x508, 0x05142400 }, + { 0x50c, 0x00010010 }, + }, + }, + { + .param = { + { 0x510, 0x05142400 }, + { 0x51c, 0x00010010 }, + }, + }, + { + .param = { + { 0x518, 0x05142400 }, + { 0x51c, 0x00010010 }, + }, + }, + { /* sentinel */ } +}; + +static const struct uniphier_u2phy_soc_data uniphier_ld11_data[] = { + { + .param = { + { 0x500, 0x82280000 }, + { 0x504, 0x00000106 }, + }, + }, + { + .param = { + { 0x508, 0x82280000 }, + { 0x50c, 0x00000106 }, + }, + }, + { + .param = { + { 0x510, 0x82280000 }, + { 0x514, 0x00000106 }, + }, + }, + { /* sentinel */ } +}; + +static const struct of_device_id uniphier_u2phy_match[] = { + { + .compatible = "socionext,uniphier-pro4-usb2-phy", + .data = &uniphier_pro4_data, + }, + { + .compatible = "socionext,uniphier-ld11-usb2-phy", + .data = &uniphier_ld11_data, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, uniphier_u2phy_match); + +static struct platform_driver uniphier_u2phy_driver = { + .probe = uniphier_u2phy_probe, + .driver = { + .name = "uniphier-usb2-phy", + .of_match_table = uniphier_u2phy_match, + }, +}; +module_platform_driver(uniphier_u2phy_driver); + +MODULE_AUTHOR("Kunihiko Hayashi "); +MODULE_DESCRIPTION("UniPhier PHY driver for USB2 controller"); +MODULE_LICENSE("GPL v2");