From patchwork Thu May 13 00:37:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 439018 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F4FFC433B4 for ; Thu, 13 May 2021 00:42:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0D191613F7 for ; Thu, 13 May 2021 00:42:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232968AbhEMAnR (ORCPT ); Wed, 12 May 2021 20:43:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237628AbhEMAkw (ORCPT ); Wed, 12 May 2021 20:40:52 -0400 Received: from mail-qk1-x732.google.com (mail-qk1-x732.google.com [IPv6:2607:f8b0:4864:20::732]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD0B3C061763 for ; Wed, 12 May 2021 17:39:03 -0700 (PDT) Received: by mail-qk1-x732.google.com with SMTP id k127so24122754qkc.6 for ; Wed, 12 May 2021 17:39:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek-ca.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OWZAMSO2hYSW16tUIYHpicH/GLn/3fYypp5Jz9VSm00=; b=U4o7cwX2QQVVTuDryXGCKWLw0coEb16npVBu/jFofLo4GTjmsF8dA6MYmsiPfPhL6k 7aMlrAqXx/H6Pa4kuBluRMbfC247VwlqE0yooUKjYvApRKrTskwNrJBHYywJUAG2X7ZA VQXOMtLtIOPk3tDvIg5SVdRe9RAwpOkkNNNFBVO9EHxnkLiovJXusp6fgipw2FGdIazc cjmJd/iLu+KsJIxKRLXf4zI1sOEvxLypncNuNAUbrYar2eBfztYVQSj/RZ2iqy5QXSXb 2xhLZY6lyGwAnZZBDNeBnBzMFx55muQBXIO7309s7AB4U2TuElmMFmNEZQZL0Ogeze8S WZTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OWZAMSO2hYSW16tUIYHpicH/GLn/3fYypp5Jz9VSm00=; b=Xv4U5sTwsTmlq8+xW6C8y4cFQWzINOPUXrWFnuIL8pxF0EXFNpYGQ1CRRgD9Jo/6DC YDtR9yMtvUiV/Md5KZONs4JDWBwF2k9Cc3yQYcvDGffjHh0cYAPIbnR7BAyNeh8nsutl WXSac2izFUc/TFVkz2ndjWcHcIjDEqVcJu0bAbgUQ+SMS29FVSIh7NS5hYiF7y4klELK UhTFtTBPVXhxoPqC60NmBpcIA2fAotz5WRtEOhj56F9oIrV84MllnFABJoRR9wIkpBYT Ww36hamyppQgzvBN/ylUnYQZeSCpGdZjkyS1ZvYs3vP7VOUtsjMGtRngeh2iBv13TjCE LISQ== X-Gm-Message-State: AOAM5328Q6sBDcK5jxddqAXvfQM3TxWsVbliLfartjjjGRwS3kd1GASn gTJuuxjpF5VF7b9W9Rq9GIvXIQ== X-Google-Smtp-Source: ABdhPJyDGD9edTt/pecm2J2HYiTGtCLsMV1PL5FrxPOMfc9PT5J5phKcxKXCTRi/AnZO7jbXTmddog== X-Received: by 2002:a37:4017:: with SMTP id n23mr34108146qka.338.1620866343100; Wed, 12 May 2021 17:39:03 -0700 (PDT) Received: from localhost.localdomain (modemcable068.184-131-66.mc.videotron.ca. [66.131.184.68]) by smtp.gmail.com with ESMTPSA id w16sm1204201qts.70.2021.05.12.17.39.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 May 2021 17:39:02 -0700 (PDT) From: Jonathan Marek To: freedreno@lists.freedesktop.org Cc: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Jordan Crouse , Sai Prakash Ranjan , Bjorn Andersson , Sharat Masetty , Akhil P Oommen , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 1/5] drm/msm: remove unused icc_path/ocmem_icc_path Date: Wed, 12 May 2021 20:37:45 -0400 Message-Id: <20210513003811.29578-2-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20210513003811.29578-1-jonathan@marek.ca> References: <20210513003811.29578-1-jonathan@marek.ca> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org These aren't used by anything anymore. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 --- drivers/gpu/drm/msm/msm_gpu.h | 9 --------- 2 files changed, 12 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 8fd0777f2dc9..009f4c560f16 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -946,7 +946,4 @@ void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu) pm_runtime_disable(&priv->gpu_pdev->dev); msm_gpu_cleanup(&adreno_gpu->base); - - icc_put(gpu->icc_path); - icc_put(gpu->ocmem_icc_path); } diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 18baf935e143..c302ab7ffb06 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -118,15 +118,6 @@ struct msm_gpu { struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk; uint32_t fast_rate; - /* The gfx-mem interconnect path that's used by all GPU types. */ - struct icc_path *icc_path; - - /* - * Second interconnect path for some A3xx and all A4xx GPUs to the - * On Chip MEMory (OCMEM). - */ - struct icc_path *ocmem_icc_path; - /* Hang and Inactivity Detection: */ #define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */ From patchwork Thu May 13 00:37:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 437395 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C14EBC433ED for ; Thu, 13 May 2021 00:42:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9EE8D61412 for ; Thu, 13 May 2021 00:42:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232100AbhEMAnw (ORCPT ); Wed, 12 May 2021 20:43:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233287AbhEMAlu (ORCPT ); Wed, 12 May 2021 20:41:50 -0400 Received: from mail-qt1-x832.google.com (mail-qt1-x832.google.com [IPv6:2607:f8b0:4864:20::832]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E7C8FC06138A for ; Wed, 12 May 2021 17:39:06 -0700 (PDT) Received: by mail-qt1-x832.google.com with SMTP id m13so3429506qtk.13 for ; Wed, 12 May 2021 17:39:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek-ca.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/Suj7rUF8MJYpSENOVcgNKkIQ7HdP/cqmF4RJs83xUg=; b=Ok4b06fm240rt6q8SJwuDlWX3p0+7j3KUQCdoVM61MLZizJKrH3WzYjt2R8/VHvuHd nlwYxjoVLi7VSPzGhiBjj9Ha4Hzv6Uo+Pn62IGsq/M+YOZ+gKmWIsPSO7Aitg0gN3/Dx zOAcsoAv8bo8pcDo+Y6KUR43zefAjHUfQdHktVOHb+916Dxmo2JHKI8lUwEop6tI806V KHffv1x5FOG5QrIEeBdhKrq30VOi7LpDmA7oFXZRBDDZD3IqKueXGVVFto0nqfeurDM/ kulCd2rG9bue1lCuX3n4+ow6bDIKfsBLLLnw0X0dScRtw074SOK18O4AlF3R6EOTrR61 EQXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/Suj7rUF8MJYpSENOVcgNKkIQ7HdP/cqmF4RJs83xUg=; b=GRj2YiYjdU7+i6keYFCyZD/VMcc5Tm7E8aSoXvoJBw7O3NjhFUFaRCWisMNmgPhN7g OOiEAKXakNflWldwzudvXWH0AfMe9iih90+rBiClsQyp6nVucAqj7yIhWSYnw5lPwEeZ R2gxlE/nuwTNPI6jdj9hh+3IsBHAW2fajKRY8lqZANxUm5wi8egQOP9Jts8hXW05W18h sJfzOy8PQnHAqPky5uVp3oezaVJCpB+dpJUC5x0i822Un0DSW66eRvJtiJyzdcEUeF67 tgt9KRigo13ljSaEAXh89XZwinq6qwpOgzMNG7xwl9myQebOF/+Tyw4U/TE1X79ov0rn znqw== X-Gm-Message-State: AOAM530FWXIMicG9nrUa0P767quUnkEcyJraw+397BLV90+W8dSU7VUx ZHr3pzNYaGr3PAUOLmbfY6/+vA== X-Google-Smtp-Source: ABdhPJxTw1P3oaoCV0WfoXRiB/+wKSwQTK+iAtqp6IJbfH0cUqEkpY2KsJRruijFgA1FamuFr24gBQ== X-Received: by 2002:a05:622a:154:: with SMTP id v20mr4064234qtw.91.1620866346172; Wed, 12 May 2021 17:39:06 -0700 (PDT) Received: from localhost.localdomain (modemcable068.184-131-66.mc.videotron.ca. [66.131.184.68]) by smtp.gmail.com with ESMTPSA id w16sm1204201qts.70.2021.05.12.17.39.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 May 2021 17:39:05 -0700 (PDT) From: Jonathan Marek To: freedreno@lists.freedesktop.org Cc: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Jordan Crouse , Akhil P Oommen , Sai Prakash Ranjan , Eric Anholt , Sharat Masetty , Douglas Anderson , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 2/5] drm/msm/a6xx: avoid shadow NULL reference in failure path Date: Wed, 12 May 2021 20:37:46 -0400 Message-Id: <20210513003811.29578-3-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20210513003811.29578-1-jonathan@marek.ca> References: <20210513003811.29578-1-jonathan@marek.ca> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org If a6xx_hw_init() fails before creating the shadow_bo, the a6xx_pm_suspend code referencing it will crash. Change the condition to one that avoids this problem (note: creation of shadow_bo is behind this same condition) Fixes: e8b0b994c3a5 ("drm/msm/a6xx: Clear shadow on suspend") Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 727d111a413f..01bd31b3c504 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1211,7 +1211,7 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu) if (ret) return ret; - if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) + if (a6xx_gpu->shadow_bo) for (i = 0; i < gpu->nr_rings; i++) a6xx_gpu->shadow[i] = 0; From patchwork Thu May 13 00:37:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 439017 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EF4FC433B4 for ; Thu, 13 May 2021 00:42:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6F9BB61406 for ; Thu, 13 May 2021 00:42:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231743AbhEMAny (ORCPT ); Wed, 12 May 2021 20:43:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57354 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233664AbhEMAlu (ORCPT ); Wed, 12 May 2021 20:41:50 -0400 Received: from mail-qk1-x734.google.com (mail-qk1-x734.google.com [IPv6:2607:f8b0:4864:20::734]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A3DFC061760 for ; Wed, 12 May 2021 17:39:19 -0700 (PDT) Received: by mail-qk1-x734.google.com with SMTP id f29so11887265qka.0 for ; Wed, 12 May 2021 17:39:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek-ca.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=45A3QuMXm6Cyn55olGRnsIeedlfjDiFJm3+n93w3le0=; b=r3orxArIAv0zYElpqQVDuHhzY/qET51DSExBOf+TPazQZm5taJrECw5ePBDuTTOBEp MICrmqZNdgj4EAHZjO/NOD9FUrL1A3aZChcgZmdL/F+9+i/zmGKvTT7NesfxzZVlub80 Zwb/wcRKB/jS/pM3JbOS8BJh2Gyet6UsyEz91xbC4cD5jRaeR8+UITn9FB9N9xOCp7XU fNRuAAJjHI2iJ/wVc4REdSZF+t4sJuBuEtNeA+9pzKso0pKAiZsRqbPwKFl7wJaMwQHe C3VUrzaHWn+CJV8YPIMs261qtu12trzWg8h7xh5nKRpYU/6W5fX//B/uAOrvVxAVjfQl ixHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=45A3QuMXm6Cyn55olGRnsIeedlfjDiFJm3+n93w3le0=; b=TJO3l8amvRb/5t7L8O6C3xx0WzgJs7aU+fi/Jh0QhZd5d3JV1uLShqlklNrP+WDjCX rQD3eSAdHzebD+A995atVGnGGZbUzndGB7B2NGWVzrM1/Nh1eFN8NLM5GKnUPL7j/EnO nLZyUzbyp6XEEpvqF2Rt26sbw7dSJ9x0Pvdln5gy/7bOdDLejsZZCnZAcE5/GVII8doW U+El9ZcBvQp3Q19seCIffEahfHUL1ai6Je7y2m/6bvQTRbf1dumPnlp7OSBDLMNYzB+I nueSttkjvoJO6ueSV/FpcvZZZ4aGa4tRbZIvL+uyr+g4VyhgHySZAi/f88cdUrT5tY3D X7+w== X-Gm-Message-State: AOAM53207obu2V3zNmuIzmFxbTfzz6CBKtItE2Z55lRyoPbeoJuGfVpU g9jUmEe56AG6wYn/QyDHQf8v4Bfo6e71S0L+ass= X-Google-Smtp-Source: ABdhPJx89p2JzrSGS2YTdIUxAAZa74mJWiKGGeKzCBCG3uVa7vroeHHzKlhBRNr2qGX0hEkQ3qanzg== X-Received: by 2002:a05:620a:1390:: with SMTP id k16mr36612135qki.99.1620866358773; Wed, 12 May 2021 17:39:18 -0700 (PDT) Received: from localhost.localdomain (modemcable068.184-131-66.mc.videotron.ca. [66.131.184.68]) by smtp.gmail.com with ESMTPSA id w16sm1204201qts.70.2021.05.12.17.39.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 May 2021 17:39:18 -0700 (PDT) From: Jonathan Marek To: freedreno@lists.freedesktop.org Cc: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Jordan Crouse , Eric Anholt , Akhil P Oommen , Sharat Masetty , Sai Prakash Ranjan , Douglas Anderson , kbuild test robot , AngeloGioacchino Del Regno , Bjorn Andersson , Iskren Chernev , Shawn Guo , Konrad Dybcio , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 3/5] drm/msm/a6xx: add support for Adreno 660 GPU Date: Wed, 12 May 2021 20:37:47 -0400 Message-Id: <20210513003811.29578-4-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20210513003811.29578-1-jonathan@marek.ca> References: <20210513003811.29578-1-jonathan@marek.ca> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add adreno_is_{a660,a650_family} helpers and convert update existing adreno_is_a650 usage based on downstream driver's logic (changing into adreno_is_a650_family or adding adreno_is_a660). And add the remaining changes required for A660, again based on the downstream driver: missing GMU allocations, additional register init, dummy hfi BW table, entry in gpulist table. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/a6xx.xml.h | 4 +++ drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 32 +++++++++++++++------ drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 24 +++++++++++----- drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 33 ++++++++++++++++++++++ drivers/gpu/drm/msm/adreno/adreno_device.c | 12 ++++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 12 ++++++++ 7 files changed, 103 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h index 920c5e6b8e96..631c36672560 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h @@ -2240,6 +2240,8 @@ static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630 +#define REG_A6XX_CP_LPAC_PROG_FIFO_SIZE 0x00000b34 + #define REG_A6XX_VSC_PERFCTR_VSC_SEL_0 0x00000cd8 #define REG_A6XX_VSC_PERFCTR_VSC_SEL_1 0x00000cd9 @@ -2340,6 +2342,8 @@ static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val) #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL_11 0x00000e27 +#define REG_A6XX_UCHE_CMDQ_CONFIG 0x00000e3c + #define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01 #define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 3d55e153fa9c..e25c41984336 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -520,7 +520,7 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu)) pdc_address_offset = 0x30090; - else if (adreno_is_a650(adreno_gpu)) + else if (adreno_is_a650_family(adreno_gpu)) pdc_address_offset = 0x300a0; else pdc_address_offset = 0x30080; @@ -542,7 +542,7 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514); /* Load RSC sequencer uCode for sleep and wakeup */ - if (adreno_is_a650(adreno_gpu)) { + if (adreno_is_a650_family(adreno_gpu)) { gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0); gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab); gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581); @@ -587,7 +587,7 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108); pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000); - if (adreno_is_a618(adreno_gpu) || adreno_is_a650(adreno_gpu)) + if (adreno_is_a618(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2); else pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3); @@ -687,7 +687,7 @@ static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu) u32 itcm_base = 0x00000000; u32 dtcm_base = 0x00040000; - if (adreno_is_a650(adreno_gpu)) + if (adreno_is_a650_family(adreno_gpu)) dtcm_base = 0x10004000; if (gmu->legacy) { @@ -740,7 +740,7 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) int ret; u32 chipid; - if (adreno_is_a650(adreno_gpu)) + if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1); if (state == GMU_WARM_BOOT) { @@ -1483,12 +1483,28 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) if (ret) goto err_put_device; + + /* A660 now requires handling "prealloc requests" in GMU firmware + * For now just hardcode allocations based on the known firmware. + * note: there is no indication that these correspond to "dummy" or + * "debug" regions, but this "guess" allows reusing these BOs which + * are otherwise unused by a660. + */ + gmu->dummy.size = SZ_4K; + if (adreno_is_a660(adreno_gpu)) { + ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_4K * 7, 0x60400000); + if (ret) + goto err_memory; + + gmu->dummy.size = SZ_8K; + } + /* Allocate memory for the GMU dummy page */ - ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, SZ_4K, 0x60000000); + ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, gmu->dummy.size, 0x60000000); if (ret) goto err_memory; - if (adreno_is_a650(adreno_gpu)) { + if (adreno_is_a650_family(adreno_gpu)) { ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache, SZ_16M - SZ_16K, 0x04000); if (ret) @@ -1530,7 +1546,7 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) goto err_memory; } - if (adreno_is_a650(adreno_gpu)) { + if (adreno_is_a650_family(adreno_gpu)) { gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc"); if (IS_ERR(gmu->rscc)) goto err_mmio; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 01bd31b3c504..4467273e66c0 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -477,7 +477,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) if (adreno_is_a640(adreno_gpu)) amsbc = 1; - if (adreno_is_a650(adreno_gpu)) { + if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) { /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ lower_bit = 3; amsbc = 1; @@ -690,7 +690,7 @@ static int a6xx_hw_init(struct msm_gpu *gpu) a6xx_set_hwcg(gpu, true); /* VBIF/GBIF start*/ - if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu)) { + if (adreno_is_a640(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) { gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); @@ -715,7 +715,7 @@ static int a6xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000); gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff); - if (!adreno_is_a650(adreno_gpu)) { + if (!adreno_is_a650_family(adreno_gpu)) { /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */ gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO, REG_A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x00100000); @@ -728,17 +728,20 @@ static int a6xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4); - if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu)) + if (adreno_is_a640(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); else gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0); gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); + if (adreno_is_a660(adreno_gpu)) + gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); + /* Setting the mem pool size */ gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); /* Setting the primFifo thresholds default values */ - if (adreno_is_a650(adreno_gpu)) + if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300000); else if (adreno_is_a640(adreno_gpu)) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200000); @@ -763,7 +766,7 @@ static int a6xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1); /* Set weights for bicubic filtering */ - if (adreno_is_a650(adreno_gpu)) { + if (adreno_is_a650_family(adreno_gpu)) { gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0); gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, 0x3fe05ff4); @@ -812,6 +815,13 @@ static int a6xx_hw_init(struct msm_gpu *gpu) A6XX_PROTECT_RDONLY(0x980, 0x4)); gpu_write(gpu, REG_A6XX_CP_PROTECT(25), A6XX_PROTECT_RW(0xa630, 0x0)); + if (adreno_is_a660(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1); + gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0); + /* Set dualQ + disable afull for A660 GPU but not for A635 */ + gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x66906); + } + /* Enable expanded apriv for targets that support it */ if (gpu->hw_apriv) { gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL, @@ -1488,7 +1498,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) */ info = adreno_info(config->rev); - if (info && info->revn == 650) + if (info && (info->revn == 650 || info->revn == 660)) adreno_gpu->base.hw_apriv = true; a6xx_llc_slices_init(pdev, a6xx_gpu); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c index ccd44d0418f8..919433732b43 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c @@ -351,6 +351,37 @@ static void a650_build_bw_table(struct a6xx_hfi_msg_bw_table *msg) msg->cnoc_cmds_data[1][0] = 0x60000001; } +static void a660_build_bw_table(struct a6xx_hfi_msg_bw_table *msg) +{ + /* + * Send a single "off" entry just to get things running + * TODO: bus scaling + */ + msg->bw_level_num = 1; + + msg->ddr_cmds_num = 3; + msg->ddr_wait_bitmask = 0x01; + + msg->ddr_cmds_addrs[0] = 0x50004; + msg->ddr_cmds_addrs[1] = 0x500a0; + msg->ddr_cmds_addrs[2] = 0x50000; + + msg->ddr_cmds_data[0][0] = 0x40000000; + msg->ddr_cmds_data[0][1] = 0x40000000; + msg->ddr_cmds_data[0][2] = 0x40000000; + + /* + * These are the CX (CNOC) votes - these are used by the GMU but the + * votes are known and fixed for the target + */ + msg->cnoc_cmds_num = 1; + msg->cnoc_wait_bitmask = 0x01; + + msg->cnoc_cmds_addrs[0] = 0x50070; + msg->cnoc_cmds_data[0][0] = 0x40000000; + msg->cnoc_cmds_data[1][0] = 0x60000001; +} + static void a6xx_build_bw_table(struct a6xx_hfi_msg_bw_table *msg) { /* Send a single "off" entry since the 630 GMU doesn't do bus scaling */ @@ -401,6 +432,8 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu) a640_build_bw_table(&msg); else if (adreno_is_a650(adreno_gpu)) a650_build_bw_table(&msg); + else if (adreno_is_a660(adreno_gpu)) + a660_build_bw_table(&msg); else a6xx_build_bw_table(&msg); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index b3337b93be91..e4db0683d381 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -287,6 +287,18 @@ static const struct adreno_info gpulist[] = { .init = a6xx_gpu_init, .zapfw = "a650_zap.mdt", .hwcg = a650_hwcg, + }, { + .rev = ADRENO_REV(6, 6, 0, ANY_ID), + .revn = 660, + .name = "A660", + .fw = { + [ADRENO_FW_SQE] = "a660_sqe.fw", + [ADRENO_FW_GMU] = "a660_gmu.bin", + }, + .gmem = SZ_1M + SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a6xx_gpu_init, + .zapfw = "a660_zap.mdt", }, }; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 009f4c560f16..326ca3123746 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -239,7 +239,7 @@ int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value) *value = adreno_gpu->gmem; return 0; case MSM_PARAM_GMEM_BASE: - *value = !adreno_is_a650(adreno_gpu) ? 0x100000 : 0; + *value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0; return 0; case MSM_PARAM_CHIP_ID: *value = adreno_gpu->rev.patchid | diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index ccac275aa7a2..63c050919d85 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -247,6 +247,18 @@ static inline int adreno_is_a650(struct adreno_gpu *gpu) return gpu->revn == 650; } +static inline int adreno_is_a660(struct adreno_gpu *gpu) +{ + return gpu->revn == 660; +} + +/* check for a650, a660, or any derivatives */ +static inline int adreno_is_a650_family(struct adreno_gpu *gpu) +{ + return gpu->revn == 650 || gpu->revn == 620 || + gpu->revn == 660 || gpu->revn == 635; +} + int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value); const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu, const char *fwname); From patchwork Thu May 13 00:37:48 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 437394 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2E97C433ED for ; Thu, 13 May 2021 00:45:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 92823613F7 for ; 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[66.131.184.68]) by smtp.gmail.com with ESMTPSA id w16sm1204201qts.70.2021.05.12.17.39.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 May 2021 17:39:21 -0700 (PDT) From: Jonathan Marek To: freedreno@lists.freedesktop.org Cc: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Jordan Crouse , Eric Anholt , Sai Prakash Ranjan , Akhil P Oommen , Sharat Masetty , Douglas Anderson , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 4/5] drm/msm/a6xx: update a6xx_ucode_check_version for a660 Date: Wed, 12 May 2021 20:37:48 -0400 Message-Id: <20210513003811.29578-5-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20210513003811.29578-1-jonathan@marek.ca> References: <20210513003811.29578-1-jonathan@marek.ca> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Accept all SQE firmware versions for A660. Re-organize the function a bit and print an error message for unexpected GPU IDs instead of failing silently. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 36 +++++++++++++-------------- 1 file changed, 17 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 4467273e66c0..261a20076f9d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -541,6 +541,11 @@ static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu, * Targets up to a640 (a618, a630 and a640) need to check for a * microcode version that is patched to support the whereami opcode or * one that is new enough to include it by default. + * + * a650 tier targets don't need whereami but still need to be + * equal to or newer than 0.95 for other security fixes + * + * a660 targets have all the critical security fixes from the start */ if (adreno_is_a618(adreno_gpu) || adreno_is_a630(adreno_gpu) || adreno_is_a640(adreno_gpu)) { @@ -564,27 +569,20 @@ static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu, DRM_DEV_ERROR(&gpu->pdev->dev, "a630 SQE ucode is too old. Have version %x need at least %x\n", buf[0] & 0xfff, 0x190); - } else { - /* - * a650 tier targets don't need whereami but still need to be - * equal to or newer than 0.95 for other security fixes - */ - if (adreno_is_a650(adreno_gpu)) { - if ((buf[0] & 0xfff) >= 0x095) { - ret = true; - goto out; - } - - DRM_DEV_ERROR(&gpu->pdev->dev, - "a650 SQE ucode is too old. Have version %x need at least %x\n", - buf[0] & 0xfff, 0x095); + } else if (adreno_is_a650(adreno_gpu)) { + if ((buf[0] & 0xfff) >= 0x095) { + ret = true; + goto out; } - /* - * When a660 is added those targets should return true here - * since those have all the critical security fixes built in - * from the start - */ + DRM_DEV_ERROR(&gpu->pdev->dev, + "a650 SQE ucode is too old. Have version %x need at least %x\n", + buf[0] & 0xfff, 0x095); + } else if (adreno_is_a660(adreno_gpu)) { + ret = true; + } else { + DRM_DEV_ERROR(&gpu->pdev->dev, + "unknown GPU, add it to a6xx_ucode_check_version()!!\n"); } out: msm_gem_put_vaddr(obj); From patchwork Thu May 13 00:37:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 439016 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36AEDC433B4 for ; Thu, 13 May 2021 00:45:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E6EA0613F7 for ; Thu, 13 May 2021 00:45:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230265AbhEMAqz (ORCPT ); Wed, 12 May 2021 20:46:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56968 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235874AbhEMAmG (ORCPT ); Wed, 12 May 2021 20:42:06 -0400 Received: from mail-qt1-x82c.google.com (mail-qt1-x82c.google.com [IPv6:2607:f8b0:4864:20::82c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C1EAC061344 for ; Wed, 12 May 2021 17:39:28 -0700 (PDT) Received: by mail-qt1-x82c.google.com with SMTP id g13so18668204qts.4 for ; Wed, 12 May 2021 17:39:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marek-ca.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TgKjFxo4GNtA551k9IwbSEG3Ja6mAkE8h5bonM5ao9E=; b=oVAHKRN/CsCFO6Ca0g0oSy97YAiMrDlRrXdfSTmE99E386LTW4gh1ejqcjyGXsuwFq +s+CQvsJthifM1bCfKJwXdZNvH7R/TYfWL1xwttjFhaOJAjes3dUzV7aZzNzpxa/yG5+ EJVoHbPl6UTdmHXPULoWq+NgoauD6HSVawdQ7r7o9f6itNLtOT6IJm7K7cP/2lv5A9Nc 6vmPs0hAsntCpTkQCKJUanv+cP/Z4/2ikPn+xottqb+BxFFNUTxQStzjDhgHrJtAcLKV BS3UcQgUFtRtCEASeyKg2SVYWcWpKPzrZBVh0bfSG738pTM/jgOtuEMjrWCBbtTJD3wn cRZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TgKjFxo4GNtA551k9IwbSEG3Ja6mAkE8h5bonM5ao9E=; b=hyFmRl805+hx4Oa+7R4kbea1+1DDx/td0FcFuv+iWBEUDruByFuJmHB9xDWUAqL6pX 4wc21FYPdHrb5XEjbWWepIumRbW9RtaI8+mA05PXugwdoPyRW4B047nDc8xrqPSbzd9W W4NF5VlDK310V5lKQs+i0o5wtQwXk26PFRg+btb0YCdsTJUDfQRHB2OsLbX7mbuELkL6 u5tDbPHtjRYRaKTQbGBpxc0n8bMYtKQGYhHTFpAMrKBVWrwm3PZE6XgEHUBPm0PaNKUc lYQywvsw9tA8NMyUV2hTthtsnKlTlotvzN5oL1oUQNQL7BaOKBLjdAQAF1nkYbuUc4qe VbQA== X-Gm-Message-State: AOAM533KgopcbxLU+4qcPKiiz0wVKC6zYbbQYYYnYXUs6zI2EaNdMgoc 3p6LVmkbY9KWY+xECsB+H9xZiQ== X-Google-Smtp-Source: ABdhPJyzmpbHNmhnEUA/B2MVZlnr/xMDVak3h+t0SqceA73W5LaOXRES7ubMQXiJWuiakHFbrTgEeA== X-Received: by 2002:ac8:7a7d:: with SMTP id w29mr35182479qtt.357.1620866367891; Wed, 12 May 2021 17:39:27 -0700 (PDT) Received: from localhost.localdomain (modemcable068.184-131-66.mc.videotron.ca. [66.131.184.68]) by smtp.gmail.com with ESMTPSA id w16sm1204201qts.70.2021.05.12.17.39.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 May 2021 17:39:27 -0700 (PDT) From: Jonathan Marek To: freedreno@lists.freedesktop.org Cc: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Jordan Crouse , Sai Prakash Ranjan , Eric Anholt , Akhil P Oommen , Sharat Masetty , Douglas Anderson , AngeloGioacchino Del Regno , Bjorn Andersson , Shawn Guo , Konrad Dybcio , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 5/5] drm/msm/a6xx: add a660 hwcg table Date: Wed, 12 May 2021 20:37:49 -0400 Message-Id: <20210513003811.29578-6-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20210513003811.29578-1-jonathan@marek.ca> References: <20210513003811.29578-1-jonathan@marek.ca> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a660 hwcg table, ported over from downstream. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 53 ++++++++++++++++++++++ drivers/gpu/drm/msm/adreno/adreno_device.c | 1 + drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 +- 3 files changed, 55 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 261a20076f9d..d9753c62035c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -427,6 +427,59 @@ const struct adreno_reglist a650_hwcg[] = { {}, }; +const struct adreno_reglist a660_hwcg[] = { + {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, + {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, + {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, + {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, + {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, + {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, + {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, + {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222}, + {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, + {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, + {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022}, + {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, + {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, + {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, + {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, + {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, + {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, + {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, + {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, + {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222}, + {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111}, + {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, + {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, + {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, + {REG_A6XX_RBBM_ISDB_CNT, 0x00000182}, + {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000}, + {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000}, + {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, + {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, + {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}, + {}, +}; + static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index e4db0683d381..6dad8015c9a1 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -299,6 +299,7 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a6xx_gpu_init, .zapfw = "a660_zap.mdt", + .hwcg = a660_hwcg, }, }; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 63c050919d85..e6b11e6ec82d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -55,7 +55,7 @@ struct adreno_reglist { u32 value; }; -extern const struct adreno_reglist a630_hwcg[], a640_hwcg[], a650_hwcg[]; +extern const struct adreno_reglist a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[]; struct adreno_info { struct adreno_rev rev;