From patchwork Sun Jul 1 17:23:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 140714 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp3132906ljj; Sun, 1 Jul 2018 10:24:05 -0700 (PDT) X-Google-Smtp-Source: ADUXVKKT766FsVuKmZvyMiuJc6VJNNmaya8gdcqwfSskiZO6J0jc1+jOUY9uOzJUn+bXqcvr2VeI X-Received: by 2002:a17:902:89:: with SMTP id a9-v6mr22324209pla.326.1530465845310; Sun, 01 Jul 2018 10:24:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530465845; cv=none; d=google.com; s=arc-20160816; b=m7O5qCsoTBrraSES82EJymSoZ823gmi//2njJA7WbUg+YapazRIyF7lhQUpcTcUTps pKc+fiE5ACLYQlGH34RXxhBBuDCqj3rVc0q53SFtnXPYMT5hqQ/RVQkrZ/IyWy84Chu5 h5XsLf6WTX8dRAW06Gh7DDbas0HwczUHugom3k2vTexnBQKwM00yixtT/EnbZsuzez5b hKWcOEdUDhKQ1upovK7dkb9XiSPx3ss9Qvl7tK23RWPKnfynwPqNVI2n9zlGt7PfqHpy ek2sDvlSakE7QnbMUkt/z6Zy6DTDCVqdgf4iRMWtZ54oRGRVXDHxlOegdUfgMI3rUlmP 1M6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=m8j4K0OgFnkwV3OnMDuDaGpr4NaQAyDW001o+7K9wQQ=; b=hlLVP714jm3qgk5DH4qZdiwAyKRha+H1JxIy9nJItm85PBsi/9kblDkhOdO5R1UB+G /xl01CxqB5RkpHGEA3hRhJfrfI9Kcskcd7JbOCLNQdJppwTz0NsDq1smJtzw15IBNN2f S+qw0ixj4aKsfJjAbSeY21nq5i9qJP3qoD+PQi6S6ONLkc7he9ayIBdh+IrjPIMHgJHC N4lmC0ETVVp40L1Hys/ngfT2bjvz79Kncm/sMG6f6ijAxZu4JDXKkuAYFl+WukxYewSN JUNUKdTl+V7Ifz2ZmaZrlYJGUonpavI+C2vJtRyM2/p+FW+KmefvOBtZeX7In2jEoc0r NGGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=YsfNWhf8; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m18-v6si9828436pgg.693.2018.07.01.10.24.04; Sun, 01 Jul 2018 10:24:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=YsfNWhf8; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1031202AbeGARYC (ORCPT + 5 others); Sun, 1 Jul 2018 13:24:02 -0400 Received: from mail-pl0-f66.google.com ([209.85.160.66]:38222 "EHLO mail-pl0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965867AbeGARX6 (ORCPT ); Sun, 1 Jul 2018 13:23:58 -0400 Received: by mail-pl0-f66.google.com with SMTP id d10-v6so6802084plo.5 for ; Sun, 01 Jul 2018 10:23:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=G9Pra/HIrTIdZzogTmPr0pWDqZgp6mkljxVwg8UNDhk=; b=YsfNWhf8iMxCGRYDJ9O4Pqs0HloPgbMBO0z3Bj2JC2qYpcKnlfY3+17XhH3hHvkMt3 J42cVf5kHo7uPGoTzlmq9Hwj7XZgO0J5E+tVGI1HuO3Hb3Ia3hNHX2vqhgVvDjLarsUl RhmGSIQDJwGObo+PuJU2Sv38mL6zJY5FSyk9I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=G9Pra/HIrTIdZzogTmPr0pWDqZgp6mkljxVwg8UNDhk=; b=ZhpTXZ8kfGcoILiFsd0/pKN/ZaQc39Bdc6E+F8xZ1nWITY7sqMLeyJrOE9SDKR7mIK SbcpgeAfhkCnQ2uSRFsMTUWw4c1EyAT8Sc8IS3KHy0+4VSqyDcfB8AKn3a3oD658SCr/ pu9CGrqpqIJ0E6NnpDRKyFX5w1GuPmVnJ8UodFUT4bxNOlKbuPYdsradRVuCrgmTSUga DAV4W0v+wnj7Poa4f0ZIoiSQ+q+Wq2SYsyG00Utek4BCPPwgmtMr4+V5jx3ykA7YVnNZ GyjT9Lfz6FwklUNAthjA9rrOZsChh967NgQi3q93zQayM9OfriWNxp2075SnvC5s8m7x vkTw== X-Gm-Message-State: APt69E1ZCR8H+YzhnvvE1V0OUolFB2tfbaAjM1gi5rHW2YVl587GY6gs pqqFZKq27FxE59fQaCLYmet/ X-Received: by 2002:a17:902:b418:: with SMTP id x24-v6mr22792424plr.2.1530465837721; Sun, 01 Jul 2018 10:23:57 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:900:ea77:2c06:3367:1893:796]) by smtp.gmail.com with ESMTPSA id f10-v6sm17989836pgr.30.2018.07.01.10.23.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 01 Jul 2018 10:23:57 -0700 (PDT) From: Manivannan Sadhasivam To: wsa@the-dreams.de, robh+dt@kernel.org, afaerber@suse.de Cc: linus.walleij@linaro.org, linux-i2c@vger.kernel.org, liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, andy.shevchenko@gmail.com, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, thomas.liau@actions-semi.com, jeff.chen@actions-semi.com, Manivannan Sadhasivam Subject: [PATCH v4 2/6] arm64: dts: actions: Add pinctrl definition for S900 I2C controller Date: Sun, 1 Jul 2018 22:53:01 +0530 Message-Id: <20180701172305.15663-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180701172305.15663-1-manivannan.sadhasivam@linaro.org> References: <20180701172305.15663-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add pinctrl definition for Actions Semiconductor S900 I2C controller. Pinctrl definitions are only available for I2C0, I2C1, and I2C2. Signed-off-by: Manivannan Sadhasivam --- .../dts/actions/s900-bubblegum-96-pins.dtsi | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 arch/arm64/boot/dts/actions/s900-bubblegum-96-pins.dtsi -- 2.17.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96-pins.dtsi b/arch/arm64/boot/dts/actions/s900-bubblegum-96-pins.dtsi new file mode 100644 index 000000000000..95e8b31071f9 --- /dev/null +++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96-pins.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +&pinctrl { + + i2c0_default: i2c0_default { + pinmux { + groups = "i2c0_mfp"; + function = "i2c0"; + }; + pinconf { + pins = "i2c0_sclk", "i2c0_sdata"; + bias-pull-up; + }; + }; + + i2c1_default: i2c1_default { + pinconf { + pins = "i2c1_sclk", "i2c1_sdata"; + bias-pull-up; + }; + }; + + i2c2_default: i2c2_default { + pinconf { + pins = "i2c2_sclk", "i2c2_sdata"; + bias-pull-up; + }; + }; +}; From patchwork Sun Jul 1 17:23:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 140716 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp3133268ljj; Sun, 1 Jul 2018 10:24:38 -0700 (PDT) X-Google-Smtp-Source: ADUXVKI8yaCmQg6YPceOMqyR1lwUZPux2WnzUhahAyDd268kBu2ALVEOA0LrG4fPgsFSzyA6iJFL X-Received: by 2002:a17:902:850b:: with SMTP id bj11-v6mr22682432plb.210.1530465878191; Sun, 01 Jul 2018 10:24:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1530465878; cv=none; d=google.com; s=arc-20160816; b=zk7KocBKeuGJlYcL0VrN5lSQQLQhdFFWpm/hFhDN6bgxAJaUj9YTkHfPECYGFMao4K 4Z2TQe9l/xOhqeCQ0p5Nc72iC7TjaS4aHFQINYPj1bOJKI+14Ah6XPOGqXbZHmtkIxM2 ueXun3yGv9fDBns1FRnBUjDkx7VnTrCpef/nV00E+WvZWmbFoe/pXcE9BMfdN09Xd29w ByM/9ksvVhpmyOibMP5H1NvuKp3vayPJJrAKc7qThh7MC3upre/AG/Z22JbbK8MHOgnl muXq0Uul/7a/Mm52KmpRJGkQ5cZBsrphvZOMVeSYpsoe82IwLKZhzAF/SMQa4fIW0Be0 oR+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=NyzItzC7kivkyFlDty35ii03Bw2yPPuhyFaUEYLieJM=; b=kJ2ZmAV68kEK/BaW3WPN0aL1wBtT9cKb+1sqbIu+md+FdgHFwdVYhefDKLN5stB/UR fRRHUBCZWOg227I2kQRXX/GkKX8nSC3js8Juii0tRF28YTYVdA+4AcJLwXmh/j8xC8Wf YYmk+2DNFDfe52038wAf1TbVARvf6UTA5cx3QDDW/gu2GChZNOXvqoIeNMZbGrxfDNda ZdJXQPezzOG74zlutI+41GOUJptv0SZrD7Oy6CpINAZzp4om7KxAChFS2RIVB9XzAfE9 CT5YuQrpjvShvegnp4Tf369E/71EBaBnc+YxpZBtAnlg0tBE2uHDt6za0FhWCn+F4gdq 4mKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b="X9WsC+5/"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c13-v6si12223124pgq.316.2018.07.01.10.24.37; Sun, 01 Jul 2018 10:24:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b="X9WsC+5/"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1031489AbeGARYf (ORCPT + 5 others); Sun, 1 Jul 2018 13:24:35 -0400 Received: from mail-pg0-f68.google.com ([74.125.83.68]:40872 "EHLO mail-pg0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030847AbeGARYd (ORCPT ); Sun, 1 Jul 2018 13:24:33 -0400 Received: by mail-pg0-f68.google.com with SMTP id w8-v6so6080535pgp.7 for ; Sun, 01 Jul 2018 10:24:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UhiR7H08wCxqg5M0uiiOTDPE7OFq/XiHgBLjQbg5BS0=; b=X9WsC+5/5aoaXVhDU3e0idOWYnADv6iaOmVw5a5cChQYcLR5S2pYKO+Jpuyob/iofB gfliH5JvZEsSYCr9SjAZ9hrz84wrdnyV7Vnc45ux4+mMFDNYigUAr6NuWLRLQJ0PORfx PAaRZpHcfUP/6+sQU1iVAnuF9ZsDDh9zJXiYU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UhiR7H08wCxqg5M0uiiOTDPE7OFq/XiHgBLjQbg5BS0=; b=S3Xuofee/f8Bw1h+LFm7+OfhDt6+YMNouOylHO7lfXRAwRHQQXXHMGbAyHLODCY2W8 zk/4DUSFSS1edRC4vuJNY9Pc69iN4mIOu9WlBmHLdvzVeedR3B26y9D2vmFZ1FSGfVB/ RzZUalP+AXPCDoUOmFXaa5LkhA28OnDaUDkAHCzCSfhi8tVRg9194ziS7nLreSroEmE5 IhsdkUo0XasVceICI9IsmBMHIgkAVwtx9j18SNgSmWsbEeJRC+HhWVAJ0mL0zlkZxElU MoczqugDofmcXkp6ws7SkTj0tXDeDqTQL1leTe6TJVYzPSOBPaieIRDLdzk+3HapGRVc u1SQ== X-Gm-Message-State: APt69E3EBlVAdNq66eZ6yxZiKYyNZXtRjKGcUeIRuoSTPTZSjBVX/zkQ TgZzrtObiVnTnvGRtpTZ1+vB X-Received: by 2002:aa7:8713:: with SMTP id b19-v6mr14461052pfo.151.1530465872755; Sun, 01 Jul 2018 10:24:32 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:900:ea77:2c06:3367:1893:796]) by smtp.gmail.com with ESMTPSA id f10-v6sm17989836pgr.30.2018.07.01.10.24.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 01 Jul 2018 10:24:32 -0700 (PDT) From: Manivannan Sadhasivam To: wsa@the-dreams.de, robh+dt@kernel.org, afaerber@suse.de Cc: linus.walleij@linaro.org, linux-i2c@vger.kernel.org, liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, andy.shevchenko@gmail.com, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, thomas.liau@actions-semi.com, jeff.chen@actions-semi.com, Manivannan Sadhasivam Subject: [PATCH v4 5/6] i2c: Add Actions Semiconductor Owl family S900 I2C driver Date: Sun, 1 Jul 2018 22:53:04 +0530 Message-Id: <20180701172305.15663-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180701172305.15663-1-manivannan.sadhasivam@linaro.org> References: <20180701172305.15663-1-manivannan.sadhasivam@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add Actions Semiconductor Owl family S900 I2C driver. Signed-off-by: Manivannan Sadhasivam --- drivers/i2c/busses/Kconfig | 7 + drivers/i2c/busses/Makefile | 1 + drivers/i2c/busses/i2c-owl.c | 504 +++++++++++++++++++++++++++++++++++ 3 files changed, 512 insertions(+) create mode 100644 drivers/i2c/busses/i2c-owl.c -- 2.17.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 4f8df2ec87b1..8c8025f87ce4 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -762,6 +762,13 @@ config I2C_OMAP Like OMAP1510/1610/1710/5912 and OMAP242x. For details see http://www.ti.com/omap. +config I2C_OWL + tristate "Actions Semiconductor Owl I2C Controller" + depends on ARCH_ACTIONS || COMPILE_TEST + help + Say Y here if you want to use the I2C bus controller on + the Actions Semiconductor Owl SoC's. + config I2C_PASEMI tristate "PA Semi SMBus interface" depends on PPC_PASEMI && PCI diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 5a869144a0c5..b71618f77880 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -76,6 +76,7 @@ obj-$(CONFIG_I2C_MXS) += i2c-mxs.o obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o obj-$(CONFIG_I2C_OCORES) += i2c-ocores.o obj-$(CONFIG_I2C_OMAP) += i2c-omap.o +obj-$(CONFIG_I2C_OWL) += i2c-owl.o obj-$(CONFIG_I2C_PASEMI) += i2c-pasemi.o obj-$(CONFIG_I2C_PCA_PLATFORM) += i2c-pca-platform.o obj-$(CONFIG_I2C_PMCMSP) += i2c-pmcmsp.o diff --git a/drivers/i2c/busses/i2c-owl.c b/drivers/i2c/busses/i2c-owl.c new file mode 100644 index 000000000000..580f8d092302 --- /dev/null +++ b/drivers/i2c/busses/i2c-owl.c @@ -0,0 +1,504 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Actions Semiconductor Owl SoC's I2C driver + * + * Copyright (c) 2014 Actions Semi Inc. + * Author: David Liu + * + * Copyright (c) 2018 Linaro Ltd. + * Author: Manivannan Sadhasivam + */ + +#include +#include +#include +#include +#include +#include +#include + +/* I2C registers */ +#define OWL_I2C_REG_CTL 0x0000 +#define OWL_I2C_REG_CLKDIV 0x0004 +#define OWL_I2C_REG_STAT 0x0008 +#define OWL_I2C_REG_ADDR 0x000C +#define OWL_I2C_REG_TXDAT 0x0010 +#define OWL_I2C_REG_RXDAT 0x0014 +#define OWL_I2C_REG_CMD 0x0018 +#define OWL_I2C_REG_FIFOCTL 0x001C +#define OWL_I2C_REG_FIFOSTAT 0x0020 +#define OWL_I2C_REG_DATCNT 0x0024 +#define OWL_I2C_REG_RCNT 0x0028 + +/* I2Cx_CTL Bit Mask */ +#define OWL_I2C_CTL_RB BIT(1) +#define OWL_I2C_CTL_GBCC(x) (((x) & 0x3) << 2) +#define OWL_I2C_CTL_GBCC_NONE OWL_I2C_CTL_GBCC(0) +#define OWL_I2C_CTL_GBCC_START OWL_I2C_CTL_GBCC(1) +#define OWL_I2C_CTL_GBCC_STOP OWL_I2C_CTL_GBCC(2) +#define OWL_I2C_CTL_GBCC_RSTART OWL_I2C_CTL_GBCC(3) +#define OWL_I2C_CTL_IRQE BIT(5) +#define OWL_I2C_CTL_EN BIT(7) +#define OWL_I2C_CTL_AE BIT(8) +#define OWL_I2C_CTL_SHSM BIT(10) + +#define OWL_I2C_DIV_FACTOR(x) ((x) & 0xff) + +/* I2Cx_STAT Bit Mask */ +#define OWL_I2C_STAT_RACK BIT(0) +#define OWL_I2C_STAT_BEB BIT(1) +#define OWL_I2C_STAT_IRQP BIT(2) +#define OWL_I2C_STAT_LAB BIT(3) +#define OWL_I2C_STAT_STPD BIT(4) +#define OWL_I2C_STAT_STAD BIT(5) +#define OWL_I2C_STAT_BBB BIT(6) +#define OWL_I2C_STAT_TCB BIT(7) +#define OWL_I2C_STAT_LBST BIT(8) +#define OWL_I2C_STAT_SAMB BIT(9) +#define OWL_I2C_STAT_SRGC BIT(10) + +/* I2Cx_CMD Bit Mask */ +#define OWL_I2C_CMD_SBE BIT(0) +#define OWL_I2C_CMD_RBE BIT(4) +#define OWL_I2C_CMD_DE BIT(8) +#define OWL_I2C_CMD_NS BIT(9) +#define OWL_I2C_CMD_SE BIT(10) +#define OWL_I2C_CMD_MSS BIT(11) +#define OWL_I2C_CMD_WRS BIT(12) +#define OWL_I2C_CMD_SECL BIT(15) + +#define OWL_I2C_CMD_AS(x) (((x) & 0x7) << 1) +#define OWL_I2C_CMD_SAS(x) (((x) & 0x7) << 5) + +/* I2Cx_FIFOCTL Bit Mask */ +#define OWL_I2C_FIFOCTL_NIB BIT(0) +#define OWL_I2C_FIFOCTL_RFR BIT(1) +#define OWL_I2C_FIFOCTL_TFR BIT(2) + +/* I2Cc_FIFOSTAT Bit Mask */ +#define OWL_I2C_FIFOSTAT_RNB BIT(1) +#define OWL_I2C_FIFOSTAT_RFE BIT(2) +#define OWL_I2C_FIFOSTAT_TFF BIT(5) +#define OWL_I2C_FIFOSTAT_TFD GENMASK(23, 16) +#define OWL_I2C_FIFOSTAT_RFD GENMASK(15, 8) + +/* I2C bus timeout */ +#define OWL_I2C_TIMEOUT msecs_to_jiffies(4 * 1000) + +#define OWL_I2C_MAX_RETRIES 50 + +#define OWL_I2C_DEF_SPEED_HZ 100000 +#define OWL_I2C_MAX_SPEED_HZ 400000 + +struct owl_i2c_dev { + struct i2c_adapter adap; + struct i2c_msg *msg; + struct completion msg_complete; + struct clk *clk; + spinlock_t lock; + void __iomem *base; + unsigned long clk_rate; + u32 bus_freq; + u32 msg_ptr; +}; + +static void owl_i2c_update_reg(void __iomem *reg, unsigned int val, bool state) +{ + unsigned int regval; + + regval = readl(reg); + + if (state) + regval |= val; + else + regval &= ~val; + + writel(regval, reg); +} + +static void owl_i2c_reset(struct owl_i2c_dev *i2c_dev) +{ + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, + OWL_I2C_CTL_EN, false); + mdelay(1); + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, + OWL_I2C_CTL_EN, true); + + /* Clear status registers */ + writel(0, i2c_dev->base + OWL_I2C_REG_STAT); +} + +static int owl_i2c_reset_fifo(struct owl_i2c_dev *i2c_dev) +{ + unsigned int val, timeout = 0; + + /* Reset FIFO */ + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, + OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR, + true); + + /* Wait 50ms for FIFO reset complete */ + do { + val = readl(i2c_dev->base + OWL_I2C_REG_FIFOCTL); + if (!(val & (OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR))) + break; + usleep_range(500, 1000); + } while (timeout++ < OWL_I2C_MAX_RETRIES); + + if (timeout > OWL_I2C_MAX_RETRIES) { + dev_err(&i2c_dev->adap.dev, "FIFO reset timeout"); + return -ETIMEDOUT; + } + + return 0; +} + +static void owl_i2c_set_freq(struct owl_i2c_dev *i2c_dev) +{ + unsigned int val; + + val = DIV_ROUND_UP(i2c_dev->clk_rate, i2c_dev->bus_freq * 16); + + /* Set clock divider factor */ + writel(OWL_I2C_DIV_FACTOR(val), i2c_dev->base + OWL_I2C_REG_CLKDIV); +} + +static irqreturn_t owl_i2c_interrupt(int irq, void *_dev) +{ + struct owl_i2c_dev *i2c_dev = _dev; + struct i2c_msg *msg = i2c_dev->msg; + unsigned long flags; + unsigned int stat, fifostat; + + spin_lock_irqsave(&i2c_dev->lock, flags); + + fifostat = readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT); + if (fifostat & OWL_I2C_FIFOSTAT_RNB) { + dev_dbg(&i2c_dev->adap.dev, "received NACK from device"); + goto stop; + } + + stat = readl(i2c_dev->base + OWL_I2C_REG_STAT); + if (stat & OWL_I2C_STAT_BEB) { + dev_dbg(&i2c_dev->adap.dev, "bus error"); + goto stop; + } + + /* Handle FIFO read */ + if (msg->flags & I2C_M_RD) { + while ((readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) & + OWL_I2C_FIFOSTAT_RFE) && + (i2c_dev->msg_ptr < msg->len)) { + msg->buf[i2c_dev->msg_ptr++] = readl(i2c_dev->base + + OWL_I2C_REG_RXDAT); + } + } else { + /* Handle the remaining bytes which were not sent */ + while (!(readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) & + OWL_I2C_FIFOSTAT_TFF) && + i2c_dev->msg_ptr < msg->len) { + writel(msg->buf[i2c_dev->msg_ptr++], i2c_dev->base + + OWL_I2C_REG_TXDAT); + } + } + +stop: + /* Clear pending interrupts */ + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT, + OWL_I2C_STAT_IRQP, true); + + complete_all(&i2c_dev->msg_complete); + spin_unlock_irqrestore(&i2c_dev->lock, flags); + + return IRQ_HANDLED; +} + +static u32 owl_i2c_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static int owl_i2c_check_bus_busy(struct i2c_adapter *adap) +{ + struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap); + unsigned long timeout; + + /* Check for Bus busy */ + timeout = jiffies + OWL_I2C_TIMEOUT; + while (readl(i2c_dev->base + OWL_I2C_REG_STAT) & OWL_I2C_STAT_BBB) { + if (time_after(jiffies, timeout)) { + dev_err(&adap->dev, "Bus busy timeout"); + return -ETIMEDOUT; + } + } + + return 0; +} + +static int owl_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, + int num) +{ + struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap); + struct i2c_msg *msg; + unsigned long time_left, flags; + unsigned int i2c_cmd, val; + unsigned int addr; + int ret, idx; + + spin_lock_irqsave(&i2c_dev->lock, flags); + + /* Reset I2C controller */ + owl_i2c_reset(i2c_dev); + + /* Set bus frequency */ + owl_i2c_set_freq(i2c_dev); + + /* + * Spinlock should be released before calling reset FIFO and + * bus busy check since those functions may sleep + */ + spin_unlock_irqrestore(&i2c_dev->lock, flags); + + /* Reset FIFO */ + ret = owl_i2c_reset_fifo(i2c_dev); + if (ret) { + /* Disable I2C controller */ + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, + OWL_I2C_CTL_EN, false); + return ret; + } + + /* Check for bus busy */ + ret = owl_i2c_check_bus_busy(adap); + if (ret) { + /* Disable I2C controller */ + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, + OWL_I2C_CTL_EN, false); + return ret; + } + + spin_lock_irqsave(&i2c_dev->lock, flags); + + /* Check for Arbitration lost */ + val = readl(i2c_dev->base + OWL_I2C_REG_STAT); + if (val & OWL_I2C_STAT_LAB) { + val &= ~OWL_I2C_STAT_LAB; + writel(val, i2c_dev->base + OWL_I2C_REG_STAT); + ret = -EAGAIN; + goto err_exit; + } + + reinit_completion(&i2c_dev->msg_complete); + + /* Enable I2C controller interrupt */ + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, + OWL_I2C_CTL_IRQE, true); + + /* + * Select: FIFO enable, Master mode, Stop enable, Data count enable, + * Send start bit + */ + i2c_cmd = (OWL_I2C_CMD_SECL | OWL_I2C_CMD_MSS | OWL_I2C_CMD_SE + | OWL_I2C_CMD_NS | OWL_I2C_CMD_DE | OWL_I2C_CMD_SBE); + + /* Handle repeated start condition */ + if (num > 1) { + /* Set internal address length and enable repeated start */ + i2c_cmd |= (OWL_I2C_CMD_AS(msgs[0].len + 1) + | OWL_I2C_CMD_SAS(1) | OWL_I2C_CMD_RBE); + + /* Write slave address */ + addr = i2c_8bit_addr_from_msg(&msgs[0]); + writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT); + + /* Write internal register address */ + for (idx = 0; idx < msgs[0].len; idx++) + writel(msgs[0].buf[idx], i2c_dev->base + + OWL_I2C_REG_TXDAT); + + msg = &msgs[1]; + } else { + /* Set address length */ + i2c_cmd |= OWL_I2C_CMD_AS(1); + msg = &msgs[0]; + } + + i2c_dev->msg = msg; + i2c_dev->msg_ptr = 0; + + /* Set data count for the message */ + writel(msg->len, i2c_dev->base + OWL_I2C_REG_DATCNT); + + addr = i2c_8bit_addr_from_msg(msg); + writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT); + + if (!(msg->flags & I2C_M_RD)) { + /* Write data to FIFO */ + for (idx = 0; idx < msg->len; idx++) { + /* Check for FIFO full */ + if (readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) + & OWL_I2C_FIFOSTAT_TFF) + break; + + writel(msg->buf[idx], + i2c_dev->base + OWL_I2C_REG_TXDAT); + } + + i2c_dev->msg_ptr = idx; + } + + /* Ignore the NACK if needed */ + if (msg->flags & I2C_M_IGNORE_NAK) + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, + OWL_I2C_FIFOCTL_NIB, true); + else + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, + OWL_I2C_FIFOCTL_NIB, false); + + /* Start the transfer */ + writel(i2c_cmd, i2c_dev->base + OWL_I2C_REG_CMD); + + spin_unlock_irqrestore(&i2c_dev->lock, flags); + + time_left = wait_for_completion_timeout(&i2c_dev->msg_complete, + adap->timeout); + + spin_lock_irqsave(&i2c_dev->lock, flags); + if (time_left == 0) { + dev_err(&adap->dev, "Transaction timed out"); + /* Send stop condition and release the bus */ + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, + OWL_I2C_CTL_GBCC_STOP | OWL_I2C_CTL_RB, true); + ret = -ETIMEDOUT; + goto err_exit; + } + + /* + * Here, -ENXIO will be returned if interrupt occurred but no + * read or write happened. Else if msg_ptr equals to message length, + * message count will be returned. + */ + ret = (i2c_dev->msg_ptr == msg->len) ? num : -ENXIO; + +err_exit: + + /* Disable I2C controller */ + owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, + OWL_I2C_CTL_EN, false); + + spin_unlock_irqrestore(&i2c_dev->lock, flags); + + return ret; +} + +static const struct i2c_algorithm owl_i2c_algorithm = { + .master_xfer = owl_i2c_master_xfer, + .functionality = owl_i2c_func, +}; + +static const struct i2c_adapter_quirks owl_i2c_quirks = { + .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST, + .max_read_len = 240, + .max_write_len = 240, + .max_comb_1st_msg_len = 6, + .max_comb_2nd_msg_len = 240, +}; + +static int owl_i2c_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct owl_i2c_dev *i2c_dev; + struct resource *res; + int ret, irq; + + i2c_dev = devm_kzalloc(dev, sizeof(*i2c_dev), GFP_KERNEL); + if (!i2c_dev) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + i2c_dev->base = devm_ioremap_resource(dev, res); + if (IS_ERR(i2c_dev->base)) + return PTR_ERR(i2c_dev->base); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(dev, "failed to get IRQ number\n"); + return irq; + } + + if (of_property_read_u32(dev->of_node, "clock-frequency", + &i2c_dev->bus_freq)) + i2c_dev->bus_freq = OWL_I2C_DEF_SPEED_HZ; + + /* We support only frequencies of 100k and 400k for now */ + if (i2c_dev->bus_freq != OWL_I2C_DEF_SPEED_HZ && + i2c_dev->bus_freq != OWL_I2C_MAX_SPEED_HZ) { + dev_err(dev, "invalid clock-frequency %d\n", i2c_dev->bus_freq); + return -EINVAL; + } + + i2c_dev->clk = devm_clk_get(dev, NULL); + if (IS_ERR(i2c_dev->clk)) { + dev_err(dev, "failed to get clock\n"); + return PTR_ERR(i2c_dev->clk); + } + + ret = clk_prepare_enable(i2c_dev->clk); + if (ret) + return ret; + + i2c_dev->clk_rate = clk_get_rate(i2c_dev->clk); + if (!i2c_dev->clk_rate) { + dev_err(dev, "input clock rate should not be zero\n"); + ret = -EINVAL; + goto disable_clk; + } + + init_completion(&i2c_dev->msg_complete); + spin_lock_init(&i2c_dev->lock); + i2c_dev->adap.owner = THIS_MODULE; + i2c_dev->adap.algo = &owl_i2c_algorithm; + i2c_dev->adap.timeout = OWL_I2C_TIMEOUT; + i2c_dev->adap.quirks = &owl_i2c_quirks; + i2c_dev->adap.dev.parent = dev; + i2c_dev->adap.dev.of_node = dev->of_node; + snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name), + "%s", "OWL I2C adapter"); + i2c_set_adapdata(&i2c_dev->adap, i2c_dev); + + platform_set_drvdata(pdev, i2c_dev); + + ret = devm_request_irq(dev, irq, owl_i2c_interrupt, 0, pdev->name, + i2c_dev); + if (ret) { + dev_err(dev, "failed to request irq %d\n", irq); + goto disable_clk; + } + + return i2c_add_adapter(&i2c_dev->adap); + +disable_clk: + clk_disable_unprepare(i2c_dev->clk); + + return ret; +} + +static const struct of_device_id owl_i2c_of_match[] = { + {.compatible = "actions,s900-i2c"}, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, owl_i2c_of_match); + +static struct platform_driver owl_i2c_driver = { + .probe = owl_i2c_probe, + .driver = { + .name = "owl-i2c", + .of_match_table = of_match_ptr(owl_i2c_of_match), + }, +}; +module_platform_driver(owl_i2c_driver); + +MODULE_AUTHOR("David Liu "); +MODULE_AUTHOR("Manivannan Sadhasivam "); +MODULE_DESCRIPTION("Actions Semiconductor Owl SoC's I2C driver"); +MODULE_LICENSE("GPL");