From patchwork Tue May 2 10:08:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 98432 Delivered-To: patch@linaro.org Received: by 10.140.109.52 with SMTP id k49csp1794318qgf; Tue, 2 May 2017 03:10:08 -0700 (PDT) X-Received: by 10.84.176.100 with SMTP id u91mr40186859plb.39.1493719808149; Tue, 02 May 2017 03:10:08 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[45.125.195.13]) by smtp.gmail.com with ESMTPSA id 70sm29713046pfk.49.2017.05.02.03.09.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 02 May 2017 03:09:31 -0700 (PDT) From: Leo Yan To: Jonathan Corbet , Rob Herring , Mark Rutland , Wei Xu , Catalin Marinas , Will Deacon , Andy Gross , David Brown , Mathieu Poirier , Greg Kroah-Hartman , Suzuki K Poulose , Stephen Boyd , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, Mike Leach , Sudeep Holla Cc: Leo Yan Subject: [PATCH v8 1/7] coresight: bindings for CPU debug module Date: Tue, 2 May 2017 18:08:31 +0800 Message-Id: <1493719717-27698-2-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1493719717-27698-1-git-send-email-leo.yan@linaro.org> References: <1493719717-27698-1-git-send-email-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org According to ARMv8 architecture reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate debug module and it can support self-hosted debug and external debug. Especially for supporting self-hosted debug, this means the program can access the debug module from mmio region; and usually the mmio region is integrated with coresight. So add document for binding debug component, includes binding to APB clock; and also need specify the CPU node which the debug module is dedicated to specific CPU. Suggested-by: Mike Leach Reviewed-by: Mathieu Poirier Reviewed-by: Suzuki K Poulose Acked-by: Rob Herring Signed-off-by: Leo Yan --- .../bindings/arm/coresight-cpu-debug.txt | 49 ++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt -- 2.7.4 diff --git a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt new file mode 100644 index 0000000..2982912 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt @@ -0,0 +1,49 @@ +* CoreSight CPU Debug Component: + +CoreSight CPU debug component are compliant with the ARMv8 architecture +reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The +external debug module is mainly used for two modes: self-hosted debug and +external debug, and it can be accessed from mmio region from Coresight +and eventually the debug module connects with CPU for debugging. And the +debug module provides sample-based profiling extension, which can be used +to sample CPU program counter, secure state and exception level, etc; +usually every CPU has one dedicated debug module to be connected. + +Required properties: + +- compatible : should be "arm,coresight-cpu-debug"; supplemented with + "arm,primecell" since this driver is using the AMBA bus + interface. + +- reg : physical base address and length of the register set. + +- clocks : the clock associated to this component. + +- clock-names : the name of the clock referenced by the code. Since we are + using the AMBA framework, the name of the clock providing + the interconnect should be "apb_pclk" and the clock is + mandatory. The interface between the debug logic and the + processor core is clocked by the internal CPU clock, so it + is enabled with CPU clock by default. + +- cpu : the CPU phandle the debug module is affined to. When omitted + the module is considered to belong to CPU0. + +Optional properties: + +- power-domains: a phandle to the debug power domain. We use "power-domains" + binding to turn on the debug logic if it has own dedicated + power domain and if necessary to use "cpuidle.off=1" or + "nohlt" in the kernel command line or sysfs node to + constrain idle states to ensure registers in the CPU power + domain are accessible. + +Example: + + debug@f6590000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0 0xf6590000 0 0x1000>; + clocks = <&sys_ctrl HI6220_DAPB_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + }; From patchwork Tue May 2 10:08:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 98437 Delivered-To: patch@linaro.org Received: by 10.140.109.52 with SMTP id k49csp1794632qgf; Tue, 2 May 2017 03:10:54 -0700 (PDT) X-Received: by 10.98.139.208 with SMTP id e77mr30620239pfl.64.1493719854469; Tue, 02 May 2017 03:10:54 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[45.125.195.13]) by smtp.gmail.com with ESMTPSA id 70sm29713046pfk.49.2017.05.02.03.10.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 02 May 2017 03:10:39 -0700 (PDT) From: Leo Yan To: Jonathan Corbet , Rob Herring , Mark Rutland , Wei Xu , Catalin Marinas , Will Deacon , Andy Gross , David Brown , Mathieu Poirier , Greg Kroah-Hartman , Suzuki K Poulose , Stephen Boyd , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, Mike Leach , Sudeep Holla Cc: Leo Yan Subject: [PATCH v8 6/7] arm64: dts: hi6220: register debug module Date: Tue, 2 May 2017 18:08:36 +0800 Message-Id: <1493719717-27698-7-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1493719717-27698-1-git-send-email-leo.yan@linaro.org> References: <1493719717-27698-1-git-send-email-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Bind debug module driver for Hi6220. Signed-off-by: Leo Yan --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 64 +++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) -- 2.7.4 diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 470461d..467aa15 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -913,5 +913,69 @@ }; }; }; + + debug@f6590000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0 0xf6590000 0 0x1000>; + clocks = <&sys_ctrl HI6220_DAPB_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + }; + + debug@f6592000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0 0xf6592000 0 0x1000>; + clocks = <&sys_ctrl HI6220_DAPB_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu1>; + }; + + debug@f6594000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0 0xf6594000 0 0x1000>; + clocks = <&sys_ctrl HI6220_DAPB_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu2>; + }; + + debug@f6596000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0 0xf6596000 0 0x1000>; + clocks = <&sys_ctrl HI6220_DAPB_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu3>; + }; + + debug@f65d0000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0 0xf65d0000 0 0x1000>; + clocks = <&sys_ctrl HI6220_DAPB_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu4>; + }; + + debug@f65d2000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0 0xf65d2000 0 0x1000>; + clocks = <&sys_ctrl HI6220_DAPB_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu5>; + }; + + debug@f65d4000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0 0xf65d4000 0 0x1000>; + clocks = <&sys_ctrl HI6220_DAPB_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu6>; + }; + + debug@f65d6000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0 0xf65d6000 0 0x1000>; + clocks = <&sys_ctrl HI6220_DAPB_CLK>; + clock-names = "apb_pclk"; + cpu = <&cpu7>; + }; }; }; From patchwork Tue May 2 10:08:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 98438 Delivered-To: patch@linaro.org Received: by 10.140.109.52 with SMTP id k49csp1794712qgf; Tue, 2 May 2017 03:11:07 -0700 (PDT) X-Received: by 10.98.155.28 with SMTP id r28mr1198100pfd.198.1493719867406; Tue, 02 May 2017 03:11:07 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[45.125.195.13]) by smtp.gmail.com with ESMTPSA id 70sm29713046pfk.49.2017.05.02.03.10.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 02 May 2017 03:10:52 -0700 (PDT) From: Leo Yan To: Jonathan Corbet , Rob Herring , Mark Rutland , Wei Xu , Catalin Marinas , Will Deacon , Andy Gross , David Brown , Mathieu Poirier , Greg Kroah-Hartman , Suzuki K Poulose , Stephen Boyd , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, Mike Leach , Sudeep Holla Cc: Leo Yan Subject: [PATCH v8 7/7] arm64: dts: qcom: msm8916: Add debug unit Date: Tue, 2 May 2017 18:08:37 +0800 Message-Id: <1493719717-27698-8-git-send-email-leo.yan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1493719717-27698-1-git-send-email-leo.yan@linaro.org> References: <1493719717-27698-1-git-send-email-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add debug unit on Qualcomm msm8916 based platforms, including the DragonBoard 410c board. Signed-off-by: Leo Yan --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) -- 2.7.4 diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 68a8e67..3af814b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1104,6 +1104,38 @@ }; }; + debug@850000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0x850000 0x1000>; + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + cpu = <&CPU0>; + }; + + debug@852000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0x852000 0x1000>; + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + cpu = <&CPU1>; + }; + + debug@854000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0x854000 0x1000>; + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + cpu = <&CPU2>; + }; + + debug@856000 { + compatible = "arm,coresight-cpu-debug","arm,primecell"; + reg = <0x856000 0x1000>; + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + cpu = <&CPU3>; + }; + etm@85c000 { compatible = "arm,coresight-etm4x", "arm,primecell"; reg = <0x85c000 0x1000>;