From patchwork Wed May 3 09:56:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Tucker X-Patchwork-Id: 98479 Delivered-To: patch@linaro.org Received: by 10.140.89.200 with SMTP id v66csp216760qgd; Wed, 3 May 2017 02:57:30 -0700 (PDT) X-Received: by 10.98.15.73 with SMTP id x70mr3884896pfi.86.1493805450032; Wed, 03 May 2017 02:57:30 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g6si20961239pgn.9.2017.05.03.02.57.29; Wed, 03 May 2017 02:57:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753246AbdECJ5N (ORCPT + 25 others); Wed, 3 May 2017 05:57:13 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:33848 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752956AbdECJ46 (ORCPT ); Wed, 3 May 2017 05:56:58 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: gtucker) with ESMTPSA id BBA40269FAC From: Guillaume Tucker To: Rob Herring , Mark Rutland , =?utf-8?q?Heiko_St=C3=BCbner?= , Neil Armstrong Cc: Sjoerd Simons , Enric Balletbo i Serra , John Reitan , Wookey , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Guillaume Tucker Subject: [PATCH v5 1/5] dt-bindings: gpu: add bindings for the ARM Mali Midgard GPU Date: Wed, 3 May 2017 10:56:25 +0100 Message-Id: X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The ARM Mali Midgard GPU family is present in a number of SoCs from many different vendors such as Samsung Exynos and Rockchip. Import the device tree bindings documentation from the r16p0 release of the Mali Midgard GPU kernel driver: https://developer.arm.com/-/media/Files/downloads/mali-drivers/kernel/mali-midgard-gpu/TX011-SW-99002-r16p0-00rel0.tgz Remove the copyright and GPL licence header as deemed not necessary. Redesign the "compatible" property strings to list all the Mali Midgard GPU types and add vendor specific ones. Drop the "clock-names" property as the Mali Midgard GPU uses only one clock (the driver now needs to call clk_get with NULL). Convert the "interrupt-names" property values to lower-case: "job", "mmu" and "gpu". Replace the deprecated "operating-points" optional property with "operating-points-v2". Omit the following optional properties in this initial version as they are only used in very specific cases: * snoop_enable_smc * snoop_disable_smc * jm_config * power_model * system-coherency * ipa-model Update the example accordingly to reflect all these changes, based on rk3288 mali-t760. CC: John Reitan Tested-by: Enric Balletbo i Serra Signed-off-by: Guillaume Tucker --- .../devicetree/bindings/gpu/arm,mali-midgard.txt | 86 ++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt -- 2.11.0 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt new file mode 100644 index 000000000000..d3b6e1a4713a --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt @@ -0,0 +1,86 @@ +ARM Mali Midgard GPU +==================== + +Required properties: + +- compatible : + * Must contain one of the following: + + "arm,mali-t604" + + "arm,mali-t624" + + "arm,mali-t628" + + "arm,mali-t720" + + "arm,mali-t760" + + "arm,mali-t820" + + "arm,mali-t830" + + "arm,mali-t860" + + "arm,mali-t880" + * which must be preceded by one of the following vendor specifics: + + "amlogic,meson-gxm-mali" + + "rockchip,rk3288-mali" + +- reg : Physical base address of the device and length of the register area. + +- interrupts : Contains the three IRQ lines required by Mali Midgard devices. + +- interrupt-names : Contains the names of IRQ resources in the order they were + provided in the interrupts property. Must contain: "job", "mmu", "gpu". + + +Optional properties: + +- clocks : Phandle to clock for the Mali Midgard device. + +- mali-supply : Phandle to regulator for the Mali device. Refer to + Documentation/devicetree/bindings/regulator/regulator.txt for details. + +- operating-points-v2 : Refer to Documentation/devicetree/bindings/power/opp.txt + for details. + + +Example for a Mali-T760: + +gpu@ffa30000 { + compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard"; + reg = <0xffa30000 0x10000>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + clocks = <&cru ACLK_GPU>; + mali-supply = <&vdd_gpu>; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&power RK3288_PD_GPU>; +}; + +gpu_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + opp@533000000 { + opp-hz = /bits/ 64 <533000000>; + opp-microvolt = <1250000>; + }; + opp@450000000 { + opp-hz = /bits/ 64 <450000000>; + opp-microvolt = <1150000>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1125000>; + }; + opp@350000000 { + opp-hz = /bits/ 64 <350000000>; + opp-microvolt = <1075000>; + }; + opp@266000000 { + opp-hz = /bits/ 64 <266000000>; + opp-microvolt = <1025000>; + }; + opp@160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <925000>; + }; + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <912500>; + }; +}; From patchwork Wed May 3 09:56:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Tucker X-Patchwork-Id: 98483 Delivered-To: patch@linaro.org Received: by 10.140.89.200 with SMTP id v66csp217077qgd; Wed, 3 May 2017 02:58:20 -0700 (PDT) X-Received: by 10.99.225.83 with SMTP id h19mr38582290pgk.38.1493805500273; Wed, 03 May 2017 02:58:20 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e64si20428390pgc.32.2017.05.03.02.58.20; Wed, 03 May 2017 02:58:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753548AbdECJ6F (ORCPT + 25 others); Wed, 3 May 2017 05:58:05 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:33855 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752989AbdECJ47 (ORCPT ); Wed, 3 May 2017 05:56:59 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: gtucker) with ESMTPSA id 2E8E126B01C From: Guillaume Tucker To: Rob Herring , Mark Rutland , =?utf-8?q?Heiko_St=C3=BCbner?= , Neil Armstrong Cc: Sjoerd Simons , Enric Balletbo i Serra , John Reitan , Wookey , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Guillaume Tucker Subject: [PATCH v5 2/5] ARM: dts: rockchip: add ARM Mali GPU node for rk3288 Date: Wed, 3 May 2017 10:56:26 +0100 Message-Id: <4b93ea388fa72c6dda0bf954104e99bcd1925267.1493804968.git.guillaume.tucker@collabora.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add Mali GPU device tree node for the rk3288 SoC, with devfreq opp table. Tested-by: Enric Balletbo i Serra Signed-off-by: Guillaume Tucker --- arch/arm/boot/dts/rk3288.dtsi | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) -- 2.11.0 diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index df8a0dbe9d91..35969041eae2 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -43,6 +43,7 @@ #include #include #include +#include #include #include #include @@ -1117,6 +1118,48 @@ }; }; + gpu: mali@ffa30000 { + compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard"; + reg = <0xffa30000 0x10000>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + clocks = <&cru ACLK_GPU>; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&power RK3288_PD_GPU>; + status = "disabled"; + }; + + gpu_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + opp@100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <950000>; + }; + opp@200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <950000>; + }; + opp@300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1000000>; + }; + opp@400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1100000>; + }; + opp@500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1200000>; + }; + opp@600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1250000>; + }; + }; + qos_gpu_r: qos@ffaa0000 { compatible = "syscon"; reg = <0xffaa0000 0x20>; From patchwork Wed May 3 09:56:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Tucker X-Patchwork-Id: 98481 Delivered-To: patch@linaro.org Received: by 10.140.89.200 with SMTP id v66csp216841qgd; Wed, 3 May 2017 02:57:42 -0700 (PDT) X-Received: by 10.84.241.65 with SMTP id u1mr47225097plm.28.1493805462429; Wed, 03 May 2017 02:57:42 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 44si20736762pla.332.2017.05.03.02.57.42; Wed, 03 May 2017 02:57:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753362AbdECJ5h (ORCPT + 25 others); Wed, 3 May 2017 05:57:37 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:33866 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753024AbdECJ47 (ORCPT ); Wed, 3 May 2017 05:56:59 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: gtucker) with ESMTPSA id 3C4BF26B035 From: Guillaume Tucker To: Rob Herring , Mark Rutland , =?utf-8?q?Heiko_St=C3=BCbner?= , Neil Armstrong Cc: Sjoerd Simons , Enric Balletbo i Serra , John Reitan , Wookey , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Guillaume Tucker Subject: [PATCH v5 4/5] ARM: dts: rockchip: enable ARM Mali GPU on rk3288-firefly Date: Wed, 3 May 2017 10:56:28 +0100 Message-Id: X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add reference to the Mali GPU device tree node on rk3288-firefly. Tested on Firefly board. Signed-off-by: Guillaume Tucker --- arch/arm/boot/dts/rk3288-firefly.dtsi | 5 +++++ 1 file changed, 5 insertions(+) -- 2.11.0 diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index 10793ac18599..f520589493b4 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -594,3 +594,8 @@ &wdt { status = "okay"; }; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; From patchwork Wed May 3 09:56:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Tucker X-Patchwork-Id: 98480 Delivered-To: patch@linaro.org Received: by 10.140.89.200 with SMTP id v66csp216840qgd; Wed, 3 May 2017 02:57:42 -0700 (PDT) X-Received: by 10.84.216.26 with SMTP id m26mr29842950pli.79.1493805462074; Wed, 03 May 2017 02:57:42 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 44si20736762pla.332.2017.05.03.02.57.41; Wed, 03 May 2017 02:57:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753335AbdECJ53 (ORCPT + 25 others); Wed, 3 May 2017 05:57:29 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:33873 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753070AbdECJ5A (ORCPT ); Wed, 3 May 2017 05:57:00 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: gtucker) with ESMTPSA id B482326B039 From: Guillaume Tucker To: Rob Herring , Mark Rutland , =?utf-8?q?Heiko_St=C3=BCbner?= , Neil Armstrong Cc: Sjoerd Simons , Enric Balletbo i Serra , John Reitan , Wookey , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Guillaume Tucker Subject: [PATCH v5 5/5] ARM: dts: rockchip: enable ARM Mali GPU on rk3288-veyron Date: Wed, 3 May 2017 10:56:29 +0100 Message-Id: <000831729017aaf278618b76205a4f1029c2575b.1493804968.git.guillaume.tucker@collabora.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Enric Balletbo i Serra Add reference to the Mali GPU device tree node on rk3288-veyron. Tested on Minnie and Jerry boards. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Guillaume Tucker --- arch/arm/boot/dts/rk3288-veyron.dtsi | 5 +++++ 1 file changed, 5 insertions(+) -- 2.11.0 diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 5d1eb0a25827..9847d5c6db3b 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -447,6 +447,11 @@ status = "okay"; }; +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + &wdt { status = "okay"; };