From patchwork Mon Jul 9 03:19:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 141361 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp2166912ljj; Sun, 8 Jul 2018 20:21:39 -0700 (PDT) X-Google-Smtp-Source: AAOMgpdTJlhZ0IIh58J7V3KEkBpaq3t+MUXOfAg5WjZcs893WdFJW5Jzb3hTtKLWfUC9j4hrB1i4 X-Received: by 2002:a65:5c42:: with SMTP id v2-v6mr11132618pgr.224.1531106499406; Sun, 08 Jul 2018 20:21:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531106499; cv=none; d=google.com; s=arc-20160816; b=UjJa+dGcZcrQGnMO2iBIbLIavFNwX0OB24QWPO2dZtWgK9z9VECbbFUKdN1qehX89m 7KkEGCoXFzC8u8C84PxfuoYKfSbQakFaGuyM+uKju4EE37LAdHoondrRvvGLoFZVdjxu u02wIrHuDz4eBxlv4X9z1Yus65YD5CL+FNtHNiylc5LnnMtEwP5UFeRKvO9UJS5Yru0i ORSwKWiC0+LmoKcoc93mqcLkS2BsDTBRZFBouPB0hFBbhbW/iOaqUbLMHz4vgpli9wJ/ F/Y98jMcUe54RUNchyMP6z3qEsB0RH7UB8PxODgJNk6KM/sbDoHcZUcWa4ftLTMd01Y0 H69A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=fRGwE55C+87JEZEZfreG1eB0oRkGj0Cu0G2/o3bFsd8=; b=R8JXPrDhzA4GvZopgaqS1xpAiPF9gNt9PoiLHkPyNChIoqc2BffNSsgfuo2nXCtx/S j85fl10arr4DD/YFNKJ0HUpt5T9LF5aUo8yDnbMAdWmdaU+rPeNh9gAM0X9vXRp0d9Rf ANz8tHOfCp6gRmzMFrSI2SSWnqw6fpIK8FA1ZeXmzP5qYQ839gylwfgBe9r2siXjbexe xDxQtpXpc4URzRCPz7RUcuAW6Xcy5nl+Vhd6oX7VbNA2/P9ZiIMmNEeTPiOn33GXOlWg qcw5D39yMUD5B+lGeo1dZGdnwZL+rOAQQ2dobE8Ev3ILpVb71D8ceHIyZrZaZIC8wuU1 vV2w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OUnNmxnd; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b23-v6si13219207pls.341.2018.07.08.20.21.39; Sun, 08 Jul 2018 20:21:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OUnNmxnd; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933436AbeGIDVi (ORCPT + 28 others); Sun, 8 Jul 2018 23:21:38 -0400 Received: from mail-pf0-f193.google.com ([209.85.192.193]:46130 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933267AbeGIDVf (ORCPT ); Sun, 8 Jul 2018 23:21:35 -0400 Received: by mail-pf0-f193.google.com with SMTP id l123-v6so12582854pfl.13 for ; Sun, 08 Jul 2018 20:21:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fRGwE55C+87JEZEZfreG1eB0oRkGj0Cu0G2/o3bFsd8=; b=OUnNmxnd90/PL36RCvFkWozRxm7UTfigLaMXM3FirfZ7oOT3/eHLbSW6cX9XvGiyaf WkExAtzjRHJJmvefN0ZP3mzEagykZlarSt7j6/svK4Whf10OLQVfImXnG3/vTpgyFYIw CvZfsbG/JVMyAc0D7iowiyu33sDetSIom+PSw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fRGwE55C+87JEZEZfreG1eB0oRkGj0Cu0G2/o3bFsd8=; b=e113JePKwDyJsbU1r2Eqz5QvKWtOib/IEbUVHe+Er+lpMZm/ubNrVshu8NrmFYlwe1 ATRoKECjetR2Uo+uzmPkbpxnssDmLlLosYziAdJLNq0quQtdudtpzNXZG4/9cMlvT09p iR8LAIN8MG1ryJwDF+LXfK7OYM1drAsAZYRmAKul0uAAPcJEDUSFvjc+PJ53hBjW4kz5 DhsVbSlAm3uuAKJCfU3BxG0UIGMYrEQuyfZdh88buFY308FBS2Q/Ffu2cav9G16Qggwf ZOr1okqyCNKBia+0qykMtRHsUuh2AuvId0Eb/luSa3Krn8PzFtUBD+IIrVOaUAyMO0P1 ez0g== X-Gm-Message-State: APt69E3J08zqjHyoerk8O73LKHkGsD9J3UyB8Wn5eQRDoLmqJZ64JGJJ IyjXxmZ6BKVqDNyaDdEndr1jdw== X-Received: by 2002:a62:2c46:: with SMTP id s67-v6mr19152809pfs.153.1531106495238; Sun, 08 Jul 2018 20:21:35 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id e82-v6sm41458950pfk.87.2018.07.08.20.21.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 08 Jul 2018 20:21:34 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , zhang.lyra@gmail.com Subject: [PATCH V3 3/7] mmc: sdhci: add ADMA2 64-bit addressing support for V4 mode Date: Mon, 9 Jul 2018 11:19:54 +0800 Message-Id: <1531106398-14062-4-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531106398-14062-1-git-send-email-zhang.chunyan@linaro.org> References: <1531106398-14062-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ADMA2 64-bit addressing support is divided into V3 mode and V4 mode. So there are two kinds of descriptors for ADMA2 64-bit addressing i.e. 96-bit Descriptor for V3 mode, and 128-bit Descriptor for V4 mode. 128-bit Descriptor is aligned to 8-byte. For V4 mode, ADMA2 64-bit addressing is enabled via Host Control 2 register. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 28 ++++++++++++++++++++++++---- drivers/mmc/host/sdhci.h | 14 ++++++++++++-- 2 files changed, 36 insertions(+), 6 deletions(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index c7de6a5..7871ae2 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3486,6 +3486,26 @@ static int sdhci_allocate_bounce_buffer(struct sdhci_host *host) return 0; } +static inline bool sdhci_use_64bit_dma(struct sdhci_host *host) +{ + u32 addr64bit_en; + + /* + * According to SD Host Controller spec v4.10, bit[27] added from + * version 4.10 in Capabilities Register is used as 64-bit System + * Address support for V4 mode, 64-bit DMA Addressing for V4 mode + * is enabled only if 64-bit Addressing =1 in the Host Control 2 + * register. + */ + if (host->version == SDHCI_SPEC_410 && host->v4_mode) { + addr64bit_en = (sdhci_readw(host, SDHCI_HOST_CONTROL2) & + SDHCI_CTRL_64BIT_ADDR); + return addr64bit_en && (host->caps & SDHCI_CAN_64BIT_V4); + } + + return host->caps & SDHCI_CAN_64BIT; +} + int sdhci_setup_host(struct sdhci_host *host) { struct mmc_host *mmc; @@ -3557,7 +3577,7 @@ int sdhci_setup_host(struct sdhci_host *host) * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to * implement. */ - if (host->caps & SDHCI_CAN_64BIT) + if (sdhci_use_64bit_dma(host)) host->flags |= SDHCI_USE_64_BIT_DMA; if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { @@ -3591,8 +3611,8 @@ int sdhci_setup_host(struct sdhci_host *host) */ if (host->flags & SDHCI_USE_64_BIT_DMA) { host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * - SDHCI_ADMA2_64_DESC_SZ; - host->desc_sz = SDHCI_ADMA2_64_DESC_SZ; + SDHCI_ADMA2_64_DESC_SZ(host); + host->desc_sz = SDHCI_ADMA2_64_DESC_SZ(host); } else { host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * SDHCI_ADMA2_32_DESC_SZ; @@ -3600,7 +3620,7 @@ int sdhci_setup_host(struct sdhci_host *host) } host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN; - buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz + + buf = dma_zalloc_coherent(mmc_dev(mmc), host->align_buffer_sz + host->adma_table_sz, &dma, GFP_KERNEL); if (!buf) { pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n", diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index e98249b..24fa58a 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -185,6 +185,7 @@ #define SDHCI_CTRL_EXEC_TUNING 0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 #define SDHCI_CTRL_V4_MODE 0x1000 +#define SDHCI_CTRL_64BIT_ADDR 0x2000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 #define SDHCI_CAPABILITIES 0x40 @@ -205,6 +206,7 @@ #define SDHCI_CAN_VDD_330 0x01000000 #define SDHCI_CAN_VDD_300 0x02000000 #define SDHCI_CAN_VDD_180 0x04000000 +#define SDHCI_CAN_64BIT_V4 0x08000000 #define SDHCI_CAN_64BIT 0x10000000 #define SDHCI_SUPPORT_SDR50 0x00000001 @@ -271,6 +273,8 @@ #define SDHCI_SPEC_100 0 #define SDHCI_SPEC_200 1 #define SDHCI_SPEC_300 2 +#define SDHCI_SPEC_400 3 +#define SDHCI_SPEC_410 4 /* * End of controller registers. @@ -306,8 +310,14 @@ struct sdhci_adma2_32_desc { */ #define SDHCI_ADMA2_DESC_ALIGN 8 -/* ADMA2 64-bit DMA descriptor size */ -#define SDHCI_ADMA2_64_DESC_SZ 12 +/* + * ADMA2 64-bit DMA descriptor size + * According to SD Host Controller spec v4.10, there are two kinds of + * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit + * Descriptor, if Host Version 4 Enable is set in the Host Control 2 + * register, 128-bit Descriptor will be selected. + */ +#define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12) /* * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte From patchwork Mon Jul 9 03:19:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 141362 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp2167060ljj; Sun, 8 Jul 2018 20:21:54 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfNJv8YudlAUaI4jvGjJenWI25D2zGazFny2OEGODrQpoxAMPJKkZdiPKy9OhWBOXvKn7n4 X-Received: by 2002:a17:902:184:: with SMTP id b4-v6mr4600003plb.340.1531106514182; Sun, 08 Jul 2018 20:21:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531106514; cv=none; d=google.com; s=arc-20160816; b=KATsPnbeP6hDNQmiZ2vtItj+ZEdD903GlgDO1F7sKHbqEIqUryQi3WoMBi1O4uuoPV jjko2EvlVVa+R1SYU62EWTxDXgzLiTP+6bnGy9F0ODLtoPBw5a4y3tdGpNkos8V6Q0ay aMdj3tpJ2AdZyezAq07NTXdRf/+RNrFmHsXOEcMK44MyDVX+xwAM+iZSoZOH9rtZN6eQ S8t1WzRI4xmNuI6/hiRITeNdd2zIWa3lwQs/8XfIwyJMf/0c6pTpYHb/allh3g98TV+0 drC+s3adisTfvT6ckBEBb8hSEMTPvbJdGTT9pduwT93QMKpOXBbKHUg/v2kCffXBdpR7 cfOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=phQAPKjHuXaJ49E6Z2SoJBvzQ21pOgO1IGo0W1Ifx3w=; b=oqaFcuNUnDKfj7UVaFFim5/uzWipGIyd0KXkinX4eO5XBEY108abPGauM779FALxwQ zpNrr1dstMB4jberZWFqAMoWUDC+q3TZzDSLoEAFfZTSS+jn4x3hROwVU0T+1cF5M6/R e9T2LLZlQkvzCYCU9AYlXKgW1o7Sv544OOVNUVvXPYq04WWOwA55x4rND1KRxcD6yp5Q RU4osW/rnk8WuxoS+bSodnaAtenjBsVgV3VoR6bEdCrenhfDXN3gvsVfvL3C4EwyQHds /LdkCzWUMoJC8tOWMNFqPHyvFvpDPGlWDjPsOeD2Kg+//gl3LvRPZ3SQTAVWllNsC1pH boGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=T3hsvKmA; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b23-v6si13219207pls.341.2018.07.08.20.21.53; Sun, 08 Jul 2018 20:21:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=T3hsvKmA; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933476AbeGIDVx (ORCPT + 28 others); Sun, 8 Jul 2018 23:21:53 -0400 Received: from mail-pf0-f193.google.com ([209.85.192.193]:35852 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933053AbeGIDVu (ORCPT ); Sun, 8 Jul 2018 23:21:50 -0400 Received: by mail-pf0-f193.google.com with SMTP id u16-v6so12590139pfh.3 for ; Sun, 08 Jul 2018 20:21:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=phQAPKjHuXaJ49E6Z2SoJBvzQ21pOgO1IGo0W1Ifx3w=; b=T3hsvKmA5wT9bOLw8EqwK6etiLU05GuEo3vZ+YpAYSKfjW3csF+1Q7pdLYJ6/v4ED8 l8RXa8EkfE9ekym5jHnM529DFGgmIEMxk+NDm+nwli0yrfKXZsK55gdGbig7U1pVB3bu MhtgToBx7tvnqDlbu7IYsjqm+HoU079p3BgdU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=phQAPKjHuXaJ49E6Z2SoJBvzQ21pOgO1IGo0W1Ifx3w=; b=D41Vsgo7/t3qh8sZweckgDdSGZeeaNXb/lWWgZZiJPVOAeSjL335vJixUuEBUabJtE kzif6q6/U3+Dmto1/NyT9gb6Rdc65S8Ax44oMU2SyFYJt2zqX7N0F8ISlBz0MxOW4DB7 ZrFWh7jq11Os+fvTdnqMD4oS3v3jxCmamc9OmiT2cQJHqZltu3lPUCgw6UiLwVSKucv7 3F19ZB6Jkjsl38DP68VWgUMSO6aWPVZbUIlibmByXmh1ZZ+TrM45L1tmAKtPeyOVAHXk A5KeSdJxNVQw0p25lfy7/Gh3pZLomVVa/YSP+Ujebo2+ob/lwVqYVlBpwx07cHcifo1I Zwug== X-Gm-Message-State: APt69E04of/yOAANv1MBk2xZb8+8DmGZb1cRZwRoNtuVt+Fzuoj9frM6 xruufTWFIEqPTXO+mw+Ujptrew== X-Received: by 2002:a63:d518:: with SMTP id c24-v6mr11351335pgg.357.1531106510392; Sun, 08 Jul 2018 20:21:50 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id e82-v6sm41458950pfk.87.2018.07.08.20.21.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 08 Jul 2018 20:21:49 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , zhang.lyra@gmail.com Subject: [PATCH V3 4/7] mmc: sdhci: add 32-bit block count support for v4 mode Date: Mon, 9 Jul 2018 11:19:55 +0800 Message-Id: <1531106398-14062-5-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531106398-14062-1-git-send-email-zhang.chunyan@linaro.org> References: <1531106398-14062-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When Host Version 4 is enabled, SDMA System Address register is re-defined as 32-bit Block Count, and SDMA uses ADMA System Address register (05Fh-058h) instead. Signed-off-by: Chunyan Zhang --- drivers/mmc/host/sdhci.c | 4 +++- drivers/mmc/host/sdhci.h | 1 + 2 files changed, 4 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 7871ae2..f64e766 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -889,6 +889,7 @@ static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) { u8 ctrl; + u32 reg; struct mmc_data *data = cmd->data; host->data_timeout = 0; @@ -1021,7 +1022,8 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) /* Set the DMA boundary value and block size */ sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz), SDHCI_BLOCK_SIZE); - sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); + reg = host->v4_mode ? SDHCI_32BIT_BLK_CNT : SDHCI_BLOCK_COUNT; + sdhci_writew(host, data->blocks, reg); } static inline bool sdhci_auto_cmd12(struct sdhci_host *host, diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 24fa58a..889e48b 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -28,6 +28,7 @@ #define SDHCI_DMA_ADDRESS 0x00 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS +#define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS #define SDHCI_BLOCK_SIZE 0x04 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) From patchwork Mon Jul 9 03:19:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 141364 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp2167253ljj; Sun, 8 Jul 2018 20:22:14 -0700 (PDT) X-Google-Smtp-Source: AAOMgpcfV2/+ESO1qGO8C+3EGtB+NTmbNF7RH2+kToURFx8F2U04cxNS4pVu6l9qg6GA6I/SjubM X-Received: by 2002:a62:2541:: with SMTP id l62-v6mr19735275pfl.0.1531106534048; Sun, 08 Jul 2018 20:22:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531106534; cv=none; d=google.com; s=arc-20160816; b=P9RKIVtRQathpr4/V74bkl2FWdtdDgtu1NBv+v3HZWrK7UqhimlfMRb6SkmkaXjSiI o2m9nzEdc4mGL/IRvY5zd8t2agNsvxyk3NtP5Dwxt6XgWjw21NUglWdZ5KzAqswLCG71 Yw4BhKXisBs/1dUcoDYjwtDSt2+NuTA3hqAQkLXY98yPUydKGRzaWQMjCDglhKSO580L +2juLl1bvRuiGlULoaZZIUPRRo1A/QWjnWcFvB51sGDGnb1VifBFxBaAPESVY1lMRInO 3x6oKnPbvCb+jZNxagCsuKR/VgUyiwvIgc/snjqp5AZf+/m7uO26rRloM7GYWXzq4Je3 moDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=UmULmCwZp4AJUeDgqozwLxQLG8G8Z5paZHToIoI6E00=; b=lIhSL4nwTff68TkAomNDbcWoWZKkdlcbIOtVAhrUiYSU5wYwJZ6hju3E70bWKHgRwW e9JCDQHSA2pb6bU6+7pLNO6NOBmMFWNZW/w1vNPQqmY+l3R9xSfcwWcnusghQOzZfFlO tF3d404kc5N6cylHrjwfkmBsdWDbb80bmGAdTNlVrmV2WskaksI7QgzNDFNzgx5a97z7 Giqzk8R+ZakAYn2R54MpzyPwesDhktUGMwFW0nQs4A3ToYI5mOKq99k1RZ9eobbH5m5o CbFbUYvTEFPbs+EzcnKsjeLYOVsRDcf40IkFeI0+C0XBcA+BVhVku+FFEA4QFH+/sY6m jF0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IfJzONKf; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z3-v6si13437501plk.48.2018.07.08.20.22.13; Sun, 08 Jul 2018 20:22:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IfJzONKf; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933512AbeGIDWN (ORCPT + 28 others); Sun, 8 Jul 2018 23:22:13 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:46162 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932996AbeGIDWK (ORCPT ); Sun, 8 Jul 2018 23:22:10 -0400 Received: by mail-pg1-f195.google.com with SMTP id p23-v6so810608pgv.13 for ; Sun, 08 Jul 2018 20:22:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UmULmCwZp4AJUeDgqozwLxQLG8G8Z5paZHToIoI6E00=; b=IfJzONKflNu+ckv805I91JSJJGrn8qWA+8eVAwSaSRtMCGSsjCBXUzW80tXTOEpzc9 YX/WtPzM8rWLtvkb5n9xUlTnkvZXYm8um3nr30/0mZ77i54YVluvXHOXAIJFAKHIlsOm YVGOm6DxBUpy2PUS+uIde70422ov+buh3pf08= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UmULmCwZp4AJUeDgqozwLxQLG8G8Z5paZHToIoI6E00=; b=pXw5cEXpNsv6lYMcjIkxjk1TORE/+79J9IsgP0TNkyLmBw8bghOhc5UOr7Dv/FYLr2 F0LpeAyFYSXsCVbUgkReF2rJiWrs65NtO670TAN7ZtAl734Ofj7oDIjnYoqcSwQelkC+ F67r19Vr0KEagY7h863RuwNQZKytGDC+6nUcMDmN87FdgXc3PPTbvcLvGwduGs4uxSCB PdIDYxjpeTnZ1Smx4dSSdMhGBe+0/vxjxukQE6BS2LJmRBX1ThK9zw028Lr8FrD55drs 7j0jvNGWw7wxSC0GEORzw5+aLxUV0U1re47ON2oG5rNa3cUjUE2p03mH/WjeP4OGAe6W Tj5w== X-Gm-Message-State: APt69E3nZ5BIsXFhMLVoS6YchTSFIUM60bdbrm/+fJ5sSegSsR1hl7VK zvlcoPI5ntVSqoX3bbFHSehnvw== X-Received: by 2002:a63:1513:: with SMTP id v19-v6mr16020327pgl.358.1531106530104; Sun, 08 Jul 2018 20:22:10 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id e82-v6sm41458950pfk.87.2018.07.08.20.22.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 08 Jul 2018 20:22:09 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , zhang.lyra@gmail.com Subject: [PATCH V3 6/7] mmc: sdhci-sprd: added Spreadtrum's initial host controller Date: Mon, 9 Jul 2018 11:19:57 +0800 Message-Id: <1531106398-14062-7-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531106398-14062-1-git-send-email-zhang.chunyan@linaro.org> References: <1531106398-14062-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chunyan Zhang This patch adds the initial support of Secure Digital Host Controller Interface compliant controller found in some latest Spreadtrum chipsets. This patch has been tested on the version of SPRD-R11 controller. R11 is a variant based on SD v4.0 specification. With this driver, R11 mmc can be initialized, can be mounted, read and written. Original-by: Billows Wu Signed-off-by: Chunyan Zhang --- drivers/mmc/host/Kconfig | 13 ++ drivers/mmc/host/Makefile | 1 + drivers/mmc/host/sdhci-sprd.c | 437 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 451 insertions(+) create mode 100644 drivers/mmc/host/sdhci-sprd.c -- 2.7.4 diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 0581c19..c5424dc 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -581,6 +581,19 @@ config MMC_SDRICOH_CS To compile this driver as a module, choose M here: the module will be called sdricoh_cs. +config MMC_SDHCI_SPRD + tristate "Spreadtrum SDIO host Controller" + depends on ARCH_SPRD + depends on MMC_SDHCI_PLTFM + select MMC_SDHCI_IO_ACCESSORS + help + This selects the SDIO Host Controller in Spreadtrum + SoCs, this driver supports R11(IP version: R11P0). + + If you have a controller with this interface, say Y or M here. + + If unsure, say N. + config MMC_TMIO_CORE tristate diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 85dc132..b0b6802 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -89,6 +89,7 @@ obj-$(CONFIG_MMC_SDHCI_ST) += sdhci-st.o obj-$(CONFIG_MMC_SDHCI_MICROCHIP_PIC32) += sdhci-pic32.o obj-$(CONFIG_MMC_SDHCI_BRCMSTB) += sdhci-brcmstb.o obj-$(CONFIG_MMC_SDHCI_OMAP) += sdhci-omap.o +obj-$(CONFIG_MMC_SDHCI_SPRD) += sdhci-sprd.o obj-$(CONFIG_MMC_CQHCI) += cqhci.o ifeq ($(CONFIG_CB710_DEBUG),y) diff --git a/drivers/mmc/host/sdhci-sprd.c b/drivers/mmc/host/sdhci-sprd.c new file mode 100644 index 0000000..8d37ecb --- /dev/null +++ b/drivers/mmc/host/sdhci-sprd.c @@ -0,0 +1,437 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Secure Digital Host Controller +// +// Copyright (C) 2018 Spreadtrum, Inc. +// Author: Chunyan Zhang + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "sdhci-pltfm.h" + +#define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208 +#define SDHCIBSPRD_IT_WR_DLY_INV BIT(5) +#define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13) +#define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21) +#define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29) + +#define SDHCI_SPRD_REG_32_BUSY_POSI 0x250 +#define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25) +#define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24) + +#define SDHCI_SPRD_REG_DEBOUNCE 0x28C +#define SDHCI_SPRD_BIT_DLL_BAK BIT(0) +#define SDHCI_SPRD_BIT_DLL_VAL BIT(1) + +#define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B + +/* SDHCI_HOST_CONTROL2 */ +#define SDHCI_SPRD_CTRL_HS200 0x0005 +#define SDHCI_SPRD_CTRL_HS400 0x0006 + +/* SDHCI_SOFTWARE_RESET */ +#define SDHCI_HW_RESET_CARD 0x8 /* For Spreadtrum's design */ + +#define SDHCI_SPRD_MAX_CUR 0xFFFFFF +#define SDHCI_SPRD_CLK_MAX_DIV 1023 + +#define SDHCI_SPRD_CLK_DEF_RATE 26000000 + +struct sdhci_sprd_host { + u32 version; + struct clk *clk_sdio; + struct clk *clk_enable; + u32 base_rate; +}; + +#define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host)) + +static void sdhci_sprd_init_config(struct sdhci_host *host) +{ + u16 val; + + /* set 64-bit addressing modes */ + val = sdhci_readw(host, SDHCI_HOST_CONTROL2); + val |= SDHCI_CTRL_64BIT_ADDR; + sdhci_writew(host, val, SDHCI_HOST_CONTROL2); + + /* set dll backup mode */ + val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); + val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL; + sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); + + /* set CMD23 enabled */ + val = sdhci_readw(host, SDHCI_HOST_CONTROL2); + val |= SDHCI_CMD23_ENABLE; + sdhci_writew(host, val, SDHCI_HOST_CONTROL2); +} + +static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg) +{ + if (unlikely(reg == SDHCI_MAX_CURRENT)) + return SDHCI_SPRD_MAX_CUR; + + return readl_relaxed(host->ioaddr + reg); +} + +static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg) +{ + /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */ + if (unlikely(reg == SDHCI_MAX_CURRENT)) + return; + + if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE)) + val = val & SDHCI_SPRD_INT_SIGNAL_MASK; + + writel_relaxed(val, host->ioaddr + reg); +} + +static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg) +{ + if (unlikely(reg == SDHCI_SOFTWARE_RESET)) { + if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD) + val |= SDHCI_HW_RESET_CARD; + } + + writeb_relaxed(val, host->ioaddr + reg); +} + +static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host) +{ + u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + + ctrl &= ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); +} + +static inline void +sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en) +{ + u32 dll_dly_offset; + + dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); + if (en) + dll_dly_offset |= mask; + else + dll_dly_offset &= ~mask; + sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); +} + +static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk) +{ + u32 div; + + /* select 2x clock source */ + if (base_clk <= clk * 2) + return 0; + + div = (u32) (base_clk / (clk * 2)); + + if ((base_clk / div) > (clk * 2)) + div++; + + if (div > SDHCI_SPRD_CLK_MAX_DIV) + div = SDHCI_SPRD_CLK_MAX_DIV; + + if (div % 2) + div = (div + 1) / 2; + else + div = div / 2; + + return div; +} + +static inline void _sdhci_sprd_set_clock(struct sdhci_host *host, + unsigned int clk) +{ + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + u32 div, val, mask; + + div = sdhci_sprd_calc_div(sprd_host->base_rate, clk); + + clk |= ((div & 0x300) >> 2) | ((div & 0xFF) << 8); + sdhci_enable_clk(host, clk); + + /* enable auto gate sdhc_enable_auto_gate */ + val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); + mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | + SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; + if (mask != (val & mask)) { + val |= mask; + sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); + } +} + +static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock) +{ + bool en = false; + + if (clock == 0) { + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); + } else if (clock != host->clock) { + sdhci_sprd_sd_clk_off(host); + _sdhci_sprd_set_clock(host, clock); + + if (clock <= 400000) + en = true; + sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV | + SDHCI_SPRD_BIT_POSRD_DLY_INV, en); + } else { + _sdhci_sprd_set_clock(host, clock); + } +} + +static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host) +{ + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + + return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX); +} + +static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host) +{ + return 400000; +} + +static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host, + unsigned int timing) +{ + u16 ctrl_2; + + if (timing == host->timing) + return; + + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + /* Select Bus Speed Mode for host */ + ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; + switch (timing) { + case MMC_TIMING_UHS_SDR12: + ctrl_2 = SDHCI_CTRL_UHS_SDR12; + break; + case MMC_TIMING_MMC_HS: + case MMC_TIMING_SD_HS: + case MMC_TIMING_UHS_SDR25: + ctrl_2 = SDHCI_CTRL_UHS_SDR25; + break; + case MMC_TIMING_UHS_SDR50: + ctrl_2 = SDHCI_CTRL_UHS_SDR50; + break; + case MMC_TIMING_UHS_SDR104: + ctrl_2 = SDHCI_CTRL_UHS_SDR104; + break; + case MMC_TIMING_UHS_DDR50: + case MMC_TIMING_MMC_DDR52: + ctrl_2 = SDHCI_CTRL_UHS_DDR50; + break; + case MMC_TIMING_MMC_HS200: + ctrl_2 = SDHCI_SPRD_CTRL_HS200; + break; + case MMC_TIMING_MMC_HS400: + ctrl_2 = SDHCI_SPRD_CTRL_HS400; + break; + default: + break; + } + + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); +} + +static void sdhci_sprd_hw_reset(struct sdhci_host *host) +{ + int val; + + /* Note: don't use sdhci_readb/writeb() API here */ + val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET); + val &= ~SDHCI_HW_RESET_CARD; + writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); + udelay(10); + + val |= SDHCI_HW_RESET_CARD; + writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); + udelay(300); +} + +static struct sdhci_ops sdhci_sprd_ops = { + .read_l = sdhci_sprd_readl, + .write_l = sdhci_sprd_writel, + .write_b = sdhci_sprd_writeb, + .set_clock = sdhci_sprd_set_clock, + .get_max_clock = sdhci_sprd_get_max_clock, + .get_min_clock = sdhci_sprd_get_min_clock, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_sprd_set_uhs_signaling, + .hw_reset = sdhci_sprd_hw_reset, +}; + +static const struct sdhci_pltfm_data sdhci_sprd_pdata = { + .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, + .quirks2 = SDHCI_QUIRK2_BROKEN_HS200, + .ops = &sdhci_sprd_ops, +}; + +static int sdhci_sprd_probe(struct platform_device *pdev) +{ + struct sdhci_host *host; + struct sdhci_sprd_host *sprd_host; + struct clk *clk; + int ret = 0; + + host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host)); + if (IS_ERR(host)) + return PTR_ERR(host); + + host->dma_mask = DMA_BIT_MASK(64); + pdev->dev.dma_mask = &host->dma_mask; + + host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | + MMC_CAP_ERASE | MMC_CAP_CMD23; + ret = mmc_of_parse(host->mmc); + if (ret) + goto pltfm_free; + + sprd_host = TO_SPRD_HOST(host); + + clk = devm_clk_get(&pdev->dev, "sdio"); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + goto pltfm_free; + } + sprd_host->clk_sdio = clk; + sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio); + if (!sprd_host->base_rate) + sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE; + + clk = devm_clk_get(&pdev->dev, "enable"); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + goto pltfm_free; + } + sprd_host->clk_enable = clk; + + ret = clk_prepare_enable(sprd_host->clk_sdio); + if (ret) + goto pltfm_free; + + clk_prepare_enable(sprd_host->clk_enable); + if (ret) + goto clk_disable; + + sdhci_sprd_init_config(host); + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >> + SDHCI_VENDOR_VER_SHIFT); + + pm_runtime_get_noresume(&pdev->dev); + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + pm_runtime_set_autosuspend_delay(&pdev->dev, 50); + pm_runtime_use_autosuspend(&pdev->dev); + pm_suspend_ignore_children(&pdev->dev, 1); + + sdhci_enable_v4_mode(host); + ret = sdhci_add_host(host); + if (ret) { + dev_err(&pdev->dev, "failed to add mmc host: %d\n", ret); + goto pm_runtime_disable; + } + + pm_runtime_mark_last_busy(&pdev->dev); + pm_runtime_put_autosuspend(&pdev->dev); + + return 0; + +pm_runtime_disable: + pm_runtime_disable(&pdev->dev); + pm_runtime_set_suspended(&pdev->dev); + + clk_disable_unprepare(sprd_host->clk_enable); + +clk_disable: + clk_disable_unprepare(sprd_host->clk_sdio); + +pltfm_free: + sdhci_pltfm_free(pdev); + return ret; +} + +static int sdhci_sprd_remove(struct platform_device *pdev) +{ + struct sdhci_host *host = platform_get_drvdata(pdev); + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + struct mmc_host *mmc = host->mmc; + + mmc_remove_host(mmc); + clk_disable_unprepare(sprd_host->clk_sdio); + clk_disable_unprepare(sprd_host->clk_enable); + + mmc_free_host(mmc); + + return 0; +} + +static const struct of_device_id sdhci_sprd_of_match[] = { + { .compatible = "sprd,sdhci-r11", }, + { } +}; +MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match); + +#ifdef CONFIG_PM +static int sdhci_sprd_runtime_suspend(struct device *dev) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + + sdhci_runtime_suspend_host(host); + + clk_disable_unprepare(sprd_host->clk_sdio); + clk_disable_unprepare(sprd_host->clk_enable); + + return 0; +} + +static int sdhci_sprd_runtime_resume(struct device *dev) +{ + struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); + + clk_prepare_enable(sprd_host->clk_enable); + clk_prepare_enable(sprd_host->clk_sdio); + + sdhci_runtime_resume_host(host); + + return 0; +} +#endif + +static const struct dev_pm_ops sdhci_sprd_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) + SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend, + sdhci_sprd_runtime_resume, NULL) +}; + +static struct platform_driver sdhci_sprd_driver = { + .probe = sdhci_sprd_probe, + .remove = sdhci_sprd_remove, + .driver = { + .name = "sdhci_sprd_r11", + .of_match_table = of_match_ptr(sdhci_sprd_of_match), + .pm = &sdhci_sprd_pm_ops, + }, +}; +module_platform_driver(sdhci_sprd_driver); + +MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:sdhci-sprd-r11"); From patchwork Mon Jul 9 03:19:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 141365 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp2167375ljj; Sun, 8 Jul 2018 20:22:26 -0700 (PDT) X-Google-Smtp-Source: AAOMgpeLaUQwV4K8+hD5cPZLJcHXmKFrPtH8ZpSW5OGpD47ikQdSPFbX3FSUOW7j2/T1c5MP1i/e X-Received: by 2002:a17:902:ab8e:: with SMTP id f14-v6mr19248757plr.5.1531106545878; Sun, 08 Jul 2018 20:22:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531106545; cv=none; d=google.com; s=arc-20160816; b=OO99iNu58B0hDf2pkeMg3KW6P/etCrevjhUA0A3GHLJlOhJegYm81w7153Ek18O5KK 99zeqfG1Dn9wLK4b95A5hXyf2Dtbblr0duGLCgfH/wfyOFJh13f6+iJUWY322AKJ+TsH 6OAR7Ve39m53ToSBX83uX2r04ukL6hufhT0BKPHv8NkPwP8g3tpkrvkVXUdiv+qrSMrE f1BCWMxKGWil7HZLgQbeVPRkFjvS0wZcudcBlqExSTSGdGowqp5zHrSeXs2Nbw+vVLAr 6ZflBWuLtQtC5NFUad8OWSdo0iydBdlMU666OHVHkWs9QcpBLQTxgUvOdvbbZjpiligH 9DXQ== ARC-Message-Signature: i=1; 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Signed-off-by: Chunyan Zhang --- .../devicetree/bindings/mmc/sdhci-sprd.txt | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-sprd.txt -- 2.7.4 diff --git a/Documentation/devicetree/bindings/mmc/sdhci-sprd.txt b/Documentation/devicetree/bindings/mmc/sdhci-sprd.txt new file mode 100644 index 0000000..45c9978 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/sdhci-sprd.txt @@ -0,0 +1,41 @@ +* Spreadtrum SDHCI controller (sdhci-sprd) + +The Secure Digital (SD) Host controller on Spreadtrum SoCs provides an interface +for MMC, SD and SDIO types of cards. + +This file documents differences between the core properties in mmc.txt +and the properties used by the sdhci-sprd driver. + +Required properties: +- compatible: Should contain "sprd,sdhci-r11". +- reg: physical base address of the controller and length. +- interrupts: Interrupts used by the SDHCI controller. +- clocks: Should contain phandle for the clock feeding the SDHCI controller +- clock-names: Should contain the following: + "sdio" - SDIO source clock (required) + "enable" - gate clock which used for enabling/disabling the device (required) + +Optional properties: +- assigned-clocks: the same with "sdio" clock +- assigned-clock-parents: the default parent of "sdio" clock + +Examples: + +sdio0: sdio@20600000 { + compatible = "sprd,sdhci-r11"; + reg = <0 0x20600000 0 0x1000>; + interrupts = ; + + clock-names = "sdio", "enable"; + clocks = <&ap_clk CLK_EMMC_2X>, + <&apahb_gate CLK_EMMC_EB>; + assigned-clocks = <&ap_clk CLK_EMMC_2X>; + assigned-clock-parents = <&rpll CLK_RPLL_390M>; + + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + cap-mmc-hw-reset; + status = "okay"; +};