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Fri, 21 May 2021 10:27:13 +0000 From: "Peng Fan (OSS)" To: robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, p.zabel@pengutronix.de, l.stach@pengutronix.de, krzk@kernel.org, agx@sigxcpu.org, marex@denx.de, andrew.smirnov@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, ping.bai@nxp.com, frieder.schrempf@kontron.de, aford173@gmail.com, abel.vesa@nxp.com, Peng Fan , Rob Herring Subject: [PATCH V5 1/4] dt-bindings: power: Add defines for i.MX8MM BLK-CTL power domains Date: Fri, 21 May 2021 18:59:16 +0800 Message-Id: <20210521105919.20167-2-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210521105919.20167-1-peng.fan@oss.nxp.com> References: <20210521105919.20167-1-peng.fan@oss.nxp.com> X-Originating-IP: [119.31.174.71] X-ClientProxiedBy: SG2PR06CA0163.apcprd06.prod.outlook.com (2603:1096:1:1e::17) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by SG2PR06CA0163.apcprd06.prod.outlook.com (2603:1096:1:1e::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4150.23 via Frontend Transport; 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Signed-off-by: Peng Fan Reviewed-by: Frieder Schrempf Acked-by: Rob Herring --- include/dt-bindings/power/imx8mm-power.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.30.0 diff --git a/include/dt-bindings/power/imx8mm-power.h b/include/dt-bindings/power/imx8mm-power.h index fc9c2e16aadc..982ca2939cdc 100644 --- a/include/dt-bindings/power/imx8mm-power.h +++ b/include/dt-bindings/power/imx8mm-power.h @@ -19,4 +19,17 @@ #define IMX8MM_POWER_DOMAIN_DISPMIX 10 #define IMX8MM_POWER_DOMAIN_MIPI 11 +#define IMX8MM_BLK_CTL_PD_VPU_G2 0 +#define IMX8MM_BLK_CTL_PD_VPU_G1 1 +#define IMX8MM_BLK_CTL_PD_VPU_H1 2 +#define IMX8MM_BLK_CTL_PD_VPU_BUS 3 +#define IMX8MM_BLK_CTL_PD_VPU_MAX 4 + +#define IMX8MM_BLK_CTL_PD_DISPMIX_CSI_BRIDGE 0 +#define IMX8MM_BLK_CTL_PD_DISPMIX_LCDIF 1 +#define IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_DSI 2 +#define IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_CSI 3 +#define IMX8MM_BLK_CTL_PD_DISPMIX_BUS 4 +#define IMX8MM_BLK_CTL_PD_DISPMIX_MAX 5 + #endif From patchwork Fri May 21 10:59:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 444652 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp840602jac; Fri, 21 May 2021 03:28:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyusYnk7SRS6HCO/QL32FJ35kAfheG9ff6cGPXAzIVP/rmtHhgVPnr0NPt+Wd1O+pzTVHtg X-Received: by 2002:a17:906:c448:: with SMTP id ck8mr9496819ejb.497.1621592926918; Fri, 21 May 2021 03:28:46 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1621592926; cv=pass; d=google.com; s=arc-20160816; b=AwCElCQUDMpB0xiwUIQz1CANxQkixm42F+ibyEoGv3m4NfOOCtwqA/pNp0TUcRc0P/ FgeaPFxOJSRlOuKw5kYDY8cq2EKrXeINaOOUwyWOPi+WIxOpM3JN8s+gpvYr4sY7+x6a qRnlRst8N0GH/HmuvpFVCjFiuNrfelJfN79FBjifUA5tuf3IocUMHER8TNbpXiKKLvsC ejOsqDhVQ9kq98qB6inEKswD6UbwQmsvGkWl53Lzfuz3vOpT9GIk38oMkD5kfDU/Redu 3VT3D3xvuq/b1c364OaoLOWsZH8txlTwllsCF7JJpNY5nJkrms2U4c07+xMt2vxS727A ao+A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=0aB9k0PrMCYDScMBixgBT3+fJPleWCeHpDcOqnFBs8Q=; b=IvAQncAnDbxm+m1t28/Ks0s157aaDSnjvQzR9rHjaRFoSiGlyIpD7p5E+Mqdyzl40j Tb5y0KnGus/4ThRgF8Bs7QoMlyRw4jeDPBV9nIpqFpxCu3alcMepSwN5Yp8NbHzc3KLv AZBAUCVQ/1TdG3lcwAQcFuBdBdv/cFXMwjtfvMytepod8kI4EouRDsfzglV1Imbil/7G lOCPJyYcCO5k6WnBDOJrHvzfNygsC3R6MpmkrB3UTmBwyXlNufbprqARguEbyZa6At+h NEvnhKN8MTjluWhCCHKR2RussZ0rlU47Bru5LfZzo3pulhtc/q8kwPF2kdKkrnU1kVfC Za+w== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@NXP1.onmicrosoft.com header.s=selector2-NXP1-onmicrosoft-com header.b=E99e+TER; arc=pass (i=1 spf=pass spfdomain=oss.nxp.com dkim=pass dkdomain=oss.nxp.com dmarc=pass fromdomain=oss.nxp.com); spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Fri, 21 May 2021 10:27:20 +0000 From: "Peng Fan (OSS)" To: robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, p.zabel@pengutronix.de, l.stach@pengutronix.de, krzk@kernel.org, agx@sigxcpu.org, marex@denx.de, andrew.smirnov@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, ping.bai@nxp.com, frieder.schrempf@kontron.de, aford173@gmail.com, abel.vesa@nxp.com, Peng Fan , Rob Herring Subject: [PATCH V5 2/4] Documentation: bindings: clk: Add bindings for i.MX BLK_CTL Date: Fri, 21 May 2021 18:59:17 +0800 Message-Id: <20210521105919.20167-3-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210521105919.20167-1-peng.fan@oss.nxp.com> References: <20210521105919.20167-1-peng.fan@oss.nxp.com> X-Originating-IP: [119.31.174.71] X-ClientProxiedBy: SG2PR06CA0163.apcprd06.prod.outlook.com (2603:1096:1:1e::17) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by SG2PR06CA0163.apcprd06.prod.outlook.com (2603:1096:1:1e::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4150.23 via Frontend Transport; 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Each BLK CTL have different power domain inputs and they have different names, so we are not able to list all the power domain names for each BLK CTL here. For example: i.MX8MM dispmix BLK CTL, it has power-domains = <&pgc_dispmix>, <&pgc_mipi>; power-domain-names = "dispmix", "mipi"; vpumix BLK CTL, it has power-domains = <&vpumix_pd>, <&vpu_g1_pd>, <&vpu_g2_pd>, <&vpu_h1_pd>; power-domain-names = "vpumix", "g1", "g2", "h1"; Reviewed-by: Rob Herring Signed-off-by: Peng Fan --- .../bindings/soc/imx/fsl,imx-blk-ctl.yaml | 66 +++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml -- 2.30.0 diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml new file mode 100644 index 000000000000..a66f11acc6b4 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx-blk-ctl.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx-blk-ctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX BLK_CTL + +maintainers: + - Peng Fan + +description: + i.MX BLK_CTL is a conglomerate of different GPRs that are + dedicated to a specific subsystem. It usually contains + clocks and resets amongst other things. Here we take the clocks + and resets as virtual PDs, the reason we could not take it as + clock provider is there is A/B lock issue between power domain + and clock. + +properties: + compatible: + items: + - enum: + - fsl,imx8mm-dispmix-blk-ctl + - fsl,imx8mm-vpumix-blk-ctl + - const: syscon + + reg: + maxItems: 1 + + "#power-domain-cells": + const: 1 + + power-domains: + minItems: 1 + maxItems: 32 + + power-domain-names: + minItems: 1 + maxItems: 32 + + clocks: + minItems: 1 + maxItems: 32 + +required: + - compatible + - reg + - power-domains + - power-domain-names + +additionalProperties: false + +examples: + - | + #include + + dispmix_blk_ctl: blk-ctl@32e28000 { + compatible = "fsl,imx8mm-dispmix-blk-ctl", "syscon"; + reg = <0x32e28000 0x100>; + #power-domain-cells = <1>; + power-domains = <&pgc_dispmix>, <&pgc_mipi>; + power-domain-names = "dispmix", "mipi"; + clocks = <&clk IMX8MM_CLK_DISP_ROOT>, <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>; + }; From patchwork Fri May 21 10:59:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 444653 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp841368jac; Fri, 21 May 2021 03:29:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyhy7Ed1sGfyY56MQ3Ocwpd6hHQ3DrDMT8sPNbpRFS8qzGvhcTIiIQe2w43HS/6/Ckori8l X-Received: by 2002:aa7:cc9a:: with SMTP id p26mr10346467edt.74.1621592991349; Fri, 21 May 2021 03:29:51 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1621592991; cv=pass; d=google.com; s=arc-20160816; b=lmBR8vL8o5hLQwoDKMPRdpDa9+HfL1zVEWS5C+X55JPk9B3iY96tPg/R0iMHJvffz0 TRw9BDO4W4i14Rh+VJdmtLhkYSKLjlwIZ1k8DQ30zo7E/pJI7Zd8fia8Q6VeYVa2nFEo YHfIcGxhDh9YezlQ/gn2MLyQ0z680gPIsHLFKQQNE8oSbxmIwL0FB5TL7/70459wYWCt jlFnD3STvpmAdcr29fN+mWBFUqv3KKjeAiiU/BG9pWpEq1GxFvT0Th+teidPP7/YmF0g 9fpW+yei3o0JDzoTMhIF7j4PwFg3kjCOzZ2GNVOt4iXyQhgT2S52mwAmiJhlCC78WVuj tvqw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9ZsWnY3TezvfbLH4aC9Y4cb+Zf1RCoEJxJEx8A03Lhg=; b=zihyd83bKQxFal6l0g6MyZjE2YIGR5Cx+aH1B9PK7NWumTBQTHx201K/18V1QrKRmo 1w7TyOarDQLspL6Q0kFUGyIijdrSXHF6ek279GruSZxnjTFq7L90nmNjAjXfwPS82nKS rxW5X4sSidprnDTs3veAoXgLH8U0qDUic/kauJ/2/J41kdAeyHKXqoFQ/jju2uLNfQ1S I8cu3PRrUeYrOZigwAmuaUVouJPuUWxRwnSK4OPNuAUUzb/DAgKJmdpZXEWLXR13bvNm kO1gpTTKsiOUbZAvQSYO5njIupEL8deV3HaaisYLbEpJMpv/jPBARlwvlT55cPjy6lKr ay7w== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@NXP1.onmicrosoft.com header.s=selector2-NXP1-onmicrosoft-com header.b=TBhzF4Om; arc=pass (i=1 spf=pass spfdomain=oss.nxp.com dkim=pass dkdomain=oss.nxp.com dmarc=pass fromdomain=oss.nxp.com); spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Fri, 21 May 2021 10:27:27 +0000 From: "Peng Fan (OSS)" To: robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, p.zabel@pengutronix.de, l.stach@pengutronix.de, krzk@kernel.org, agx@sigxcpu.org, marex@denx.de, andrew.smirnov@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, ping.bai@nxp.com, frieder.schrempf@kontron.de, aford173@gmail.com, abel.vesa@nxp.com, Peng Fan Subject: [PATCH V5 3/4] soc: imx: Add generic blk-ctl driver Date: Fri, 21 May 2021 18:59:18 +0800 Message-Id: <20210521105919.20167-4-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210521105919.20167-1-peng.fan@oss.nxp.com> References: <20210521105919.20167-1-peng.fan@oss.nxp.com> X-Originating-IP: [119.31.174.71] X-ClientProxiedBy: SG2PR06CA0163.apcprd06.prod.outlook.com (2603:1096:1:1e::17) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by SG2PR06CA0163.apcprd06.prod.outlook.com (2603:1096:1:1e::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4150.23 via Frontend Transport; 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The GPRs has some clock bits and reset bits, but here we take it as virtual PDs, because of the clock and power domain A/B lock issue when taking it as a clock controller. For some bits, it might be good to also make it as a reset controller, but to i.MX8MM, we not add that support for now. Signed-off-by: Peng Fan --- drivers/soc/imx/Makefile | 2 +- drivers/soc/imx/blk-ctl.c | 311 ++++++++++++++++++++++++++++++++++++++ drivers/soc/imx/blk-ctl.h | 85 +++++++++++ 3 files changed, 397 insertions(+), 1 deletion(-) create mode 100644 drivers/soc/imx/blk-ctl.c create mode 100644 drivers/soc/imx/blk-ctl.h -- 2.30.0 diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile index 078dc918f4f3..d3d2b49a386c 100644 --- a/drivers/soc/imx/Makefile +++ b/drivers/soc/imx/Makefile @@ -4,4 +4,4 @@ obj-$(CONFIG_ARCH_MXC) += soc-imx.o endif obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o -obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o +obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o blk-ctl.o diff --git a/drivers/soc/imx/blk-ctl.c b/drivers/soc/imx/blk-ctl.c new file mode 100644 index 000000000000..1025415eef42 --- /dev/null +++ b/drivers/soc/imx/blk-ctl.c @@ -0,0 +1,311 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2021 NXP. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "blk-ctl.h" + +static inline struct imx_blk_ctl_domain *to_imx_blk_ctl_pd(struct generic_pm_domain *genpd) +{ + return container_of(genpd, struct imx_blk_ctl_domain, genpd); +} + +static int imx_blk_ctl_enable_hsk(struct device *dev) +{ + struct imx_blk_ctl *blk_ctl = dev_get_drvdata(dev); + const struct imx_blk_ctl_hw *hw = blk_ctl->dev_data->hw_hsk; + struct regmap *regmap = blk_ctl->regmap; + int ret; + + if (hw->flags & IMX_BLK_CTL_PD_RESET) { + ret = regmap_update_bits(regmap, hw->rst_offset, hw->rst_mask, hw->rst_mask); + if (ret) + return ret; + } + + ret = regmap_update_bits(regmap, hw->offset, hw->mask, hw->mask); + + /* Wait for handshake */ + udelay(5); + + return ret; +} + +int imx_blk_ctl_power_on(struct generic_pm_domain *domain) +{ + struct imx_blk_ctl_domain *pd = to_imx_blk_ctl_pd(domain); + struct imx_blk_ctl *blk_ctl = pd->blk_ctl; + struct regmap *regmap = blk_ctl->regmap; + const struct imx_blk_ctl_hw *hw = &blk_ctl->dev_data->pds[pd->id]; + int ret; + + mutex_lock(&blk_ctl->lock); + + ret = clk_bulk_prepare_enable(blk_ctl->num_clks, blk_ctl->clks); + if (ret) { + mutex_unlock(&blk_ctl->lock); + return ret; + } + + if (hw->flags & IMX_BLK_CTL_PD_HANDSHAKE) { + ret = imx_blk_ctl_enable_hsk(blk_ctl->dev); + if (ret) + dev_err(blk_ctl->dev, "Hankshake failed when power on\n"); + + goto disable_clk; + } + + if (hw->flags & IMX_BLK_CTL_PD_RESET) { + ret = regmap_clear_bits(regmap, hw->rst_offset, hw->rst_mask); + if (ret) + goto disable_clk; + } + + /* Wait for reset propagate */ + udelay(5); + + if (hw->flags & IMX_BLK_CTL_PD_RESET) { + ret = regmap_update_bits(regmap, hw->rst_offset, hw->rst_mask, hw->rst_mask); + if (ret) + goto disable_clk; + } + + ret = regmap_update_bits(regmap, hw->offset, hw->mask, hw->mask); + if (ret) + goto disable_clk; + +disable_clk: + clk_bulk_disable_unprepare(blk_ctl->num_clks, blk_ctl->clks); + + mutex_unlock(&blk_ctl->lock); + + return ret; +} + +int imx_blk_ctl_power_off(struct generic_pm_domain *domain) +{ + struct imx_blk_ctl_domain *pd = to_imx_blk_ctl_pd(domain); + struct imx_blk_ctl *blk_ctl = pd->blk_ctl; + struct regmap *regmap = blk_ctl->regmap; + const struct imx_blk_ctl_hw *hw = &blk_ctl->dev_data->pds[pd->id]; + int ret; + + mutex_lock(&blk_ctl->lock); + + ret = clk_bulk_prepare_enable(blk_ctl->num_clks, blk_ctl->clks); + if (ret) { + mutex_unlock(&blk_ctl->lock); + return ret; + } + + if (!(hw->flags & IMX_BLK_CTL_PD_HANDSHAKE)) { + ret = regmap_clear_bits(regmap, hw->offset, hw->mask); + if (ret) + goto hsk_fail; + + if (hw->flags & IMX_BLK_CTL_PD_RESET) { + ret = regmap_clear_bits(regmap, hw->rst_offset, hw->rst_mask); + if (ret) + goto hsk_fail; + } + } + + if (hw->flags & IMX_BLK_CTL_PD_HANDSHAKE) { + ret = imx_blk_ctl_enable_hsk(blk_ctl->dev); + if (ret) + dev_err(blk_ctl->dev, "Hankshake failed when power off\n"); + } + +hsk_fail: + clk_bulk_disable_unprepare(blk_ctl->num_clks, blk_ctl->clks); + + mutex_unlock(&blk_ctl->lock); + + return ret; +} + +static int imx_blk_ctl_probe(struct platform_device *pdev) +{ + struct imx_blk_ctl_domain *domain = pdev->dev.platform_data; + struct imx_blk_ctl *blk_ctl = domain->blk_ctl; + struct generic_pm_domain *parent_genpd; + struct device *dev = &pdev->dev; + struct device *active_pd; + int ret; + + if (domain->hw->active_pd_name) { + active_pd = dev_pm_domain_attach_by_name(dev, domain->hw->active_pd_name); + if (IS_ERR_OR_NULL(active_pd)) { + ret = PTR_ERR(active_pd) ? : -ENODATA; + return ret; + } + domain->active_pd = active_pd; + } else { + if (!blk_ctl->bus_domain) + return -EPROBE_DEFER; + } + + if (domain->hw->active_pd_name) + parent_genpd = pd_to_genpd(active_pd->pm_domain); + else + parent_genpd = blk_ctl->bus_domain; + + if (pm_genpd_add_subdomain(parent_genpd, &domain->genpd)) { + pr_warn("failed to add subdomain: %s\n", domain->genpd.name); + } else { + mutex_lock(&blk_ctl->lock); + domain->hooked = true; + mutex_unlock(&blk_ctl->lock); + } + + return 0; +} + +static int imx_blk_ctl_remove(struct platform_device *pdev) +{ + return 0; +} + +static const struct platform_device_id imx_blk_ctl_id[] = { + { "imx-vpumix-blk-ctl", }, + { "imx-dispmix-blk-ctl", }, + { }, +}; + +static struct platform_driver imx_blk_ctl_driver = { + .driver = { + .name = "imx-blk-ctl", + }, + .probe = imx_blk_ctl_probe, + .remove = imx_blk_ctl_remove, + .id_table = imx_blk_ctl_id, +}; +builtin_platform_driver(imx_blk_ctl_driver) + +static struct generic_pm_domain *imx_blk_ctl_genpd_xlate(struct of_phandle_args *genpdspec, + void *data) +{ + struct genpd_onecell_data *genpd_data = data; + unsigned int idx = genpdspec->args[0]; + struct imx_blk_ctl_domain *domain; + struct generic_pm_domain *genpd = ERR_PTR(-EINVAL); + + if (genpdspec->args_count != 1) + return ERR_PTR(-EINVAL); + + if (idx >= genpd_data->num_domains) { + pr_err("%s: invalid domain index %u\n", __func__, idx); + return ERR_PTR(-EINVAL); + } + + if (!genpd_data->domains[idx]) + return ERR_PTR(-ENOENT); + + domain = to_imx_blk_ctl_pd(genpd_data->domains[idx]); + mutex_lock(&domain->blk_ctl->lock); + if (domain->hooked) + genpd = genpd_data->domains[idx]; + mutex_unlock(&domain->blk_ctl->lock); + + return genpd; +} + +int imx_blk_ctl_register(struct device *dev) +{ + struct imx_blk_ctl *blk_ctl = dev_get_drvdata(dev); + const struct imx_blk_ctl_dev_data *dev_data = blk_ctl->dev_data; + int num = dev_data->pds_num; + struct imx_blk_ctl_domain *domain; + struct generic_pm_domain *genpd; + struct platform_device *pd_pdev; + int domain_index; + int i, ret; + + blk_ctl->onecell_data.num_domains = num; + blk_ctl->onecell_data.xlate = imx_blk_ctl_genpd_xlate; + blk_ctl->onecell_data.domains = devm_kcalloc(dev, num, sizeof(struct generic_pm_domain *), + GFP_KERNEL); + if (!blk_ctl->onecell_data.domains) + return -ENOMEM; + + for (i = 0; i < num; i++) { + domain_index = dev_data->pds[i].id; + if (domain_index >= num) { + dev_warn(dev, "Domain index %d is out of bounds\n", domain_index); + continue; + } + + domain = devm_kzalloc(dev, sizeof(struct imx_blk_ctl_domain), GFP_KERNEL); + if (!domain) + goto error; + + pd_pdev = platform_device_alloc(dev_data->name, domain_index); + if (!pd_pdev) { + dev_err(dev, "Failed to allocate platform device\n"); + goto error; + } + + pd_pdev->dev.platform_data = domain; + + domain->blk_ctl = blk_ctl; + domain->hw = &dev_data->pds[i]; + domain->id = domain_index; + domain->genpd.name = dev_data->pds[i].name; + domain->genpd.power_off = imx_blk_ctl_power_off; + domain->genpd.power_on = imx_blk_ctl_power_on; + domain->dev = &pd_pdev->dev; + domain->hooked = false; + + ret = pm_genpd_init(&domain->genpd, NULL, true); + pd_pdev->dev.parent = dev; + pd_pdev->dev.of_node = dev->of_node; + + if (domain->hw->flags & IMX_BLK_CTL_PD_HANDSHAKE) + blk_ctl->bus_domain = &domain->genpd; + + ret = platform_device_add(pd_pdev); + if (ret) { + platform_device_put(pd_pdev); + goto error; + } + blk_ctl->onecell_data.domains[i] = &domain->genpd; + } + + return of_genpd_add_provider_onecell(dev->of_node, &blk_ctl->onecell_data); + +error: + for (; i >= 0; i--) { + genpd = blk_ctl->onecell_data.domains[i]; + if (!genpd) + continue; + domain = to_imx_blk_ctl_pd(genpd); + if (domain->dev) + platform_device_put(to_platform_device(domain->dev)); + } + return ret; +} +EXPORT_SYMBOL_GPL(imx_blk_ctl_register); + +const struct dev_pm_ops imx_blk_ctl_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) +}; +EXPORT_SYMBOL_GPL(imx_blk_ctl_pm_ops); diff --git a/drivers/soc/imx/blk-ctl.h b/drivers/soc/imx/blk-ctl.h new file mode 100644 index 000000000000..6780d00ec8c5 --- /dev/null +++ b/drivers/soc/imx/blk-ctl.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __SOC_IMX_BLK_CTL_H +#define __SOC_IMX_BLK_CTL_H + +enum imx_blk_ctl_pd_type { + BLK_CTL_PD, +}; + +struct imx_blk_ctl_hw { + int type; + char *name; + char *active_pd_name; + u32 offset; + u32 mask; + u32 flags; + u32 id; + u32 rst_offset; + u32 rst_mask; + u32 errata; +}; + +struct imx_blk_ctl_domain { + struct generic_pm_domain genpd; + struct device *active_pd; + struct imx_blk_ctl *blk_ctl; + struct imx_blk_ctl_hw *hw; + struct device *dev; + bool hooked; + u32 id; +}; + +struct imx_blk_ctl_dev_data { + struct regmap_config config; + struct imx_blk_ctl_hw *pds; + struct imx_blk_ctl_hw *hw_hsk; + u32 pds_num; + u32 max_num; + char *name; +}; + +struct imx_blk_ctl { + struct device *dev; + struct regmap *regmap; + struct genpd_onecell_data onecell_data; + const struct imx_blk_ctl_dev_data *dev_data; + struct clk_bulk_data *clks; + u32 num_clks; + struct generic_pm_domain *bus_domain; + + struct mutex lock; +}; + +#define IMX_BLK_CTL(_type, _name, _active_pd, _id, _offset, _mask, _rst_offset, _rst_mask, \ + _flags, _errata) \ + { \ + .type = _type, \ + .name = _name, \ + .active_pd_name = _active_pd, \ + .id = _id, \ + .offset = _offset, \ + .mask = _mask, \ + .flags = _flags, \ + .rst_offset = _rst_offset, \ + .rst_mask = _rst_mask, \ + .errata = _errata, \ + } + +#define IMX_BLK_CTL_PD(_name, _active_pd, _id, _offset, _mask, _rst_offset, _rst_mask, _flags) \ + IMX_BLK_CTL(BLK_CTL_PD, _name, _active_pd, _id, _offset, _mask, _rst_offset, \ + _rst_mask, _flags, 0) + +#define IMX_BLK_CTL_PD_ERRATA(_name, _active_pd, _id, _offset, _mask, _rst_offset, _rst_mask, \ + _flags, _errata) \ + IMX_BLK_CTL(BLK_CTL_PD, _name, _active_pd, _id, _offset, _mask, _rst_offset, \ + _rst_mask, _flags, _errata) + +int imx_blk_ctl_register(struct device *dev); + +#define IMX_BLK_CTL_PD_HANDSHAKE BIT(0) +#define IMX_BLK_CTL_PD_RESET BIT(1) +#define IMX_BLK_CTL_PD_BUS BIT(2) + +const extern struct dev_pm_ops imx_blk_ctl_pm_ops; + +#endif From patchwork Fri May 21 10:59:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 444654 Delivered-To: patch@linaro.org Received: by 2002:a02:7a1b:0:0:0:0:0 with SMTP id a27csp841377jac; Fri, 21 May 2021 03:29:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxmxjpdPe2Dd50ZFpE4hN/Puad24P33dkb7Ije1clVJ/lRWdjKBiX97wvzqET9GTmyokiiD X-Received: by 2002:aa7:c9ce:: with SMTP id i14mr10306084edt.148.1621592992595; Fri, 21 May 2021 03:29:52 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1621592992; cv=pass; d=google.com; s=arc-20160816; b=onInK1BSNB8EiBtf8MmFBc0WRcxaqzLfipsqoxEs7Qdw9zm/M5iBB1Bo9XZ4ETWX7Y X57jXOXSxWXBQfsNa/IwWAOZk7o5Pfi2nt3QekAuwcXZWVZwehV1OAvu5G0iWs2Yrwou sPDEyF6qmmXnC5yTtzhbvIn9pvswGy8XjTYG7BT/3j9NCuqNBdee26RThMfp7twlJH9q Hqzdou6Hd11R7IoCyXUgizOGa3VAzXoLByYRSZ3K3xHIRPcIBN6i5XHauufIRyUP6knN hNsr3pnKz95AXdIP670aVhOTPtbVyKiwPHRdDbBkVjQO0xJcsgIjMQkzmpa/iYPresBs Owhg== ARC-Message-Signature: i=2; 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Fri, 21 May 2021 10:27:33 +0000 From: "Peng Fan (OSS)" To: robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de Cc: kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, p.zabel@pengutronix.de, l.stach@pengutronix.de, krzk@kernel.org, agx@sigxcpu.org, marex@denx.de, andrew.smirnov@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, ping.bai@nxp.com, frieder.schrempf@kontron.de, aford173@gmail.com, abel.vesa@nxp.com, Peng Fan Subject: [PATCH V5 4/4] soc: imx: Add blk-ctl driver for i.MX8MM Date: Fri, 21 May 2021 18:59:19 +0800 Message-Id: <20210521105919.20167-5-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210521105919.20167-1-peng.fan@oss.nxp.com> References: <20210521105919.20167-1-peng.fan@oss.nxp.com> X-Originating-IP: [119.31.174.71] X-ClientProxiedBy: SG2PR06CA0163.apcprd06.prod.outlook.com (2603:1096:1:1e::17) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by SG2PR06CA0163.apcprd06.prod.outlook.com (2603:1096:1:1e::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4150.23 via Frontend Transport; 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Reviewed-by: Abel Vesa Signed-off-by: Peng Fan --- drivers/soc/imx/Makefile | 2 +- drivers/soc/imx/blk-ctl-imx8mm.c | 139 +++++++++++++++++++++++++++++++ 2 files changed, 140 insertions(+), 1 deletion(-) create mode 100644 drivers/soc/imx/blk-ctl-imx8mm.c -- 2.30.0 diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile index d3d2b49a386c..c260b962f495 100644 --- a/drivers/soc/imx/Makefile +++ b/drivers/soc/imx/Makefile @@ -4,4 +4,4 @@ obj-$(CONFIG_ARCH_MXC) += soc-imx.o endif obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o -obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o blk-ctl.o +obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o blk-ctl.o blk-ctl-imx8mm.o diff --git a/drivers/soc/imx/blk-ctl-imx8mm.c b/drivers/soc/imx/blk-ctl-imx8mm.c new file mode 100644 index 000000000000..59443588f892 --- /dev/null +++ b/drivers/soc/imx/blk-ctl-imx8mm.c @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2021 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "blk-ctl.h" + +#define MEDIA_BLK_BUS_RSTN_BLK_SYNC_SFT_EN BIT(6) +#define MEDIA_BLK_MIPI_DSI_I_PRESETN_SFT_EN BIT(5) +#define MEDIA_BLK_MIPI_CSI_I_PRESETN_SFT_EN BIT(4) +#define MEDIA_BLK_CAMERA_PIXEL_RESET_N_SFT_EN BIT(3) +#define MEDIA_BLK_CSI_BRIDGE_SFT_EN GENMASK(2, 0) + +#define MEDIA_BLK_BUS_PD_MASK BIT(12) +#define MEDIA_BLK_MIPI_CSI_PD_MASK GENMASK(11, 10) +#define MEDIA_BLK_MIPI_DSI_PD_MASK GENMASK(9, 8) +#define MEDIA_BLK_LCDIF_PD_MASK GENMASK(7, 6) +#define MEDIA_BLK_CSI_BRIDGE_PD_MASK GENMASK(5, 0) + +static struct imx_blk_ctl_hw imx8mm_dispmix_blk_ctl_pds[] = { + IMX_BLK_CTL_PD("CSI_BRIDGE", NULL, IMX8MM_BLK_CTL_PD_DISPMIX_CSI_BRIDGE, 0x4, + MEDIA_BLK_CSI_BRIDGE_PD_MASK, 0, MEDIA_BLK_CSI_BRIDGE_SFT_EN, + IMX_BLK_CTL_PD_RESET), + IMX_BLK_CTL_PD("LCDIF", NULL, IMX8MM_BLK_CTL_PD_DISPMIX_LCDIF, 0x4, + MEDIA_BLK_LCDIF_PD_MASK, -1, -1, 0), + IMX_BLK_CTL_PD("MIPI_DSI", "mipi", IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_DSI, 0x4, + MEDIA_BLK_MIPI_DSI_PD_MASK, 0, MEDIA_BLK_MIPI_DSI_I_PRESETN_SFT_EN, + IMX_BLK_CTL_PD_RESET), + IMX_BLK_CTL_PD("MIPI_CSI", "mipi", IMX8MM_BLK_CTL_PD_DISPMIX_MIPI_CSI, 0x4, + MEDIA_BLK_MIPI_CSI_PD_MASK, 0, + MEDIA_BLK_MIPI_CSI_I_PRESETN_SFT_EN | MEDIA_BLK_CAMERA_PIXEL_RESET_N_SFT_EN, + IMX_BLK_CTL_PD_RESET), + IMX_BLK_CTL_PD("DISPMIX_BUS", "dispmix", IMX8MM_BLK_CTL_PD_DISPMIX_BUS, 0x4, + MEDIA_BLK_BUS_PD_MASK, 0, MEDIA_BLK_BUS_RSTN_BLK_SYNC_SFT_EN, + IMX_BLK_CTL_PD_HANDSHAKE | IMX_BLK_CTL_PD_RESET) +}; + +static struct imx_blk_ctl_hw imx8mm_vpumix_blk_ctl_pds[] = { + IMX_BLK_CTL_PD("VPU_BLK_CTL_G2", "vpu-g2", IMX8MM_BLK_CTL_PD_VPU_G2, 0x4, + BIT(0), 0, BIT(0), IMX_BLK_CTL_PD_RESET), + IMX_BLK_CTL_PD("VPU_BLK_CTL_G1", "vpu-g1", IMX8MM_BLK_CTL_PD_VPU_G1, 0x4, + BIT(1), 0, BIT(1), IMX_BLK_CTL_PD_RESET), + IMX_BLK_CTL_PD("VPU_BLK_CTL_H1", "vpu-h1", IMX8MM_BLK_CTL_PD_VPU_H1, 0x4, + BIT(2), 0, BIT(2), IMX_BLK_CTL_PD_RESET), + IMX_BLK_CTL_PD("VPU_BLK_CTL_BUS", "vpumix", IMX8MM_BLK_CTL_PD_VPU_BUS, 0x4, + BIT(2), 0, BIT(2), IMX_BLK_CTL_PD_HANDSHAKE | IMX_BLK_CTL_PD_RESET) +}; + +static const struct regmap_config imx8mm_blk_ctl_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x30, + .fast_io = true, +}; + +static const struct imx_blk_ctl_dev_data imx8mm_vpumix_blk_ctl_dev_data = { + .pds = imx8mm_vpumix_blk_ctl_pds, + .pds_num = ARRAY_SIZE(imx8mm_vpumix_blk_ctl_pds), + .max_num = IMX8MM_BLK_CTL_PD_VPU_MAX, + .hw_hsk = &imx8mm_vpumix_blk_ctl_pds[3], + .config = imx8mm_blk_ctl_regmap_config, + .name = "imx-vpumix-blk-ctl", +}; + +static const struct imx_blk_ctl_dev_data imx8mm_dispmix_blk_ctl_dev_data = { + .pds = imx8mm_dispmix_blk_ctl_pds, + .pds_num = ARRAY_SIZE(imx8mm_dispmix_blk_ctl_pds), + .max_num = IMX8MM_BLK_CTL_PD_DISPMIX_MAX, + .hw_hsk = &imx8mm_dispmix_blk_ctl_pds[4], + .config = imx8mm_blk_ctl_regmap_config, + .name = "imx-dispmix-blk-ctl", +}; + +static int imx8mm_blk_ctl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct imx_blk_ctl_dev_data *dev_data = of_device_get_match_data(dev); + struct regmap *regmap; + struct imx_blk_ctl *ctl; + void __iomem *base; + + ctl = devm_kzalloc(dev, sizeof(*ctl), GFP_KERNEL); + if (!ctl) + return -ENOMEM; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap = devm_regmap_init_mmio(dev, base, &dev_data->config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + ctl->regmap = regmap; + ctl->dev = dev; + mutex_init(&ctl->lock); + + ctl->num_clks = devm_clk_bulk_get_all(dev, &ctl->clks); + if (ctl->num_clks < 0) + return ctl->num_clks; + + dev_set_drvdata(dev, ctl); + ctl->dev_data = dev_data; + + return imx_blk_ctl_register(dev); +} + +static const struct of_device_id imx_blk_ctl_of_match[] = { + { .compatible = "fsl,imx8mm-vpumix-blk-ctl", .data = &imx8mm_vpumix_blk_ctl_dev_data }, + { .compatible = "fsl,imx8mm-dispmix-blk-ctl", .data = &imx8mm_dispmix_blk_ctl_dev_data }, + { /* Sentinel */ } +}; +MODULE_DEVICE_TABLE(of, imx_blk_ctl_of_match); + +static struct platform_driver imx_blk_ctl_driver = { + .probe = imx8mm_blk_ctl_probe, + .driver = { + .name = "imx8mm-blk-ctl", + .of_match_table = of_match_ptr(imx_blk_ctl_of_match), + .pm = &imx_blk_ctl_pm_ops, + }, +}; +module_platform_driver(imx_blk_ctl_driver);